JP5023723B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a plurality of wiring layers and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device capable of suppressing dielectric breakdown between wiring layers and a method for manufacturing the same.

  FIG. 5 is a cross-sectional view for explaining the configuration of a conventional semiconductor device. The semiconductor device shown in this figure has a low breakdown voltage transistor in the first element region 100a of the first conductivity type semiconductor substrate 100 and a high breakdown voltage transistor in the second element region 100b. On the first element region 100a and the second element region 100b, a first interlayer insulating film 109, a first wiring layer, a second interlayer insulating film 112, and a second wiring layer Are stacked in this order.

  The first wiring layer has Al alloy wirings 111a and 111c located above the first element region 100a and Al alloy wirings 111b and 111d located above the second element region 100b. The Al alloy wiring 111a is electrically connected to a part of the low breakdown voltage transistor (for example, the second conductivity type impurity region 107a serving as a source or a drain), and the Al alloy wiring 111c is used to apply a substrate potential. It is electrically connected to the impurity region 108a of one conductivity type. The Al alloy wiring 111b is electrically connected to a part of the high breakdown voltage transistor (for example, the second conductivity type impurity region 107b serving as a source or drain), and the Al alloy wiring 111d is used for applying a substrate potential. It is electrically connected to the first conductivity type impurity region 108b.

  The second wiring layer has Al alloy wirings 114a and 114c located above the first element region 100a and Al alloy wirings 114b and 114d located above the second element region 100b. The Al alloy wiring 114a is electrically connected to the Al alloy wiring 111a, and the Al alloy wiring 114c is electrically connected to the Al alloy wiring 111c. The Al alloy wiring 114b is electrically connected to the Al alloy wiring 111b, and the Al alloy wiring 114d is electrically connected to the Al alloy wiring 111d. A semiconductor device similar to this is described in Patent Document 1.

JP-A-6-151730 (FIG. 4)

  In recent years, miniaturization of low breakdown voltage transistors has progressed, and interlayer dielectric films have been made low dielectric and thin. On the other hand, in the above-described conventional technology, in all the wiring layers, the wiring is arranged above the first element region where the low breakdown voltage transistor is formed and the second element region where the high breakdown voltage transistor is formed. . However, the wiring arranged above the second element region includes a wiring to which a high voltage is applied (for example, a wiring connected to a high voltage transistor) and a wiring to which a low voltage is applied (for example, a wiring for installation). For this reason, in the state where the interlayer insulating film is low dielectric and thin, when the wiring to which a high voltage is applied and the wiring to which a low voltage is applied are arranged above and below through a single interlayer insulating film, the interlayer insulating film Insufficient breakdown voltage could cause dielectric breakdown between the wiring layers.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of dielectric breakdown between wiring layers and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device according to the present invention includes a first interlayer insulating film formed above a first element region and a second element region of a semiconductor substrate,
A first wiring layer formed on the first interlayer insulating film;
A second interlayer insulating film formed on the first interlayer insulating film and the first wiring layer;
A second wiring layer formed on the second interlayer insulating film;
A third interlayer insulating film formed on the second interlayer insulating film and the second wiring layer;
A third wiring layer formed on the third interlayer insulating film;
Comprising
The first wiring layer is located above the first element region, the second wiring located above the second element region, and the second element region. A third wiring having a potential different from that of the second wiring;
The second wiring layer is located above the first element region and is electrically connected to the first wiring and a part of the third wiring. Comprising a conductive pattern for connection electrically connected to the third wiring;
The third wiring layer is located above the first element region and electrically connected to the fourth wiring, and is located above the second element region and the connection A sixth wiring electrically connected to the third wiring through the conductive pattern for electrical use;
The second wiring layer has no wiring above the second element region.

  According to this semiconductor device, wiring is formed in each wiring layer above the first element region, and every other layer above the second element region having a plurality of wirings to which different potentials are applied. A wiring is formed. For this reason, it is possible to suppress dielectric breakdown between the wiring layers above the second element region.

The second interlayer insulating film may have a thickness that causes dielectric breakdown when the potential difference between the upper surface and the lower surface is greater than or equal to the potential difference between the second wiring and the third wiring.
A part of the sixth wiring electrically connected to the third wiring may be located above the second wiring. Even in this case, it is possible to suppress the occurrence of dielectric breakdown between the wiring layers. The potential difference between the third wiring and the second wiring may be larger than the potential difference between the first wiring and the substrate potential.

  A first transistor formed on the semiconductor substrate located in the first element region; and a second transistor formed on the semiconductor substrate located in the second element region and having an operating voltage higher than that of the first transistor. May be. In this case, for example, the second wiring electrically connects the source or drain of the first transistor and the gate electrode of the second transistor, and the third wiring includes, for example, the source or drain of the second transistor. Connected to the drain.

  The first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film may be made of at least one of carbon-containing silica, fluorine-containing silica, and a silsesquioxane compound. .

Another semiconductor device according to the present invention includes a first transistor formed in a first element region of a semiconductor substrate,
A second transistor formed in a second element region of the semiconductor substrate and having a drive voltage higher than that of the first transistor;
A first interlayer insulating film formed on the first element region and the second element region;
A first wiring layer formed on the first interlayer insulating film;
A second interlayer insulating film formed on the first interlayer insulating film and the first wiring layer;
A second wiring layer formed on the second interlayer insulating film;
Comprising
The first wiring layer includes a first wiring located above the first element region,
The second wiring layer is located above the first element region and electrically connected to the first wiring, and is located above the second element region and the second element layer. A third wiring having a different potential from the two wirings;
And the first wiring layer has no wiring above the second element region.

  According to this semiconductor device, wiring is formed in each wiring layer above the first element region, and above the second element region having the third wiring having a potential different from that of the second wiring. No wiring is formed on the first wiring layer. For this reason, it is possible to suppress dielectric breakdown between the wiring layers above the second element region.

A part of the third wiring may be located above the gate electrode or the gate wiring of the second transistor.
The first interlayer insulating film and the second interlayer insulating film may be composed of at least one of carbon-containing silica, fluorine-containing silica, and a silsesquioxane-based compound.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first interlayer insulating film above a first element region and a second element region of a semiconductor substrate,
Forming a first wiring layer on the first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring layer;
Forming a second wiring layer on the second interlayer insulating film;
Forming a third interlayer insulating film on the second interlayer insulating film and the second wiring layer;
Forming a third wiring layer on the third interlayer insulating film;
Comprising
In the step of forming the first wiring layer, a first wiring located above the first element region, a second wiring located above the second element region, and a position above the second element region And forming a third wiring having a potential different from that of the second wiring,
In the step of forming the second wiring layer, a fourth wiring that is located above the first element region and is electrically connected to the first wiring is formed, and the fourth wiring layer is formed above the second element region and A conductive pattern for connection that is located above a part of the third wiring and is electrically connected to the third wiring is formed, and a wiring that is located above the second element region is not formed. ,
In the step of forming the third wiring layer, a fifth wiring located above the first element region and electrically connected to the fourth wiring, and located above the second element region. Then, a sixth wiring connected to the third wiring through the connection conductive pattern is formed.

In another method of manufacturing a semiconductor device according to the present invention, a first transistor is formed in a first element region of a semiconductor substrate, and a second driving voltage is higher in the second element region of the semiconductor substrate than the first transistor. Forming a transistor;
Forming a first interlayer insulating film on the first element region and the second element region;
Forming a first wiring layer on the first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring layer;
Forming a second wiring layer on the second interlayer insulating film;
Comprising
In the step of forming the first wiring layer, the first wiring located above the first element region is formed, and the wiring is not formed above the second element region,
In the step of forming the second wiring layer, the second wiring is located above the first element region and is electrically connected to the first wiring, and the second wiring layer is located above the second element region. Then, a third wiring having a potential different from that of the second wiring is formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each drawing in FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. The semiconductor device manufactured according to the present embodiment has a low breakdown voltage transistor in the first element region 1a of the first conductivity type silicon substrate 1, and has a high breakdown voltage transistor in the second element region 1b of the silicon substrate 1. is doing. The operating voltage of the low withstand voltage transistor is, for example, 5 V or less, and the operating voltage of the high withstand voltage transistor is, for example, 30 V or more.

  First, as shown in FIG. 1A, in the silicon substrate 1 located in the second element region 1b, the portions located between the channel region and the source of the high breakdown voltage transistor and between the channel region and the drain respectively. A two-conductivity type impurity is selectively introduced to form a low-concentration impurity region 6b.

  Next, an element isolation film 2b is formed on the silicon substrate 1 located in the second element region 1b by a LOCOS oxidation method. Thereby, the region where the high breakdown voltage transistor is formed and the region where the wiring for applying the substrate potential is connected are separated from other regions by the element isolation film 2b. Further, in the second element region 1b, the portion that becomes the channel region of the high breakdown voltage transistor, the portion that becomes the source, and the portion that becomes the drain are separated from other regions by the element isolation film 2b.

  Next, a groove is formed in the silicon substrate 1 located in the first element region 1a, and an insulating film is embedded in the groove. Thereby, the element isolation film 2a is formed. The element isolation film 2a isolates the region where the low breakdown voltage transistor is formed and the region where the wiring for applying the substrate potential is connected from other regions.

  Next, the silicon substrate 1 is thermally oxidized. Thereby, the gate insulating film 3b of the high breakdown voltage transistor is formed on the silicon substrate 1 located in the channel region of the second element region 1b. A thermal oxide film (not shown) is also formed on the silicon substrate 1 located in the first element region 1a.

  Next, a photoresist film (not shown) is applied on the entire surface including the first element region 1a and the second element region 1b, and the photoresist film is exposed and developed. Thereby, the photoresist film located on the first element region 1a is removed. Next, the thermal oxide film located in the first element region 1a is removed by etching using the photoresist film as a mask. Thereafter, the photoresist film is removed.

Next, the silicon substrate 1 is thermally oxidized again. Thereby, the gate insulating film 3a of the low breakdown voltage transistor is formed on the silicon substrate 1 located in the first element region 1a. Further, the gate insulating film 3b is also thickened.
In the two thermal oxidation steps described above, a thermal oxide film (not shown) is also formed on the silicon substrate 1 located in the source and drain regions of the high voltage transistor and the region to which the wiring for applying the substrate potential is connected. ) Is formed.

  Next, a polysilicon film is formed on the entire surface including the element isolation films 2a and 2b and the gate insulating films 3a and 3b by a CVD method, and the polysilicon film is selectively removed. Thereby, the gate electrode 4a of the low breakdown voltage transistor is formed on the gate insulating film 3a, and the gate electrode 4b of the high breakdown voltage transistor is formed on the gate insulating film 3b. A gate wiring (not shown) is also formed.

  Next, a region to which a wiring for applying a substrate potential is connected is covered with a resist pattern (not shown), and a second pattern is formed on the silicon substrate 1 using the resist pattern, element isolation films 2a and 2b, and gate electrodes 4a and 4b as a mask. A conductivity type impurity is implanted. Thereby, a low concentration impurity region 6a is formed in the silicon substrate 1 located in the first element region 1a. Thereafter, the resist pattern is removed.

  Next, a silicon oxide film is formed on the entire surface including the gate electrodes 4a and 4b, and the silicon oxide film is etched back. Thereby, sidewalls 5 are formed on the side walls of the gate electrodes 4a and 4b. Note that in this etching step, the thermal oxide film formed in each of the regions serving as the source and drain of the high voltage transistor and the region to which the wiring for applying the substrate potential is connected is removed.

Next, a region to which wiring for applying a substrate potential is connected is covered with a resist pattern (not shown), and a silicon substrate is formed using the resist pattern, element isolation films 2a and 2b, gate electrodes 4a and 4b, and sidewalls 5 as a mask. 1 is implanted with a second conductivity type impurity. As a result, two impurity regions 7 a serving as the source and drain of the low breakdown voltage transistor and two impurity regions 7 b serving as the source and drain of the high breakdown voltage transistor are formed in the silicon substrate 1. Thereafter, the resist pattern is removed.
In this way, a low breakdown voltage transistor and a high breakdown voltage transistor are formed.

  Next, the low breakdown voltage transistor and the high breakdown voltage transistor are covered with a resist pattern (not shown), and impurities of the first conductivity type are implanted into the silicon substrate 1 using the resist pattern and the element isolation films 2a and 2b as a mask. Thereby, impurity regions 8a and 8b are formed in the region to which the wiring for applying the substrate potential is connected. Thereafter, the resist pattern is removed.

  Next, an interlayer insulating film 20 having a thickness of 1 μm or less is formed on each of the low breakdown voltage transistor, the high breakdown voltage transistor, the impurity regions 8a and 8b, and the element isolation films 2a and 2b. The interlayer insulating film 20 is made of an insulating film having a low dielectric constant, for example, at least one of carbon-containing silica, fluorine-containing silica, and a silsesquioxane compound. Specifically, silicon compounds such as silica (SiOx), hydrogen silsesquioxane (HSQ) and silsesquioxane compounds such as methyl silsesquioxane (MSQ), silicon compounds such as polyethylene oxide, polypropylene Olefin resins such as polyisobutylene and polybutene, polyparaxylylene compounds such as polystyrene, polyamideimide, polyvinylphenylene, polycarbonate (PC), and polydichloroparaxylylene, and acrylics such as polymethyl methacrylate (PMMA) Resin, polyimide resin such as fluorinated polyimide, thermoplastic resin such as fluorine resin such as polytetrafluoroethylene (PTFE), benzocyclobutene resin such as benzocyclobutene (BCB), polyvinylphenol or novo It is a thermoplastic resin such as a phenol resin such as a rack resin, or a carbon compound such as amorphous carbon.

  Next, a plurality of connection holes are formed on the interlayer insulating film 20. Next, a tungsten film is formed in these connection holes and on the interlayer insulating film 20, and the tungsten film located on the interlayer insulating film 20 is polished and removed by CMP. As a result, tungsten plugs 21a, 21b, 21c, and 21d are embedded in the interlayer insulating film 20. The tungsten plugs 21a and 21c are located above the first element region 1a and are electrically connected to the impurity regions 7a and 8b of the low breakdown voltage transistor, respectively. The tungsten plugs 21b and 21d are located above the second element region 1b, and are electrically connected to the impurity region 7b and the impurity region 8b of the high breakdown voltage transistor, respectively.

  Next, an Al alloy film is formed on the interlayer insulating film 20 and the tungsten plugs 21a to 21d, and the Al alloy film is selectively removed. Thereby, Al alloy wirings 22a and 22c and Al alloy patterns 22b and 22d are formed on the interlayer insulating film 9. The Al alloy wiring 21a is located above the first element region 1a and is connected to the impurity region 7a of the low breakdown voltage transistor through the tungsten plug 21a. The Al alloy pattern 21b is located above the second element region 1b, and is connected to the impurity region 7b of the high breakdown voltage transistor through the tungsten plug 21b. The Al alloy wiring 21c is located above the first element region 1a and is connected to the impurity region 8a through the tungsten plug 21c. The Al alloy pattern 22d is located above the second element region 1b and is connected to the impurity region 8b through the tungsten plug 21d. The Al alloy patterns 22b and 22d are formed in order to electrically connect the tungsten plugs 21b and 21d to the tungsten plugs 10b and 10d described later, and the size thereof is a cross section of each tungsten plug. Slightly larger.

  Next, the interlayer insulating film 9 is formed on the interlayer insulating film 20, the Al alloy wirings 22a and 22c, and the Al alloy patterns 22b and 22d, respectively. The configuration of the interlayer insulating film 9 is the same as that of the interlayer insulating film 20. Next, tungsten plugs 10 a, 10 b, 10 c, and 10 d are embedded in the interlayer insulating film 9. The tungsten plug 10a is located above the first element region 1a and is electrically connected to the Al alloy wiring 22a. The tungsten plug 10b is located above the second element region 1b and is electrically connected to the Al alloy pattern 22b. The tungsten plug 10c is located above the first element region 1a and is electrically connected to the Al alloy wiring 22c. The tungsten plug 10d is located above the second element region 1b and is electrically connected to the Al alloy pattern 22d. The method of filling the tungsten plugs 10a to 10d is substantially the same as the method of filling the tungsten plugs 21a to 21d.

  Next, Al alloy wirings 11 a, 11 b, 11 c and 11 d are formed on the interlayer insulating film 9. The formation method of the Al alloy wirings 11a, 11b, 11c and 11d is the same as the formation method of the Al alloy wirings 22a and 22b and the Al alloy patterns 22b and 22d. The Al alloy wiring 11a is located above the first element region 1a and is electrically connected to the Al alloy wiring 22a via the tungsten plug 10a. The Al alloy wiring 11b is located above the second element region 1b and is electrically connected to the Al alloy pattern 22b via the tungsten plug 10b. The Al alloy wiring 11c is located above the first element region 1a and is electrically connected to the Al alloy wiring 22c via the tungsten plug 10c. The Al alloy wiring 11d is located above the second element region 1b and is connected to the Al alloy pattern 22d via the tungsten plug 10d.

  Next, as shown in FIG. 1B, an interlayer insulating film 12 is formed on the interlayer insulating film 9 and the Al alloy wirings 11a to 11d. The configuration of the interlayer insulating film 12 is the same as the configuration of the interlayer insulating film 20. Next, tungsten plugs 13 a, 13 b and 13 c are embedded in the interlayer insulating film 12. The tungsten plug 13a is located above the first element region 1a and is electrically connected to the Al alloy wiring 11a. The tungsten plug 13b is located above the second element region 1b and is electrically connected to the Al alloy wiring 11b. The tungsten plug 13c is located above the first element region 1a and is electrically connected to the Al alloy wiring 11c. The method for filling the tungsten plugs 13a to 13c is substantially the same as the method for filling the tungsten plugs 21a to 21d. In this step, a tungsten plug A (not shown) located on the Al alloy wiring 11d is also embedded in the interlayer insulating film 12.

  Next, Al alloy wirings 14 a and 14 c and an Al alloy pattern 14 b are formed on the interlayer insulating film 12. The Al alloy wirings 14a and 14c are located above the first element region 1a and are connected to the Al alloy wirings 11a and 11c through tungsten plugs 13a and 13c, respectively. The Al alloy pattern 14b is located above the second element region 1b and is connected to the Al alloy wiring 11b through the tungsten plug 13b. The Al alloy pattern 14b is formed to electrically connect the tungsten plug 13b to a tungsten plug 16b, which will be described later, and its size is slightly larger than the cross section of the tungsten plug 13b. The formation method of the Al alloy wirings 11a and 11c and the Al alloy pattern 14b is the same as the formation method of the Al alloy wirings 22a and 22b and the Al alloy patterns 22b and 22d. In this step, an Al alloy pattern B (not shown) that is electrically connected to the Al alloy wiring 11d through the tungsten plug A is also formed in the interlayer insulating film 12. The Al alloy pattern B is provided to connect the tungsten plug A to a tungsten plug C described later, and the configuration thereof is substantially the same as the configuration of the Al alloy pattern 14b.

  Next, as shown in FIG. 1C, an interlayer insulating film 15 is formed on the interlayer insulating film 12, the Al alloy wirings 14a and 14c, and the Al alloy pattern 14b. The configuration of the interlayer insulating film 15 is the same as the configuration of the interlayer insulating film 20. Next, tungsten plugs 16 a and 16 b are embedded in the interlayer insulating film 15. The tungsten plug 16a is located above the first element region 1a and is electrically connected to the Al alloy wiring 14a. The tungsten plug 16b is located above the second element region 1b and is electrically connected to the Al alloy pattern 14b. The method for filling the tungsten plugs 16a and 16b is substantially the same as the method for filling the tungsten plugs 21a to 21d. In this step, a tungsten plug C (not shown) located on the Al alloy pattern B is also embedded in the interlayer insulating film 15.

  Next, Al alloy wirings 17 a and 17 b are formed on the interlayer insulating film 15. The formation method of the Al alloy wirings 17a and 17b is the same as the formation method of the Al alloy wirings 22a and 22b and the Al alloy patterns 22b and 22d. The Al alloy wiring 17a is located above the first element region 1a and is connected to the Al alloy wiring 14a through the tungsten plug 16a. A part of the Al alloy wiring 17a is located above the Al alloy wiring 14c. The Al alloy wiring 14c is a wiring for applying a substrate potential, and the Al alloy wiring 17a is a wiring connected to the impurity region 7a of the low breakdown voltage transistor. As described above, the interlayer insulating film 15 is 1 μm or less and has a low dielectric constant. However, since the potential difference between the Al alloy wiring 17a and the Al alloy wiring 14c is not large, the interlayer insulating film 15 may cause dielectric breakdown. Absent.

  On the other hand, the Al alloy wiring 17b is located above the second element region 1b, and the impurities of the high breakdown voltage transistor are passed through the tungsten plug 16b, the Al alloy pattern 14b, the tungsten plug 10b, the Al alloy pattern 22b, and the tungsten plug 21b. It is connected to the region 7b. A part of the Al alloy wiring 17b is located above the Al alloy wiring 11d. Since the Al alloy wiring 11d is a wiring that gives a substrate potential, the potential difference between the Al alloy wiring 17b and the Al alloy wiring 11d is large, and when the interlayer insulating film 12 is a single layer or the interlayer insulating film 15 is a single layer, The interlayer insulating film may cause dielectric breakdown. However, since there are two insulating films, the interlayer insulating films 15 and 12, between the Al alloy wiring 17b and the Al alloy wiring 11d, the interlayer insulating films 15 and 12 are low dielectric constant insulating films. And even if each thickness is 1 micrometer or less, it is suppressed that a dielectric breakdown arises between Al alloy wiring 17b and Al alloy wiring 11d.

  On the interlayer insulating film 15, an Al alloy wiring D (not shown) located on the tungsten plug C is also formed. A part of the Al alloy wiring D is located above the Al alloy wiring 11b. However, the Al alloy wiring D is located between the Al alloy wiring D and the Al alloy wiring 11b by the same action as that of the Al alloy wiring 17b and the Al alloy wiring 11d. Thus, the occurrence of dielectric breakdown is suppressed.

  As described above, according to the embodiment of the present invention, above the first element region 1a where the low breakdown voltage transistor is formed, each wiring layer is electrically connected to the wiring and the substrate electrically connected to the low breakdown voltage transistor. Both wirings to be formed are formed, and miniaturization of the low breakdown voltage transistor can be achieved. On the other hand, wiring is formed every other layer above the second element region 1a where the high voltage transistor is formed. For this reason, even if the interlayer insulating film has a low dielectric constant and becomes thin, it is possible to suppress dielectric breakdown between the wiring layers located above the second element region 1a.

  Each drawing in FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The manufacturing method of each component is the same as that of the first embodiment.

  First, as shown in FIG. 2A, a low breakdown voltage transistor and a high breakdown voltage transistor having the same configuration as in the first embodiment are formed, and further, an interlayer insulating film 20, tungsten plugs 21a, 21b, 21c, 21e, Al Alloy wirings 22a, 22c, Al alloy patterns 22b, 22e, interlayer insulating film 9, and tungsten plugs 10a, 10b, 10c, 10e are formed. The tungsten plug 21e is embedded in the interlayer insulating film 20 located in the second element region 1b, and is electrically connected to the gate electrode 4b of the high voltage transistor. The Al alloy pattern 22e is located on the interlayer insulating film 20 in the second element region 1b and is electrically connected to the tungsten plug 21e. The tungsten plug 10e is embedded in the interlayer insulating film 9, and is electrically connected to the Al alloy pattern 22e. Next, Al alloy wirings 11 a, 11 b and 11 c are formed on the interlayer insulating film 9. In the present embodiment, the Al alloy wiring 11a electrically connects the tungsten plugs 10a and 10e to each other through a portion not shown.

  Next, as shown in FIG. 2B, an interlayer insulating film 12, tungsten plugs 13a, 13b, 13c, Al alloy wirings 14a, 14c, and an Al alloy pattern 14b are formed.

  Next, as shown in FIG. 2C, an interlayer insulating film 15, tungsten plugs 16a and 16b, and Al alloy wirings 17a and 17b are formed. A part of the Al alloy wiring 17b is located above the Al alloy wiring 11a, but since the interlayer insulating films 15 and 12 are located between them, dielectric breakdown occurs between these wirings. This can be suppressed.

Further, the tungsten plug A, the Al alloy pattern B, the tungsten plug C, and the Al alloy wiring D described in the first embodiment are formed by the above-described steps.
As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 3 is a cross-sectional view for explaining a semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device manufactured according to the first embodiment except that the tungsten plug 21b is connected to the gate electrode 4b of the high breakdown voltage transistor. The method for manufacturing the semiconductor device is the same as that in the first embodiment.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  Each drawing in FIG. 4 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The manufacturing method of each component is the same as that of the first embodiment.

  As shown in FIG. 4A, a low breakdown voltage transistor and a high breakdown voltage transistor having the same configuration as in the first embodiment are formed, and an interlayer insulating film 20 is further formed. Next, tungsten plugs 21 a, 21 b, 21 c, 21 f are formed in the interlayer insulating film 20. The tungsten plug 21f is electrically connected to the gate electrode 4b of the high voltage transistor. Next, Al alloy wirings 22 a and 22 c and Al alloy patterns 22 b and 22 f are formed on the interlayer insulating film 20. The Al alloy pattern 22f is formed to electrically connect the tungsten plug 21f to a tungsten plug 10f described later, and the size thereof is slightly larger than the cross section of each tungsten plug.

  Next, as shown in FIG. 4B, an interlayer insulating film 9, tungsten plugs 10a to 10c and 10f, and Al alloy wirings 11a to 11c and 11f are formed. The Al alloy wiring 11b is electrically connected to the tungsten plug 10b, and a portion not shown is located above the gate electrode 4b or the gate wiring (not shown). However, since the interlayer insulating films 20 and 9 are located between the Al alloy wiring 10b and the gate electrode 4b, it is possible to suppress dielectric breakdown between these wirings. The Al alloy wiring 11f is electrically connected to the tungsten plug 10f.

  As described above, also in this embodiment, wiring is formed every other layer above the second element region 1a where the high breakdown voltage transistor is formed. For this reason, even when the difference between the voltage applied to the gate electrode 4b and the voltage applied to the impurity region 7b is large, even if the interlayer insulating film becomes low dielectric and thin, the wiring layers positioned above the second element region 1a It is possible to suppress dielectric breakdown between the two.

  In this embodiment, the Al alloy pattern 22b may be electrically connected to the tungsten plug 21d shown in the first embodiment instead of the tungsten plug 21b. In this case, when the difference between the voltage applied to the gate electrode 4b and the substrate potential is large, the dielectric breakdown occurs between the wiring layers located above the second element region 1a even if the interlayer insulating film is made low dielectric and thin. Can be suppressed.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in each of the embodiments described above, Al alloy wiring is used as the wiring, but wiring (for example, Cu wiring) embedded in the interlayer insulating film by the damascene method may be used. The configuration of the high breakdown voltage transistor is not limited to the above configuration, and may be the same configuration as the low breakdown voltage transistor.

Each drawing is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Each drawing is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Sectional drawing explaining the structure of the semiconductor device which concerns on 3rd Embodiment. Each drawing is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. Sectional drawing for demonstrating the structure of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,100 ... Silicon substrate, 1a, 100a ... 1st element area | region, 1b, 100b ... 2nd element area | region, 2a, 2b ... Element isolation film, 3a, 3b ... Gate insulating film, 4a, 4b ... Gate electrode, 5 ... Side walls, 6a, 6b ... low concentration impurity regions, 7a, 7b, 8a, 8b, 107a, 107b, 108a, 108b ... impurity regions, 9, 12, 15, 20, 109, 112 ... interlayer insulation films, 10a-10f , 13a to 13e, 16a, 16b, 21a to 21e ... tungsten plug, 11a to 11d, 14a, 14c to 14e, 17a, 17b, 22a, 22c, 111a to 111d, 114a to 114d ... Al alloy wiring, 11e, 11f, 14b, 22b, 22d, 22e ... Al alloy pattern

Claims (7)

A first interlayer insulating film formed above the first element region and the second element region of the semiconductor substrate;
A first wiring layer formed on the first interlayer insulating film;
A second interlayer insulating film formed on the first interlayer insulating film and the first wiring layer;
A second wiring layer formed on the second interlayer insulating film;
A third interlayer insulating film formed on the second interlayer insulating film and the second wiring layer;
A third wiring layer formed on the third interlayer insulating film;
Comprising
The first wiring layer is located above the first element region, the second wiring located above the second element region, and the second element region. A third wiring having a potential different from that of the second wiring;
The second wiring layer is located above the first element region and is electrically connected to the first wiring and a part of the third wiring. Comprising a conductive pattern for connection electrically connected to the third wiring;
The third wiring layer is located above the first element region and electrically connected to the fourth wiring, and is located above the second element region and the connection A sixth wiring electrically connected to the third wiring through the conductive pattern for electrical use;
The second wiring layer is a semiconductor device having no wiring above the second element region.   The semiconductor device according to claim 1, wherein a part of the sixth wiring is located above the second wiring.   3. The semiconductor device according to claim 1, wherein the second interlayer insulating film has a thickness that causes dielectric breakdown when a potential difference between an upper surface and a lower surface is greater than or equal to a potential difference between the second wiring and the third wiring.   The semiconductor device according to claim 1, wherein a potential difference between the third wiring and the second wiring is larger than a potential difference between the first wiring and the substrate potential. A first transistor formed on the semiconductor substrate located in the first element region;
A second transistor formed on the semiconductor substrate located in the second element region and having a higher operating voltage than the first transistor;
Comprising
The second wiring electrically connects the source or drain of the first transistor and the gate electrode of the second transistor,
5. The semiconductor device according to claim 1, wherein the third wiring is connected to a source or a drain of the second transistor.   The first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film are made of at least one of carbon-containing silica, fluorine-containing silica, and a silsesquioxane compound. The semiconductor device as described in any one of -5. Forming a first interlayer insulating film above the first element region and the second element region of the semiconductor substrate;
Forming a first wiring layer on the first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring layer;
Forming a second wiring layer on the second interlayer insulating film;
Forming a third interlayer insulating film on the second interlayer insulating film and the second wiring layer;
Forming a third wiring layer on the third interlayer insulating film;
Comprising
In the step of forming the first wiring layer, a first wiring located above the first element region, a second wiring located above the second element region, and a position above the second element region And forming a third wiring having a potential different from that of the second wiring,
In the step of forming the second wiring layer, a fourth wiring that is located above the first element region and is electrically connected to the first wiring is formed, and the fourth wiring layer is formed above the second element region and A conductive pattern for connection that is located above a part of the third wiring and is electrically connected to the third wiring is formed, and a wiring that is located above the second element region is not formed. ,
In the step of forming the third wiring layer, a fifth wiring located above the first element region and electrically connected to the fourth wiring, and located above the second element region. A method of manufacturing a semiconductor device, comprising: forming a sixth wiring connected to the third wiring via the connection conductive pattern.

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