JP4996268B2 - Printed circuit board inspection equipment - Google Patents

Description

  The present invention inspects whether the state of a printed circuit board (which may be referred to as a “bare substrate”) before mounting an electronic component is in a normal pattern state as designed, that is, there is no open or short circuit. The printed circuit board inspection apparatus provides a new method for the structure itself of the apparatus main body and the data processing / determination function for determining the quality of the measurement result as a checker. Hereinafter, this checker is referred to as a BBC (Bare board checker).

  There are currently four main types of BBC on the market. The first method A is a method using a so-called “pin jig”, in which all the probe pins corresponding to the respective measurement points on the substrate are positioned so as to be in contact with each other. In this method, an attachment jig installed in the sword mountain state is prepared for each measurement board. Or, instead of directly probing the measurement point of the board to be inspected, a grid conversion board (sometimes called a "conversion adapter") and an anisotropic conductive sheet are used as a pair instead of a contact probe pin. However, there is also a method of detecting the measurement point part indirectly. The method A is a method in which the measurement points are contacted and measured collectively including both of them directly or indirectly. This method has the disadvantage that the jig itself is often expensive, but has the advantage that the measurement time is very short. Also, with this method, it is necessary to implant the probe pins finely in order to deal with the fine substrates that have been put into practical use recently, but it is difficult to implant the probe pins finely enough to accommodate fine substrates. It also has the disadvantage of becoming. However, in this regard, various ideas and inventions are being made, and improvements and improvements have been made.

  Next, as the B method, there is a flying prober method (FP method). This is a method in which a probe, which is a contact, contacts a measurement point while detecting movement on the plane of the measurement substrate while repeating movement in the XY direction. This method has the greatest merit that it does not require a jig or the like for each measurement substrate, but has the disadvantage that the measurement time becomes long. However, it is very effective for testing prototypes and high-mix low-volume products, and the market share is growing.

  The measurement methods of A and B are based on the principle of “resistance measurement between two measurement points or on / off measurement” and are repeated for all necessary measurement points. In this method, a scanner or a flying probe pin is used to select a necessary two-point node from the following (hereinafter referred to as “node”). FIG. 23 shows the correlation between the functional units when the A method is used, and FIG. 24 shows the B method when the two-point resistance measurement method is adopted as the electrical measurement method. In FIG. 23, reference numeral 1 is a printed circuit board to be inspected, 2 is a probe pin for sucking up a measurement point of the inspected printed circuit board 1, 3 is a cable, 4 is a connector B, 5 is a connector A, and 6 is a cable. 7 is a scanner, 8 is a resistance measuring device, and 9 is a computer. 24, reference numeral 1 denotes a printed circuit board to be inspected, 11 denotes a flying probe, 10 denotes positioning means for the flying probe 11, 8 denotes a resistance value measuring device, and 9 denotes a computer.

  As shown in FIGS. 23 and 24, the resistance measuring instrument 8 plays an important role in the measurement methods A and B described above. According to the inspection apparatus shown in FIG. 23, the resistance value measuring device 8 is versatile, but the cables for connecting the resistance value measuring device 8 and the scanner 7 and the connectors 4 and 5 are necessary. It has problems such as high costs and reduced connection reliability due to connectors.

  In the FP method shown in FIG. 24, in order to speed up the measurement, a capacitance method has also been developed as a method to replace the two-point resistance method. According to this test method, a resistance value measuring instrument is not necessary, but a procedure of sequentially measuring capacitance at necessary measurement points as instructed by the controller. In the capacitance method, open / short test of the electric circuit is possible by contact measurement of only one point on the same electric circuit. In addition, there are devices having a plurality of pairs of probe pins as means for reducing the measurement time in this capacitance method, but the user's satisfaction with respect to the measurement time is still insufficient.

  As the third C method, there is an appearance inspection method AOI (= Automated Optical Inspection) by image processing. (Alternatively, there is an AVI system.) This system is a method for determining pass / fail of open / short by converting a pattern generated on a substrate into image data and determining processing. This method belongs to the kind of non-contact side fixed method, but no jig or the like is required for each substrate, and therefore the running cost is almost unnecessary. There is also an advantage that the measurement time is short. On the other hand, in the case of pattern connection with an inner layer such as a through hole, an inner via, or a build-up substrate, there is a drawback that the inspection cannot be performed. Therefore, the field actually used is often used for inspection at the interior sheet substrate stage before a plurality of substrates are stacked.

  As the other method D, the technology has been further advanced recently, and a non-contact method different from the C method has been developed. In this method, an electrode serving as an antenna corresponding to the pattern of the measurement circuit is formed, and an electromagnetic field or electrostatic field is formed between the patterns, measurement is performed using an electromagnetic sensor or electrostatic sensor, and the measurement result is judged. It is. The advantage of this method is that it can handle fine patterns. Since it is a non-contact method, it has the merit that the measurement point of the substrate to be measured is not wrinkled and the measurement time is short as in the AOI method. However, there is a drawback that the jig cost is very expensive and that a substrate with many branch patterns cannot be checked.

  As described above, there are various methods in the printed circuit board checker (BBC). However, if the present invention is roughly classified, the measurement point contact method close to A is not a kind of non-contact C and D. It is similar to However, as described above, the conventional method A or B is based on the two-point resistance measurement method, but the present invention introduces a measurement algorithm based on a completely different idea. Briefly speaking, two types of measurement / judgment algorithms are introduced into the electric system tester unit, and the measurement is made possible by a configuration of only a commercially available FPGA (Field Programmable Gate Array). In addition, this system can simplify the electrical measurement unit (tester substrate), and as a result, it is possible to omit the wiring connection processing to each functional unit, which was indispensable in the conventional method A. In other words, a great advantage is created that the tester board can be installed directly above, directly under or near the printed circuit board to be inspected, resulting in smaller equipment, lower equipment cost, improved reliability, and shorter measurement time. , Etc. can be improved.

  As described above, the present invention does not use the point-to-point resistance measurement logic. To outline the measurement theory, two types of measurement theory are introduced. The first method is to check which node (measurement point) the signal given to each measurement node has reached. By constructing an open drain drive circuit, one node is grounded and all other nodes are short-circuited. In this method, the nodes are driven to a weak VCC (power supply voltage) and the voltages of all the nodes are examined. In this measurement, it is determined that the node with voltage 0 is connected to the grounded node and the node with voltage 1 is not connected. By repeating this measurement method by changing the node that is shorted to ground, all nodes are connected. It is a way to know nothing. Only the continuity test is performed. However, when the electrical circuit is short-circuited, it is found that there is a difference from the master data in the continuity confirmation state, and as a result, the existence of the short-circuit can be clarified.

  The second method is applied when the first method is not applicable, and is effective particularly in measuring a semiconductor assembly interposer substrate (IP substrate) by assembling a complementary drive circuit. There are many things. This is the introduction of a measurement algorithm when there is a circuit in which one circuit is multi-branched (including the case where it exists artificially for the convenience of measurement). In the circuit theory according to the first method, when one node is short-circuited to the ground, current flows from the other node branched to the open-drain drive circuit that is short-circuited through the pull-up resistor. There is no problem with commercially available ICs that are inflow from 100 node points at all, but if it exceeds that, the maximum allowable current of the open drain drive circuit will be exceeded, and detection using this circuit theory will occur. The determination of the node voltage 1 or 0 causes uncertainty in measurement. In other words, in the first method, the node to be switched and the insulated node are in a high impedance state, the voltage is indefinite, and the measurement result is uncertain when determining the node voltage level. Therefore, we decided to introduce the circuit theory by the second method as a countermeasure in that case. Instead of giving a constant voltage (current) to a node to be switched, if a high and low voltage of a constant time-series pattern is given, the same voltage pattern is applied to the node that is conductive with the switch node, and the pattern is correlated with the isolated node. Since no voltage pattern is detected, this is a measurement method using the determination algorithm. Details of the above two measurement circuit algorithms will be described later.

  There is no method similar to the present invention as a conventional electrical system measurement / processing method of this type of apparatus. If it dares to mention, it can be said that the flow in the data processing system of FPGA used for this invention is close to the technique of patent document 1. FIG. However, the technology described in Patent Document 1 utilizes the functions of general electrical measurement element technology and CPU technology, and as in the present invention, the entire function of pass / fail judgment of measurement results is fully controlled by an FPGA device ( It can be said that there is a big difference in that it is not imposed only on a dedicated ASIC).

JP-A-10-170585

  As described above, there are several types of BBC roughly classified as described above. However, the present invention is premised on a probe pin jig or a measurement point batch contact method that performs the same function. This collective contact jig method has the advantage of requiring a short measurement time, so it is still widely used for mass-produced products, but the inspection equipment in the market is expensive and very large. Is. Also, jigs that need to be prepared for each substrate to be measured are very expensive. The present invention focuses on solving these problems of the prior art, that is, reducing the size and size of the apparatus, reducing the cost, and reducing the cost of the jig as a running cost.

The present invention is based on a new method that does not have a conventional test measurement / determination theory that is the basis of the idea , and the tester board can be reduced in size and simplified. It was positioned directly below and the size of the device could be reduced. The main contents of specific improvements when the present invention is compared with the conventional apparatus are as follows.

  (1) In the conventional collective contact jig method, the measurement data (measurement signal) from the measurement point is transmitted to the electrical scanner via the probe pin (including other methods). Was necessary. However, it is not rare that the number of measurement points is several thousand points or 10,000 points or more. The measurement point and the electrical system tester or scanner are usually separated from each other in distance, and the connection / bundling with the wire or lead wire connecting them is considerably large. Also, when manufacturing a device, this wiring or lead wire connection is generally made via a connector, but the work man-hours become enormous, causing the device to become larger, expensive, or less reliable. It has become. The present invention makes it possible to reduce the size and size of the tester substrate and the test apparatus and provide them to the user at low cost by making full use of the measurement theory and the commercially available IC chip which are completely different from the two-point resistance measurement method.

  (2) In terms of miniaturization of the device, particularly when the inspection is limited to the inspection of the semiconductor IP substrate, the conventional device must be tested by a considerably large device even when the IP substrate is in a strip state. It was normal to have to. In that respect, according to the present invention, a very compact desktop type inspection apparatus can be realized.

(3) The jig used for the conventional inspection apparatus was prepared according to the specifications for each measurement target IP board, but it was very expensive. In the meaning of the jig, although there is a need to manufacture a conversion board for each different type of measurement board, the main body of the apparatus is a universal machine in a sense (since the measurement part is simplified, the maximum measurement point is Therefore, the conversion substrate can be dealt with with a very inexpensive one. In this regard, not only in view of saving jig manufacturing cost, the difficulty of the fixture build, Ru can also contribute to the release from conventional problems had to the partial division of the jig. Since the measurement by dividing the jig requires an extra measurement time, the present invention can contribute to shortening the measurement time.

The present invention has a tester circuit board that has all inspection lands of a printed circuit board to be inspected and test terminals connected thereto and is positioned above or below the inspected printed circuit board,
A measurement point conversion jig that is interposed between the printed circuit board to be inspected and the tester circuit board and converts between the inspection land and the test terminal and converts the measurement point;
A tester circuit having a test terminal and supplying an electric signal only to one inspection land of all inspection lands by this test terminal to detect the presence or absence of an electric signal in another inspection land;
The tester circuit repeats the operation of detecting the presence or absence of electrical signals in other inspection lands while switching the inspection lands of the printed circuit board to which electrical signals are applied, over all inspection lands, and the continuity between all inspection lands is established. The main feature is that the printed circuit board pattern is cut and a short circuit is inspected by detection.

  The present invention is based on the idea that the measurement system is greatly simplified by developing a completely different measurement theory from the conventional two-point resistance measurement method. Specifically, the tester circuit has a simple configuration in which a commercially available FPGA-IC or a similar chip is arranged on the substrate, and the above two measurement theories are used so that the test can be completed within the range of the tester substrate. It is a thing. In other words, the measurement / judgment function by the electric system related to the open / short of the inspection apparatus as the BBC can be processed only by the IC board on which the FPGA is mounted. In the conventional apparatus, a scanner, a resistance value measuring device, a cable, a multi-terminal connector, a personal computer, etc. are necessary. However, since the apparatus according to the present invention can be made unnecessary, the apparatus itself is very simple. It can be a hardware structure with electrical and mechanical systems.

According to the present invention, the following effects can be obtained.
(1) Since the tester circuit can be configured using a chip such as an FPGA, the apparatus can be integrated in a very compact and smart manner. Conventional inspection methods consist of many devices with different functions, such as scanners, resistance measuring instruments, and personal computers (hereinafter referred to as “PCs”). Wiring, connectors, etc. are required to connect them together. However, according to the present invention, it can be constituted by a chip such as an FPGA instead of a scanner, a resistance measuring instrument, a PC, etc., and an inexpensive inspection apparatus can be obtained.
(2) Since it is not necessary to use many devices having different functions, the reliability is improved and the maintainability is improved. In addition, poor wiring connection that tends to occur over time takes a lot of time and cost to repair, but according to the present invention, it is freed from such problems.
(3) If the board to be measured becomes large and the number of measurement points increases, it is possible to construct a structure such as an FPGA or other chip that can be additionally added to the board, and the measurement apparatus will be greatly modified. It is possible to add more chips with a single touch.
(4) The strip-shaped IP substrate inspection apparatus may be very small and can be a so-called “desktop machine”, which has the effect of reducing the installation area of the apparatus.
(5) The production of the conversion board is simplified, and the cost can be reduced. Thereby, universalization of the inspection apparatus can be achieved.

Hereinafter, a printed circuit board inspection apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a conceptual explanatory diagram of the method of the present invention, and FIG. 2 is a diagram illustrating the connection relationship between a printed circuit board to be measured and a tester unit in more detail. 1 and 2, reference numeral 1 denotes a substrate to be measured. As shown in FIG. 2, the tester circuit boards 24 and 34 which are measurement units are mounted with an FPGA 26, and the measurement point 27 of the printed circuit board 1 to be measured includes the conversion board 22 and the two anisotropic conductive sheets 21 and 23. The tester circuit board 24 is connected to the tester circuit board 24. In the embodiment shown in FIG. 2, a plurality of FPGAs 26 are mounted on the tester circuit board 24, but only one FPGA 26 may be mounted. As shown in FIG. 1, tester circuit boards 24 and 34 are arranged immediately above and below the printed circuit board 1 to be measured, and the tester circuit boards 24 and 34 function as a circuit network analyzer to have a measurement determination function.

  The conversion boards 22 and 32 convert the measurement point position of the printed circuit board 1 to be converted into a position corresponding to the purpose. The purpose of making the conversion boards 22 and 32 exist is to ensure the versatility of the tester unit for the measurement of the different board and the reason for the design when mounting the FPGA 26, corresponding to each different board The converted conversion board is used properly. This method is more advantageous in terms of total running cost. As a result, most wiring can be made unnecessary by this system. Even if a PC or the like is provided for various information display applications, the connection cable may be the minimum necessary. In FIG. 2, only the upper surface side of the printed circuit board 1 to be measured is shown, but the rear surface side has the same structure.

  In the present invention, the grid pattern of the tester circuit board 24 is passed through the converted grid positions 28 of the conversion boards 22 and 32 through all the measurement points 27 of the printed circuit board 1 to be measured without using a personal computer, a scanner, a resistance measuring instrument, or the like. The printed circuit board 1 to be measured is inspected by guiding it to the position 29 and corresponding the part to the measurement node of the commercially available FPPGA 26 and operating the measurement logic circuit. However, the measurement node (measurement terminal) assigned to the measurement / determination function of the FPGA 26 mounted on the tester circuit board 24 is configured to have a structure having more than the required number of measurement nodes expected in advance, and the printed circuit board to be measured Regardless of the number of inspection nodes of one, all are routinely measured and processed. In that regard, in the conventional method, it is normal to operate the measurement location and measurement timing according to the printed circuit board to be measured according to the program (role of the scanner) according to instructions from the controller (= computer). It is a difference. For this reason, the conventional method takes a little measurement time. However, in the above-described method of the present invention, the measurement test itself ignores the measurement time because the measurement node is routinely processed according to an algorithm. It can be done in as short a time as possible. The measurement operation procedure by the FPGA 26 and the function and role of each unit will be described later.

  In FIG. 2, the measurement point 27 of the printed circuit board 1 to be measured is sucked up by the grid conversion board 22 through the anisotropic conductive sheet 21. The position of the measurement point on the lower surface side of the grid conversion substrate 22 remains the positional relationship of the printed circuit board 1 to be measured, but is converted (= moved) to the grid lattice position on the upper surface side of the conversion substrate 22. The converted lattice pitch is arbitrary. When the inspection apparatus is not a target for a fine substrate, a coarse pitch specification is used, and when the inspection device is a target for a fine substrate, a fine pitch specification is used. The converted measurement point is further sucked up by the second anisotropic conductive sheet 23 and guided to the tester circuit board 24.

  The pattern on the back side of the tester substrate 24 on which the FPGA-IC is not mounted, that is, the surface facing the conversion substrate 22 is the same as the pattern after conversion of the conversion substrate 22 and the pitch of the lattice is the same. Then, it is re-converted into the pattern positional relationship of the detection terminals allocated when the FPGA 26 is mounted. That is, the pattern is routed in the inner layer of the tester substrate 24 at the node position allocated for the measurement object so that the FPGA 26 can be mounted. In order to be able to mount the FPGA 26 on the tester board 24, it is necessary to adapt to the model number of the FPGA-IC to be adopted and the measurement target node interval. In order to obtain an effective connection pattern, the pattern positional relationship is repeated again. Conversion may be necessary.

  Examples of the grid pitch of the tester circuit board 24 include 2.54 mm, 2 mm, and 1.5 mm. The grid pitch tends to become even finer and may become about 1 mm pitch in the near future. The present invention is not limited by the grid pitch of the tester circuit board 24, that is, the grid pitch is arbitrary. The pitch is re-converted by the tester substrate 24 and patterned by the tester substrate 24 so that the FPGA 26 can be mounted. In this case, the FPGAs 26 can be two-dimensionally mounted in a two-dimensional manner with an appropriate interval. As a result, the tester substrate 24 (including the FPGA 26) can be shared with different types of measurement substrates, and the running cost borne by the user of the inspection apparatus can be reduced. The initial cost for measuring the dissimilar substrate is only the cost for creating the grid conversion substrate 22.

  The structure shown in FIG. 2 is an example as one implementation method, and structures other than this structure are also conceivable. For example, in FIG. 2, anisotropic conductive sheets 21 and 23 are used. Instead, for example, the converted point 28 of the grid conversion board 22 is connected to a tester via a spring-operated probe pin. It is also possible to guide to the back surface of the circuit board 24. In this case, it is not necessary to use a wire or a lead wire. The technical contents to be described later are based on the configuration of the embodiment shown in FIG. 4 shows only the upper surface side of the printed circuit board 1 to be measured, the back surface side has the same structure.

  In the example shown in FIG. 2, the FPGA 26 is mounted on the tester circuit board 24. Instead of the FPGA 26, an element having a function similar to the FPGA 26, for example, a chip such as an ASIC may be used. By adopting a chip such as an FPGA or ASIC as in the present invention, a compact printed circuit board inspection apparatus can be realized. As specific means for realizing this, there are two kinds of means described below depending on the method of using the FPGA, which makes it possible to apply a commercially available FPGA device. Since it is possible to design all logic circuits in the entire measurement system within the FPGA, it is possible to reduce the area of the required tester circuit board even on the measurement circuit mounting surface and to make the apparatus compact.

  The first of the two ways of using the FPGA is as follows, and FIG. 4 shows an outline thereof. In FIG. 4, a block denoted by reference numeral 35 indicates a circuit built in the test terminal of the FPGA. The circuit 35 includes a pull-up resistor 36, a switch 37 that is grounded to ground, and a voltage that is equal to or higher than a threshold value. A detection circuit 38 for outputting a “1” or “0” signal is provided. Reference numeral 39 denotes a circuit pattern of the printed circuit board to be inspected, and 40 denotes a contact point between the inspection node of the printed circuit board to be inspected and the inspection terminal of the FPGA. As shown in FIG. 4, an open drain drive circuit including a pull-up resistor 36 to a power supply voltage and a switch 37 to ground is used as a method of supplying an electrical signal to the FPGA when measuring an inspection land of a printed circuit board to be inspected. Use logically. In this method, an open / short circuit is detected by the detection circuit 38 that is only above and below the threshold voltage. This method is characterized in that the inspection time is extremely short, but the total number of measurement points determined to be the same electric circuit is limited. This is because there is a limit to the maximum allowable current flowing into the open drain drive circuit via the pull-up resistor 36. In the case of a circuit with many branches, the branched circuit is also regarded as the same electric circuit, and a current proportional to the number of branches flows into the drive circuit.

The second method was considered as a way of using the FPGA. The example shown in FIG. 15, which will be described in detail later, is a method of a complementary drive circuit having a disable function and switching to a power source or a ground. In this method, no voltage is applied by a pull-up resistor. For this reason, the potential of the land that is not conductive is not fixed and is undefined, and land conduction cannot be determined by detecting the threshold value above and below. Therefore, as a solution to this, there is a method in which a time series pattern of voltage is given and it is determined whether or not it is a conductive land with a degree of coincidence with a logical time series pattern. According to this method, although it takes some measurement time, it is an allowable range. The restriction on the number of identical conduction groups can be greatly relaxed.
In the present invention, an optimal inspection system can be realized by arbitrarily combining the first method and the second method.

  As an example of applying the second method, there is an IC interposer substrate (hereinafter referred to as “IP substrate”). When inspecting an IP substrate, the silicon wafer bonding surface is characterized in that the measurement jig relationship can be simplified in most cases by short-circuiting the entire surface during measurement. In the continuity test, most of the measurement points on the surface wafer bonding side can be measured by regarding the majority as the same electric circuit. That is, the test can be performed in a state where the conductor is short-circuited. However, in the short detection test, it is necessary not to short-circuit the upper surface but to be in an isolated independent point state. The measurement schematic is shown in FIG.

In the example shown in FIG. 3, the tester unit 44 corresponds to the tester circuit board 24 on which the FPGA 26 in the example of FIG. 2 is mounted, and the tester unit 44 is opposed only to the back side of the IP board 41 that is the board to be measured. In most cases, measurement is possible. A conversion substrate 42 that also serves as a jig substrate is placed on the upper surface of the tester unit 44, an anisotropic conductive sheet 43 is placed on the conversion substrate 42, and an IP substrate 41 that is a substrate to be inspected is placed thereon. It has been. The conversion board 42 corresponds to the conversion board 22 in the example shown in FIG. The anisotropic conductive sheet 43 is a sheet having a property of conducting only in the thickness direction, and transmits the circuit pattern appearing on the lower surface of the IP substrate 41 to the conversion substrate 42 as it is.
During the continuity test, the simultaneous conduction short-circuit plate 45 moves to the upper surface side of the IP substrate 41 that is the substrate to be inspected, and the IP substrate 41 is directed toward the tester unit 44 with the anisotropic conductive sheet 43 and the conversion substrate 42 interposed therebetween. To press. The simultaneous conduction short-circuit plate 45 is used to make a plurality of measurement nodes into one node. Thus, the conduction between the upper and lower surfaces of the inspected substrate 41 can be confirmed.

  In the short detection test, instead of the simultaneous conduction short-circuit plate 45, the insulator pressing plate 46 presses the measured IP substrate 41 toward the tester section 44 with the anisotropic conductive sheet 43 and the conversion substrate 42 interposed therebetween. To the state. The tester unit 44 can perform a short detection test by measuring only from the back side of the IP substrate 41. In the case of an IP board, in most cases, it is a general characteristic that the measurement points on the upper and lower surfaces are connected. However, there are exceptional cases where the patterns on the upper surface are connected. In that case, it is treated as a specific point. Specifically, the insulator pressing plate 46 is devised. Reference numeral 47 indicates a probe pin provided on the insulator pressing plate 46 in order to pick up the specific point. This probe pin 47 is composed of a limited number of conductive confirmation measuring pins, and it is only necessary to conduct a continuity test only on the limited point portion during a short discovery test. The basic measurement method is the same as when the probe pin 47 is not present.

  The inspection method according to the present invention is a method for examining which other measurement point a signal applied to one place is conducting. The measurement / judgment procedure of the tester includes two kinds of measurement points at any one place. In this method, the voltages at all measurement points are examined by applying a power supply voltage or connecting to the ground by the driving switching method. And this test method can only confirm the continuity test, but if the opposite way of thinking is used, even if there is a short, if the continuity points are grouped together, the regular pattern and the grouping result Since there is a difference, it is determined that a short circuit exists. It goes without saying that a difference also occurs when a disconnection exists. The above two inspection methods will be described more specifically.

  The main function of the tester board is to generate a “net list” of the printed circuit board to be inspected. In the present invention, this is the same as the test itself. Finally, the net list generated for the printed circuit board to be inspected is compared with that of a normal product. Alternatively, the net list of normal products can be obtained from CAD data in advance. If the comparison matches, it passes, and if it does not match, it fails. FIG. 5 is a flowchart conceptually showing an example of netlist generation by the first method, and FIG. 6 is a structural diagram of a group memory (hereinafter referred to as “GPM”) for storing the netlist.

First, an example of netlist generation shown in FIG. 5 will be described. S1, S2,... Represent steps.
S1: All nodes are turned off, and a voltage is applied via a pull-up resistor (reference numeral 36 in FIG. 4).
S2: Determine a node to turn on only one switch. The node with the lowest number among the nodes not belonging to any group is determined.
S3: The node switch is turned on. There is only a slight time lag until the voltage at all nodes stabilizes.
S4: Read all voltages with 1/2 of the power supply voltage as a threshold, 0 for 1/2 or less and 1 for 1/2 or more.
S5: If the voltage is 0, the node belongs to the same group as the switched-on node, so the group number and flag = 1 are written into the GPM.
S6: Returning to S2, the node to be switched on next is determined. The GPM is read out and the youngest address with flag = 0 is set as the node to be switched on.
S7: End if flag of all addresses of GPM = 1.

Next, an example of the GPM structure shown in FIG. 6 will be described.
As a premise of the contents described below, the number of measurement nodes was assumed to be 128. In fact, there are cases where there are several tens of times that. A countermeasure for this will be described separately.
-Nodes with continuity are collectively numbered as one group, and group numbers are assigned while checking the continuity state of all nodes.
The memory address is a node number, and the data is a registered flag 1 bit and a group number.
For example, if there are 128 check nodes, the address is 0 to 127, and the group number is the largest when all the nodes are independent isolated patterns, and is 7 bits from 0 to 127, so the data has the flag 1 bit. Including 8 bits.
For example, if the # 3 node, the # 4 node, and the # 100 node are conductive and the group number is 2, the data of the addresses 3, 4, and 100 is 130 including the flag 1 bit.

  The concept of a group is introduced with respect to the electric circuit formed by the pattern, and this will be described. An electric circuit is a simple circuit between two points, has a branch, or has the same circuit with a complicated ground short-circuit pattern. Similarly, the power input unit (VCC unit) has various branches. The concept of group at this time considers the connected electric circuit as one group.

7 and 8 show an example of the internal structure and operation flow of the FPGA when generating a netlist for the first method. Each block shown in FIG. 7 will be described.
ODR [open drain with pull-up register]: 128 input / output terminals of an FPGA, which are connected to an inspection node of a printed circuit board as an inspection terminal of a tester, and are applied to a voltage applied or switched on to GND A driver is connected to the VSC described below.
VSC [Voltage sense circuit]: An input circuit having a voltage detection function, which is connected to the ODR and outputs 0 when the threshold is greater than or equal to 1 and less than 0.
GPM [group memory]: A memory that stores node numbers as addresses and group numbers as data. Since the number of nodes is 128, the node number is 0 to 127 with 7 bits. The data is 8 bits, and the most significant 1 bit is 1 if the node has already been registered in the group, 0 if it is not registered, and the following 7 bits indicate the group number of 0 to 127.
NC [node counter]: a 7-bit counter indicating a node number.
GC [group counter]: A 7-bit counter indicating a group number.
SAR [switch address register]: a 7-bit register that receives and holds the number of the ODR to be switched on from the NC.
dec1 [decoder1]: a decoder that detects that the SAR indicates the last node number 127.
dec2 [decoder2]: a decoder that allocates the 7-bit number held by the SAR to 128 ODRs.
dec3 [decoder3]: A decoder that detects that the NC indicates the last node number 127.
Mux [multiplexer]: a multiplexer that selects the output of the 128-node voltage detection circuit by NC.
CONT [controller]: A sequencer that receives an operation start command from a computer or a push button switch, etc., controls each part of the circuit, and executes an action up to generation of a net list.

FIG. 8 shows an example of netlist generation by the first method in more detail. In the following description, numerals 0 to 7 represent steps, and in FIG. 8, numerals other than “0” are represented by circled numbers.
0 [idling]: Standby state. When a netlist generation start instruction is received by an external computer or a push button switch operation, the process proceeds to the next 1 [clear GPM]. It stays in this state if there is no instruction.
1 [clear GPM]: Set all GPM data to 0. After GC and NC are cleared to 0 (cleared), NC is incremented by 1 and NC = 127 is continuously written to GPM until dec3 is detected.
2 [read and test GPM]: Search for a node to be GND and switch the node to GND.
If the highest level of GPM data is 0, the node is the node to be grounded because the initial state = unwritten (= ungroup registration). If the highest level is 1, it is already written (= group registered), so there is no need to check the continuity with other nodes by GND.
When NC = 0 and +1 counts up and when the most significant bit becomes 0, the count-up is stopped and the NC at that time is loaded into the SAR. Since the NC value loaded in the SAR is an unwritten node number, it is decoded by dec2 and the node is switched to GND by ODR.
If the highest level = 1 until NC = 127, the writing of all the nodes has already been completed, so the net list has been generated on the GPM, so the process returns to 0 [idling].
3 [delay]: Wait for a certain period of time from the GND of the node until the voltages of all the nodes are detected.
When one node is grounded, all nodes that are electrically connected to that node become the GND potential through the pull-up resistor. The voltage detection requires time until the influence of the delay time of the ODR, the transmission time for transmitting the GND potential through the pattern of the printed circuit board, the vibration due to reflection, etc. can be ignored.
For example, if the pattern length is 1 meter, the transmission time is 4 ns, the reflection time is 16 ns, the ODR delay time is 5 ns, and the waiting time is about 50 ns with a margin.
4 [sense V]: The node voltage is checked. If 0, the same group is written to the GPM. The node voltage selected by Mux by the NC in operation 2 is examined. If it is 0, it moves to 5 [read and write GPM] in order to write to GPM, and if it is 1, it moves to 6 [test NC] that checks the NC value without writing.
5 [read and write GPM]: Reads the GPM for the node of voltage 0, and writes it if not written. Similarly to 2 [read and test GPM], the GPM is read, and if the highest level is 0, it is not written, so the group number is written to the GPM. Data is written as most significant bit = 1, and thereafter 7 bits = GC.
6 [test NC]: Check whether NC has reached 127 in the end. If it is not 127, increment +1 and return to 4 [sense V]. If 127, writing to GPM of all nodes with voltage 0 is completed. Therefore, in order to check the next group, the process moves to 7 [test SAR and inc GC].
7 [test SAR and inc GC]: If the node to be GND has reached the final value of 127, the writing of all the nodes is completed, and the net list is generated on the GPM, so that it returns to 0. If it is less than 127, the group number is incremented by 1, and the process returns to 2.

The main function of the tester is the netlist creation function = measurement / inspection function described so far, but the test is finally completed by comparison with the master data. To create master data necessary for pass / fail judgment,
(1) A method of measuring a board that is completely judged to be a good product and using it as master data,
(2) Method of creating externally based on a net list output from printed circuit board design CAD software and using it as master data,
There is. In the present invention, any of the above two methods may be adopted. The net list generated from the printed circuit board to be inspected is compared with the master data.

FIG. 9 and FIG. 10 show an example of a functional block diagram and flowchart of the pass / fail judgment by comparison of netlists. In the example shown in FIG. 9 and FIG. 10, two GPMs (GPM0, GPM1) are prepared, a normal netlist is written in GPM0, a netlist read from a printed circuit board to be tested is written in GPM1, and both The data is compared for each same address to judge whether it is good or bad. In this embodiment, both the GPM0 and GPM1 use the memory in the FPGA, but actually there are some variations as follows in addition to this method.
A: A net list in which the result of inspecting and generating a non-defective printed circuit board by the above-described method is normal is written in GPM0.
B: A normal net list written from outside (for example, a computer) is written into GPM0.
C: GPM0 is not held inside the FPGA, but is prepared in advance, for example, outside a computer or the like, and the data of GPM1 is transmitted to the outside, and both are compared and determined externally.
In either case, there is no practical problem. It may be adopted arbitrarily.

  The contents described so far have been based on the assumption that one FPGA measures 128 measurement points. In actual tests, it is natural that the measurement target point of a large printed circuit board to be measured exceeds several tens of times or 10,000 points. As a countermeasure, a plurality of FPGAs are used. The points in this case are (1) that all FPGAs have the same structure, and (2) that the number of FPGAs can be easily increased or decreased. FIG. 11 shows an example, in which the number of check nodes = measurement points is 12800. The number of FPGAs is 100, and each FPGA is responsible for 128 inspection nodes. If FPGAs with different specifications are selected, the total number of FPGAs is different, and the number of inspection nodes that one FPGA is responsible for is also different. In addition, it is assumed that the number of check nodes handled by one FPGA is 128, and it is assumed that the total number of check nodes is 12800, and it may be more or less.

  A net list generation operation when using a plurality of FPGAs will be described. A condition for using a plurality of FPGAs is that all FPGAs have the same structure. This can be easily dealt with by increasing or decreasing the FPGA without changing the electrical design even when the measurement point increases or decreases depending on the size of the printed circuit board to be measured. This is a means for simplifying a large measurement circuit and is one of the features of the present invention. The measurement data comparison and pass / fail judgment other than the netlist generation step (flow) are the same as when one FPGA is used, and the description thereof will be omitted. This embodiment will be described below.

  FIG. 12 is a timing chart of the entire FPGA, FIG. 13 is an operation flowchart when generating a netlist of a plurality of FPGAs, and FIG. 14 is an explanatory diagram of the internal structure of each FPGA when a plurality of FPGAs are formed. Details will be described below.

First, the overall configuration (FIG. 11) and the structure of each FPGA (FIG. 14) will be described. Communication means are added between 100 FPGAs. Each FPGA has the following terminals.
1: 128 inspection terminals tp0 to tp127
This is a terminal connected to the inspection node of the printed circuit board to be inspected.
2: Communication input terminal: A part for inputting the command signal CM and the confirmation signal ACK.
Adjacent FPGAs are connected by a CM signal terminal and an ACK signal terminal. Signals CM and ACK transmitted from one FPGA are daisy chain connected to the adjacent FPGA, and between adjacent FPGAs, the transmitting side is called upstream and the receiving side is called downstream. Apriori has no upstream or downstream.
3: Inspection start command input terminal ··· S terminal This S terminal is a terminal for inputting an inspection start signal S. When this S signal is given to an arbitrary FPGA, this FPGA becomes the most upstream at this point and the inspection is started. It is maintained that this FPGA is the most upstream until the end of the inspection. The most upstream FPGA is called FPGAs. The S signal must be given to any one FPGA and not to more than one FPGA.
4: Inspection end flag transmission terminal... E terminal At the end of inspection, an end flag signal is transmitted to the E terminal of the most upstream FPGA.
5: Normal display transmission terminal When a flag is transmitted from this terminal, it is a pass product.
6: Defect display transmission terminal When a flag is transmitted from this terminal, it is a rejected product.

Next, the operation flow of the FPGA (FIG. 13) will be described.
1. Command signals include inspection start STR, drive increase NSI, drive end NSE, and inspection end END. It is arbitrary whether this is made into four individual signal lines, encoded with two 2-bits, or serially encoded with one. The confirmation signal notifies the end of processing for the received command.
2. The FPGA given S becomes the most upstream FPGA and starts writing 0 to its own GPM, and simultaneously transmits the STA command.
3. When receiving the STA signal, the downstream FPGA starts writing 0 to its own GPM, and transmits ACK when the writing is completed.
4). When the ACK returns, the FPGAs recognize that the GPMs of all the FPGAs have been cleared, and switch on their own tp0 before transmitting the NSI. An FPGA that switches on its own inspection terminal is called a master. At this point, FPGAs are the master. An FPGA other than the master is called a slave.
5. The FPGAs recognize that the test terminal with the detection voltage 0 among np1 to np127 is in conduction with np0, and write group number = 0 and flag = 1 to the terminal address of the GPM.
6). All slaves that have received NSI recognize that the test terminal with the detection voltage 0 among the own test terminals is in conduction with tp0 of the FPGAs, and writes group number = 0 and flag = 0 to the terminal address of its own GPM. .
7). When FPGAs receive ACK, the group counter is incremented by 1 and NSI is stopped.
8). The slave stops ACK transmission when NSI is stopped.
9. When receiving the stop of ACK, the FPGAs read and search for a test terminal to be switched on next from the GPM. When the GPM is read sequentially toward addresses 0 to 127 and an address of flag = 0 is found, it is a test terminal to be switched on next.
10. NSI is transmitted after the switch is turned on.
11. The slave that has received the NSI increments the group counter by +1 and then executes the same as in step 6 above.
12 The FPGAs then return to the above 4 and repeat the same operation up to 9. If the address of flag = 0 is not found in 9 above, since all of tp0 to tp127 have been written, the FPGAs are terminated as masters.
13. When the FPGAs are finished as masters, NSE is transmitted.
14 The FPGA that has received the NSE next recognizes that it is the master. Since the NSE receives only the downstream FPGA adjacent to the output FPGA, the other FPGAs remain slaves.
15. The FPGA which became the master executes the above 4 to 11.
16. Repeating the above, the master moves downstream.
17. When the FPGAs receive the NSE, it means that all the FPGAs are master data, and thus the inspection is completed, and a netlist obtained as a result of the inspection is generated for each FPGA. This is END transmitted, and the inspection end flag E is transmitted.

  Next, a description will be given of a second embodiment of the printed circuit board inspection apparatus for executing the second inspection method having a disable function and making a complementary drive circuit for switching to the power source or the ground. 15 to 21 show a second embodiment. 15 shows the connection between the node to be inspected and the test terminal of the tester, FIG. 16 shows a conceptual flow chart of netlist generation, FIG. 17 shows the internal structure of the FPGA at the time of netlist generation, and FIG. 19 is a circuit example for generating a voltage pattern for driving the push-pull output circuit at the measurement node, FIG. 20 is an operation timing chart of the voltage pattern generation circuit, and FIG. FIG. 22 shows an operation timing chart of the voltage pattern detection circuit.

  Unlike the example shown in FIG. 4, the connection example between the node to be inspected and the test terminal of the tester shown in FIG. In the first inspection method, the presence or absence of conduction with the switch-on node can be immediately determined based on the detection node voltage level (1 or 0). However, in the second inspection method, it is insulated from the switched node. Since the potential of the node being in a high impedance state is indefinite, the correctness probability is halved only by the high or low node voltage, making it impossible to determine whether the node is good or bad. As a countermeasure, instead of applying a constant current (direct current) to the node to be switched, a high and low voltage (VPG circuit signal to be described later) having a constant time series pattern is applied. With this configuration, the voltage detection circuit 58 detects the same voltage pattern at a node that is conductive with the switch node, and a voltage pattern that has no correlation with the pattern at an insulated node. The pass / fail judgment of the printed circuit board to be inspected can be made from this voltage pattern.

FIG. 16 is a conceptual flowchart when generating a netlist, and FIGS. 17 and 18 are an internal structure and flow of the FPGA when generating a netlist. Compared with the example shown in FIG. 7, the internal structure of the FPGA is a VPG circuit that generates a time series pattern and drives a check node, stores a time series of high and low test voltages, and has a degree of coincidence compared to the VPG. A VPD circuit to detect is added. Other structures are the same as those of the circuit example used in the first inspection method. The operation flow shown in FIG. 16 is as follows.
S60: Reading of the inspected printed circuit board is started.
S61: All G / V switches (ground switch and voltage addition switch) are turned off to make all node voltages unstable.
S62: Only one G / V switch is alternately turned on. The node with the lowest number among the nodes not belonging to any group is determined.
S63: The G / V switch of the node is turned on alternately.
S64: Measure the voltages of all nodes.
S65: The node in which the same voltage pattern as the G / V switch is detected is written in the memory as belonging to the same group as n.
S66: Returning to S22, a node to turn on the G / V switch alternately is determined.
S67: End when all nodes are registered in the group.

  Next, the operation of the VPG and VPD will be described. FIG. 19 is a VPG configuration diagram that is a circuit that generates a voltage to be applied to the measurement node via the push-pull output circuit, and FIG. 20 is a VPG operation timing chart. First, a 7-bit counter (Q0 to Q6) is counted up at 50 MHz. When the “VPG output” indicated by the circled number 3 in the flowchart shown in FIG. 18 is reached, the count is enabled and the count is started. When the full count of Q0 to Q6 = 1 is reached, the “VPG output” is ended. During this time, Q4 becomes an alternating signal every 16 clocks, and this outputs a time series voltage pattern of the check node through a push-pull drive circuit with enable control. In the time-series voltage pattern, the power supply voltage having the same width as the GND voltage of 16 clocks = 320 ns is repeated four times. Only the drive circuit for which the switch operation is selected is enabled and the above voltage pattern is output, but the drive circuit that is not selected is disabled and is indefinite potential in a high impedance state that is not switched by the power supply or GND. It has become.

  FIG. 21 shows the operation of the VPD, which is a detection circuit that detects the node voltage and checks for a match with the generation pattern. The inspection node voltage subjected to threshold processing by the voltage detection circuit is “1” if it is high, and “0” if it is low, and is input to ex-nor (exclusive-nor circuit) and compared with QPG of VPG (VPG pattern). Is done. If both the check node voltage and the VPG pattern are the same, the ex-nor output is “1”, otherwise, it is “0”. The counter is counted up during the period when the Ex-nor output is “1”. The count value increases according to the degree of coincidence of both patterns. The count value counted up during the “VPG output” period is subjected to threshold processing by the comparison circuit, and if it is equal to or greater than the threshold, it is regarded as coincidence and conduction is determined. The determination result is selected by the node number by Mux, and the presence or absence of conduction is determined for each node.

  FIG. 22 shows three examples of changes in the count value of a representative node. Since the drive node and the detection pattern coincide with each other in the conductive node, the count value increases linearly. A node which is not conducting and whose voltage is equal to or higher than a threshold value and is constant during this period will be referred to as a node A. In this case, while the drive pattern is “1”, the count increases with a match, but during the period when the drive pattern is “0”, the count value does not increase due to a mismatch. A node that is not conducting and whose voltage is equal to or lower than a threshold value and is constant during this period will be referred to as a node B. In this case, while the drive pattern is “0”, the count increases with a match, but during the drive pattern “1”, the count value does not match and does not increase. The pattern matching degree is determined at the time when “VPG output” ends, and only the conduction node exceeds the threshold. In this way, it is possible to determine the pass / fail of the printed circuit board to be inspected.

It is a conceptual diagram which shows schematically the Example of the printed circuit board inspection apparatus concerning this invention. It is a front view which expands and shows the connection part of the to-be-measured board which is a part of the said Example, and a tester board | substrate. It is a schematic diagram for demonstrating schematically the example of the measuring method in case a to-be-inspected printed circuit board is an interposer board | substrate. It is a typical circuit diagram which shows the example of the connection relation of the test | inspection node and tester board | substrate for demonstrating the measurement logic by the 1st measurement method applicable to this invention. It is a flowchart explaining the concept of the net list production | generation by the pattern reading of the to-be-inspected printed circuit board by the said 1st method. It is a structural diagram showing an example of a net list storage memory that can be used for printed circuit board inspection by the first method. It is a block diagram which shows the example of the internal structure of FPGA at the time of the net list production | generation which can be used for the printed circuit board test | inspection by the said 1st method. It is a flowchart which shows the operation example of said FPGA. It is a functional block diagram which shows the example of the pass / fail determination part by the comparison of a net list. It is a flowchart which shows the operation example of the pass / fail determination by the comparison of a net list. It is a connection diagram which shows the example of a connection structure of FPGA when using several FPGA. It is a timing chart which shows the operation example at the time of using the said some FPGA. It is a flowchart which shows the example of netlist production | generation when the said some FPGA is connected. It is a block diagram which shows the example of the internal structure of each FPGA when the said several FPGA is connected. It is a typical circuit diagram which shows the example of the connection relation of the test | inspection node and tester board | substrate for demonstrating the measurement logic by the 2nd measuring method applicable to this invention. It is a flowchart explaining the concept of the net list generation by the pattern reading of the printed circuit board to be inspected by the second method. It is a block diagram which shows the example of the internal structure of FPGA at the time of the net list production | generation which can be used for the printed circuit board test | inspection by the said 2nd method. It is a flowchart which shows the operation example of said FPGA. It is a circuit diagram which shows the example of the voltage pattern generation circuit which can be used for the printed circuit board test | inspection by the said 2nd method. It is a timing chart which shows operation | movement of the said voltage pattern generation circuit. It is a circuit diagram which shows the example of the voltage pattern detection circuit which can be used for the printed circuit board test | inspection by the said 2nd method. It is a timing chart which shows the operation example of the said voltage pattern detection circuit. It is a schematic explanatory drawing of the conventional point-to-point resistance method scanner type tester. It is a schematic explanatory drawing of the conventional flying prober system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate to be measured 21 Anisotropic conductive sheet 22 Measurement point conversion jig 23 Anisotropic conductive sheet 24 Tester circuit board 26 FPGA
27 Measurement point 28 Grid position after conversion 29 Grid pattern position 31 Anisotropic conductive sheet 32 Measurement point conversion jig 33 Anisotropic conductive sheet 34 Tester circuit board 36 Pull-up resistor 37 Ground switch 38 Detection circuit 39 Printed circuit board to be inspected Circuit pattern 40 Contact point between inspection node and inspection terminal

Claims (6)

A tester circuit board having all inspection lands of the inspected printed circuit board and test terminals connected thereto, and positioned above or below the inspected printed circuit board;
A measurement point conversion jig that is interposed between the printed circuit board to be inspected and the tester circuit board and converts between the inspection land and the test terminal and converts the measurement point;
A tester circuit having a test terminal and supplying an electric signal only to one inspection land of all inspection lands by this test terminal to detect the presence or absence of an electric signal in another inspection land;
The tester circuit repeats the operation of detecting the presence or absence of electrical signals in other inspection lands while switching the inspection lands of the printed circuit board to which electrical signals are applied, over all inspection lands, and the continuity between all inspection lands is established. A printed circuit board inspection device that inspects cuts and short circuits of printed circuit board patterns by detection.   The tester circuit has a test terminal having a signal transmission function for supplying an electrical signal and a signal detection function for detecting the presence or absence of an electrical signal, having a number of test lands or more, and a memory for storing the conduction state between all test lands. 2. The printed circuit board inspection apparatus according to claim 1, further comprising a logic function for inspecting data coincidence between memories and a signal transmission function for transmitting memory contents to the outside. As a signal transmission function, it has a pull-up resistor connected to the power supply voltage and a source ground open drain drive circuit having a switch function to the ground, and a voltage detection circuit having a threshold with high input impedance as a signal detection function,
The voltage detection circuit detects the voltage of all inspection lands by turning on the open drain drive circuit in one arbitrary inspection land and grounding it, and turning off the other inspection lands and applying the power supply voltage via the pull-up resistor. Configured to
The voltage of all inspection lands that are in conduction with the inspection land grounded by turning on the open drain drive circuit is a low voltage close to the ground level. With the electronic circuit theory that the voltage is close to the power supply voltage due to only a voltage drop, the conduction and non-conduction states between the inspection land that is grounded on by the high and low voltage detected by the voltage detection circuit and all other inspection lands 3. The printed circuit board inspection apparatus according to claim 2, wherein the printed circuit board inspection apparatus knows the continuity and non-conduction between all the inspection lands by performing the ground-on inspection repeatedly for all the inspection lands. A 3-state complementary drive circuit with an enable state in which the switch to either the power supply voltage or the ground potential is turned on as a signal transmission function and a disable state in which both switches are turned off, and a high input impedance as a signal detection function A voltage detection circuit having a threshold,
The voltage detection circuit enables a complementary drive circuit in one arbitrary inspection land to be in an enabled state and alternately turns on the power supply voltage and the ground potential, disables the three-state driving circuits in other inspection lands, and disables all inspection lands. Configured to detect voltage,
The power supply voltage and the ground potential are alternately turned on and all the test lands in the conductive state have the same time-series pattern potential as the power supply voltage and the ground potential that are alternately turned on by the drive circuit. land the voltage of the test lands in the non-conducting state, undefined potential no correlation with the time series pattern of the alternating by being connected to the disabled complementary driving circuit, the driving pattern and the voltage detection circuit By knowing the conduction / non-conduction state between the inspection land in the enabled state and all other inspection lands by matching or non-coincidence of the time-series patterns of the detected voltage, all inspection lands are repeated by repeating the enable inspection land for all inspection lands. The printed circuit board inspection apparatus according to claim 2, wherein the state of electrical conduction and non-conduction between the printed circuit boards is known.
  5. The printed circuit board inspection apparatus according to claim 3 or 4, comprising a plurality of field programmable gate arrays (FPGAs) or ASICs (application-specific integrated circuits) having the same structure as the tester circuit according to claim 3 or 4. A printed circuit board inspection apparatus that divides into chips and transmits a control signal of an inspection start signal, a drive increase signal, a drive end signal, an inspection end signal, and an acknowledgment signal for each signal between adjacent chips. The net list collected from the non-defective printed circuit board after the connection of the test terminal and the inspection land and the net list collected from the printed circuit board to be inspected are stored in separate memories. By
Satisfies all test terminal number ≧ total inspection lands number of conditions, claim to the quality determination of the printed circuit board without predetermining the connection between the individual test terminals and individual land objective printed circuit board of the test chip 5 The printed circuit board inspection apparatus described.

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