JP4993399B1 - Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device - Google Patents

Semiconductor junction protecting glass composition, semiconductor device manufacturing method, and semiconductor device Download PDF

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JP4993399B1
JP4993399B1 JP2012511480A JP2012511480A JP4993399B1 JP 4993399 B1 JP4993399 B1 JP 4993399B1 JP 2012511480 A JP2012511480 A JP 2012511480A JP 2012511480 A JP2012511480 A JP 2012511480A JP 4993399 B1 JP4993399 B1 JP 4993399B1
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JPWO2012160631A1 (en
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一彦 伊藤
浩二 伊東
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Shindengen Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00—Glass compositions
    • C03C3/04—Glass compositions containing silica
    • C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/083—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound
    • C03C3/085—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal
    • C03C3/087—Glass compositions containing silica with 40% to 90% silica, by weight containing aluminium oxide or an iron compound containing an oxide of a divalent metal containing calcium oxide, e.g. common sheet or container glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Abstract

少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないことを特徴とする半導体接合保護用ガラス組成物。ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２６ｍｏｌ％の範囲内にあり、ＭｇＯの含有量が１１ｍｏｌ％〜２６ｍｏｌ％の範囲内にあり、ＣａＯの含有量が３ｍｏｌ％〜９ｍｏｌ％の範囲内にあることが好ましい。
本発明の半導体接合保護用ガラス組成物によれば、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス」を用いた場合と同様に高耐圧の半導体装置を製造することが可能となる。
【選択図】図５Contains at least SiO 2 , Al 2 O 3 , MgO, and CaO, and substantially contains Pb, B, P, As, Sb, Li, Na, and K The glass composition for semiconductor junction protection characterized by not performing. The content of SiO 2 is in the range of 53 mol% to 73 mol%, the content of Al 2 O 3 is in the range of 11 mol% to 26 mol%, and the content of MgO is in the range of 11 mol% to 26 mol%. And the CaO content is preferably in the range of 3 mol% to 9 mol%.
According to the glass composition for protecting a semiconductor junction of the present invention, a high breakdown voltage semiconductor device is manufactured using a glass material not containing lead as in the case of using a conventional “glass mainly composed of lead silicate”. It becomes possible to do.
[Selection] Figure 5

Description

本発明は、半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device.

メサ型の半導体装置を製造する過程でｐｎ接合露出部を覆うようにパッシベーション用のガラス層を形成する半導体装置の製造方法が知られている（例えば、特許文献１参照。）。   2. Description of the Related Art A method for manufacturing a semiconductor device is known in which a passivation glass layer is formed so as to cover a pn junction exposed portion in the process of manufacturing a mesa semiconductor device (see, for example, Patent Document 1).

図６及び図７は、そのような従来の半導体装置の製造方法を説明するために示す図である。図６（ａ）〜図６（ｄ）及び図７（ａ）〜図７（ｄ）は各工程図である。
従来の半導体装置の製造方法は、図６及び図７に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で含む。以下、従来の半導体装置の製造方法を工程順に説明する。6 and 7 are views for explaining such a conventional method of manufacturing a semiconductor device. 6 (a) to 6 (d) and FIGS. 7 (a) to 7 (d) are process diagrams.
As shown in FIGS. 6 and 7, the conventional semiconductor device manufacturing method includes a “semiconductor substrate forming step”, a “groove forming step”, a “glass layer forming step”, a “photoresist forming step”, and an “oxide removal”. Step, “roughened region forming step”, “electrode forming step” and “semiconductor substrate cutting step” are included in this order. Hereinafter, a conventional method for manufacturing a semiconductor device will be described in the order of steps.

（ａ）半導体基体形成工程
まず、ｎ−型半導体基板（ｎ−型シリコン基板）９１０の一方の表面からのｐ型不純物の拡散によりｐ＋型拡散層９１２、他方の表面からのｎ型不純物の拡散によりｎ＋型拡散層９１４を形成して、主面に平行なｐｎ接合が形成された半導体基体を形成する。その後、熱酸化によりｐ＋型拡散層９１２及びｎ＋型拡散層９１４の表面に酸化膜９１６，９１８を形成する（図６（ａ）参照。）。(A) Semiconductor Base Formation Step First, p + -type diffusion layer 912 is diffused from one surface of n − -type semiconductor substrate (n − -type silicon substrate) 910, and n-type impurities from the other surface are diffused. An n + -type diffusion layer 914 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed. Thereafter, oxide films 916 and 918 are formed on the surfaces of the p + type diffusion layer 912 and the n + type diffusion layer 914 by thermal oxidation (see FIG. 6A).

（ｂ）溝形成工程
次に、フォトエッチング法によって、酸化膜９１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からｐｎ接合を超える深さの溝９２０を形成する（図６（ｂ）参照。）。(B) Groove Formation Step Next, a predetermined opening is formed at a predetermined portion of the oxide film 916 by a photoetching method. After the oxide film is etched, the semiconductor substrate is subsequently etched to form a groove 920 having a depth exceeding the pn junction from one surface of the semiconductor substrate (see FIG. 6B).

（ｃ）ガラス層形成工程
次に、溝９２０の表面に、電気泳動法により溝９２０の内面及びその近傍の半導体基体表面に半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層９２４を形成する（図６（ｃ）参照。）。(C) Glass layer forming step Next, a layer composed of a glass composition for protecting a semiconductor junction is formed on the inner surface of the groove 920 and the surface of the semiconductor substrate in the vicinity thereof on the surface of the groove 920 by electrophoresis. A layer made of the protective glass composition is baked to form a passivation glass layer 924 (see FIG. 6C).

（ｄ）フォトレジスト形成工程
次に、ガラス層９１２の表面を覆うようにフォトレジスト９２６を形成する（図６（ｄ）参照。）。(D) Photoresist Formation Step Next, a photoresist 926 is formed so as to cover the surface of the glass layer 912 (see FIG. 6D).

（ｅ）酸化膜除去工程
次に、フォトレジスト９２６をマスクとして酸化膜９１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位９３０における酸化膜９１６を除去する（図７（ａ）参照。）。(E) Oxide Film Removal Step Next, the oxide film 916 is etched using the photoresist 926 as a mask to remove the oxide film 916 in the portion 930 where the Ni plating electrode film is to be formed (see FIG. 7A).

（ｆ）粗面化領域形成工程
次に、Ｎｉめっき電極膜を形成する部位９３０における半導体基体表面の粗面化処理を行い、Ｎｉめっき電極と半導体基体との密着性を高くするための粗面化領域９３２を形成する（図７（ｂ）参照。）。(F) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 930 where the Ni-plated electrode film is formed. The formation region 932 is formed (see FIG. 7B).

（ｇ）電極形成工程
次に、半導体基体にＮｉめっきを行い、粗面化領域９３２上にアノード電極９３４を形成するとともに、半導体基体の他方の表面にカソード電極９３６を形成する（図７（ｃ）参照。）。(G) Electrode formation step Next, Ni plating is performed on the semiconductor substrate to form the anode electrode 934 on the roughened region 932, and the cathode electrode 936 is formed on the other surface of the semiconductor substrate (FIG. 7C). )reference.).

（ｈ）半導体基体切断工程
次に、ダイシング等により、ガラス層９２４の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置（ｐｎダイオード）を作成する（図７（ｄ）参照。）。(H) Semiconductor Substrate Cutting Step Next, the semiconductor substrate is cut at the center of the glass layer 924 by dicing or the like to form a semiconductor substrate into a chip, thereby producing a mesa semiconductor device (pn diode) (FIG. 7D). )reference.).

以上説明したように、従来の半導体装置の製造方法は、主面に平行なｐｎ接合が形成された半導体基体の一方の表面からｐｎ接合を超える深さの溝９２０を形成する工程（図６（ａ）及び図６（ｂ）参照。）と、当該溝９２０の内部におけるｐｎ接合露出部を覆うようにパッシベーション用のガラス層９２４を形成する工程（図６（ｃ）参照。）とを含む。このため、従来の半導体装置の製造方法によれば、溝９２０の内部にパッシベーション用のガラス層９２４を形成した後半導体基体を切断することにより、高耐圧のメサ型半導体装置を製造することができる。   As described above, in the conventional method for manufacturing a semiconductor device, a step of forming a groove 920 having a depth exceeding the pn junction from one surface of a semiconductor substrate on which a pn junction parallel to the main surface is formed (FIG. 6 ( a) and FIG. 6B), and a step of forming a passivation glass layer 924 so as to cover the exposed portion of the pn junction in the groove 920 (see FIG. 6C). Therefore, according to the conventional method for manufacturing a semiconductor device, a high-breakdown-voltage mesa semiconductor device can be manufactured by forming a passivation glass layer 924 in the groove 920 and then cutting the semiconductor substrate. .

特開２００４−８７９５５号公報JP 2004-87955 A

ところで、パッシベーション用のガラス層に用いるガラス材料としては、（ａ）適正な温度（例えば１０５０℃以下）で焼成できること、（ｂ）工程で使用する薬品に耐えること、（ｃ）シリコンに近い熱膨張係数を有すること及び（ｄ）優れた絶縁性を有することという条件を満たす必要があることから、従来より「珪酸鉛を主成分としたガラス材料」が広く用いられている。   By the way, as a glass material used for the glass layer for passivation, (a) it can be fired at an appropriate temperature (for example, 1050 ° C. or less), (b) can withstand chemicals used in the process, and (c) thermal expansion close to silicon. Since it is necessary to satisfy the conditions of having a coefficient and (d) having excellent insulating properties, a “glass material mainly composed of lead silicate” has been widely used.

しかしながら、「珪酸鉛を主成分としたガラス材料」には環境負荷の大きい鉛が含まれており、近未来にはそのような「珪酸鉛を主成分としたガラス材料」の使用が禁止されていくことになると考えられる。   However, “glass material based on lead silicate” contains lead with a large environmental impact, and in the near future, the use of such “glass material based on lead silicate” is prohibited. It is thought that it will go.

そこで、本発明は、上記した事情に鑑みてなされたもので、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に、高耐圧の半導体装置を製造することを可能とする、半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置を提供することを目的とする。   Therefore, the present invention has been made in view of the above circumstances, and uses a glass material that does not contain lead, as in the case of using the conventional “glass material mainly composed of lead silicate”. An object of the present invention is to provide a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device, which make it possible to manufacture the semiconductor device.

［１］本発明の半導体接合保護用ガラス組成物は、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないことを特徴とする。[1] glass composition for protecting a semiconductor junction of the present invention, at least SiO 2, and Al 2 O 3, containing the MgO, and CaO, and the Pb, and B, and P, a As, Sb And Li, Na, and K are not substantially contained.

［２］本発明の半導体接合保護用ガラス組成物においては、ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることが好ましい。[2] In the glass composition for protecting a semiconductor junction of the present invention, the content of SiO 2 is in the range of 53 mol% to 73 mol%, and the content of Al 2 O 3 is in the range of 11 mol% to 21 mol%. Yes, the MgO content is preferably in the range of 11 mol% to 21 mol%, and the CaO content is preferably in the range of 3 mol% to 6 mol%.

［３］本発明の半導体装置の製造方法は、ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子を準備する第１工程と、前記ｐｎ接合露出部を覆うようにガラス層を形成する第２工程とをこの順序で含む半導体装置の製造方法であって、前記第２工程においては、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物を用いて前記ガラス層を形成することを特徴とする。[3] A method of manufacturing a semiconductor device according to the present invention includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion. And in the second step, at least SiO 2 , Al 2 O 3 , MgO, and CaO, and Pb, B, and the like. , P, As, Sb, Li, Na, and K, the glass layer is formed using a glass composition for protecting a semiconductor junction.

［４］本発明の半導体装置の製造方法においては、前記第１工程は、主面に平行なｐｎ接合を備える半導体基体を準備する工程と、前記半導体基体の一方の表面から前記ｐｎ接合を超える深さの溝を形成することにより、前記溝の内部に前記ｐｎ接合露出部を形成する工程とを含み、前記第２工程は、前記溝の内部における前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程を含むことが好ましい。 [4] In the method for manufacturing a semiconductor device of the present invention, the first step includes a step of preparing a semiconductor substrate having a pn junction parallel to the main surface, and the pn junction is exceeded from one surface of the semiconductor substrate. Forming the pn junction exposed portion in the groove by forming a groove having a depth, and the second step covers the pn junction exposed portion in the groove. It is preferable to include a step of forming a layer.

［５］本発明の半導体装置の製造方法においては、前記第２工程は、前記溝の内部における前記ｐｎ接合露出部を直接覆うように前記ガラス層を形成する工程を含むことが好ましい。この場合において、ｐｎ接合露出部を「直接」覆うようにガラス層を形成するとは、ｐｎ接合露出部を「絶縁層などを介することなく直接」覆うようにガラス層を形成することを意味する。 [5] In the method for manufacturing a semiconductor device of the present invention, it is preferable that the second step includes a step of forming the glass layer so as to directly cover the exposed portion of the pn junction inside the groove. In this case, forming the glass layer so as to cover the pn junction exposed portion “directly” means forming the glass layer so as to cover the pn junction exposed portion “directly without an insulating layer or the like”.

［６］本発明の半導体装置の製造方法においては、前記第２工程は、前記溝の内部における前記ｐｎ接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程とを含むことが好ましい。 [6] In the method of manufacturing a semiconductor device of the present invention, the second step includes a step of forming an insulating film on the pn junction exposed portion in the trench, and the pn junction exposure through the insulating film. And forming the glass layer so as to cover the portion.

［７］本発明の半導体装置の製造方法においては、前記第１工程は、半導体基体の表面に前記ｐｎ接合露出部を形成する工程を含み、前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程を含むことが好ましい。 [7] In the method for manufacturing a semiconductor device of the present invention, the first step includes a step of forming the pn junction exposed portion on the surface of the semiconductor substrate, and the second step includes the step on the surface of the semiconductor substrate. It is preferable to include a step of forming the glass layer so as to cover the pn junction exposed portion.

［８］本発明の半導体装置の製造方法においては、前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部を直接覆うように前記ガラス層を形成する工程を含むことが好ましい。この場合において、ｐｎ接合露出部を「直接」覆うようにガラス層を形成するとは、ｐｎ接合露出部を「絶縁層などを介することなく直接」覆うようにガラス層を形成することを意味する。 [8] In the method of manufacturing a semiconductor device of the present invention, it is preferable that the second step includes a step of forming the glass layer so as to directly cover the pn junction exposed portion on the surface of the semiconductor substrate. In this case, forming the glass layer so as to cover the pn junction exposed portion “directly” means forming the glass layer so as to cover the pn junction exposed portion “directly without an insulating layer or the like”.

［９］本発明の半導体装置の製造方法においては、前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程とを含むことが好ましい。 [9] In the method of manufacturing a semiconductor device of the present invention, the second step includes a step of forming an insulating film on the pn junction exposed portion on the surface of the semiconductor substrate, and the pn junction via the insulating film. And a step of forming the glass layer so as to cover the exposed portion.

［１０］本発明の半導体装置の製造方法においては、前記半導体接合保護用ガラス組成物は、ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることが好ましい。[10] In the method for manufacturing a semiconductor device of the present invention, the glass composition for protecting a semiconductor junction has a SiO 2 content in the range of 53 mol% to 73 mol% and an Al 2 O 3 content of 11 mol. It is preferable that the MgO content is in the range of 11 mol% to 21 mol%, and the CaO content is in the range of 3 mol% to 6 mol%.

［１１］本発明の半導体装置は、ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子と、前記ｐｎ接合露出部を覆うように形成されたガラス層とを備える半導体装置であって、前記ガラス層は、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物を用いて形成されたものであることを特徴とする。[11] A semiconductor device according to the present invention is a semiconductor device comprising a semiconductor element having a pn junction exposed portion from which a pn junction is exposed, and a glass layer formed so as to cover the pn junction exposed portion, wherein the glass The layer contains at least SiO 2 , Al 2 O 3 , MgO, and CaO, and substantially contains Pb, B, P, As, Sb, Li, Na, and K. It is formed using the glass composition for semiconductor junction protection which is not contained in general.

［１２］本発明の半導体装置においては、前記半導体接合保護用ガラス組成物は、ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることが好ましい。[12] In the semiconductor device of the present invention, the glass composition for protecting a semiconductor junction has an SiO 2 content in the range of 53 mol% to 73 mol%, and an Al 2 O 3 content of 11 mol% to 21 mol. %, The MgO content is preferably in the range of 11 mol% to 21 mol%, and the CaO content is preferably in the range of 3 mol% to 6 mol%.

本発明の半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置によれば、後述する実施例からも明らかなように、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に高耐圧の半導体装置を製造することが可能となる。   According to the glass composition for protecting a semiconductor junction, the method for manufacturing a semiconductor device, and the semiconductor device of the present invention, as will be apparent from Examples described later, a glass material containing no lead is used, A high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using “a glass material having a main component”.

なお、本発明の半導体接合保護用ガラス組成物において、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないとは、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを成分として含有しないという意味であり、ガラスを構成する各成分の原料中に不純物として上記が混入したガラス組成物を排除するものではない。本発明の半導体装置の製造方法及び半導体装置においても同様である。   In the glass composition for protecting a semiconductor junction according to the present invention, Pb, B, P, As, Sb, Li, Na, and K are not substantially contained. , P, As, Sb, Li, Na, and K are not included as components, and the glass composition in which the above is mixed as an impurity in the raw material of each component constituting the glass is excluded. Not what you want. The same applies to the semiconductor device manufacturing method and the semiconductor device of the present invention.

ここで、Ｐｂを実質的に含有しないこととしたのは、本発明の目的が「鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に高耐圧の半導体装置を製造することを可能とする」ことにあるからである。   Here, Pb is not substantially contained because the purpose of the present invention is to use a conventional “glass material containing lead silicate as a main component using a glass material not containing lead”. Similarly, it is possible to manufacture a semiconductor device having a high breakdown voltage.

また、Ｂと、Ｐと、Ａｓと、Ｓｂとを実質的に含有しないこととしたのは、これらの成分を含有する場合には焼成温度の点では有利なのではあるが、焼成中にこれらの成分が半導体基体に拡散することに起因して絶縁性が低下する場合があるからである。   In addition, the fact that B, P, As, and Sb are not substantially contained is advantageous in terms of the firing temperature when these components are contained, but during firing, these This is because the insulating properties may deteriorate due to the diffusion of components into the semiconductor substrate.

また、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないこととしたのは、これらの成分を含有する場合には焼成温度の点では有利なのではあるが、絶縁性や耐薬品性が低下する場合があるからである。   In addition, the fact that Li, Na, and K are not substantially contained is advantageous in terms of the firing temperature when these components are contained, but the insulation and chemical resistance are reduced. Because there is a case to do.

本発明の発明者らの研究により、これらの成分（すなわち、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋ。）を実質的に含有しない場合であっても、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有するガラス組成物は、半導体接合保護用ガラス組成物として使用可能であることが分かった。すなわち、本発明の半導体接合保護用ガラス組成物によれば、後述する実施例からも明らかなように、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に高耐圧の半導体装置を製造することが可能となる。According to the study of the inventors of the present invention, these components (that is, Pb, B, P, As, Sb, Li, Na, and K.) are not substantially contained. also, at least SiO 2, and Al 2 O 3, and MgO, and mixtures thereof and CaO were found to be usable as a glass composition for protecting a semiconductor junction. That is, according to the glass composition for protecting a semiconductor junction of the present invention, as will be apparent from Examples described later, a conventional “glass material mainly composed of lead silicate” using a glass material not containing lead. A high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using.

実施形態２に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment. 実施形態２に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment. 実施形態３に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment. 実施形態３に係る半導体装置の製造方法を説明するために示す図である。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment. 実施例の結果を示す図表である。It is a graph which shows the result of an Example. 従来の半導体装置の製造方法を説明するために示す図である。It is a figure shown in order to demonstrate the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明するために示す図である。It is a figure shown in order to demonstrate the manufacturing method of the conventional semiconductor device.

以下、本発明の半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置について、図に示す実施の形態に基づいて説明する。   Hereinafter, a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device of the present invention will be described based on the embodiments shown in the drawings.

［実施形態１］
実施形態１は、半導体接合保護用ガラス組成物に係る実施形態である。[Embodiment 1]
Embodiment 1 is an embodiment according to a glass composition for protecting a semiconductor junction.

実施形態１に係る半導体接合保護用ガラス組成物は、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないものである。The glass composition for protecting a semiconductor junction according to Embodiment 1 contains at least SiO 2 , Al 2 O 3 , MgO, and CaO, and Pb, B, P, As, and Sb. , Li, Na, and K are not substantially contained.

具体的には、ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内（例えば６３．２ｍｏｌ％）にあり、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内（例えば１５．５ｍｏｌ％）にあり、ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内（例えば１５．７ｍｏｌ％にあり、ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内（例えば５．６ｍｏｌ％）にある。Specifically, the content of SiO 2 is in the range of 53 mol% to 73 mol% (eg, 63.2 mol%), and the content of Al 2 O 3 is in the range of 11 mol% to 21 mol% (eg, 15.5 mol). %), And the content of MgO is in the range of 11 mol% to 21 mol% (for example, 15.7 mol%, and the content of CaO is in the range of 3 mol% to 6 mol% (for example, 5.6 mol%).

実施形態１に係る半導体接合保護用ガラス組成物によれば、後述する実施例からも明らかなように、鉛を含まないガラス材料を用いて、従来の「珪酸鉛を主成分としたガラス材料」を用いた場合と同様に高耐圧の半導体装置を製造することが可能となる。   According to the glass composition for protecting a semiconductor junction according to the first embodiment, as is clear from examples described later, a conventional “glass material mainly composed of lead silicate” using a glass material not containing lead. A high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using.

ここで、ＳｉＯ２の含有量を５３ｍｏｌ％〜７３ｍｏｌ％の範囲内としたのは、ＳｉＯ２の含有量が５３ｍｏｌ％未満である場合には、耐薬品性が低下したり、絶縁性が低下したりする場合があるからであり、ＳｉＯ２の含有量が７３ｍｏｌ％を超える場合には、焼成温度が高くなる傾向にあるからである。Here, the content of SiO 2 is set within the range of 53 mol% to 73 mol%. When the content of SiO 2 is less than 53 mol%, the chemical resistance decreases or the insulation decreases. This is because if the content of SiO 2 exceeds 73 mol%, the firing temperature tends to increase.

また、Ａｌ２Ｏ３の含有量を１１ｍｏｌ％〜２１ｍｏｌ％の範囲内としたのは、Ａｌ２Ｏ３の含有量が１１ｍｏｌ％未満である場合には、耐薬品性が低下したり、絶縁性が低下したりする場合があるからであり、Ａｌ２Ｏ３の含有量が２１ｍｏｌ％を超える場合には、焼成温度が高くなる傾向にあるからである。In addition, the content of Al 2 O 3 is in the range of 11 mol% to 21 mol% because when the content of Al 2 O 3 is less than 11 mol%, the chemical resistance decreases or the insulating property This is because the firing temperature tends to increase when the Al 2 O 3 content exceeds 21 mol%.

また、ＭｇＯの含有量を１１ｍｏｌ％〜２１ｍｏｌ％の範囲内としたのは、ＭｇＯの含有量が１１ｍｏｌ％未満である場合には、耐薬品性が低下したり、絶縁性が低下したりする場合があるからであり、ＭｇＯの含有量が２１ｍｏｌ％を超える場合には、焼成温度が高くなる傾向にあるからである。   In addition, the MgO content is within the range of 11 mol% to 21 mol% when the MgO content is less than 11 mol% when the chemical resistance is lowered or the insulation is lowered. This is because the firing temperature tends to increase when the MgO content exceeds 21 mol%.

また、ＣａＯの含有量を３ｍｏｌ％〜９ｍｏｌ％の範囲内としたのは、ＣａＯの含有量が３ｍｏｌ％未満である場合には、焼成温度が高くなる傾向にあるからであり、ＣａＯの含有量が９ｍｏｌ％を超える場合には、耐薬品性が低下したり、絶縁性が低下したりする場合があるからである。   The reason why the content of CaO is within the range of 3 mol% to 9 mol% is that when the content of CaO is less than 3 mol%, the firing temperature tends to increase, and the content of CaO This is because when the amount exceeds 9 mol%, chemical resistance may be lowered or insulation may be lowered.

実施形態１に係る半導体接合保護用ガラス組成物は、以下のようにして製造することができる。すなわち、上記した組成比（モル比）になるように原料（ＳｉＯ２、Ａｌ（ＯＨ）３、Ｍｇ（ＯＨ）２及びＣａＣＯ３）を調合し、混合機でよく攪拌した後、その混合した原料を電気炉中で所定温度に上昇させた白金ルツボに入れ、所定時間溶融させる。その後、融液を水冷ロールに流し出して薄片状のガラスフレークを得る。その後、このガラスフレークをボールミルなどで所定の平均粒径となるまで粉砕して、粉末状のガラス組成物を得る。The glass composition for protecting a semiconductor junction according to Embodiment 1 can be manufactured as follows. That is, the raw materials (SiO 2 , Al (OH) 3 , Mg (OH) 2 and CaCO 3 ) were prepared so as to have the above-described composition ratio (molar ratio), stirred well with a mixer, and then the mixed raw materials Is placed in a platinum crucible raised to a predetermined temperature in an electric furnace and melted for a predetermined time. Thereafter, the melt is poured into a water-cooled roll to obtain flaky glass flakes. Thereafter, the glass flakes are pulverized with a ball mill or the like to a predetermined average particle diameter to obtain a powdery glass composition.

［実施形態２］
実施形態２は、半導体装置の製造方法に係る実施形態である。[Embodiment 2]
The second embodiment is an embodiment according to a method for manufacturing a semiconductor device.

実施形態２に係る半導体装置の製造方法は、ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子を準備する第１工程と、ｐｎ接合露出部を覆うようにガラス層を形成する第２工程とをこの順序で含む半導体装置の製造方法である。そして、当該第２工程においては、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物（実施形態１に係る半導体接合保護用ガラス組成物）を用いてガラス層を形成することとしている。第１工程は、主面に平行なｐｎ接合を備える半導体基体を準備する工程と、半導体基体の一方の表面からｐｎ接合を超える深さの溝を形成することにより、溝の内部にｐｎ接合露出部を形成する工程とを含み、第２工程は、溝の内部におけるｐｎ接合露出部を直接覆うようにガラス層を形成する工程を含む。The manufacturing method of the semiconductor device according to the second embodiment includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion. In this order. In the second step, at least SiO 2 , Al 2 O 3 , MgO, and CaO are contained, and Pb, B, P, As, Sb, Li, and Na are contained. A glass layer is formed using a glass composition for protecting a semiconductor junction that substantially does not contain K (a glass composition for protecting a semiconductor junction according to Embodiment 1). In the first step, a semiconductor substrate having a pn junction parallel to the main surface is prepared, and a groove having a depth exceeding the pn junction is formed from one surface of the semiconductor substrate to expose the pn junction inside the groove. The second step includes a step of forming a glass layer so as to directly cover the pn junction exposed portion inside the groove.

図１及び図２は、実施形態２に係る半導体装置の製造方法を説明するために示す図である。図１（ａ）〜図１（ｄ）及び図２（ａ）〜図２（ｄ）は各工程図である。
実施形態２に係る半導体装置の製造方法は、図１及び図２に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態２に係る半導体装置の製造方法を工程順に説明する。1 and 2 are views for explaining a method of manufacturing a semiconductor device according to the second embodiment. FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D are process diagrams.
As shown in FIGS. 1 and 2, the method for manufacturing a semiconductor device according to the second embodiment includes a “semiconductor substrate forming step”, a “groove forming step”, a “glass layer forming step”, a “photoresist forming step”, “ The “oxide film removing step”, “roughened region forming step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order. The semiconductor device manufacturing method according to the second embodiment will be described below in the order of steps.

（ａ）半導体基体形成工程
まず、ｎ−型半導体基板（ｎ−型シリコン基板）１１０の一方の表面からのｐ型不純物の拡散によりｐ＋型拡散層１１２、他方の表面からのｎ型不純物の拡散によりｎ＋型拡散層１１４を形成して、主面に平行なｐｎ接合が形成された半導体基体を形成する。その後、熱酸化によりｐ＋型拡散層１１２及びｎ＋型拡散層１１４の表面に酸化膜１１６，１１８を形成する（図１（ａ）参照。）。(A) Semiconductor Substrate Formation Step First, p + type diffusion layer 112 is diffused from one surface of n − type semiconductor substrate (n − type silicon substrate) 110, and n type impurities from the other surface are diffused. An n + -type diffusion layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed. Thereafter, oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (see FIG. 1A).

（ｂ）溝形成工程
次に、フォトエッチング法によって、酸化膜１１６の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からｐｎ接合を超える深さの溝１２０を形成する（図１（ｂ）参照。）。(B) Groove Formation Step Next, a predetermined opening is formed at a predetermined portion of the oxide film 116 by a photoetching method. After the oxide film is etched, the semiconductor substrate is subsequently etched to form a groove 120 having a depth exceeding the pn junction from one surface of the semiconductor substrate (see FIG. 1B).

（ｃ）ガラス層形成工程
次に、溝１２０の表面に、電気泳動法により溝１２０の内面及びその近傍の半導体基体表面に実施形態１に係る半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層１２４を形成する（図１（ｃ）参照。）。従って、溝１２０の内部におけるｐｎ接合露出部はガラス層１２４に直接覆われた状態となる。(C) Glass Layer Formation Step Next, a layer made of the glass composition for protecting a semiconductor junction according to the first embodiment is formed on the inner surface of the groove 120 and the semiconductor substrate surface in the vicinity thereof on the surface of the groove 120 by electrophoresis. At the same time, a layer made of the glass composition for protecting a semiconductor junction is baked to form a glass layer 124 for passivation (see FIG. 1C). Therefore, the exposed pn junction in the groove 120 is directly covered with the glass layer 124.

（ｄ）フォトレジスト形成工程
次に、ガラス層１１２の表面を覆うようにフォトレジスト１２６を形成する（図１（ｄ）参照。）。(D) Photoresist Formation Step Next, a photoresist 126 is formed so as to cover the surface of the glass layer 112 (see FIG. 1D).

（ｅ）酸化膜除去工程
次に、フォトレジスト１２６をマスクとして酸化膜１１６のエッチングを行い、Ｎｉめっき電極膜を形成する部位１３０における酸化膜１１６を除去する（図２（ａ）参照。）。(E) Oxide Film Removal Step Next, the oxide film 116 is etched using the photoresist 126 as a mask to remove the oxide film 116 at the site 130 where the Ni plating electrode film is to be formed (see FIG. 2A).

（ｆ）粗面化領域形成工程
次に、Ｎｉめっき電極膜を形成する部位１３０における半導体基体表面の粗面化処理を行い、Ｎｉめっき電極と半導体基体との密着性を高くするための粗面化領域１３２を形成する（図２（ｂ）参照。）。(F) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed. The formation region 132 is formed (see FIG. 2B).

（ｇ）電極形成工程
次に、半導体基体にＮｉめっきを行い、粗面化領域１３２上にアノード電極１３４を形成するとともに、半導体基体の他方の表面にカソード電極１３６を形成する（図２（ｃ）参照。）。(G) Electrode forming step Next, Ni plating is performed on the semiconductor substrate to form the anode electrode 134 on the roughened region 132 and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 2C). )reference.).

（ｈ）半導体基体切断工程
次に、ダイシング等により、ガラス層１２４の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置（ｐｎダイオード）を作成する（図２（ｄ）参照。）。(H) Semiconductor Substrate Cutting Step Next, the semiconductor substrate is cut at the center of the glass layer 124 by dicing or the like to form a semiconductor substrate into a chip, thereby producing a mesa semiconductor device (pn diode) (FIG. 2D). )reference.).

以上のようにして、高耐圧のメサ型半導体装置（実施形態２に係る半導体装置）を製造することができる。   As described above, a high voltage mesa semiconductor device (semiconductor device according to Embodiment 2) can be manufactured.

［実施形態３］
実施形態３は、半導体装置の製造方法に係る実施形態である。[Embodiment 3]
The third embodiment is an embodiment according to a method for manufacturing a semiconductor device.

実施形態３に係る半導体装置の製造方法は、実施形態２に係る半導体装置の製造方法と同様に、ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子を準備する第１工程と、ｐｎ接合露出部を覆うようにガラス層を形成する第２工程とをこの順序で含む半導体装置の製造方法である。そして、当該第２工程においては、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物（実施形態１に係る半導体接合保護用ガラス組成物）を用いてガラス層を形成することとしている。但し、実施形態２に係る半導体装置の製造方法の場合とは異なり、第１工程は、半導体基体の表面にｐｎ接合露出部を形成する工程を含み、第２工程は、半導体基体の表面におけるｐｎ接合露出部を直接覆うようにガラス層を形成する工程とを含む。As in the method for manufacturing a semiconductor device according to the second embodiment, the method for manufacturing a semiconductor device according to the third embodiment includes a first step of preparing a semiconductor element having a pn junction exposed portion where the pn junction is exposed, and pn junction exposure. And a second step of forming a glass layer so as to cover the part in this order. In the second step, at least SiO 2 , Al 2 O 3 , MgO, and CaO are contained, and Pb, B, P, As, Sb, Li, and Na are contained. A glass layer is formed using a glass composition for protecting a semiconductor junction that substantially does not contain K (a glass composition for protecting a semiconductor junction according to Embodiment 1). However, unlike the method of manufacturing the semiconductor device according to the second embodiment, the first step includes a step of forming a pn junction exposed portion on the surface of the semiconductor substrate, and the second step includes a pn on the surface of the semiconductor substrate. Forming a glass layer so as to directly cover the joint exposed portion.

図３及び図４は、実施形態３に係る半導体装置の製造方法を説明するために示す図である。図３（ａ）〜図３（ｃ）及び図４（ａ）〜図４（ｃ）は各工程図である。
実施形態３に係る半導体装置の製造方法は、図３及び図４に示すように、「半導体基体準備工程」、「ｐ＋型拡散層形成工程」、「ｎ＋型拡散層形成工程」、「ガラス層形成工程」、「ガラス層エッチング工程」及び「電極形成工程」をこの順序で実施する。以下、実施形態３に係る半導体装置の製造方法を工程順に説明する。3 and 4 are views for explaining the semiconductor device manufacturing method according to the third embodiment. 3A to FIG. 3C and FIG. 4A to FIG. 4C are process diagrams.
As shown in FIGS. 3 and 4, the method for manufacturing a semiconductor device according to the third embodiment includes a “semiconductor substrate preparation step”, a “p + -type diffusion layer formation step”, an “n + -type diffusion layer formation step”, “ The “glass layer forming step”, “glass layer etching step” and “electrode forming step” are performed in this order. The semiconductor device manufacturing method according to the third embodiment will be described below in the order of steps.

（ａ）半導体基体準備工程
まず、ｎ＋型シリコン基板２１０上にｎ−型エピタキシャル層２１２が積層された半導体基体を準備する（図３（ａ）参照。）。(A) Semiconductor Base Preparation Step First, a semiconductor base in which an n − type epitaxial layer 212 is stacked on an n + type silicon substrate 210 is prepared (see FIG. 3A).

（ｂ）ｐ＋型拡散層形成工程
次に、マスクＭ１を形成した後、当該マスクＭ１を介してｎ−型エピタキシャル層２１２の表面における所定領域にイオン注入法によりｐ型不純物（例えばボロンイオン）を導入する。その後、熱拡散することにより、ｐ＋型拡散層２１４を形成する（図３（ｂ参照。）。(B) Step of forming p + type diffusion layer Next, after forming the mask M1, a p-type impurity (for example, boron ions) is implanted into a predetermined region on the surface of the n − type epitaxial layer 212 through the mask M1. Is introduced. Thereafter, the p + type diffusion layer 214 is formed by thermal diffusion (see FIG. 3B).

（ｃ）ｎ＋型拡散層形成工程
次に、マスクＭ１を除去するとともにマスクＭ２を形成した後、当該マスクＭ２を介してｎ−型エピタキシャル層２１２の表面における所定領域にイオン注入法によりｎ型不純物（例えばヒ素イオン）を導入する。その後、熱拡散することにより、ｎ＋型拡散層２１６を形成する（図３（ｃ）参照。）。(C) n + -type diffusion layer forming step Next, after removing the mask M1 and forming the mask M2, an n - type is formed on the surface of the n − -type epitaxial layer 212 via the mask M2 by ion implantation. Impurities (for example, arsenic ions) are introduced. Thereafter, an n + -type diffusion layer 216 is formed by thermal diffusion (see FIG. 3C).

（ｄ）ガラス層形成工程
次に、マスクＭ２を除去した後、ｎ−型エピタキシャル層２１２の表面に、スピンコート法により、実施形態１に係る半導体接合保護用ガラス組成物からなる層を形成し、その後、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層２１５を形成する（図４（ａ）参照。）。(D) Glass Layer Formation Step Next, after removing the mask M2, a layer made of the glass composition for protecting a semiconductor junction according to Embodiment 1 is formed on the surface of the n − -type epitaxial layer 212 by spin coating. Thereafter, a layer made of the glass composition for protecting a semiconductor junction is baked to form a glass layer 215 for passivation (see FIG. 4A).

（ｅ）ガラス層エッチング工程
次に、ガラス層２１５の表面にマスクＭ３を形成した後、ガラス層のエッチングを行う（図４（ｂ）参照。）。これにより、ｎ−型エピタキシャル層２１２の表面における所定領域にガラス層２１７が形成されることとなる。 (E) Glass Layer Etching Step Next, after the mask M3 is formed on the surface of the glass layer 215, the glass layer is etched (see FIG. 4B). As a result, the glass layer 217 is formed in a predetermined region on the surface of the n − type epitaxial layer 212.

（ｆ）電極形成工程
次に、マスクＭ３を除去した後、半導体基体の表面におけるガラス層２１６で囲まれた領域にアノード電極２１８を形成するとともに、半導体基体の裏面にカソード電極２２０を形成する（図４（ｃ）参照。）。(F) Electrode Formation Step Next, after removing the mask M3, the anode electrode 218 is formed in the region surrounded by the glass layer 216 on the surface of the semiconductor substrate, and the cathode electrode 220 is formed on the back surface of the semiconductor substrate ( (Refer FIG.4 (c)).

以上のようにして、高耐圧のプレーナ型半導体装置（実施形態３に係る半導体装置）を製造することができる。   As described above, a high breakdown voltage planar semiconductor device (semiconductor device according to Embodiment 3) can be manufactured.

［実施例］
１．試料の調整
図５は、実施例の結果を示す図表である。実施例１並びに比較例１及び２に示す組成比（図５参照。）になるように原料を調合し、混合機でよく攪拌した後、その混合した原料を電気炉中で１５５０℃まで上昇させた白金ルツボに入れ、２時間溶融させた。その後、融液を水冷ロールに流し出して薄片状のガラスフレークを得た。このガラスフレークをボールミルで平均粒径が５μｍとなるまで粉砕して、粉末状のガラス組成物を得た。[Example]
1. Sample Adjustment FIG. 5 is a chart showing the results of Examples. The raw materials were prepared so as to have the composition ratios shown in Example 1 and Comparative Examples 1 and 2 (see FIG. 5), stirred well with a mixer, and then the mixed raw materials were raised to 1550 ° C. in an electric furnace. It was put in a platinum crucible and melted for 2 hours. Thereafter, the melt was poured into a water-cooled roll to obtain flaky glass flakes. The glass flakes were pulverized with a ball mill until the average particle size became 5 μm to obtain a powdery glass composition.

なお、実施例において使用した原料は、ＳｉＯ２、Ａｌ（ＯＨ）３、Ｍｇ（ＯＨ）２、ＣａＣＯ３、ＰｂＯ、ＺｎＯ、Ｈ３ＢＯ３である。Incidentally, raw materials used in the examples, SiO 2, Al (OH) 3, Mg (OH) 2, CaCO 3, PbO, ZnO, an H 3 BO 3.

２．上記方法により得た各ガラス組成物を以下の評価方法により評価した。 2. Each glass composition obtained by the above method was evaluated by the following evaluation methods.

（１）評価方法１（環境負荷）
本発明の目的が「鉛を含まないガラス材料を用いて、従来の『珪酸鉛を主成分としたガラス材料』を用いた場合と同様に高耐圧の半導体装置を製造することを可能とする」ことにあるため、鉛成分を含まない場合に「○」の評価を与え、鉛成分を含む場合に「×」の評価を与えた。(1) Evaluation method 1 (environmental load)
The object of the present invention is “to make it possible to manufacture a semiconductor device having a high withstand voltage using a glass material containing no lead as in the case of using a conventional“ glass material mainly composed of lead silicate ”. Therefore, when the lead component is not included, an evaluation of “◯” is given, and when the lead component is included, an evaluation of “x” is given.

（２）評価方法２（焼成温度）
焼成温度が高すぎると製造中の半導体装置に与える影響が大きくなるため、焼成温度が１０５０℃以下である場合に「○」の評価を与え、焼成温度が１０５０℃〜１１００℃の範囲内にある場合に「△」の評価を与え、焼成温度が１１００℃を超える場合に「×」の評価を与えた。(2) Evaluation method 2 (firing temperature)
If the firing temperature is too high, the influence on the semiconductor device being manufactured becomes large. Therefore, when the firing temperature is 1050 ° C. or lower, the evaluation of “◯” is given and the firing temperature is in the range of 1050 ° C. to 1100 ° C. In this case, an evaluation of “Δ” was given, and an evaluation of “x” was given when the firing temperature exceeded 1100 ° C.

（３）評価方法３（耐薬品性）
ガラス組成物が王水、めっき液及びフッ酸のすべてに対して難溶性を示す場合に「○」の評価を与え、王水、めっき液及びフッ酸のいずれかに対して溶解性を示す場合に「×」の評価を与えた。(3) Evaluation method 3 (chemical resistance)
When the glass composition is poorly soluble in all of aqua regia, plating solution and hydrofluoric acid, it is evaluated as “◯”, and it is soluble in any of aqua regia, plating solution and hydrofluoric acid. Was given an “x” rating.

（４）評価方法４（平均熱膨張率）
５０℃〜５５０℃におけるガラス組成物の平均熱膨張率とシリコンの平均熱膨張率（３．７３×１０−６）との差が「０．５×１０−６」以下の場合に「○」の評価を与え、当該差が「０．５×１０−６〜１．０×１０−６」の範囲内にある場合に「△」の評価を与え、当該差が「１．０×１０−６」を超える場合に「×」の評価を与えた。(4) Evaluation method 4 (average coefficient of thermal expansion)
“◯” when the difference between the average thermal expansion coefficient of the glass composition at 50 ° C. to 550 ° C. and the average thermal expansion coefficient of silicon (3.73 × 10 −6 ) is “0.5 × 10 −6 ” or less. When the difference is in the range of “0.5 × 10 −6 to 1.0 × 10 −6 ”, an evaluation of “Δ” is given, and the difference is “1.0 × 10 − A rating of “x” was given if it exceeded 6 ”.

（５）評価方法５（絶縁性）
実施形態２に係る半導体装置の製造方法と同様の方法によって半導体装置（ｐｎダイオード）を作製し、作製した半導体装置の逆方向特性を測定した。その結果、半導体装置の逆方向特性が正常である場合に「○」の評価を与え、半導体装置の逆方向特性が異常である場合に「×」の評価を与えた。(5) Evaluation method 5 (insulating property)
A semiconductor device (pn diode) was manufactured by the same method as the method for manufacturing a semiconductor device according to Embodiment 2, and the reverse characteristics of the manufactured semiconductor device were measured. As a result, an evaluation of “◯” was given when the reverse direction characteristic of the semiconductor device was normal, and an evaluation of “x” was given when the reverse direction characteristic of the semiconductor device was abnormal.

（６）総合評価
上記した評価方法１〜５についての各評価がすべて「○」の場合に「○」の評価を与え、各評価のうち１つでも「△」がある場合に「△」の評価を与え、各評価のうち１つでも「×」がある場合に「×」の評価を与えた。(6) Comprehensive evaluation When each of the above evaluation methods 1 to 5 is “◯”, the evaluation is “○”, and when any one of the evaluations has “△”, “△” An evaluation was given, and an evaluation of “x” was given when there was “x” in any one of the evaluations.

３．評価結果
図５からも分かるように、比較例１に係るガラス組成物は、評価項目１で「×」の評価が得られた。また、比較例２に係るガラス組成物は、評価項目３で「×」の評価が得られた。これに対して、実施例１に係るガラス組成物は、いずれの評価項目（評価項目１〜５）についても「○」の評価が得られた。その結果、実施形１に係るガラス組成物は、鉛を含まないガラス材料でありながら、（ａ）適正な温度（例えば１０５０℃以下）で焼成できること、（ｂ）工程で使用する薬品に耐えること、（ｃ）シリコンに近い熱膨張係数を有すること及び（ｄ）優れた絶縁性を有することという条件をすべて満たすガラス組成物であることが分かった。3. Evaluation Results As can be seen from FIG. 5, the glass composition according to Comparative Example 1 was evaluated as “x” in Evaluation Item 1. The glass composition according to Comparative Example 2 was evaluated as “x” in Evaluation Item 3. On the other hand, the evaluation of "(circle)" was obtained about the glass composition which concerns on Example 1 about any evaluation item (evaluation items 1-5). As a result, the glass composition according to Embodiment 1 is a glass material that does not contain lead, but (a) can be fired at an appropriate temperature (for example, 1050 ° C. or less), and (b) can withstand the chemicals used in the step. It was found that the glass composition satisfies all the conditions of (c) having a thermal expansion coefficient close to that of silicon and (d) having excellent insulating properties.

以上、本発明の半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置を上記の実施形態に基づいて説明したが、本発明はこれに限定されるものではなく、その要旨を逸脱しない範囲において実施することが可能であり、例えば次のような変形も可能である。   As mentioned above, although the glass composition for semiconductor junction protection of this invention, the manufacturing method of the semiconductor device, and the semiconductor device were demonstrated based on said embodiment, this invention is not limited to this and does not deviate from the summary. For example, the following modifications are possible.

（１）上記の実施形態２においては、第２工程において、溝の内部におけるｐｎ接合露出部を直接覆うようにガラス層を形成したが、本発明はこれに限定されるものではない。例えば、溝の内部におけるｐｎ接合露出部上に絶縁膜を形成し、その後、当該絶縁膜を介してｐｎ接合露出部を覆うようにガラス層を形成してもよい。 (1) In the second embodiment, the glass layer is formed in the second step so as to directly cover the exposed pn junction in the groove, but the present invention is not limited to this. For example, an insulating film may be formed on the pn junction exposed portion inside the trench, and then a glass layer may be formed so as to cover the pn junction exposed portion via the insulating film.

（２）上記の実施形態３においては、第２工程において、半導体基体の表面におけるｐｎ接合露出部を直接覆うようにガラス層を形成したが、本発明はこれに限定されるものではない。例えば、半導体基体の表面におけるｐｎ接合露出部上に絶縁膜を形成し、その後、当該絶縁膜を介してｐｎ接合露出部を覆うようにガラス層を形成してもよい。 (2) In the third embodiment, the glass layer is formed in the second step so as to directly cover the exposed pn junction on the surface of the semiconductor substrate, but the present invention is not limited to this. For example, an insulating film may be formed on the exposed pn junction on the surface of the semiconductor substrate, and then a glass layer may be formed so as to cover the exposed pn junction via the insulating film.

１００，２００，９００…半導体装置、１１０，９１０…ｎ−型半導体基板、１１２，９１２…ｐ＋型拡散層、１１４，９１４…ｎ−型拡散層、１１６，１１８，９１６，９１８…酸化膜、１２０，９２０…溝、１２４，９２４…ガラス層、１２６，９２６…フォトレジスト、１３０，９３０…Ｎｉめっき電極膜を形成する部位、１３２，９３２…粗面化領域、１３４，９３４…アノード電極、１３６，９３６…カソード電極、２１０…ｎ＋型半導体基板、２１２…ｎ−型エピタキシャル層、２１４…ｐ＋型拡散層、２１５，２１７…ガラス層、２１６…ｎ ＋ 型拡散層、２１８…アノード電極層、２２０…カソード電極層 100,200,900 ... semiconductor device, 110,910 ... n - -type semiconductor substrate, 112,912 ... p + -type diffusion layer, 114,914 ... n - -type diffusion layer, 116,118,916,918 ... oxide film, 120, 920... Groove, 124, 924... Glass layer, 126, 926... Photoresist, 130, 930... Ni plating electrode film forming portion, 132, 932 ... roughened region, 134, 934. , 936 ... cathode electrode, 210 ... n + type semiconductor substrate, 212 ... n - type epitaxial layer, 214 ... p + type diffusion layer, 215 , 217 ... glass layer, 216 ... n + type diffusion layer , 218 ... anode electrode layer 220 ... Cathode electrode layer

Claims (12)

少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しないことを特徴とする半導体接合保護用ガラス組成物。Contains at least SiO 2 , Al 2 O 3 , MgO, and CaO, and substantially contains Pb, B, P, As, Sb, Li, Na, and K The glass composition for semiconductor junction protection characterized by not performing. ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、
Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることを特徴とする請求項１に記載の半導体接合保護用ガラス組成物。The content of SiO 2 is within the range of 53mol% ~73mol%,
The content of Al 2 O 3 is in the range of 11 mol% to 21 mol%,
The content of MgO is in the range of 11 mol% to 21 mol%,
The glass composition for protecting a semiconductor junction according to claim 1, wherein the content of CaO is in the range of 3 mol% to 6 mol%. ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子を準備する第１工程と、
前記ｐｎ接合露出部を覆うようにガラス層を形成する第２工程とをこの順序で含む半導体装置の製造方法であって、
前記第２工程においては、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物を用いて前記ガラス層を形成することを特徴とする半導体装置の製造方法。a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed;
And a second step of forming a glass layer so as to cover the exposed portion of the pn junction in this order,
In the second step, at least SiO 2 , Al 2 O 3 , MgO, and CaO are contained, and Pb, B, P, As, Sb, Li, Na, A method for producing a semiconductor device, wherein the glass layer is formed using a glass composition for protecting a semiconductor junction substantially not containing K. 前記第１工程は、主面に平行なｐｎ接合を備える半導体基体を準備する工程と、前記半導体基体の一方の表面から前記ｐｎ接合を超える深さの溝を形成することにより、前記溝の内部に前記ｐｎ接合露出部を形成する工程とを含み、
前記第２工程は、前記溝の内部における前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項３に記載の半導体装置の製造方法。The first step includes preparing a semiconductor substrate having a pn junction parallel to the main surface, and forming a groove having a depth exceeding the pn junction from one surface of the semiconductor substrate. Forming the pn junction exposed portion in
The method of manufacturing a semiconductor device according to claim 3, wherein the second step includes a step of forming the glass layer so as to cover the pn junction exposed portion inside the groove. 前記第２工程は、前記溝の内部における前記ｐｎ接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項４に記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 4, wherein the second step includes a step of forming the glass layer so as to directly cover the pn junction exposed portion inside the groove. 前記第２工程は、前記溝の内部における前記ｐｎ接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項４に記載の半導体装置の製造方法。  The second step includes a step of forming an insulating film on the pn junction exposed portion inside the groove, and a step of forming the glass layer so as to cover the pn junction exposed portion via the insulating film. The method of manufacturing a semiconductor device according to claim 4, further comprising: 前記第１工程は、半導体基体の表面に前記ｐｎ接合露出部を形成する工程を含み、
前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項３に記載の半導体装置の製造方法。The first step includes a step of forming the pn junction exposed portion on a surface of a semiconductor substrate,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the second step includes a step of forming the glass layer so as to cover the pn junction exposed portion on the surface of the semiconductor substrate. 前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項７に記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 7, wherein the second step includes a step of forming the glass layer so as to directly cover the pn junction exposed portion on the surface of the semiconductor substrate. 前記第２工程は、前記半導体基体の表面における前記ｐｎ接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記ｐｎ接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項７に記載の半導体装置の製造方法。  The second step includes a step of forming an insulating film on the pn junction exposed portion on the surface of the semiconductor substrate, and a step of forming the glass layer so as to cover the pn junction exposed portion via the insulating film. The method of manufacturing a semiconductor device according to claim 7, comprising: 前記半導体接合保護用ガラス組成物は、
ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、
Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることを特徴とする請求項３〜９のいずれかに記載の半導体装置の製造方法。The semiconductor bonding protective glass composition is:
The content of SiO 2 is within the range of 53mol% ~73mol%,
The content of Al 2 O 3 is in the range of 11 mol% to 21 mol%,
The content of MgO is in the range of 11 mol% to 21 mol%,
The method for manufacturing a semiconductor device according to claim 3, wherein the content of CaO is in the range of 3 mol% to 6 mol%. ｐｎ接合が露出するｐｎ接合露出部を有する半導体素子と、
前記ｐｎ接合露出部を覆うように形成されたガラス層とを備える半導体装置であって、
前記ガラス層は、少なくともＳｉＯ２と、Ａｌ２Ｏ３と、ＭｇＯと、ＣａＯとを含有し、かつ、Ｐｂと、Ｂと、Ｐと、Ａｓと、Ｓｂと、Ｌｉと、Ｎａと、Ｋとを実質的に含有しない半導体接合保護用ガラス組成物を用いて形成されたものであることを特徴とする半導体装置。a semiconductor element having a pn junction exposed portion where the pn junction is exposed;
A semiconductor device comprising a glass layer formed to cover the pn junction exposed portion,
The glass layer contains at least SiO 2 , Al 2 O 3 , MgO and CaO, and Pb, B, P, As, Sb, Li, Na, K and A semiconductor device characterized by being formed using a glass composition for protecting a semiconductor junction that does not substantially contain. 前記半導体接合保護用ガラス組成物は、
ＳｉＯ２の含有量が５３ｍｏｌ％〜７３ｍｏｌ％の範囲内にあり、
Ａｌ２Ｏ３の含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＭｇＯの含有量が１１ｍｏｌ％〜２１ｍｏｌ％の範囲内にあり、
ＣａＯの含有量が３ｍｏｌ％〜６ｍｏｌ％の範囲内にあることを特徴とする請求項１１に記載の半導体装置。The semiconductor bonding protective glass composition is:
The content of SiO 2 is within the range of 53mol% ~73mol%,
The content of Al 2 O 3 is in the range of 11 mol% to 21 mol%,
The content of MgO is in the range of 11 mol% to 21 mol%,
The semiconductor device according to claim 11, wherein the content of CaO is in a range of 3 mol% to 6 mol%.
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