JP4981006B2 - 仮想計算機を制御する方法及びシステム - Google Patents
仮想計算機を制御する方法及びシステム Download PDFInfo
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- JP4981006B2 JP4981006B2 JP2008242682A JP2008242682A JP4981006B2 JP 4981006 B2 JP4981006 B2 JP 4981006B2 JP 2008242682 A JP2008242682 A JP 2008242682A JP 2008242682 A JP2008242682 A JP 2008242682A JP 4981006 B2 JP4981006 B2 JP 4981006B2
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- vmcs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45591—Monitoring or debugging support
Description
添付図面を参照し、該添付図面は本明細書及び特許請求の範囲の一部分を構成し、該添付図面では、本発明の特定の実施例を実施し得るうえでの制約ではなく、本発明特定の実施例を例示的に表す。この実施例は、当業者が理解し、実施することを可能にするのに十分詳細に記載されており、別の実施例を利用し得ることとし、本願の開示の趣旨及び範囲から逸脱することなく、構造的な変更、論理的な変更、又は物理的な変更を行い得ることとする。下記の詳細の説明は、よって、限定する意味合いで解されるものでないこととし、本明細書及び特許請求の範囲開示の本発明の実施例の範囲は本特許請求の範囲によってのみ規定される。
● VMCSロード・ポインタ命令はメモリ・アドレスをオペランドとして有する。このアドレスは、プロセッサ112がVMCS(例えば、VMCS領域118の始点)を記憶可能な場所である。このアドレスと関連したVMCSは命令によってアクティブ状態にされる。この命令は、VMCSに関連し、VMCSによって制御されるVM(例えば、130、140、又は150)の起動と、以下の種々の別の命令の利用とを可能にするものでもある。一実施例では、アドレスは物理アドレスである。別の実施例は、仮想アドレス又は線形アドレスを用い得る。
● VMCS記憶ポインタ命令は、アクティブ状態のVMCS領域118へのポインタを(例えば、プロセッサ112上の)レジスタ又は(例えば、メモリ116における)メモリ位置に記憶させる。そのような記憶場所の位置は、命令に対するオペランドとして備え得る。
● VMCS読み取り命令は、VMCSの構成部分を(例えば、プロセッサ112上の)レジスタ又は(例えば、メモリ116における)メモリ位置に読み込む。命令は、VMCSから読み取る対象のVMCS構成部分と、VMCSから読み取られるデータを記憶する対象の場所(例えば、レジスタ又はメモリ位置)とを示す構成部分識別子を含む、いくつかのパラメータを含み得る。
● VMCS書き込み命令は、VMCSの構成部分を、(例えば、プロセッサ112上の)レジスタ又は(例えば、メモリ116における)メモリ位置からロードする。VMCS読み取り命令のように、VMCS書き込み命令はVMCS構成部分識別子のオペランドを含み得る。更に、VMCS書き込み命令は、VMCSに書き込む対象のデータの場所(例えば、レジスタ又はメモリ位置)を記述するオペランドを含み得る。
● VMCSクリア命令は、VMCSに関連したプロセッサ上の記憶機構の全ての内容がVMCS領域118にもう一度記憶され、プロセッサ上の資源におけるデータを無効化し、更にVMCSポインタを非活動化するようにしている。この命令は、現在アクティブ状態にあるVMCSポインタを消去し、非活動化して、オペランドなしで動作することが可能であるか、別の実施例では、この命令はオペランドとして、消去と非活動化が必要なVMCSポインタをとり得る。実施例では、VMCSクリア命令は、アーキテクチャ的又は非アーキテクチャ的に定義される状態表示子をVMCS領域に書き込むことによってVMCSを非アクティブ状態としてマーキングし得る。
● 最後に、VMCS入力命令は、VMアーキテクチャ100の意味論とVMCSの内容によってプロセッサ状態をロードすることによって、アクティブ状態のVMCSによって定義されるVM(例えば、130、140、150)に制御(すなわち、VMエントリ)を移すことをもたらす。あるいは、命令は、入力される対象のVMCSポインタ(又は該ポインタの位置)を備えている引数を含み得る。
110 ベース・プラットフォーム・ハードウェア
112 プロセッサ
114 VMCSキャッシュ
116 メモリ
118 VMCS領域
120 VMM
130 VM
140 VM
150 VM
150 OS
152 アプリケーション
160 OS
162 アプリケーション
170 OS
172 アプリケーション
Claims (13)
- 仮想計算機制御構造(VMCS)をアクセスする方法であって:
仮想計算機モニタ(VMM)によって、VMCSアクセス命令を実行する工程;及び
該VMCSアクセス命令に関連した、VMCS構成部分の識別子を用いて、VMCS構成部分をプロセッサによってアクセスする工程;
を備え、
該VMCS構成部分は、ゲストが実行することをVMMが妨げようとする条件を示す制御情報を含むことを特徴とする方法。 - 請求項1記載の方法であって、該VMCS構成部分をアクセスする工程において:
該VMCS構成部分の識別子が、該VMCSアクセス命令に対する明示オペランドと、該VMCSアクセス命令に対する非明示オペランドとのうちの少なくとも1つであることを特徴とする方法。 - 請求項1記載の方法であって、該VMCSアクセス命令を実行する工程において:
該VMCSアクセス命令が、該VMCS構成部分からの読み取り命令と、該VMCS構成部分に対する書き込み命令とのうちの少なくとも1つであることを特徴とする方法。 - 請求項3記載の方法であって、該VMCSアクセス命令を実行する工程において:
該VMCSアクセス命令が該VMCS構成部分に対する書き込み命令であり;
該VMCSアクセス命令が書き込みデータ値をオペランドとして含むことを特徴とする方法。 - 請求項4記載の方法であって、該VMCSアクセス命令を実行する工程において:
該書き込みデータ値の形式がアーキテクチャ的に定義されたデータ形式であることを特徴とする方法。 - 請求項4記載の方法であって、更に:
該書き込みデータ値を該VMCS構成部分に書き込む工程;
を備えることを特徴とする方法。 - 請求項1記載の方法であって、更に:
該VMCS構成部分がメモリに存在するということを判定する工程;及び
該VMCS構成部分のメモリ位置を計算する工程
を備えることを特徴とする方法。 - 請求項1記載の方法であって、更に:
該VMCS構成部分がプロセッサ上の記憶機構に存在するということを判定する工程
を備えることを特徴とする方法。 - 請求項1記載の方法であって、該VMCSアクセス命令を実行する工程において:
該VMCSアクセス命令が該VMCS構成部分からの読み取り命令であり;
該VMCS構成部分をアクセスする工程が更に:
該VMCS構成部分に関連したデータを読み取る工程;及び
該VMCS構成部分に関連した該データを該VMMに戻す工程;
を備えることを特徴とする方法。 - 請求項9記載の方法であって、該VMCS構成部分に関連した該データを該VMMに戻す工程が:
該VMCS構成部分に関連した該データを、該VMCS構成部分のアーキテクチャ的に定義されたデータ形式に一致させるよう再フォーマティングする工程;
戻りデータ値を生成する工程;及び
該戻りデータ値を該VMMに戻す工程;
を含むことを特徴とする方法。 - 請求項9記載の方法であって、該VMCS構成部分に関連した該データを該VMMに戻す工程において:
該データの形式が、該VMCS構成部分のアーキテクチャ的に定義されたデータ形式と同じ形式と、該VMCS構成部分のアーキテクチャ的に定義されたデータ形式とは異なる形式とのうちの少なくとも1つである形式であることを特徴とする方法。 - 請求項11記載の方法であって、更に:
該VMCS構成部分の実施形態特有データ形式に一致させるよう該書き込みデータを再フォーマティングする工程;
を備え;
該再フォーマティングの結果、再フォーマティング書き込みデータ値がもたらされ;
更に、該再フォーマティング書き込みデータ値を該VMCS構成部分に書き込む工程;
を備えることを特徴とする方法。 - 請求項12記載の方法であって、該書き込みデータを再フォーマティングする工程において:
該VMCS構成部分の実施形態特有データ形式が、該VMCS構成部分のアーキテクチャ的に定義された形式と同じ形式と、該VMCS構成部分のアーキテクチャ的に定義されたデータ形式とは異なる形式とのうちの少なくとも1つであることを特徴とする方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/322,003 | 2002-12-17 | ||
US10/322,003 US7318141B2 (en) | 2002-12-17 | 2002-12-17 | Methods and systems to control virtual machines |
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JP2004564979A Division JP2006516769A (ja) | 2002-12-17 | 2003-11-12 | 仮想計算機を制御する方法及びシステム |
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JP2009054169A JP2009054169A (ja) | 2009-03-12 |
JP4981006B2 true JP4981006B2 (ja) | 2012-07-18 |
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JP2004564979A Withdrawn JP2006516769A (ja) | 2002-12-17 | 2003-11-12 | 仮想計算機を制御する方法及びシステム |
JP2008242682A Expired - Fee Related JP4981006B2 (ja) | 2002-12-17 | 2008-09-22 | 仮想計算機を制御する方法及びシステム |
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JP2004564979A Withdrawn JP2006516769A (ja) | 2002-12-17 | 2003-11-12 | 仮想計算機を制御する方法及びシステム |
Country Status (8)
Country | Link |
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US (1) | US7318141B2 (ja) |
JP (2) | JP2006516769A (ja) |
KR (1) | KR100847613B1 (ja) |
CN (1) | CN100504789C (ja) |
AU (1) | AU2003290857A1 (ja) |
DE (1) | DE10393920B4 (ja) |
TW (1) | TWI273493B (ja) |
WO (1) | WO2004061645A2 (ja) |
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US7318141B2 (en) | 2008-01-08 |
KR100847613B1 (ko) | 2008-07-21 |
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DE10393920T5 (de) | 2005-12-29 |
WO2004061645A3 (en) | 2006-03-30 |
AU2003290857A1 (en) | 2004-07-29 |
CN1833225A (zh) | 2006-09-13 |
JP2006516769A (ja) | 2006-07-06 |
TW200416604A (en) | 2004-09-01 |
CN100504789C (zh) | 2009-06-24 |
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TWI273493B (en) | 2007-02-11 |
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