JP4980652B2 - Charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit that generates a negative voltage, and more particularly, to a charge pump circuit that is constructed with only a low-cost bipolar transistor that is stable at the time of start-up by constant current source driving.

  FIG. 5 shows an example of a conventional charge pump circuit composed of BiCMOS and generating a negative voltage. The circuit configuration includes a PMOSFET 10 and NMOSFETs 20, 30, and 40 that perform charging and discharging operations of the charge pump, and a control circuit 50. In this example, the inside of the dotted line is an IC, and the capacitor C1 for charge accumulation and the capacitor C2 for absorption are externally attached via IC pins 1-3. A positive power source potential Vcc (terminal is not shown) is supplied from the outside as a power source, and a negative voltage generated by the charge pump circuit is supplied to the control circuit 50 and the signal processing circuit 60 as a negative power source potential Vee.

  FIG. 4 shows the input waveforms of the FETs (FETs 10, 20, 30, 40) in the waveform diagram of the internal input terminals (FIG. 4 shares the waveform diagrams of the conventional example and the embodiment of the present invention). FET 10 and FET 30 are simultaneously turned on (the input waveform is in reverse phase, but both are on in the same phase in terms of conduction and non-conduction), and after charging the capacitor C1, the FETs 20 and 40 are simultaneously turned on. The capacitor C1 is moved and absorbed by the capacitor C2. This operation is repeated to generate a negative voltage at the IC pin 3 and supply the negative voltage to the signal processing circuit 60 as the negative power supply potential Vee to drive the signal processing circuit 60. At the same time, the negative voltage is supplied to the control circuit 50 as the negative power supply potential Vee, and the LOW voltage of the waveform for driving each FET is level-shifted corresponding to the negative voltage of the IC pin 3 and driven. Thus, in the charge pump circuit constituted by the MOSFET, a level shift circuit or the like is required in the control circuit 50. Further, if the signal processing circuit 60 is a bipolar circuit, a BiCMOS process is essential.

A charge pump circuit composed of such a MOSFET is generally widely used. For example, FIG. 5 of Patent Document 1 and FIG. 31 of Patent Document 2 also describe a similar circuit.
JP 2003-235245 A JP 2005-12904 A

  As described above, when a MOSFET and a bipolar transistor are mixed as a charge pump circuit for generating a negative voltage, a level shift circuit or the like is required in the control circuit, resulting in an increase in circuit scale and a BiCMOS process. Therefore, there is a problem that the manufacturing process is complicated and expensive as a semiconductor integrated circuit. Further, when the electric charge charged in the capacitor C1 moves to the capacitor C2, it is necessary to prevent an excessive current from flowing instantaneously and to increase the generation efficiency of the negative voltage. Further, at the time of start-up, since the capacitors are not sufficiently charged, there is a possibility that the operation becomes unstable such as a risk of latch-up.

  In order to solve the above-described problems, the present invention provides a charge pump circuit that has a small circuit scale and a low manufacturing process, increases the negative voltage generation efficiency during steady operation, and performs stable operation during startup. The purpose is to provide.

In order to achieve the above object, the invention according to claim 1 of the present application includes: a positive power supply terminal to which a positive power supply potential is supplied; a ground terminal to which a ground potential is supplied; First and third transistors connected in series from the positive power supply terminal side to the ground terminal side between the positive power supply terminal and the ground terminal, and the negative power supply terminal side between the negative power supply terminal and the ground terminal Connected between the connection point of the first and third transistors and the connection point of the second and fourth transistors. ON / OFF operation of the first capacitor, the second capacitor connected between the negative power supply terminal and the ground terminal, the ON / OFF operation of the first and second transistors, and ON / OFF of the third and fourth transistors Reverse phase operation alternately A control circuit for driving, in the charge pump circuit Ru wherein the control circuit, the fourth connecting the constant current source to the base of the transistor, said fourth transistor by supplying a current from a constant current source Is a circuit that turns on the power.

According to a second aspect of the present invention, in the charge pump circuit according to the first aspect, a diode is connected to an anode at a connection point between the base of the fourth transistor and the constant current source, and a cathode is connected to the ground terminal. It is characterized by that.

  According to the charge pump circuit of the invention according to claim 1 of the present application, the semiconductor element can be composed of only bipolar transistors. Therefore, an inexpensive charge pump circuit having a small circuit scale and a simplified manufacturing process can be realized.

  According to the charge pump circuit of the invention according to claim 2 of the present application, in addition to the above effect, the efficiency of generating the negative voltage can be controlled by optimizing the constant current source that affects the saturation voltage. Have. In addition, as a secondary effect of providing a constant current source, since a steep current change is suppressed, pulse noise on the negative power supply line is reduced, and the influence on a signal processing circuit such as an amplifier is reduced. Has an effect.

  According to the charge pump circuit of the invention of claim 3 of the present application, in addition to the above effects, circuit malfunction such as saturation of the constant current source can be prevented by adding only one diode element. Therefore, there is an effect that it is possible to avoid the risk of latch-up at the start-up without increasing the circuit scale.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the first invention (Claim 1), FIG. 2 shows an embodiment of the second invention (Claim 2), and FIG. 3 shows a circuit showing an embodiment of the third invention (Claim 3). FIG. The dotted lines in the figure are assumed to be integrated into an IC. FIG. 4 is an input waveform diagram of each transistor for explaining the circuit operation.

  As shown in FIG. 1, the circuit configuration of the first invention comprises a PNP transistor Tr1 and NPN transistors Tr2 to Tr4 for charging / discharging the charge pump, and a control circuit (not shown) for driving them. In this embodiment, a bipolar transistor is used, and the level shift circuit in the control circuit which is necessary when the MOSFET shown in the conventional example is used is not necessary. As a power source, a positive power source potential Vcc (terminal is not shown) is supplied from the outside, and a negative voltage generated by the charge pump circuit is supplied to the signal processing circuit 60 as a negative power source potential Vee. A charge storage capacitor C1 and an absorption capacitor C2 are externally connected via IC pins 1 to 3.

  Next, the operation of the circuit will be described. The output from the control circuit is supplied to the bases of the transistors Tr1 to Tr4 via the internal input terminals 1 to 4 as shown in FIG. A Low signal (not necessarily a negative voltage) is supplied to the input terminal 1 and a High signal is supplied to the input terminal 2 to simultaneously turn on the transistors Tr1 and Tr2 and charge the external capacitor C1. The voltage across the capacitor C1 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr1 and the saturation voltage Vce of the transistor Tr2 from the positive power supply potential Vcc. Therefore, the voltage across the capacitor C1 can be maximized by optimizing each saturation voltage Vce. At this time, the transistors Tr3 and Tr4 are kept off.

  Next, after simultaneously turning off the transistor Tr1 and the transistor Tr2, the transistor Tr3 and the transistor Tr4 are simultaneously saturated on, and the charge of the external capacitor C1 is moved to the external capacitor C2. The voltage across the capacitor C2 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr3 and the saturation voltage Vce of the transistor Tr4 from the voltage across the capacitor C1, and by optimizing each saturation voltage Vce, the voltage across the capacitor C1. Similar to the inter-voltage, the voltage across the capacitor C2 can be maximized. By repeating the above operation, charge is charged up in the capacitor C2 to generate a negative voltage with high generation efficiency, and the negative voltage is supplied to the signal processing circuit 60 as the negative power supply potential Vee.

  As described above, according to the charge pump circuit of the present embodiment, the semiconductor element can be composed of only bipolar transistors. Therefore, an inexpensive charge pump circuit having a small circuit scale and a simplified manufacturing process can be realized.

  As shown in FIG. 2, the circuit configuration of the second invention comprises a PNP transistor Tr1 and NPN transistors Tr2 to Tr4 for charging / discharging the charge pump, and a control circuit (not shown) for driving them. The transistor Tr4 is driven via the constant current source 5 and the constant current source switch SW1. In this embodiment, a bipolar transistor is used, and the level shift circuit in the control circuit which is necessary when the MOSFET shown in the conventional example is used is not necessary. A charge storage capacitor C1 and an absorption capacitor C2 are externally connected via IC pins 1 to 3.

  Next, the operation of the circuit will be described. The output from the control circuit is supplied to the bases of the transistors Tr1 to Tr4 via the internal input terminals 1 to 4 as shown in FIG. A Low signal (not necessarily a negative voltage) is supplied to the input terminal 1 and a High signal is supplied to the input terminal 2 to simultaneously turn on the transistors Tr1 and Tr2 and charge the external capacitor C1. The voltage across the capacitor C1 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr1 and the saturation voltage Vce of the transistor Tr2 from the positive power supply potential Vcc. Therefore, the voltage across the capacitor C1 can be maximized by optimizing each saturation voltage Vce. At this time, the transistors Tr3 and Tr4 are kept off.

  Next, after simultaneously turning off the transistor Tr1 and the transistor Tr2, the transistor Tr3 and the transistor Tr4 are simultaneously saturated on, and the charge of the external capacitor C1 is moved to the external capacitor C2. In this case, when the constant current source switch SW1 is in an on state as shown in FIG. 4, the transistor Tr4 is supplied with a driving current from the constant current source 5 and is in a saturated on state. The voltage across the capacitor C2 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr3 and the saturation voltage Vce of the transistor Tr4 from the voltage across the capacitor C1, and by optimizing each saturation voltage Vce, the voltage across the capacitor C1. Similar to the inter-voltage, the voltage across the capacitor C2 can be maximized. In particular, the saturation voltage Vce of the transistor Tr4 can be controlled by the constant current source 5. By repeating the above operation, charge is charged up in the capacitor C2 to generate a negative voltage with high generation efficiency, and the negative voltage is supplied to the signal processing circuit 60 as the negative power supply potential Vee.

  As described above, according to the charge pump circuit of the present embodiment, the semiconductor element can be composed of only bipolar transistors. Therefore, an inexpensive charge pump circuit having a small circuit scale and a simplified manufacturing process can be realized.

  In addition, it has the effect that the negative voltage generation efficiency can be controlled by optimizing the constant current source that affects the saturation voltage Vce. Further, since a steep current change is suppressed as a secondary effect by providing the constant current source 5, pulse noise on the negative power supply line is reduced, and the signal processing circuit 60 such as an amplifier is less affected. It has the effect of becoming.

  The circuit configuration of the third invention is the same as the circuit configuration of FIG. 2 except that a diode-connected NPN transistor Tr5 connected between the base of the NPN transistor Tr4 and the ground potential is added as shown in FIG. .

  Next, the operation of the circuit in the steady state will be described. The output from the control circuit is supplied to the bases of the transistors Tr1 to Tr4 via the internal input terminals 1 to 4 as shown in FIG. A Low signal (not necessarily a negative voltage) is supplied to the input terminal 1 and a High signal is supplied to the input terminal 2 to simultaneously turn on the transistors Tr1 and Tr2 to charge the external capacitor C1. The voltage across the capacitor C1 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr1 and the saturation voltage Vce of the transistor Tr2 from the positive power supply potential Vcc. Therefore, the voltage across the capacitor C1 can be maximized by optimizing each saturation voltage Vce. At this time, the transistors Tr3 and Tr4 are kept off.

  Next, after simultaneously turning off the transistor Tr1 and the transistor Tr2, the transistor Tr3 and the transistor Tr4 are simultaneously saturated on, and the charge of the external capacitor C1 is moved to the external capacitor C2. In this case, when the constant current source switch SW1 is in an on state as shown in FIG. 4, the transistor Tr4 is supplied with a driving current from the constant current source 5 and is in a saturated on state. The voltage across the capacitor C2 at this time is a value obtained by subtracting the saturation voltage Vce of the transistor Tr3 and the saturation voltage Vce of the transistor Tr4 from the voltage across the capacitor C1, and by optimizing each saturation voltage Vce, the voltage across the capacitor C1. Similar to the inter-voltage, the voltage across the capacitor C2 can be maximized. In particular, the saturation voltage Vce of the transistor Tr4 can be controlled by the constant current source 5. By repeating the above operation, charge is charged up in the capacitor C2 to generate a negative voltage with high generation efficiency, and the negative voltage is supplied to the signal processing circuit 60 as the negative power supply potential Vee.

  As described above, the operation of the circuit in the steady state is the same as that of the second embodiment, but the circuit of this embodiment is characterized by the operation at the time of startup.

  At the time of startup when the power is turned on, the capacitors C1 and C2 are not sufficiently charged. For this reason, when the charge of the capacitor C1 is not sufficient, the emitter potential of the transistor Tr4 cannot be lowered even if each transistor is turned on and off to move the charge. In this case, the saturation voltage Vce that can turn on the transistor Tr4 cannot be secured, and the transistor Tr4 remains off. At this time, the current pushed from the constant current source 5 increases the base voltage of the transistor Tr4, which may cause the constant current source 5 to be in a saturated state, and may involve a risk of latch-up.

  In order to prevent this, a diode-connected transistor Tr5 is connected, and current is passed at startup to stabilize the operation. If the capacitor C1 is charged up to obtain a saturation voltage Vce that can turn on the transistor Tr4, the current of the constant current source 5 is supplied as the base current of the transistor Tr4, and the diode-connected transistor Tr5 is turned off. Thus, by adding one diode-connected transistor Tr5 as a starter circuit, the start-up operation is stabilized.

  As described above, according to the charge pump circuit of the present embodiment, the semiconductor element can be composed of only bipolar transistors. Therefore, an inexpensive charge pump circuit having a small circuit scale and a simplified manufacturing process can be realized.

  In addition, it has the effect that the negative voltage generation efficiency can be controlled by optimizing the constant current source that affects the saturation voltage Vce. Further, since a steep current change is suppressed as a secondary effect by providing the constant current source 5, pulse noise on the negative power supply line is reduced, and the signal processing circuit 60 such as an amplifier is less affected. It has the effect of becoming.

  In addition, circuit malfunction such as saturation of the constant current source 5 can be prevented by adding only one diode element. Therefore, there is an effect that it is possible to avoid the risk of latch-up at the start-up without increasing the circuit scale.

  The charge pump circuit of the present invention is capable of high negative voltage generation efficiency and stable operation, and can be constructed with only bipolar in a system circuit in which the control circuit section is bipolar and the charge pump output section uses MOS. Therefore, the effect of cost reduction is great and the utility value is expected to be high.

It is a circuit diagram showing an embodiment of the first invention (claim 1). It is a circuit diagram which shows the Example of 2nd invention (Claim 2). It is a circuit diagram which shows the Example of 3rd invention (Claim 3). It is an input waveform diagram of each transistor explaining the circuit operation. It is a circuit diagram which shows the conventional Example.

Explanation of symbols

1-4, 10, 20, 30, 40; input terminal 5; constant current source 50; control circuit 60; signal processing circuit IC pins 1 to 3; terminal C1, C2; capacitor GND; ground potential SW1; Tr1; PNP transistor Tr2-5; NPN transistor FET10; PMOS FET
FET20, FET30, FET40; NMOS FET
Vcc: Positive power supply potential Vee: Negative power supply potential

Claims (2)

A positive power supply terminal to which a positive power supply potential is supplied, a ground terminal to which a ground potential is supplied, a negative power supply terminal to which a negative power supply potential is output, and the positive power supply terminal side between the positive power supply terminal and the ground terminal. First and third transistors connected in series toward the ground terminal side, and fourth and second transistors connected in series from the negative power supply terminal side to the ground terminal side between the negative power supply terminal and the ground terminal. Two transistors, a first capacitor connected between a connection point of the first and third transistors and a connection point of the second and fourth transistors, and between the negative power supply terminal and the ground terminal a second capacitor connected, the first and on the second transistor, the off operation the third and on the fourth transistor, and a control circuit to be driven in reverse phase alternating-off operation, Ru with a In charge pump circuit Stomach,
The control circuit is a circuit that connects a constant current source to a base of the fourth transistor and supplies the current from the constant current source to turn on the fourth transistor. circuit. The charge pump circuit according to claim 1, wherein
A charge pump circuit comprising a diode that connects an anode at a connection point between a base of the fourth transistor and the constant current source, and a cathode connected to the ground terminal .

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