JP4969513B2 - Data transfer system - Google Patents

Description

  The present invention relates to use arbitration of a PCI (Peripheral Components Interconnect) bus, and relates to a data transfer system and a target device that perform leveling control of data transfer by a plurality of bus masters.

  In conventional bus arbitration in a PCI bus or the like, a bus arbitration algorithm such as a round robin method is used so that a plurality of initiators can use the bus evenly. In the round robin method, the opportunity to acquire the right to use the bus can be given fairly to all initiators connected to the bus.

  FIG. 6 is a block diagram schematically showing a configuration of a conventional data transfer system on the PCI bus, and shows an example of a configuration for performing round-robin bus arbitration. In FIG. 6, the data transfer system 100 includes a bus arbitration unit 101, initiators A and B, and a target device 102, and the initiators A and B and the target device 102 are connected via a PCI bus 103.

  Initiators A and B are devices that transfer data via the PCI bus 103, and the target device 102 is a device that receives data from the initiator A or initiator B via the PCI bus 103. The bus arbitration unit 101 determines which of the initiators A and B connected to the PCI bus 103 should be given the right to use the PCI bus 103, and arbitrates the bus usage right in a round robin manner.

  The bus use requests REQ # 1 to REQ # 3 are request signals for acquiring the right to use the PCI bus 103, and the right to use the bus GNT # 1 to GNT # 3 is the right to use the PCI bus 103 by bus arbitration. It is a grant signal to give. The bus use request REQ # 3 and the bus use right GNT # 3 are a request signal and a grant signal when the target device 102 transfers data to the initiators A and B.

  FIG. 7 is a timing chart showing the bus arbitration operation by the data transfer system in FIG. Bus arbitration in a conventional PCI bus data transfer system will be described with reference to FIGS. Here, it is assumed that the initiators A and B make a data transfer request to the target device 102 and the target device 102 receives the transactions of the initiators A and B.

  When both initiators A and B assert the bus use requests REQ # 1 and REQ # 2 to request use of the PCI bus 103, the bus arbitration unit 101 determines the priority order based on the round-robin bus arbitration algorithm. The bus usage right GNT is asserted to the high initiator, and the PCI bus 103 is used. Here, consider a case where the bus arbitration unit 101 first asserts the bus use right GNT # 1 to the initiator A as shown in FIG.

  The initiator A that has acquired the right to use the bus makes a data transfer request to the target device 102. As shown in FIG. 7, the target device 102 is in a busy state to process a transaction (data transfer) from the initiator A. At this time, data transfer is executed with the initiator A serving as a data transfer initiator.

  When the data transfer to the initiator A is completed, the bus arbitration unit 101 asserts the bus usage right GNT to the next highest priority initiator B based on the round-robin bus arbitration algorithm, and sets the PCI bus 103 to Let it be used. As a result, the initiator B that has acquired the bus use right makes a data transfer request to the target device 102.

  However, as shown in FIG. 7, the target device 102 is busy in response to a data transfer request from the previous initiator A. Therefore, a retry response (data retransfer request) is made to the initiator B. On the other hand, since initiator A has a higher priority than initiator B, the bus arbitration unit 101 gives the bus use right while initiator B is responding to the retry.

  When the target device 102 completes the processing related to the data transfer from the initiator A after the retry response to the initiator B, the target device 102 is not in the busy state. At this time, the initiator A that has acquired the right to use the bus performs data transfer to the target device 102 again. During this time, even if the initiator B acquires the right to use the bus, the target device 102 executes processing related to data transfer from the initiator A and enters a busy state.

  If the combination of transactions shown in FIG. 7 continues, the initiator B continues to receive a retry response from the target device 102 even though both initiator A and initiator B have acquired the bus use right at the same frequency. Therefore, the initiator B cannot perform data transfer for a long time until the data transfer of the initiator A is completed.

  As described above, in round-robin bus arbitration, when a plurality of initiators A and B continuously transfer data to the same target device 102, the initiator data transfer request and the timing at which the target device 102 becomes busy Therefore, the target device that is the data transfer partner is always busy at the timing when the specific initiator acquires the right to use the bus, and data transfer may not be performed for a long time.

  As a technique for solving the above-described problems, there is a bus arbitration circuit described in Patent Document 1, for example. The bus arbitration circuit includes a busy management unit that monitors the busy state of the target system. The busy management unit monitors the busy state of the target device, and stores the initiator and the device number of the target device that have been retried due to the busy state in the storage unit. When the busy state of the target device is released, the right to use the bus is preferentially given to the initiator stored in the storage unit. By doing so, it is possible to prevent data transfer from a specific initiator from being disabled, and the right to use the bus can be given fairly.

JP 2002-366511 A

  As described above, in a conventional data transfer system, when a plurality of initiators continuously transfer data to the same target device, the timing at which the target device becomes busy when round-robin bus arbitration is performed. In some cases, only the transaction of a specific initiator continues to be retried, and there is a problem that the data transfer frequency is not fair even if the bus use right acquisition frequency is the same.

  The bus arbitration circuit of Patent Document 1 has been proposed in order to solve the above-described problem. In addition to the configuration essential for realizing the bus arbitration function, the bus arbitration circuit manages the busy state of the target device. A dedicated device such as a management unit or a storage unit for storing the initiator that has made a retry response is required. For this reason, when the invention of Patent Document 1 is applied to a PCI bus data transfer system, a bus arbitration circuit built in an off-the-shelf host bridge cannot be used as it is, and a circuit corresponding to the dedicated device is used as a host. Must be installed outside the bridge.

  The present invention has been made to solve the above-described problems, and can be used for a data transfer system that can solve the above-described problems in round-robin bus arbitration and can be realized with a simple configuration. The object is to obtain a target device.

Data transfer system according to the invention includes a bus arbitration section that gives a bus access in a round robin fashion in response to a bus use request and a plurality of initiators device accessible via a bus to a target device, the initiator device When a bus use request is output to the bus arbitration unit and a bus use right is obtained from the bus arbitration unit, a data transfer request is obtained from the target device and a data transfer enable notification is obtained from the target device. If, then the data transfer from the initiator device to the target device, the target device has a counter for counting up to a predetermined retry response count set to the number -1 of said plurality of initiator devices, from the initiator device When the data transfer is requested, the target device processes the transferred data. When the target device is busy, the target device makes a retry response to the initiator device, and when the target device is not busy and the counter has not counted the predetermined number of retry responses, the target device A retry response is made to the initiator device and the number of retry responses is counted by the counter. When the target device is not busy and the counter has counted up to a predetermined number of retry responses, the target device In addition to notifying the initiator device that data transfer is possible, the count by the counter is initialized .

According to the present invention, in the bus arbitration round robin scheme, when a plurality of initiator device to continuously transfer data to the same target device, the particular initiator device by a timing where the target device is busy transaction The problem that only keeps retrying can be solved. Further, only by adding a simple configuration to the target device, there is an effect that the system can be realized with a pre-Symbol effect.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a data transfer system according to Embodiment 1 of the present invention, and shows a configuration for performing round-robin bus arbitration. In FIG. 1, the data transfer system 1 according to the first embodiment includes initiators A and B, a bus arbitration unit 2, and a target device 3 connected to the initiators A and B via a PCI bus 7. Further, as a characteristic configuration in the present invention, a bus control unit 5 and a retry insertion unit 6 are provided in the PCI interface unit 4 of the target device 3.

  Initiators (initiator devices) A and B are devices that transfer data via the PCI bus 7. The bus arbitration unit 2 determines which of the initiators A and B connected to the PCI bus 7 is to be given the right to use the PCI bus 7 and arbitrates the bus usage right in a round robin manner.

  The bus use requests REQ # 1 to REQ # 3 are request signals for acquiring the right to use the PCI bus 7, and the right to use the bus GNT # 1 to GNT # 3 is the right to use the PCI bus 7 by bus arbitration. It is a grant signal to give. The bus use request REQ # 3 and the bus use right GNT # 3 are a request signal and a grant signal when the target device 3 transfers data to the initiators A and B.

  The target device (target device) 3 transmits / receives data to / from the initiator A or the initiator B via the PCI bus 7 by the PCI interface unit 4. The PCI interface unit 4 is a component that controls an input / output interface with the PCI bus 7, and includes a bus control unit 5 and a retry insertion unit 6.

  The bus control unit 5 notifies the retry insertion unit 6 of the data transfer request from the PCI bus 7 and the busy state of the target device 3, and the busy information from the retry insertion unit 6 (BUSY2 signal described later in FIG. 2). Based on this, decide whether to accept or retry the transaction.

  The retry insertion unit 6 has a register that holds the number of retry responses, and determines whether to retry a transaction based on information notified from the bus control unit 5 and controls the number of retry responses.

  FIG. 2 is a block diagram schematically showing the configuration of the target device in FIG. 1, and shows the relationship between the PCI interface unit and other functional units in the device. In FIG. 2, a functional unit 8 is a component that processes data received from the initiator A or the initiator B via the PCI bus 7, and determines whether or not it is busy for transaction processing. 5 is monitored.

  The bus control unit 5 includes a target interface unit 9 and an initiator interface unit 10 as an interface between the PCI bus 7 and the function unit 8. The target interface unit 9 is an interface for receiving a transaction from the PCI bus 7 side to the functional unit 8, and is connected to the functional unit 8 via the bus 11 and the signal line 14.

  The bus 11 is a bus that transmits a transaction received from the PCI bus 7 side to the functional unit 8, and the signal line 14 receives the data transfer request REQ signal received from the initiators A and B via the PCI bus 7. And a signal line transmitted to the retry insertion section 6 side.

  The initiator interface unit 10 is an interface for transmitting a transaction from the function unit 8 to the PCI bus 7 side (initiator A, B side), and is connected to the function unit 8 via the bus 12. The bus 12 is a bus that issues a transaction from the functional unit 8 to the PCI bus 7 side.

  The retry insertion unit 6 includes a retry control unit 16, a retry counter 17, and a retry count storage register 18. The retry control unit 16 receives the data transfer request REQ signal, the BUSY1 signal indicating that the function unit 8 is busy, the count value of the retry counter 17, and the value of the retry count storage register 18, and uses FIG. Based on a truth table to be described later, a BUSY2 signal for making a retry response to the PCI bus 7 side is determined, and the value of the retry counter 17 is updated.

  The retry counter 17 is a register in which the number of retry responses is set. The count value is decremented each time a retry response is made, and is initialized with the value of the retry count storage register 18 every time a data transfer transaction is received. In the retry count storage register 18, the number of retry responses is fixedly set as an initial value (a target value for counting by the retry counter 17).

  The initial value of the retry count storage register 18 is determined by the number of devices (devices that can access the target device at the same time by acquiring the bus use right) on the PCI bus 7 and is −1. For example, when there are seven initiators on the bus 7 and it is known in advance that three initiators simultaneously access the target device, the initial value of the retry count storage register 18 is 3-1 = 2.

  The signal line 13 is a signal line that connects the target interface unit 9 and the retry control unit 16 and transmits the BUSY2 signal generated by the retry control unit 16 to the target interface unit 9. The signal line 15 is a signal line that connects between the function unit 8 and the retry control unit 16 and transmits the BUSY1 signal generated by the function unit 8 to the retry control unit 16.

  The signal line 19 connects between the retry control unit 16 and the retry count storage register 18, and reads the value of the retry count storage register 18 by the retry control unit 16 and writes the initial value to the retry count storage register 18. This is a signal line. The signal line 20 connects between the retry control unit 16 and the retry counter 17, and executes the reading of the value of the retry counter 17 and the writing (initialization) of the value of the retry count storage register 18 by the retry control unit 16. This is a signal line.

  FIG. 3 is a diagram showing a truth table as an operation reference of the retry control unit in FIG. In FIG. 3, X represents a value other than 0 (count value of the number of retry responses) stored in the retry counter 17. Y indicates the initial value (the target value of the count by the retry counter 17) stored in the retry count storage register 18. X-1 indicates a case where the count value of the retry counter 17 is decremented by one.

  The retry control unit 16 combines the logical value of the data transfer request REQ signal, the logical value of the BUSY1 signal indicating that the function unit 8 is busy, the count value of the retry counter 17, and the value of the retry count storage register 18. Compared with the truth table in FIG. 3, the value of the BUSY2 signal for performing a retry response to the PCI bus 7 side is determined, and the count value of the retry counter 17 is updated.

Next, the operation will be described.
FIG. 4 is a timing chart showing the bus arbitration operation of the data transfer system according to the first embodiment. FIG. 5 is a flowchart showing the flow of operation by the target device in FIG. These show a case where data transfer is continuously performed from a plurality of initiators A and B to the same target device 3.

  First, the initiators A and B assert bus requests REQ # 1 and REQ # 2 to the bus arbitration unit 2 in order to transfer data to the target device 3. Based on a round-robin bus arbitration algorithm, the bus arbitration unit 2 asserts the bus usage right GNT # 1 to the initiator A having a higher priority, and grants the usage right of the PCI bus 7 to the initiator A. Thereafter, the initiator A transmits a data transfer request REQ signal to the target device 3 via the PCI bus 7.

  In the target device 3, the target interface unit 9 receives the data transfer request REQ signal from the initiator A. The target interface unit 9 transmits the data transfer request REQ signal to the functional unit 8 and the retry control unit 16 of the retry insertion unit 6 via the signal line 14.

  Based on the value of the data transfer request REQ signal, the retry control unit 16 determines whether the target device 3 is receiving a transaction from the PCI bus 7 side (step ST1). Here, when the data transfer request REQ signal (value 0) is input and the PCI interface unit 4 of the target device 3 has not received a transaction, the retry control unit 16 returns to the process of step ST1. The values of the signals and registers at this time are as shown in the column where the REQ signal in the truth table shown in FIG.

  On the other hand, when the data transfer request REQ signal (value 1) is input and it is determined that the PCI interface unit 4 of the target device 3 is receiving a transaction, the retry control unit 16 sends the signal from the function unit 8 via the signal line 20. Based on the value of the inputted BUSY1 signal, it is determined whether or not the functional unit 8 is busy (step ST2).

  At this time, if the function unit 8 is busy, the retry control unit 16 sets the BUSY2 signal for performing a retry response to the PCI bus 7 side to the value 1 (on), and the target interface unit 9 By transmitting to the PCI bus 7 side, a retry response is made (step ST3). Thereafter, the retry control unit 16 returns to the process of step ST1.

  When the function unit 8 is not busy, the retry control unit 16 executes a series of processes C surrounded by a broken line in FIG. 5, which is a process unique to the present invention. Specifically, when it is determined that the function unit 8 is not busy, the retry control unit 16 reads the count value of the retry counter 17 via the signal line 20 and determines whether the count value is 0 or not. Determine (step ST4).

  In step ST4, if the count value of the retry counter 17 is 0, the retry control unit 16 sets the value 0 in the BUSY2 signal and transmits it to the target interface unit 9. The target interface unit 9 notifies the initiator that has acquired the right to use the bus via the PCI bus 7 that data transfer is possible. Thereby, the target device 3 starts data transfer from the initiator via the PCI bus 7 (step ST5).

  When data transfer is started, the retry controller 16 stores the value (Y) of the retry count storage register 18 in the retry counter 17 and initializes it as shown in the truth table of FIG. 3 (step ST6). . Thereafter, the retry control unit 16 returns to the process of step ST1 and repeats the above process.

  On the other hand, when the count value of the retry counter 17 is not 0 in step ST4, the retry control unit 16 sets the value 1 in the BUSY2 signal and transmits it to the target interface unit 9. Upon receiving the BUSY2 signal (value 1), the target interface unit 9 makes a retry response to the initiator that has acquired the right to use the bus via the PCI bus 7 (step ST7).

  Next, the retry control unit 16 decrements the count value of the retry counter 17 by 1 (X-1) (step ST8). Thereafter, the retry control unit 16 returns to the process of step ST1 and repeats the above process until data transfer from all initiators that have received the transaction is completed.

  Conventionally, if the functional unit 8 is busy, a retry response is made. If the functional unit 8 is not busy, data transfer from the initiator is started. In contrast, in the retry control unit 16 according to the first embodiment, if the count value of the retry counter 17 is not 0, the transaction from the initiator is retried regardless of whether the function unit 8 is busy or not. To do.

  In this way, the retry counter 17 is set with the initial value of the retry count storage register 18, and there is a data transfer request from any initiator that has acquired the right to use the PCI bus 7 until this value becomes zero. Also responds with a retry. Note that the initial value is the number of devices (the maximum number of devices that can become initiators after obtaining the right to use the bus) −1, and in the example of FIG.

  In FIG. 4, the target device 3 first receives a transaction (data transfer) from the initiator A, and the functional unit 8 becomes busy. At this time, even if there is a data transfer request from the initiator B, the target device 3 makes a retry response to process the data transfer from the initiator A (step ST3 in FIG. 5).

  In addition, data transfer from the initiator A is started at the count value 0 of the retry counter 17, but after the data transfer starts, the retry control unit 16 retry the value of the retry count storage register 18 (1 in the example of FIG. 4). Set to the counter 17.

  As a result, the functional unit 8 completes the initial transaction processing from the initiator A and is not in a busy state, and the count value (the number of retries) of the retry counter 17 is 1 even when there is a data transfer request from the initiator A. Accordingly, the retry control unit 16 makes a retry response to the initiator A (step ST8 in FIG. 5). At this time, as shown in FIG. 4, the target device 3 is not in a busy state, but is in a ready state in which data transfer from the initiator A is not received.

  When a retry response is sent to the initiator A, the retry control unit 16 decrements the count value (the number of retries) of the retry counter 17 by one. In the example of FIG. 4, since the initial value is 1, the count value is 0. Thereafter, when the target device 3 receives a transaction (data transfer) from the initiator B, the function unit 8 is not busy (ready state) and the count value of the retry counter 17 is 0. Data transfer from is started. As a result, the functional unit 8 processes data transfer from the initiator B.

  Conventionally, the target device that has received the transaction of the initiator A is always busy at the next timing, and as a result, the initiator B that starts the next transaction continues to receive the retry response. As shown in FIG. 4, by responding to the initiator A transaction with a retry, the next initiator B transaction can be responded in a ready state.

  In the above description, the case where two initiators A and B exist on the PCI bus 7 has been described. However, even when there are three or more initiators, the same processing can be performed. For example, it is assumed that there are three initiators A to C (initial value 2), and the priority order of initiator A is the highest in round-robin bus arbitration, followed by initiator B, and then initiator C. .

  First, when the count value of the retry counter 17 is 0, data transfer from the initiator A is started, and the functional unit 8 is in a busy state for data transfer processing with the initiator A. At this time, even if there is a data transfer request from the initiator B, since the functional unit 8 is busy, the initiator B receives a retry response.

  When the data transfer is started, a count value 2 is set in the retry counter 17 and the value of the retry count storage register 18 for the initiator A is decremented by 1 to 1. Note that the value of the retry count storage register 18 for the initiators B and C remains the initial value 2.

  When the function unit 8 completes the data transfer process of the initiator A, the function unit 8 is not in a busy state. At this time, when the initiator C requests data transfer, since the count value 2 is set in the retry counter 17, the initiator C makes a retry response. As a result, the count value of the retry counter 17 is decremented by 1 and becomes 1.

  Thereafter, even if initiator A continues to request data transfer, since the count value 1 is set in retry counter 17, initiator A responds with a retry. As a result, the count value of the retry counter 17 is decremented by 1 and becomes 0. That is, the initiators C and A make a retry response in the ready state of the functional unit 8.

  Subsequently, when there is a data transfer request from the initiator B, since the functional unit 8 is not busy and the count value of the retry counter 17 is 0, data transfer from the initiator B is started. At this time, even if there is a data transfer request from the initiator C, since the functional unit 8 is busy, the initiator C makes a retry response. When the data transfer is started, the value 2 of the retry count storage register 18 for the initiator C is set as the count value of the retry counter 17.

  When the data transfer process of the initiator B is completed, the functional unit 8 is not busy. At this time, even if initiator A makes a data transfer request, since the count value 2 is set in the retry counter 17, the initiator A makes a retry response. As a result, the count value of the retry counter 17 is decremented by 1 and becomes 1.

  After this, even if initiator B continues to request data transfer, since the count value 1 is set in the retry counter 17, the initiator B responds with a retry. As a result, the count value of the retry counter 17 is decremented by 1 and becomes 0. That is, the initiators A and B make a retry response in the ready state of the functional unit 8.

  Subsequently, when there is a data transfer request from the initiator C, since the functional unit 8 is not busy and the count value of the retry counter 17 is 0, data transfer from the initiator C is started. At this time, even if there is a data transfer request from the initiator A, since the functional unit 8 is busy, the initiator A makes a retry response. When the data transfer is started, the value 2 of the retry count storage register 18 for the initiator A is set as the count value of the retry counter 17.

  When the data transfer process of the initiator C is completed, the functional unit 8 is not busy. At this time, even if initiator A makes a data transfer request, since the count value 2 is set in the retry counter 17, the initiator A makes a retry response. As a result, the count value of the retry counter 17 is decremented by 1 and becomes 1.

  In this way, the count value of the number of retry responses changes every time the target device 3 performs data transfer. In other words, the data transfer timing varies. For this reason, even when a plurality of initiators alternately acquire the right to use the bus at the same timing and perform data transfer to the target device 3, it does not get stuck in a specific pattern, and a specific initiator always responds to a retry response. You can avoid the situation of receiving.

  In addition, as described above, the present invention allows the PCI interface unit 4 of the target device 3 to be retried by simply comparing the input signal value and the register value with the bus control unit 5 serving as an interface with the PCI bus 7. This can be realized simply by providing a retry insertion unit 6 that determines whether or not to respond.

  For example, when a data transfer system according to the present invention is realized by combining an off-the-shelf host bridge and a PCI device configured with a programmable device such as an FPGA (Field Programmable Gate Array), the above-described configuration (bus By incorporating the control unit 5 and the retry insertion unit 6), the data transfer opportunities can be leveled.

  As described above, according to the first embodiment, the target device 3 has the retry counter 17 that counts the predetermined number of retry responses, and sequentially transfers data to and from each of the plurality of initiators A and B. In execution, a control signal for making a retry response is output from the time when the data transfer is completed and the busy state is released until the retry counter 17 counts a predetermined number of retry responses, and a retry response is made according to this control signal. . In this way, when multiple initiators continuously transfer data to the same target device 3, the problem that only the transaction of a specific initiator continues to be retried at the timing when the target device 3 becomes busy is solved. can do.

  In addition, the data transfer system 1 having the above-described effects can be realized simply by providing the target device 3 with the bus control unit 5 and the retry insertion unit 6 that can be realized by a simple circuit such as a bus interface, a register, and a comparison circuit. be able to. This makes it possible to use a bus arbitration circuit built in a ready-made host bridge, and can facilitate mounting, reduce costs, and improve versatility.

It is a block diagram which shows the structure of the data transfer system by Embodiment 1 of this invention. FIG. 2 is a block diagram schematically showing a configuration of a target device in FIG. 1. It is a figure which shows the truth table used as the operation | movement reference | standard of the retry control part in FIG. 3 is a timing chart illustrating a bus arbitration operation of the data transfer system according to the first embodiment. It is a flowchart which shows the flow of operation | movement by the target device in FIG. 1 is a block diagram schematically showing a configuration of a conventional data transfer system in a PCI bus. 7 is a timing chart showing a bus arbitration operation by the data transfer system in FIG. 6.

Explanation of symbols

  1 data transfer system, 2 bus arbitration unit, 3 target device (target device), 4 PCI interface unit, 5 bus control unit, 6 retry insertion unit, 7 PCI bus, 8 function unit, 9 target interface unit, 10 initiator interface unit 11, 12 bus, 13, 14, 15, 19, 20 signal line, 16 retry control unit, 17 retry counter (counter), 18 retry count storage register, A, B initiator (initiator device), 100 data transfer system, 101 bus arbitration unit, 102 target device, 103 PCI bus.

Claims (1)

A bus arbitration unit that gives a bus use right by a round robin method according to a bus use request;
And a plurality of initiators device accessible via a bus to a target device,
The initiator device is
When a bus use request is output to the bus arbitration unit and a bus use right is obtained from the bus arbitration unit, when a data transfer request is obtained from the target device and a data transfer enable notification is obtained from the target device. , Transferring data from the initiator device to the target device,
The target device is
Has a counter which counts up to a predetermined retry response count set to the number -1 of said plurality of initiator devices,
When a data transfer request is made from the initiator device,
When the target device is busy to process the transferred data, the target device sends a retry response to the initiator device,
When the target device is not busy and the counter has not counted up to a predetermined number of retry responses, the target device responds to the initiator device with a retry response, and the counter counts the number of retry responses.
When the target device is not busy and the counter counts up to a predetermined number of retry responses, the target device notifies the initiator device that data transfer is possible and initializes the count by the counter. <br/> A data transfer system characterized by the above.

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