JP2004139296A - Bus arbitration device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an internal system bus from being locked due to I/O operation delay. <P>SOLUTION: A CPU 11 and DMA controller 12 included in an LSI circuit 10 are able to perform access to either an SDRAM 30 or an input/output device 40 connected through a shared external bus 20. A shared external interface 17 carries out arbitration to access to an external bus between the memory controller 14 and the I/O controller 15. The DMA controller and CPU which has acquired the bus master right of the internal system bus 13 hand over the bus master right to the CPU and DMA controller which claim the bus mater right when the memory controller or I/O controller are not able to perform access to the SDRAM and input/output device. Then, when the memory controller and I/O controller are turned to be able to perform access to the SDRAM and input/output device, the the DMA controller and CPU preferentially acquires the bus master right. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to bus arbitration, and more particularly to bus arbitration of an internal bus in a processing device that connects external devices via a common path.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, when a plurality of devices connected to a shared bus simultaneously generate a bus request for the shared bus, the bus access is permitted in descending order of priority (for example, see Patent Document 1). ). This technique arbitrates control of a bus in a multiprocessor system when multiple independently operating processors attempt to access an internal system bus in the same clock cycle. Thereby, arbitration between a plurality of bus masters with respect to an internal system bus as a shared bus is realized.
[0003]
By the way, a slave of an internal system bus shared by a plurality of bus masters is configured to access an external device such as an external memory or an input / output device connected to the external bus which is a shared bus via a shared external interface. Processed devices are well known. For example, in recent years, a single-chip CPU type LSI circuit (Large Scale Integrated Circuit) with a built-in peripheral circuit has one terminal provided with a plurality of functions to save the number of terminals, and switches functions as needed. The pins often share the external I / F of a plurality of functional blocks. That is, some address bus and data bus terminals of an interface to an external memory and an input / output device (hereinafter, the interface is referred to as “I / F”) are used as shared external terminals, and the terminal functions are appropriately switched to change the memory system / F and the function of both the I / O I / F.
[0004]
[Patent Document 1]
JP-A-10-283310 (page 2, FIG. 3)
[0005]
[Problems to be solved by the invention]
In such a processing device, even when arbitration for an internal system bus between internal bus masters such as a CPU or a DMA controller as a core in an LSI circuit can be realized, when accessing an external bus from the internal bus master, a shared external I / O is required. Due to the arbitration between / F and the slave (memory controller, I / O controller, internal register, etc.), the slave may not be able to respond immediately. As a result, the internal bus master having acquired the control right of the internal system bus (hereinafter, referred to as “bus master right”) transfers to an external memory or an input / output device (hereinafter, referred to as “I / O”) via an external shared terminal. Access may be delayed, resulting in unacceptable latency for the system data stream.
[0006]
For example, a situation can be considered in which the DMA controller accesses an external SDRAM immediately after writing data to I / O from the CPU.
[0007]
At this time, data is written from the CPU to the I / O controller, and data from the CPU is stored in a data buffer in the I / O controller. After the write data is stored in the data buffer, the I / O controller performs a write operation on the I / O connected to the external bus. At this time, it is assumed that the I / O controller can immediately acquire the access right to the external bus and perform the access. In a series of write operations from the CPU to the I / O, the CPU terminates the access on the internal system bus when the data is stored in the data buffer in the I / O controller. The bus mastership of the bus is immediately passed to the DMA controller requesting the bus mastership.
[0008]
The DMA controller that has acquired the bus master right of the internal system bus accesses the memory controller as a slave of the internal system bus in order to access the external SDRAM. However, when the DMA controller accesses the memory controller, the I / O controller writes the data in the internal data buffer to the external I / O, and the external bus is used. It cannot respond to access from the DMA controller. The memory controller cannot access the external bus until all the data in the data buffer of the I / O controller has been written to the I / O. During this time, the memory controller keeps issuing a retry request for access to the DMA controller. Etc., and the internal system bus is locked by the DMA controller and the memory controller.
[0009]
Further, if the CPU accesses the internal register while the internal system bus is locked in the above-described situation, the writing to the I / O ends, the lock on the internal bus is released, and the DMA controller is released. The access cannot be performed by the CPU until the access is completed and the CPU can acquire the bus mastership of the internal bus again. It is fatal if the CPU needs to access the internal register within a certain period of time but cannot acquire the bus mastership of the internal system bus within the allowable time.
[0010]
In this way, unacceptable latency can occur for the data stream of the system. This symptom becomes remarkable when the CPU, the internal system bus, and the SDRAM are operated at a high speed, and the external I / O cannot operate as fast as the internal system bus.
[0011]
However, in the above-described prior art, since the result of the arbitration of the shared external I / F is not reflected in the arbitration of the internal bus, the bus hold or the access retry continues between the bus master and the slave in the internal bus. There is a problem that a state occurs and a state may occur as if the internal bus is locked.
[0012]
Therefore, a main object of the present invention is to provide a processing device that connects an external device via a common path so that an internal system bus is locked so that a waiting time that is not allowed for a system data stream does not occur. An object of the present invention is to provide a bus arbitration device in which the use efficiency of an internal system bus is improved.
[0013]
[Means for Solving the Problems]
The bus arbitration device of the present invention is a bus arbitration device for an internal bus in a processing device that connects an external device via a common path, and when the target slave side of the internal bus cannot access the external device, The bus master transfers the bus master right to another bus master requesting the bus master right, and then acquires the bus master right preferentially when the target slave side can access the external device. Is what you do.
[0014]
More specifically, the bus arbitration device of the present invention can access an SDRAM (30 in FIG. 1) or an input / output device (40 in FIG. 1) connected via a shared external bus (20 in FIG. 1). In the bus arbitration device for the internal system bus (13 in FIG. 1) of the simple processing device (10 in FIG. 1), the processing device includes a memory controller (14 in FIG. 1) for controlling the transfer of data to and from the SDRAM. An I / O controller (15 in FIG. 1) that accesses an output device and controls data transfer, and a shared external interface (FIG. 1) that performs arbitration for access to an external bus between the memory controller and the I / O controller. 1, 17), a CPU as a core (11 in FIG. 1), and a DMA controller (FIG. 1) for controlling DMA transfer. 12) and an internal system bus (13 in FIG. 1) to which a memory controller, an I / O controller, a CPU, and a DMA controller are connected. , I / O controller cannot access the SDRAM and the I / O device, transfer the bus master right to the CPU and DMA controller requesting the bus master right, and then transfer the memory controller and the I / O controller to the SDRAM and the I / O device. When the device is accessible, the bus master right is preferentially acquired.
[0015]
According to the present invention, in response to a bus master right request from a plurality of bus master candidates such as a CPU and a DMA controller, a series of arbitrations for a bus master right request solely due to the bus master side is not performed. The bus master confirms the status of the slave corresponding to the bus master of the acquired internal system bus, and if the slave cannot immediately respond to the access from the bus master, causes the bus master to relinquish the bus mastership and to grant the bus mastership. If the bus master right is given to another requesting bus master candidate and the slave is ready for access from the bus master thereafter, the bus master preferentially acquires the bus master right when the access of the other bus master is completed. Like that.
[0016]
That is, the arbitration of the internal system bus is not arbitration based on only the request for the bus master right of the plurality of bus master candidates, but the responsiveness of the slave side to the bus master is checked, and The arbitration operation of the bus master right is performed in consideration of the status of the slave of the internal system bus so that the bus master can respond to the access under the best conditions without making the bus master wait as much as possible.
[0017]
Therefore, when a bus master having an internal bus master has the bus mastership, the corresponding slave cannot immediately respond, locking the internal system bus by making the bus master wait, during which other bus masters cannot take the bus mastership. To prevent a situation in which the internal system bus is locked and the entire system is stopped by the status of a slave, and to minimize the possibility of waiting time unacceptable for the system data stream. Is obtained.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, in order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0019]
[Description of configuration]
FIG. 1 is a block diagram showing one embodiment of the bus arbitration apparatus of the present invention. This bus arbitration apparatus is an example of a system configuration using a one-chip CPU type LSI circuit incorporating a peripheral circuit. An LSI circuit 10, an SDRAM 30 and an I / O 40 are connected via a shared external bus 20. . In such a configuration, the present bus arbitration device has a function of minimizing the locking of the internal system bus by increasing the use efficiency of the arbitration of the internal system bus when the external bus is used.
[0020]
The LSI circuit 10 includes, in addition to the CPU 11, functional blocks such as a DMA controller 12, a memory controller 14, an I / O controller 15, and an internal register 16, an internal system bus 13 connecting these functional blocks, A common external IF 17 for connecting to the external SDRAM 30 and I / O 40 via a common terminal is built in.
[0021]
The CPU 11 is a central processing unit as a core, and the internal register 16 is a readable / writable register inside the LSI circuit 10. The DMA controller 12 controls DMA transfer, the memory controller 14 controls data transfer to and from the SDRAM 30, which is a general-purpose memory device, and the I / O controller 15 accesses the I / O 40 and the like to transfer data. Control.
[0022]
In this configuration example, the CPU 11 and the DMA controller 12 are candidate bus masters for the internal system bus 13, and the memory controller 14, the I / O controller 15, and the internal register 16 form the internal system bus 13 corresponding to the bus master of the internal system bus 13. Become a slave of. The present LSI circuit 10, SDRAM 30, and I / O 40 are connected by a shared external I / F 17. Which of the memory controller 14 and the I / O controller 15 can access the external bus 20 depends on the result of arbitration by the shared external I / F 17.
[0023]
The I / O controller 15 has a built-in data buffer for transferring data to and from the I / O 40 whose operation speed is slower than that of the internal system bus 13. When accessing the I / O 40 that cannot operate at a speed as high as that of the internal system bus 13 from the bus master of the internal system bus 13, the data is temporarily stored in a data buffer inside the I / O controller 15, and It is handed over.
[0024]
On the other hand, access from the internal system bus 13 to the SDRAM 30 via the memory controller 14 is performed so that the high-speed CPU 11 and the SDRAM 30 exhibit high performance, and the present system can operate at a high speed. , And can be performed in accordance with the operation speed of the internal system bus 13 without any intervention.
[0025]
In this configuration example, in order to save the number of terminals of the LSI circuit 10, some terminals (address bus and data bus) of the memory controller 14 and the I / O controller 15 and an external I / F are used as shared terminals. , Are connected to the external bus 20 via a shared external I / F 17 which is a shared I / F used by appropriately switching functions. The SDRAM 30 and the I / O 40 are connected to the external bus 20, and exchange data with the LSI circuit 10.
[0026]
When the CPU 11 or the DMA controller 12 needs to access the internal system bus 113, it requests the bus master right to the internal system bus 13. When these requests overlap, one of the bus master candidates is given the bus master right based on the arbitration of the internal system bus 13.
[0027]
When any of the candidate bus masters acquires the bus mastership and the slave to be accessed cannot immediately respond to the access, the access cycle to the internal system bus 13 is terminated without waiting for the slave to respond. Then, it can be set so as to abandon the bus master right. Here, the memory controller 14, the I / O controller 15, and the internal register 16 are slaves on the internal system bus 13 and can be accessed by the CPU 11 and the DMA controller 12, which are bus master candidates.
[0028]
The memory controller 14 reads and writes data from and to the SDRAM 30, and the I / O controller 15 reads and writes data from and to the I / O 40 via the shared external I / F 17 and the external bus 20. The shared external I / F 17 performs arbitration, and switches the functions of the shared terminals (address bus and data bus) between those for the memory controller 14 and those for the I / O controller 15. The access right from the slave (memory controller 14 or I / O controller 15) of the internal system bus 13 to the external bus 20 is determined by the arbitration of the shared external I / F 17, and the access right is determined. Either one of the acquired slaves becomes possible.
[0029]
The CPU 11, the DMA controller 12, the SDRAM 30, and the I / O 40 are well known to those skilled in the art, and are not directly related to the present invention.
[0030]
[Description of operation]
Hereinafter, the operation of the present embodiment will be described.
[0031]
First, the characteristic operation of the present embodiment will be outlined. An access request from the bus master side of the internal system bus 13 to the slave side becomes a trigger, and an access request to the external bus 20 is generated from the memory controller 14 or the I / O controller 15 which is a slave of the internal system bus 13. When this access request occurs at the same time, the access right to the external bus 20 is given to the slave of the internal system bus 13 from the shared external I / F 17 by arbitration of the shared external I / F 17.
[0032]
When the bus master of the internal system bus 13 accesses a slave (the memory controller 14 or the I / O controller 15) that needs to access the external bus 20, it is always said that the slave can access the external bus 20. Not exclusively. The slave notifies the bus master of information on whether or not the slave (memory controller 14 or I / O controller 15) can receive the access from the bus master of the internal system bus 13.
[0033]
The bus master recognizes whether or not the slave can receive the access, and if the slave cannot respond to the access request, re-executes the access while maintaining the bus master right (simple retry), or temporarily suspends the access. Then, the bus mastership is transferred until the slave side can respond to the access request. Whether the bus master simply selects access again or transfers the bus master right is set in advance by an application program or the like.
[0034]
In the operation of transferring the bus master right, as soon as the slave to be accessed can respond to the access from the bus master, the slave immediately notifies the bus master to which the bus master right has been transferred that the access is OK. At that time, the bus master can wait for the end of the access to the bus master in the other internal system bus 13 and re-acquire the bus master right preferentially. When the bus mastership is regained, the access target slave is accessed.
[0035]
Next, the operation of the embodiment shown in FIG. 1 will be described in detail with reference to the flowcharts shown in FIGS. FIG. 2 is a flowchart showing the operation as seen from the bus master side, and FIG. 3 is a flowchart showing the operation as seen from the internal system bus 13 side.
[0036]
Initially, if the bus master (CPU 11 or DMA controller 12) acquires the bus mastership and the slave cannot respond to the access request, it simply asks whether to simply retry the access or to transfer the bus mastership. The flag is set by an application program or the like. Selection criteria are based on overall system performance and constraints.
[0037]
When an access request is issued from the bus master in the standby state (step A1 in FIG. 2) and the bus master acquires the bus master right by arbitration of the bus master of the internal system bus 13 (YES in step A2), a preset simple preset is performed. The process branches to either step A12 or step A4 depending on whether the access is a retry access (step A3).
[0038]
At step A12, access is retried until the slave of the internal system bus 13 to be accessed can access the external bus 20, and when the slave to be accessed is ready, the slave is accessed (step A9).
[0039]
In step A4, if the access side of the slave of the internal system bus 13 to be accessed is OK, the bus master accesses the slave (step A9). If the access is not OK, the bus master gives the bus master right to the other internal system bus 13. The transfer is made to the bus master, and a priority reservation for acquiring the bus master right is made to the internal system bus 13 (step A5).
[0040]
Then, the process loops until the slave to be accessed becomes accessible from the bus master (NO in step A6), and when the slave becomes accessible (YES in step A6), it is confirmed that the access by the other bus master is completed ( The bus master regains the bus master right based on the priority reservation for acquiring the bus master right set in step A5 (YES in step A7) (step A8). At this time, the bus master is given priority over the other bus masters, and the bus master accesses the slave (step A9).
[0041]
When the access to the slave is completed (YES in step A10), the bus mastership is released (step A11).
[0042]
Next, in FIG. 3, from the initial idle state (step B1 in FIG. 3), the process unconditionally proceeds to step B2 to check whether there is a bus master right request or priority reservation from the bus master (step B2). If neither the bus master right request nor the priority reservation is present (NO in step B2), the bus master right is given to the CPU 11 (step B2).
[0043]
On the other hand, if there is a bus mastership request or a priority reservation (YES in step B2), it is checked whether or not there is a further priority reservation (step B4). As a result, if there is a priority reservation (YES in step B4), the bus master right is given to the bus master on a first-come-first-served basis in response to the priority reservation from the bus master of the internal system bus 13 (step B5). The priority reservation of the bus master is cleared (step B6).
[0044]
If there is no priority reservation (NO in step B4), a bus master right is given to the bus master selected by arbitration based on a normal bus master right request (step B7).
[0045]
Finally, it is checked whether the bus transaction of the internal system bus 13 has been completed (step B8), and if it has been completed, the process returns to step B1.
[0046]
In the above-described series of operations shown in the flowcharts of FIGS. 2 and 3, the process branches from step A3 to step A12 in FIG. 2 and does not proceed to step A9 until the target slave is ready for access. The conventional arbitration operation keeps holding the bus mastership of the internal system bus 13 in FIG. In addition to the conventional arbitration operation, in the present bus arbitration, the process branches from step A3 to step A4, and depending on the state of the target slave, the bus master of the internal system bus 13 transfers the bus mastership to another bus master, and An arbitration operation for preferentially regaining the bus mastership when the slave has access OK is added.
[0047]
[Other embodiments]
Next, another embodiment of the present invention will be described with reference to the flowchart of FIG. In this embodiment, the configuration is as shown in FIG. 1. However, the arbitration mode switching when the slave side of the internal system bus 13 in FIG. 1 cannot immediately respond to the access from the bus master side is further devised. ing.
[0048]
In the series of arbitration shown in the flowchart of FIG. 2, when the slave cannot immediately respond to the access from the bus master, a simple retry access is repeated, or The mode of operation or arbitration was fixed. In the embodiment of FIG. 4, such a mode is not set, and when the slave side is not ready even if the bus mastership is acquired, the bus mastership is transferred after executing a predetermined number of retries. Like that. The limit value of the number of retries is set by an application program or the like.
[0049]
With such a configuration, in the embodiment of FIG. 2, in the case of the simple retry access, if the target slave side is not access OK, the retry is repeated until the access is OK. However, in the embodiment of FIG. When the limit is reached, the bus mastership is transferred to another bus master. On the other hand, in the embodiment of FIG. 2, in the case of the non-simple retry access, if the access of the target slave is not OK, the bus master right is immediately transferred to another bus master, but in the embodiment of FIG. 4, the limit value is reached. Until the retry is repeated, the bus mastership is transferred to another bus master.
[0050]
Initially, it is in a standby state (step C1), and when an access request is issued from the bus master of the CPU 11 or the DMA controller 12 in FIG. 1 and the bus master acquires the bus master right by arbitration of the bus master of the internal system bus 13 (step C1). (YES in C2), it is checked whether or not the target slave can receive the access from the bus master (step C3). As a result, if the slave side can be accessed (YES in step C3), the bus master accesses the slave (step C9).
[0051]
However, if the slave cannot receive the access (NO in step C3), the process transits to step C4 to perform retry access. In step C4, the number of retry accesses is counted. Retry access count is retry Limit value If has not reached (NO in step C4), it is checked whether or not the target slave can receive the access from the bus master (step C3), and retry access is performed. As the limit value of the number of retries, an appropriate value can be arbitrarily set based on the characteristics and restrictions of the entire system.
[0052]
When the number of retry accesses reaches the retry limit value (YES in step C4), the bus master transfers the bus mastership to the bus master of another internal system bus 13, and makes a priority reservation for acquiring the bus mastership for the internal system bus 13. (Step C5).
[0053]
Then, the process loops until the slave to be accessed becomes accessible from the bus master (NO in step C6). If the access becomes possible (YES in step C6), it is confirmed that the access by the other bus master is completed ( The bus master regains the bus master right based on the priority reservation for acquiring the bus master right set in step C5 (YES in step C7) (step C8). At this time, the bus master is given priority over the other bus masters, and the bus master accesses the slave (step C9).
[0054]
When the access to the slave is completed (YES in step C10), the bus master right is released (step C11).
[0055]
As described above, in the bus arbitration shown in the flowchart of FIG. 4, it is possible to prevent the internal system bus 13 from being locked due to repetition of retry access depending on the situation of the slave to be accessed, and to perform the arbitration operation as shown in FIG. The arbitration operation is automatically switched according to the number of times retry access is performed, instead of being fixed by setting.
[0056]
【The invention's effect】
As described above, according to the present invention, the internal system bus has a plurality of bus master candidates, and the plurality of slaves to be accessed by the bus master are connected to the external device such as the memory or the I / O by the shared external I / F. In such a system, when an internal bus master has the bus mastership, the corresponding slave cannot immediately respond and locks the internal system bus by making the bus master wait, while another bus master acquires the bus mastership. Prevents a situation in which the system is stopped waiting, that is, a lock state of the internal system bus occurs, and the entire system is stopped by the state of the slave, and the possibility of waiting time that is not allowed for the system data stream is minimized. The effect of being able to prevent is obtained.
[0057]
It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a bus arbitration apparatus according to the present invention.
FIG. 2 is a flowchart showing an operation example when viewed from the bus master side of the embodiment shown in FIG. 1;
FIG. 3 is a flowchart showing an operation example of the embodiment shown in FIG. 1 when viewed from the internal system bus side;
FIG. 4 is a flowchart showing another example of operation when viewed from the bus master side in the embodiment shown in FIG. 1;
[Explanation of symbols]
10 LSI circuit
11 CPU
12 DMA controller
13 Internal system bus
14 Memory controller
15 I / O controller
16 Internal register
17 Shared external I / F
20 External bus
30 SDRAM
40 I / O

Claims (6)

In a bus arbitration device of an internal bus in a processing device that connects an external device via a common path,
If the target slave of the internal bus cannot access the external device, the bus master of the internal bus transfers the bus master right to another bus master requesting the bus master right, and then the target slave transfers the external device. A bus arbitration device wherein the bus master right is preferentially acquired when access becomes possible. In a bus arbitration device for an internal system bus of a processing device capable of accessing an SDRAM or an input / output device connected via a shared external bus,
A memory controller that controls data transfer with the SDRAM, an I / O controller that accesses the input / output device to control data transfer, the memory controller and the I / O controller, , A shared external interface that performs arbitration for access to the external bus, a CPU as a core, a DMA controller that controls DMA transfer, and the memory controller, the I / O controller, the CPU, and the DMA controller. Including an internal system bus,
The DMA controller or CPU that has acquired the bus master right of the internal system bus, if the memory controller and the I / O controller cannot access the SDRAM and the input / output device, sends the bus master to the CPU and the DMA controller requesting the bus master right. Bus arbitration, wherein when the memory controller and the I / O controller have access to the SDRAM and the input / output device, the bus master right is preferentially acquired. apparatus. In a bus arbitration device for an internal system bus of a processing device capable of accessing an SDRAM or an input / output device connected via a shared external bus,
A memory controller that controls data transfer with the SDRAM, an I / O controller that accesses the input / output device to control data transfer, the memory controller and the I / O controller, A shared external interface for arbitrating access to the external bus between the CPU, a CPU as a core, a DMA controller for controlling DMA transfer, and the memory controller, the I / O controller, the CPU and the DMA controller. Internal system bus,
The DMA controller or CPU that has acquired the bus master right of the internal system bus, if the memory controller and the I / O controller cannot access the SDRAM and the input / output device, sends the bus master to the CPU and the DMA controller requesting the bus master right. An operation mode in which, when the memory controller and the I / O controller are allowed to access the SDRAM and the input / output device, the bus master right is preferentially acquired.
The DMA controller and the CPU that have acquired the bus master right of the internal system bus perform one of an operation mode of performing retry access until the memory controller and the I / O controller can access the SDRAM and the input / output device if the memory controller and the I / O controller cannot access the I / O device. Bus arbitration device characterized in that it is possible to set the When the memory controller and the I / O controller cannot access the SDRAM and the input / output device, a retry is performed for a predetermined number of times to determine whether the SDRAM and the input / output device are accessible. 4. The bus arbitration device according to claim 2, wherein the DMA controller and the CPU access the memory controller and the I / O controller when the transfer and the access are permitted. The processing device includes an internal register as a data buffer used when the CPU accesses the input / output device under control of the I / O controller,
The method according to claim 1, wherein when the DMA controller acquires the bus mastership while data is being written from the internal register to the input / output device, the bus mastership is transferred to the CPU. 5. The bus arbitration device according to any one of 2 to 4. 6. The bus arbitration device according to claim 2, wherein said CPU, DMA controller, internal system bus, memory controller, I / O controller and shared external interface are accommodated in one LSI circuit. .

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