JP4965842B2 - Current mirror with fast turn-on time - Google Patents

Description

This application claims the benefit of US pending patent application No. 60 / 616,718, filed Oct. 6, 2004.
The present invention relates generally to hard disk drive data storage systems, and more particularly to a method of turning on a current mirror in a hard disk drive data storage system and an apparatus having a current mirror for a hard disk drive storage system.

  A disk drive is a cost effective data storage system for use in a computer or other data processing device. As shown in FIG. 1, a disk drive 10 includes a disk or disk-shaped magnetic recording medium 12 having a central portion 13 and a read / write transducer 14, commonly referred to as a read / write head. The read / write head 14 is suspended on the disk 12 and is attached to a suspension arm 15 fixed to a rotary actuator arm 16 or is integrally formed. The structure arm 18 fixed to the platform 20 of the disk drive 10 is pivotally connected to the actuator arm 16 by a pivot joint 22. A voice coil motor 24 drives the actuator arm 16 to position the head 14 over a selected position on the disk 12.

  When the disk 12 is rotated at a certain operating speed by a spindle motor (not shown), the moving air created by the rotating disk is combined with the physical characteristics of the suspension arm 15 to move the read / write head 14 from the disk 12. Lift away and allow the head to slide or fly over an air cushion slightly above the surface of the disk 12. The flying height of the read / write head above the disk surface is typically less than 1 micron.

  The arm electronic module 30 can have a circuit that switches the function of the head between a read operation and a write operation, and a write driver for supplying a write current to the head 14 during the write operation. The write current changes the magnetic domains in the disk 12 to store data there. The arm electronic module 30 may also include a preamplifier electrically connected to the head 14 by flexible conductive leads 32. During the read operation, the preamplifier amplifies the read signal produced by the head 14 to increase the signal-to-noise ratio of the read signal. In the write mode, the preamplifier scales a relatively low voltage level representative of the data bits written to disk from about +/− 6 to +/− 10V. The preamplifier also shapes the write signal to optimize the data write process.

  The configuration and components of the electronic module 30 will be understood by those skilled in the art, but may vary according to the design of the disk drive. The module 30 can be mounted anywhere on the disk drive 10, but the location close to the head 14 minimizes signal loss during read operations and noise induced in the head signal. A preferred mounting location for module 30 includes the sides of structure arm 18 as shown in FIG.

  As shown in FIG. 2, the disk 12 has a substrate 50 and a thin film 52 disposed thereon. The current flowing through the write head 14A during the write operation changes the magnetic domain of the ferromagnetic material in the thin film 52 to store the data bits as magnetic transitions. During a read operation, read head 14B senses the magnetic transition and determines the data bits stored on disk 12.

  In other data storage systems, the head 14 operates with various types of storage media (not shown) including, for example, hard magnetic disks, flexible magnetic disks, magnetic tapes, and magneto-optical disks.

  The disk drive read head 14B has either a magnetoresistive (MR) sensor or an inductive sensor. The former produces a high-scale output signal in response to a magnetic transition, so that the output signal exhibits a greater signal-to-noise ratio than the output signal produced by the inductive sensor. Thus, MR sensors are preferred, especially when large area data storage density is desired within the disk drive 10.

  A DC (direct current) voltage of about 0.04V to 0.2V is supplied by the preamplifier to the read head terminals 54A and 54B via the conductive lead 32 to bias the read head 14B. A magnetic domain in the thin film 52 that passes under the read head 14B changes the resistance of the magnetoresistive material and provides an AC (alternating current) component to the DC bias voltage, where the AC component represents the read data bit. This AC component is detected in the preamplifier, but has a relatively small scale (for example, several millivolts) with respect to the DC bias voltage.

  The operation of the preamplifier reading circuit is not required during the time when data is not read from the disk 12. For desktop computers, power consumption is not normally a limiting condition of operation, so the read circuitry in the desktop computer's disk drive system remains on when data is not being read from disk 12. . This feature minimizes the turn-on time for the read circuit (especially the turn-on time for the preamplifier current mirror that operates when reading data) and ensures that the preamplifier handles the magnetic transition from the beginning of the data read period. To do.

  The desktop preamplifier can be switched to a semi-operating state (idle mode) if the computer does not access the disk drive 10 for some extended time, and very low power when the computer switches to the sleep state. It can be interrupted to level (sleep mode). The disk drive system 10 is relatively long (ie, a few microseconds to a few milliseconds) to transition the preamplifier from sleep or idle mode to one of full operational modes (eg, read or write mode). Allow power-on time.

  In contrast to desktop computer systems, battery-powered mobile and portable computing devices and data processing systems, recorded music players, and other battery operated devices with mass data storage systems that operate on preamplifiers Consumption is a critical design objective. In order to minimize preamplifier power consumption and thereby conserve battery power, the preamplifier read circuit is switched off when data is not being read from the hard disk drive. For example, the reading circuit is switched off while data is being written. However, in order to avoid loss of data during a read operation and provide fast data access, it is desirable that the preamplifier read circuit turn on within about 100 ns to reach the desired steady state situation.

  Returning to FIG. 2, an output signal from read head 14B representing a data bit to be read from disk drive 10 and having an amplitude in the range of a few millivolts is input to signal processing stage 102, after which The stage is followed by an output stage or a buffer stage. Normally, both the signal processing stage 102 and the output stage 104 are included in the preamplifier. The output stage 104 scales the voltage of the head signal to a peak voltage value in the range of several hundred millivolts and provides the scaled signal to the channel circuit of the channel chip 106. The channel chip 106 detects read data bits from the voltage pulse while applying error detection and correction processing to the voltage pulse.

  FIG. 3 illustrates the output stage 104 of FIG. 2 according to conventional prior art. PMOSFET M2 is gated on to provide a reference current Iref0 (25 microamps in one embodiment), which is the collector C and n-channel of bipolar junction transistor (BJT) Q1 (operating as a current mirror master) The NMOSFET M0 is turned on by being directed to the gate G of a metal oxide semiconductor field effect transistor (NMOSFET) M0. The source S of PMOSFET M2 and the drain D of NMOSFET M0 are connected to a positive power supply voltage VP (about 3.3 V in one embodiment), and the source S of M0 is connected to the base B of transistor Q1. When NMOSFET M0 is on, BJT Q1 is gated on and current Iref0 flows through BJT Q1 and resistor R11 to ground. As is known, the BJT base current is likely to vary over a range of 5 to 1 due to variations in BJT manufacturing steps and temperature variations during operation. Resistor R7 ensures that M0 provides sufficient bias current for proper operation of current mirror transistors Q1, Q2, Q3, Q4, and Q5 across all expected steps, temperatures, and operating conditions. It operates as a pull-down resistor of the NMOSFET M0 for achieving the above. In applications where battery power saving is desirable, the current Iref0 is when data is not being read from the disk 12, ie, when data is being written to the disk 12, and during idle periods when data is neither being written nor read. Will be censored.

  BJTs Q2, Q3, Q4, and Q5 are also gated on by NMOSFET M0. The matched BJTs Q1, Q2, Q3, Q4, and Q5 have substantially the same base-emitter voltage and are accompanied by appropriately estimated emitter resistors R11, R10, R13, R14, and R15. BJT Q1, Q2, Q3, Q4, and Q5 operate as scaled current mirrors. A properly estimated emitter resistor means that each resistor R11, R10, R13, R14, and R15 is scaled based on the BJT associated with the resistor, ie R10 = R11 / k1. , R13 = R11 / k2, R14 = R11 / k3, and R15 = R11 / k4, where k1-k4 represent the emitter area ratio for each of BJTs Q2-Q5 relative to the emitter area of Q1, ie Q2 = Q1 * k1, Q3 = Q1 * k2, Q4 = Q1 * k3, and Q5 = Q1 * k4. BJTs Q2, Q3, Q4, and Q5 function as constant current sources for their associated BJTs Q7, Q6, Q12, and Q9. The current Iref0 passing through BJT Q1 is projected and scaled through BJT Q2, Q3, Q4, and Q5 (according to the accompanying conversion value k).

  The collector C of BJT Q7 is connected to power supply VP through resistor R17, and the base B of Q7 is driven by a bias voltage (not shown) and a voltage pulse coming from signal processing stage 102. When the amplifier including BJT Q6 and BJT Q7 is in operation, BJT Q7 is driven to an on state or an on state, and current Iref through BJT Q1 is current I2 through resistors R10 and R17, and BJT Q7 and Q2. It is projected as. Since BJT Q1 and Q2 form a current mirror, I2 = k1 × Iref, where k1 is the emitter area ratio of BJT Q2 to the emitter area of BJT Q1. Normally, the BJT provided with such an area ratio is formed of a plurality of unit transistors, that is, the BJT Q2 includes k1 times the number of unit transistors constituting the BJT Q1.

  The negative feedback action of the emitter resistors R10 and R11 provides an impedance that is observed when examining the collectors of BJT Q1 and BJT Q2, and the ratio of I2 to Iref is Q2 as long as the collector-emitter voltage of Q2 is greater than about 0.5V. It is sufficiently increased to be a very weak function of the collector-emitter voltage. Therefore, as can be understood by those skilled in the art, the variation of I2 with the collector-emitter voltage of BJT Q2 is ignored here.

  The state of current mirror BJT Q3 is controlled by NMOSFET M0. BJT Q6 is biased by a signal processing stage 102 that provides both signal and DC bias to the base B of BJT Q6. When both BJT Q3 and Q6 are gated on, current I3 flows through resistors R19 and R13, and BJT Q3 and Q6, where I3 = k2 × Iref, because BJT Q1 and Q3 Is a current mirror and Q3 = Q1 × k2.

  BJT Q6 and Q7 form a differential amplifier with a degeneration resistor R20 connected between the emitter of BJT Q6 and the emitter of BJT Q7, where the emitter of BJT Q7 linearizes amplification and stabilizes gain Let The signal entering from the signal processing stage 102 biases the input of the amplifier (the base of each of the BJT Q6 and Q7) and provides a processed data signal that is interconnected to the channel chip 106, ie, terminal RDP and Prior to driving the RDN, it is amplified (ie, scaled) and buffered by the output stage 104.

  BJTs Q9 and Q12 buffer collector loads R17 and R19 to drive the interconnection to channel chip 106 from a low impedance, thereby maintaining a wide bandwidth typically up to about 700 MHz.

  In FIG. 3, NMOSFET M0 provides base drive current for each of current mirrors BJT Q1, Q2, Q3, Q4, and Q5. In one embodiment, the base current of each BJT is about 16 microamps, for a total of about 80 microamps. Since substantially no current flows to the gate G of the NMOSFET M0, the current Iref is substantially equal to the collector current of the BJT Q1.

  The circuit loop including the base / collector path of BJT Q1 and the gate / source path of NMOSFET M0 forms a feedback loop, which is likely to oscillate like all feedback loops. Oscillation is limited and controlled by capacitor C0 connected between the collector of BJT Q1 and ground. The bandwidth of this loop is controlled by the current through NMOSFET M0 as determined by resistor R7 and is increased by the base current supplied to BJT Q1, Q2, Q3, Q4 and Q5.

  Although it is advantageous for capacitor C0 to prevent oscillation of the feedback loop, the current mirror BJT Q1, Q2, Q3, Q4, and Q5 turn-on times since the current mirror does not turn on until capacitor C0 has been charged. Is disadvantageous. The output signal does not appear at terminals RDP and RDN until the current mirror is switched on. Therefore, the output signal is delayed by the charging time of the capacitor C0. In some embodiments of the output stage 104, the delay of the output signal exceeds the target of about 100 nanoseconds.

  According to one embodiment, the present invention comprises a current mirror controller for controlling a current mirror, which has a reference current passing therethrough, a current mirror master connected to the control node and receiving a reference current A current mirror master connected to the current mirror, a first switching device connected to the power supply and controlling the state of the current mirror master, and the voltage at the control node during the first mode of operation. A circuit module configured to control to the first voltage, and a circuit module configured to control the voltage of the control node to the second voltage during the second operating mode, the current mirror being a reference During a second mode of operation that projects current, the first switching device controls the current mirror master to an on state.

  According to another embodiment, the present invention includes a method for controlling a current mirror, wherein the method changes the voltage of a control node to which a capacitor is connected to a first voltage during a first mode of operation, and A step of controlling to a second voltage during the second mode of operation, a reference current through the control node, which is reflected by the current mirror and scaled during the second mode of operation. Supplying the mirror master, and after the capacitor is charged to the second voltage, the capacitor is switched on at the start of the second mode of operation so that the current mirror is switched on to project the reference current. Charging from a voltage of one to a second voltage.

The invention will be more readily understood and its advantages and uses will become more readily apparent when the following detailed description of the invention is read in conjunction with the drawings.
In accordance with common practice, the features of the various described devices are not drawn to scale, but are drawn to emphasize specific features relevant to the present invention. Reference characters indicate similar elements throughout the figures and text.

  Before discussing in detail a particular method and apparatus for the output stage of a preamplifier for a disk drive system, it will be noted that the present invention is first of all a novel and unobvious combination of elements and processing steps. Should be. In order not to obscure the present disclosure with details that will be readily apparent to those skilled in the art, certain elements and steps have not been presented in so much detail, while the drawings and specification are Other elements and steps suitable for understanding are described in more detail.

  FIG. 4 illustrates a current mirror controller 112 (replaces current mirror controller 110) for use with output stage 104 of FIG. 3 during data write and non-read intervals such as idle mode conditions. By maintaining the charge on capacitor C0, the turn-on time of current mirrors BJT Q1, Q2, Q3, Q4, and Q5 is limited. As stated above, when data is read from disk 12, the current mirror is turned on to activate the amplifier with BJTs Q6, Q7, Q9, and Q12. The amplifier scales and buffers the voltage coming from the signal processing stage 102 for subsequent processing and data detection within the channel chip 106.

  In the circuit of FIG. 4, PMOSFET M2 is on to provide a reference current Iref1 that maintains the charge on capacitor C0 during non-read intervals (such as during data writing and during idle mode). Since current mirror BJT Q1, Q2, Q3, Q4, and Q5 do not turn on until capacitor C0 is charged, the process of maintaining capacitor C0 in the charged state is otherwise the current mirror at the start of the read operation. BJT

  Avoid time delays that would be required to charge capacitor C0 before switching on Q1, Q2, Q3, Q4, and Q5. PMOSFET M2 is on at all times except when the disk drive is operating in sleep mode.

  To conserve battery power, it is desirable to switch off current mirrors BJT Q1, Q2, Q3, Q4, and Q5 during the data write and idle periods. This is accomplished by switching PMOSFET M4 off to open the current path through NMOSFET M0, which provides base current drive to current mirrors BJT Q1, Q2, Q3, Q4, and Q5. PMOSFET M4 is switched off by applying an inverted read signal to gate G that is high during write and idle modes.

  Turning off BJT Q1 causes PMOSFET M2 to pull node 120 and capacitor C0 to supply voltage VP as desired during the non-read interval. Note that NMOSFET M0, BJT Q1 resistor R11, and current Iref determine the voltage at node 120 when current mirrors BJT Q1, Q2, Q3, Q4, and Q5 are in operation.

During the read operation, the inverted read signal goes low, gates PMOSFET M4 on, and NMOSFET M0 supplies the base current to switch on current mirrors BJT Q1, Q2, Q3, Q4, and Q5. Make it possible. Since the capacitor C0 is charged to the power source VP, the capacitor C0 must be discharged to the operating voltage of Vgs _M0 + Vbe _Q1 + Iref1 × R11 at the start of the read mode operation. During this discharge interval, the current I2, which is the collector current of BJT Q7 (see FIG. 3), overshoots its intended value for about 20 ns. This overshoot of the current causes the output common mode voltage at the output terminals RDP and RDN of FIG. 3 to decrease, and then gradually recovers as the capacitor C0 reaches its operating voltage. During overshoot, common mode transitions are provided to channel chip 106 through Q12 and Q9 of FIG. Clearly this is an unacceptable situation because it is likely to adversely affect the reading of the first few data bits obtained from the disk 12.

  FIG. 5 specifically shows a current mirror controller 122 for limiting the turn-on time of the current mirror. In FIG. 5, during data write and idle operation, the NMOSFET M6 is switched on (due to the high logic state of the inverted read signal applied to the gate G of the NMOSFET M6), branching the reference current Iref2 to ground, and the capacitor Short C0 and node 120 to ground. As a result, the gate G of the NMOSFET M0 becomes the ground potential, and the NMOSFET M0 is turned off. No current flows through NMOSFET M0 to supply the base current and drive the current mirror, and therefore current mirrors BJT Q1, Q2, Q3, Q4, and Q5 are off.

During data reading, NMOSFET M6 is switched off, allowing capacitor C0 to be charged to the power supply voltage, and NMOSFET M0 to be gated on to turn on current mirror BJT Q1, Q2, Q3, Q4. , And supply the base current for Q5. However, an extended mirror turn-on time (in one embodiment, on the order of 40 ns) is required to charge capacitor C0 from ground to Vgs _M0 + Vbe _Q1 + Iref2 × R11. Such a long turn-on time is likely to be unacceptable because the first few data bits read from the disk 12 are likely not to be properly processed through the output stage 104.

  6 is yet another current mirror that has a relatively fast stabilization time compared to the current mirror controller 122 of FIG. 5 and avoids the overshoot period associated with the current mirror controller 112 of FIG. The schematic of the controller 130 is shown concretely. The current mirror controller 130 can be used in place of the controller 110 of FIG.

In order to minimize the current mirror turn-on time at the beginning of each read cycle, during a non-read time interval (eg, when operating in idle / write mode), current mirror controller 130 sets the voltage at node 120 to Fix to a voltage approximating the node voltage during read mode. According to one embodiment, it is preferred that the idle / write mode bias voltage of node 120 is set slightly below the read mode voltage of the node, so that current I2 is the intended bias at the beginning of the read operation. -The level will not overshoot.
NMOSFET M0 provides the same function within current mirror controller 130 as that in the embodiments of FIGS.

  During the idle and write modes, an inverted read signal having a high logic state gates the PMOSFET M30. During idle and write modes, the inverted read signal controls PMOSFET M30 to open, thereby providing a current bias to the base of mirror master BJT Q1 and each current mirror BJT Q2, Q3, Q4, and Q5. Remove the current mirror by removing it. The process of turning off the current mirror for periods of idle and write mode saves power and is an important advantage especially for devices powered by batteries.

  The current Iref3 supplied from the power supply VP under the control of the PMOSFET M2 turns on the NMOSFET M31. During idle, write, and read modes, PMOSFET M2 is on. According to the preferred embodiment, during the sleep mode of disk drive 10, Iref3 is switched off and power is always removed from disk drive 10 by switching M2 off. An exemplary value for Iref3 is 25 μA, which is similar to Iref2 and Iref1 in other embodiments. Resistor R22 operates as a pull-down resistor for NMOSFET M31.

  PMOSFET M32 is gated on by the low logic state of the read signal applied to gate G. Thus, when the read signal is low (during idle and write operations), PMOSFET M32 is on, transistor Q10 is on, and passes through node 120, the collector-emitter path of BJT Q10, and resistor R20. Enable Iref3 current. The node voltage is equal to the sum of the collector-emitter voltage drop across BJT Q10 and the voltage drop across resistor R20. Capacitor C0 is charged to the node voltage during the idle and write modes. It should be noted that the capacitance of capacitor C0 can be the same as that in the embodiments of FIGS.

In order to control the node voltage to a value in the read mode which is almost the same as in the write / idle mode, R20 = R11 and Q10 has the same performance parameters as Q1. To ensure that the voltage at node 120 is slightly lower than the voltage during the read operation for the write / idle operation period, R7 = 10 kΩ while R22 = 40 kΩ and M0 is 10 μm wide. On the other hand, M31 is 5 μm wide, allowing Vg _M31 in write / idle mode to be slightly lower than Vgs _{M0 in} read mode.

Those skilled in the art will recognize that these values are merely exemplary and other values can be used to achieve Vg _M31 in idle and write modes lower than Vgs _{M0 in} read mode. For example, the device size identified above controls the voltage at node 120 to about 1.9V in read mode and 1.8V in write / idle mode. A voltage difference of about 0.1V was selected according to one embodiment based on expected performance variations (eg, due to component value variations) and the desired amount of undershoot and overshoot.

  During read mode, PMOSFET M30 is on and current is supplied from power supply VP to a feedback loop including MOSFET M0 and BJT Q1, which provides base current to current mirrors BJT Q2, Q3, Q4, and Q5. Supply.

  Further, during the read mode period, a read signal applied to the gate of PMOSFET M32 and the gate of NMOSFET M34 switches PMOSFET M32 off and NMOSFET M34 on. When PMOSFET M32 is off, the base drive for BJT Q10 is removed. In addition, when NMOSFET M34 is on, the base of BJT Q10 is shorted to ground, switching Q10 off. As a result, Iref3 charges capacitor C0 to its normal operating voltage, but since it is charged to the voltage at node 120 during write / idle operation, the charging time is significantly greater than that of the embodiment of FIG. Reduced to

  By maintaining node 120 at approximately the same voltage during both read and idle / write operations, the charging time of capacitor C0 is reduced and the current mirror turn-on time is also reduced.

  In other embodiments, one or more MOSFETs and BJTs as described herein are replaced with opposite polarity MOSFETs or BJTs. The accompanying gate drive signal and power supply voltage are modified to address the doping characteristics of the opposite polarity MOSFET or BJT while providing the functionality of the present invention. Further, throughout the description of the present invention, the phrase “high” signal value is used interchangeably with a “true” or “valid” state. One skilled in the art will recognize that other signal values can also be associated with a “true” or “valid” logic state, and corresponding changes in the device respond to the logic state.

  FIG. 7 shows three timing diagrams that specifically illustrate current I2 (one of the currents projected) as a function of time for three embodiments of the present invention. The “overshoot” curve is associated with the embodiment of FIG. 4, the “slow” curve is associated with the embodiment of FIG. 5, and the “fast” curve is associated with the embodiment of FIG. The significant improvement provided by the embodiment of FIG. 6 is apparent.

  While the invention has been described with reference to preferred embodiments, those skilled in the art will recognize that various modifications can be made without departing from the scope of the invention and that equivalent elements can be substituted for multiple elements. Will be understood. The scope of the present invention further includes any combination of elements derived from the various embodiments described herein. In addition, modifications may be made to the teachings of the invention without departing from the essential scope thereof to suit particular circumstances. Accordingly, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments that fall within the scope of the appended claims.

FIG. 2 illustrates a prior art disk drive to which the teachings of the present invention can be applied. FIG. 2 is a schematic diagram showing a prior art head and related components of the disk drive of FIG. FIG. 3 is a schematic diagram illustrating an output stage according to the prior art of FIG. 2. FIG. 4 is a schematic diagram illustrating several elements for use in conjunction with the output stage of FIG. 3. FIG. 4 is a schematic diagram illustrating several elements for use in conjunction with the output stage of FIG. 3. FIG. 4 is a schematic diagram illustrating several elements for use in conjunction with the output stage of FIG. 3 in accordance with the present invention. FIG. 7 is a timing diagram specifically illustrating the magnitude of current as a function of time for the three embodiments of FIGS.

Claims (10)

In the current mirror controller for controlling the current mirror,
A control node having a reference current passing therethrough;
A current mirror master connected to the control node for receiving the reference current, the current mirror master connected to the current mirror;
A first switching device connected to a power source and controlling the state of the current mirror master;
It is configured to control the voltage of the control node to the first voltage during the first operation mode, and is configured to control the voltage of the control node to the second voltage during the second operation mode. A circuit module,
During the second mode of operation, the first switching device controls the current mirror master to be on, during which the current mirror reflects the reference current ;
The first operation mode includes an off state with respect to the current mirror, and the second operation mode includes a current supply state with respect to the current mirror;
The circuit module includes a controllable current path from the control node to ground;
In the first mode of operation, the controllable current path includes a first resistor, the first voltage is responsive to the first resistor, and the first voltage is the first resistor. In response to
In the second mode of operation, the controllable current path includes a second resistor, and the second voltage is responsive to the second resistor . From the first operation mode to the second operation mode by making the first voltage during the first operation mode substantially equal to the second voltage during the second operation mode. The current mirror controller according to claim 1, wherein a turn-on time at the time of switching is reduced . A capacitor connected to the control node, wherein the circuit module charges the capacitor to the first voltage during the first operation mode and to the first voltage during the second operation mode; The current mirror controller according to claim 1, wherein the current mirror controller is controlled to a voltage of 2. From the first operation mode to the second operation mode by making the first voltage during the first operation mode substantially equal to the second voltage during the second operation mode. The current mirror controller according to claim 3 , wherein a turn-on time at the time of switching is reduced . Claims which is connected to the control node, the reference current further comprises a switching device for supplying to said control node, said switching device and controlling the reference current in response to a control signal Item 2. The current mirror controller according to Item 1. Current mirror controller of claim 1, wherein the operative to supply current to the amplifier between the data read mode of said current mirror disk drive data storage system. Includes a non-reading time interval of the first operation mode is the disk drive data storage system, wherein the second operation mode includes a data reading time interval of the disk drive data storage system The current mirror controller according to claim 6 . In the pre-amplifier for the disk drive data storage system,
A control node having a reference current passing therethrough;
A current mirror master connected to the control node and receiving the reference current;
A first switching device connected to a power source for controlling the state of the current mirror master and the corresponding current mirror;
It is configured to control the voltage of the control node to the first voltage during the first operation mode, and is configured to control the voltage of the control node to the second voltage during the second operation mode. A circuit module,
During the second mode of operation, the first switching device controls the current mirror master to be in an on state, during which the current mirror generates a current reflecting the reference current;
The response current to the current generated by the mirror, in response to a voltage further representing data bits read from the disk drive, have a amplifier for amplifying the voltage representative of said data bits,
The first operating mode includes an off state with respect to the current mirror, and the second operating mode includes a current supply state with respect to the current mirror;
The circuit module includes a controllable current path from the control node to ground;
In the first mode of operation, a controllable current path includes a first resistor, the first voltage is responsive to the first resistor;
In the second operation mode, the controllable current path includes a second resistor, and the second voltage is responsive to the second resistor . The circuit module further includes a capacitor connected to the control node, wherein the circuit module controls the charge of the capacitor to a first voltage during the first operation mode, and the capacitor of the capacitor during the second operation mode. 9. The preamplifier according to claim 8, wherein the charge is controlled to the second voltage . From the first operation mode to the second operation mode by making the first voltage during the first operation mode substantially equal to the second voltage during the second operation mode. 9. The preamplifier according to claim 8, wherein a turn-on time at the time of switching is reduced .

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