JP4964261B2 - Slot machine - Google Patents

Description

  The present invention relates to a slot machine capable of generating a predetermined winning according to a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable.

  A slot machine generally includes a variable display device having a plurality of (usually three) reels on which a plurality of types of symbols as identification information are drawn on the outer periphery, and first, a bet number is determined by a player's BET operation. The reels start to rotate when the start operation is performed with the set number of bets set, and the rotation is stopped by operating a stop button provided corresponding to each reel. When all reels stop rotating, a winning combination occurs when a predetermined winning symbol combination (for example, 7-7-7, hereinafter referred to as a symbol combination) is arranged on the winning line. To do. That is, the game is advanced by the player's operation.

  Also, in this type of slot machine, it is common to draw a role at the same time as the start operation and to win a winning combination on the condition that the lottery is won. There is a method of providing a counter that updates a numerical value within a certain range, extracting the numerical value of the counter when a start operation is detected, and using the extracted value as a random number (for example, see Patent Document 1).

JP 2005-152268 A

  As in the gaming machine described in Patent Document 1, when the start operation is detected, the counter value is extracted and the lottery is performed. After the start operation is detected and the counter value is extracted, When a numerical value is extracted from the counter again due to noise on the signal line of the start operation, a lottery is performed with a numerical value different from the value extracted by detecting the start operation.

  As a method of solving such a problem, a method of extracting a numerical value from the counter once and holding it until the extracted numerical value is read out can be considered. Even if it is made in a period that is not valid for the progress, the numerical value extracted from the counter remains retained, and a lottery is performed based on the numerical value extracted at a timing different from the timing at which the original start operation was performed Will cause serious problems.

  The present invention has been made paying attention to such problems, and can prevent a lottery from being performed using a numerical value different from the numerical value extracted at the timing when the game start operation is performed. The purpose is to provide a machine.

In order to solve the above-described problem, a slot machine according to claim 1 of the present invention provides:
The game can be started by setting a predetermined number of bets for one game using the gaming value, and a variable display device (reel 2L, 2C, 2R), the display result is derived, one game is completed, and a slot machine (where a winning can be generated according to the display result derived to the variable display device (reels 2L, 2C, 2R)) Slot machine 1)
Start operation means (start switch 7 ) operated when starting the game ,
Numerical value updating means (random number sequence changing circuit 555) for updating numerical data;
Game start means for starting a game when the start operation means (start switch 7) is operated in a startable state in which a game can be started;
When an operation means other than the start operation means (start switch 7) is operated in the startable state, the start of the game by the game start means is restricted even if the start operation means (start switch 7) is operated. Game start restriction means to play,
Regardless of whether the start operation means (start switch 7) is operated or not, whether the start is possible or whether the game start restriction means restricts the start of the game, the numerical value update means Random number extraction means (random number latch selector 558A) for extracting numerical data updated by the (random number sequence changing circuit 555) as a random value and storing it in a numerical data storage area (random number register R1D);
Numerical data reading means (reading numerical data at the start of the game) for reading numerical data stored in the numerical data storage area (random value register R1D) when the game starting means starts a game;
Data storage means for readable and writable storing data used for controlling the game;
Numerical data storage means for storing numerical data read by the numerical data reading means in the data storage means;
Predetermining means (internal lottery) for determining whether or not to allow the generation of a prize using the numerical data stored in the data storage means by the numerical data storage means ;
After the numerical data is stored in the numerical data storage area (random value register R1D) by the random number extraction means (random number latch selector 558A), the random number extraction means (random number) is read until the stored numerical data is read out. New numerical data is not stored by the latch selector 558A), and numerical data holding means for holding the stored numerical data (prohibition of latching of new numerical data);
The predetermined number (predetermined number of bets) as a game start condition is set, and the numerical data stored in the numerical data storage area (random number register R1D) when the startable state is entered. by reading the numerical data holding means hold canceling means for canceling the retention of the numerical data by the (predetermined bet number set during hold releasing means) (dummy read numerical data when the bet number of prescribed number is set) ,
Data holding means for holding data in the data storage means even when power supply is stopped;
Control state return means for returning to a control state before stopping power supply based on data held by the data holding means when power supply is started;
An interruption interrupt processing means for interrupting and executing an interruption process for enabling a return by the control state restoration means when a decrease in power supply is detected;
In the startable state, when the start operation means is operated, execution of the interrupt processing by the power interruption interrupt processing means is prohibited, and the numerical data is stored in the data storage means by the numerical data storage means Interrupt processing prohibition / permission means for permitting execution of the prohibited interrupt processing,
It is characterized by having.
According to this feature, after the numerical data extracted by the operation of the start operation means is stored in the numerical data storage area, the stored numerical data is held until the stored numerical data is read, Since it will not be overwritten by new numerical data, the numerical data will not change even if noise is applied to the signal line of the starting operation means due to static electricity or the like. There is no determination as to whether or not to allow the generation of a prize using numerical data different from the numerical data extracted at the timing when the means is operated.
The numerical value stored in the numerical data storage area is set when a predetermined number of bets serving as a game start condition are set and the start operation unit is ready to start the game. The data is read, and the numerical data holding means is released from the numerical data holding means. Before the startable state is entered, the start operating means is operated to store the numerical data in the numerical data storage area. Even if the state is held, since it becomes a state where new numerical data can be stored in the numerical data storage area at the same time as the startable state, it is extracted and held before the startable state is reached. The winning is generated using the numerical data that has been extracted, that is, the numerical data extracted at a timing different from the timing when the start operation means is operated in the startable state Nor the determination of whether allowable will take place.
Even when the start operation is possible, if the start operation means is operated while an operation means other than the start operation means is being operated, the numerical data is extracted, stored in the numerical data storage area, and retained. On the other hand, even if the game is not started by the operation of the start operation means, but the operation means other than the start operation means is operated and then the operation means is not operated, the numerical data storage area The numerical data stored in the numerical data storage means is read out, the numerical data holding means is released, and the numerical data is stored in the numerical data storage area by an invalid start operating means operation, Even if the state is held, the numerical data storage area is the same as the operation means other than the start operation means becomes non-operational and the operation of the start operation means becomes valid. Since new numerical data can be stored, it is extracted using the numerical data that has been extracted and held in a state where the operation of the start operation means is invalidated by operating an operation means other than the start operation means. It is not determined whether or not the winning is allowed.
In addition, it is possible to prevent the game from starting and determining whether or not to allow a prize to be generated even though the start operation means is erroneously detected due to noise such as static electricity.
Note that the predetermined number of bets is at least one bet number, and a game can be started by setting a bet number of two or more or setting a maximum bet number. good. Further, the game may be started by setting a bet amount determined according to a plurality of game states.
In addition, the numerical data holding means may extract new numerical data by the random number extracting means until the stored numerical data is read out after the numerical data is stored by the random number extracting means in the numerical data storage area. The numerical data stored in the numerical data storage area may be retained, or after the numerical data is stored in the numerical data storage area by the random number extraction means, The numerical data stored in the numerical data storage area is retained by prohibiting storage in the numerical data storage area until the numerical data is extracted by the random number extraction means until the numerical data is read. Anyway.
In addition, the first holding release unit and the second holding release unit are the numerical values stored in the numerical data storage area only when the numerical data extracted by the random number extraction unit is stored in the numerical data storage area. The numerical data stored in the numerical data storage area may be uniformly read regardless of whether the numerical data extracted by the random number extraction means is stored in the numerical data storage area. You may make it read.

A slot machine according to claim 2 of the present invention is the slot machine according to claim 1 ,
When numerical data is stored in the numerical data storage area (random value register R1D) by the random number extraction means (random number latch selector 558A), storage information (random number latch flag) indicating that the numerical data is newly stored is stored. Storage information setting means for setting (random number latch flag register RDFM),
The game start means starts a game in the startable state on condition that an operation of the start operation means (start switch 7) is detected and the stored information (random number latch flag) is set. It is characterized by.
According to this feature, it is not determined whether or not the game is started and the generation of a prize is allowed even though the numerical data is not extracted by the random number extraction unit. It is possible to determine whether or not the winning is surely permitted by using the numerical data extracted at the operation timing of the start operation means.

A slot machine according to claim 3 of the present invention is the slot machine according to claim 1 or 2 ,
A non-volatile memory (ROM 506) for storing an identification code (ID number) individually assigned to each slot machine;
The slot machine generates initial numerical data (start value of numerical data) based on an identification code (ID number) stored in the nonvolatile memory (ROM 506) when power supply is started. Means (random circuit setting processing),
The numerical value updating means (random number sequence changing circuit 555) is configured to output the numerical data from the initial numerical data (start value of numerical data) generated by the initial numerical data generation means (random number circuit setting process) when power supply is started. It is characterized by starting the update.
According to this feature, updating of the numerical data is started from the initial numerical data generated based on the identification code individually assigned to each slot machine. Therefore, the initial numerical data differs from slot machine to initial numerical data. Therefore, it is possible to effectively prevent fraud in which the operation of the start operation means is detected aiming at the timing of specific numerical data.

A slot machine according to claim 4 of the present invention is the slot machine according to any one of claims 1 to 3 ,
Game control means (CPU 505) for controlling the progress of the game,
The numerical data updating means (random number sequence changing circuit 555) inputs an operation clock (random number clock) having a period different from the operation clock (control clock) for operating the game control means (CPU 505). It is characterized by updating numerical data.
According to this feature, since the operation of the game control unit and the update cycle of the numerical data are synchronized, it is possible to prevent the random number value used by the predetermining unit from being biased, and the game control unit includes an illegal board. Even if is connected, it is impossible to specify the update interval of numerical data from the operation of the game control means, so it is possible to effectively prevent fraud in which the operation of the start operation means is detected aiming at the timing of specific numerical data it can.

A slot machine according to claim 5 of the present invention is the slot machine according to any one of claims 1 to 4 ,
The numerical data updating means (random number sequence changing circuit 555) inputs an operation clock (random number clock) with a predetermined period to update the numerical data,
The slot machine has an abnormality in the operating state of the numerical value updating means (random number sequence changing circuit 555) based on the input state of the operation clock (random number clock) input to the numerical data updating means (random number sequence changing circuit 555). It is characterized by comprising an operation clock abnormality determining means (random circuit abnormality inspection processing) for determining whether or not an error has occurred.
According to this feature, it is possible to prevent fraud in which it is possible to determine whether or not to allow the generation of a prize while the numerical data is not normally updated by the numerical value updating means, that is, while the numerical data is fixed.

It is a front view of the slot machine of the Example to which this invention was applied. It is an internal structure figure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure which shows an example of the address map in a main control part. It is a figure which illustrates the main part of a program management area and a built-in register. It is a figure which shows an example of the setting content in a header and function setting. It is a figure which shows an example of the setting content in 1st random number initial setting, 2nd random number initial setting, and interruption initial setting. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is a figure which shows the structural example etc. of a random value acquisition register. It is a figure which shows the structural example etc. of a random number latch selection register. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example etc. of a random number latch flag register. It is a figure which shows the structural example etc. of a random number interrupt control register. It is a figure which shows the structural example etc. of an input port register. It is a figure which shows the object combination of the internal lottery classified according to the structure of the winning combination determined by winning and a gaming state. It is a flowchart which shows the control content of the starting process (main) which a main control part performs at the time of starting. It is a flowchart which shows the control content of the security check process which a main control part performs. It is a flowchart which shows the control content of the security check process which a main control part performs. It is a flowchart which shows the control content of the random circuit abnormality inspection process which a main control part performs. It is a flowchart which shows the control content of the error process which a main control part performs when an error generate | occur | produces. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the game process which a main control part performs after a setting change process. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the BET process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the switch input determination process which a main control part performs in a timer interruption process (main). It is a flowchart which shows the control content of the interruption interruption process (main) performed when a main control part inputs a voltage drop signal from an interruption detection circuit. It is a timing chart for demonstrating operation | movement in a random number circuit. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the relationship between operation of a start switch, and a random value register. It is a timing chart which shows the detection condition of a start switch.

  Examples of the present invention will be described below.

  An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. A slot machine 1 according to the present embodiment includes a housing 1a having an open front surface, and a pivotable pivot at a side end of the housing 1a. The front door 1b is supported.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C and 2R (hereinafter referred to as a left reel, a middle reel and a right reel) in which a plurality of types of symbols are arranged on the outer periphery. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, on the outer periphery of the reels 2L, 2C, and 2R, “black 7”, “net 7 (shaded 7 in the figure)”, “white 7”, “BAR”, “replay”, A plurality of identifiable symbols such as “watermelon”, “black cherry”, “white cherry”, “bell”, and “orange” are drawn in a predetermined order, 21 pieces each. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3, respectively.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and rotated by reel motors 32L, 32C, and 32R (see FIG. 4), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R are reel sensors 33L, 33C, and 33R that detect a reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. , Is provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the front side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a normally white liquid crystal panel having transparency in a state where no voltage is applied to the liquid crystal element, and a transmissive region 51b corresponding to the see-through window 3 of the display region 51a. The reels 2L, 2C, and 2R can be visually recognized from the player side through the see-through window 3. Further, a backlight (not shown) for irradiating the display area 51a from behind is provided on the back surface of the display area 51a excluding the transmissive area 51b, and the back surface further has a concealing member for concealing the inside. (Not shown) is provided.

  On the front door 1b, a medal insertion unit 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a game value owned by the player) are used for one medal. A single bet switch 5 that is operated when setting the bet number, and using a credit, the maximum bet number (a game in this embodiment) among a specified number of bets determined in accordance with the game state within the range. When the state is RB (BB), 2 in the normal gaming state, the MAXBET switch 6 that is operated when setting, the medal stored as credits and the medals used for setting the number of bets are settled ( A settlement switch 10 that is operated when the credits and the amount of medals used for setting the bet are returned), a start switch 7 that is operated when starting the game, reels 2L, 2C, 2 Stop switch 8L is operated to each stop of the rotation, 8C, 8R, but are provided operable by the player.

  The front door 1b also displays a credit indicator 11 that displays the number of medals stored as credits, the number of medals acquired in BB, which will be described later, and an error code that indicates the contents when an error occurs. An auxiliary indicator 12 and a payout indicator 13 for displaying the number of medals paid out due to the occurrence of a prize are provided.

  Further, on the front door 1b, a 1BETLED 14 that notifies that the bet number is set to 1 by lighting, a 2BETLED 15 that notifies that the bet number is set to 2, and 3 bets are set. 3BET LED 16 to notify when lit, insertion request LED 17 to notify that a medal can be inserted is lit, start valid LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, wait (previous Waiting state LED 19 for informing that it is in the state of waiting for the start of reel rotation since a certain period of time has not elapsed since the start of the game, during replay informing that it is in the replay game described later An LED 20 is provided.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the betting number by operating the one-sheet BET switch 5 and the MAXBET switch 6 is effective. Inside the stop switches 8L, 8C, and 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R for informing that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective by lighting (FIG. 4).

  Inside the front door 1b, there is a reset switch 23 for detecting a reset operation for releasing an error state described later and a stop state described later by a predetermined key operation, while changing a set value and confirming a set value described later. A set value display 24 for displaying the set value at that time, and a flow path of medals inserted from the medal insertion unit 4 on the side of a hopper tank 34a (see FIG. 2) described later provided in the housing 1a or A medal selector having a insertion medal sensor 31 for detecting a medal that is inserted from the flow path switching solenoid 30 and the medal insertion unit 4 and selectively flows to the hopper tank 34a side to selectively switch to one of the medal payout exits 9 side. The door opening detection switch 25 (refer FIG. 4) which detects the open state of the front door 1b is provided.

  As shown in FIG. 2, a reel sensor 33L that can detect the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R, and the reels 2L, 2C, and 2R, as shown in FIG. , 33C, 33R (see FIG. 4), an external output board 1000 for outputting an external output signal, a hopper tank 34a for storing medals inserted from the medal insertion section 4, and a hopper tank 34a. A hopper unit 34 including a hopper motor 34b for paying out medals from the medal payout opening 9, a payout sensor 34c for detecting medals paid out by driving the hopper motor 34b, and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full sensor 35 a made up of a pair of electrically conductive members spaced apart from each other and provided at a height capable of detecting a predetermined amount of stored medals is provided. It is possible to detect that the medal storage amount stored in the inside when it is conductive by contacting through the medal stored in the inside exceeds a predetermined amount, that is, that the overflow tank is full. It has become.

  On the front surface of the power supply box 100 is a stop switch for selecting whether to enable / disable a stop function for controlling the stop state at the end of BB, which will be described later (a state in which the progress of the game is restricted until a reset operation is performed). 36a, automatic checkout for selecting whether the automatic checkout function is effective / invalid for controlling automatic checkout processing (processing for adjusting (returning) medals stored as credits regardless of the player's operation) at the end of BB described later A switch 36b, a setting key switch 37 for switching to a setting change state or a setting confirmation state, and functions as a reset switch for canceling an error state or a stop state in a normal state. A reset / setting switch 38 that functions as a setting switch for changing the setting value of the winning probability (race rate). Power switch 39 is operated when FF is provided.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or the bet number is set using credits. In order to use credits, the single BET switch 5 or the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 1) become effective, and the operation of the start switch 7 is effective, that is, the game can be started. It becomes a state. In the present embodiment, as the specified number of bets, two are determined in the gaming state RB (BB) and three in the normal gaming state. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, the winning line L1 set across the symbols arranged in the middle of each reel 2L, 2C, 2R and the symbols arranged in the upper row of each reel 2L, 2C, 2R are straddled. The winning line L2, the winning line L3, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, the lower side of the reel 2R, that is set across the symbols arranged in the lower stage of the reels 2L, 2C, 2R. There are five types of winning lines L4 set across straddling symbols, the lower line of reel 2L, the middle part of reel 2C, the upper part of reel 2R, that is, the winning line L5 set straddling the symbols lined up to the right. It is defined as.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  When one of the reels 2L, 2C, 2R is stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is set on any of the activated pay lines L1 to L5. When the reels 2L, 2C, and 2R are stopped as a display result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). If a combination of symbols with a medal payout is arranged on a plurality of activated pay lines, the total number of payouts determined for each of the symbol combinations arranged on the activated pay line is totaled. The total number of medals is awarded to the player. However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game, and when the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. It will be. In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, stop switch 36a, automatic checkout switch 36b, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101. Yes.

  On the game control board 40, the one-sheet BET switch 5, the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, the settlement switch 10, the reset switch 23, the insertion medal sensor 31, the door opening detection switch 25, The reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, stop switch 36a, automatic settlement switch 36b, setting key switch 37, reset / setting switch 38 are connected via the power supply board 101. Are connected, and the detection signals of these connected switches are inputted.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other, and are described above via the power supply board 101. The hopper motor 34b is connected, and these electric components are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 is configured by a one-chip microcomputer, executes a control program stored in a ROM 506, which will be described later, and performs processing related to the progress of the game, and also includes a control circuit mounted on the game control board 40. Control each part directly or indirectly.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502 via, for example, a control external clock terminal EXC of the main control unit 41 as shown in FIG. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41. The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuit 509 via the random number external clock terminal ERC of the main control unit 41 as shown in FIG. 5, for example. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 gives a reset signal to the main control unit 41 in a state where the power supply is unstable, such as when the power is turned on or when the power is turned off.

  FIG. 5 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5 is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset / interrupt controller 504, a CPU 505, a ROM 506, and a RAM 507. A CTC (counter / timer circuit) 508, a random number circuit 509, a PIP (parallel input port) 510, a serial communication circuit 511, and an address decoding circuit 512.

  FIG. 6 shows an example of an address map in the main control unit 41. As shown in FIG. 6, the area from address 0000H to address 1FFFH is allocated to the ROM 506 and includes a user program area and a program management area. FIG. 7A shows an example of the usage and contents of the main part of the program management area in the ROM 506. The area from address 2000H to address 20FFH is a built-in register area assigned to the built-in register of the main control unit 41. FIG. 7B shows an example of the usage and contents of the main part of the built-in register area. An area from address 7E00H to address 7FFFH is a work area assigned to the RAM 507, and can be assigned to an I / O map or a memory map. An area from address FDD0H to address FDFBH is an XCS decode area allocated to the address decode circuit 512.

  The program management area is a storage area for storing information necessary for the CPU 505 to execute the user program. As shown in FIG. 7A, the program management area includes a header KHDR, a function setting KFCS, a first random number initial setting KRS1, a second random number initial setting KRS2, an interrupt initial setting KIIS, a security time setting KSES, include.

  A header KHDR stored in the program management area indicates reading setting of internal data in the main control unit 41. FIG. 8A illustrates the correspondence between setting data and operation in the header KHDR. Here, the main control unit 41 can set a ROM read prevention function and a bus output mask function. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 506 provided in the main control unit 41. When the read prohibition is set, the data stored in the ROM 506 cannot be read. The bus output mask function is used for address bus output, data bus output, and control signal output in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the main control unit 41. This function disables reading of internal data from an external device by applying a mask. As shown in FIG. 8A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 8A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The function setting KFCS stored in the program management area indicates the operation setting of the watchdog timer in the main control unit 41 and the use setting of various function shared terminals. FIG. 8B shows an example of setting contents in the function setting KFCS.

  The bit number [7-5] of the function setting KFCS indicates, for example, permission / prohibition of the operation of the watchdog timer that can be set as an interrupt factor in the reset / interrupt controller 504, and the cycle when it is permitted. The bit number [4] of the function setting KFCS indicates that the predetermined function shared terminal (first shared terminal) in the main control unit 41 is the second channel transmission terminal TXB used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXB terminal setting that designates whether to use as the chip select output terminal XCS13. In the example shown in FIG. 8B, if the bit value in the bit number [4] of the function setting KFCS is “0”, the first shared terminal is used for the second channel transmission in the serial communication circuit 511. This is the setting for the 2-channel transmission terminal TXB. On the other hand, if the bit value is “1”, the first dual-purpose terminal is set to the chip select output terminal XCS13 used in the address decode circuit 512. In this embodiment, the bit number [4] of the function setting KFCS is set to “0” and the first shared terminal is set to the second channel transmission terminal TXB, so that serial communication with the effect control board 90 is possible. To.

  The bit number [3] of the function setting KFCS indicates that the predetermined function shared terminal (second shared terminal) in the main control unit 41 is the first channel transmission terminal TXA used by the serial communication circuit 511 or the address decoding circuit 512. Is a TXA terminal setting indicating whether the chip select output terminal XCS12 is used. In the example shown in FIG. 8B, if the bit value in the bit number [3] of the function setting KFCS is “0”, the second shared terminal is used for the first channel transmission in the serial communication circuit 511. 1 channel transmission terminal TXA is set. On the other hand, if the bit value is “1”, the second dual-purpose terminal is set to the chip select output terminal XCS12 used in the address decode circuit 512. In this embodiment, the bit number [3] of the function setting KFCS is set to “0” and the second shared terminal is set to the first channel transmission terminal TXA, but the first channel reception is not used.

  For the bit number [2] of the function setting KFCS, a predetermined function shared terminal (third shared terminal) in the main control unit 41 is used as the first channel reception terminal RXA used by the serial communication circuit 511, or is used by the PIP 510. This is an RXA terminal setting indicating whether the input port is P5. In the example shown in FIG. 8B, if the bit value in the bit number [2] of the function setting KFCS is “0”, the third shared terminal is used for the first channel reception in the serial communication circuit 511. 1 channel receiving terminal RXA is set. On the other hand, if the bit value is “1”, the third shared terminal is set to the input port P5 used in the PIP 510. In this embodiment, the bit number [2] of the function setting KFCS is set to “0” and the third shared terminal is set to the first channel reception terminal RXA, but the first channel reception is not used.

  The bit number [1] of the function setting KFCS is an input used by the PIP 510, or a predetermined function shared terminal (fourth shared terminal) in the main control unit 41 is an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. This is an NMI connection setting indicating whether to set the port P4. In the example shown in FIG. 8B, if the bit value [1] in the bit number [1] of the function setting KFCS is “0”, the setting of the external non-maskable interrupt terminal XNMI whose fourth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fourth shared terminal is set for the input port P4 used in the PIP 510 (CPU disconnected). In this embodiment, the bit number [1] of the function setting KFCS is set to “1” and the fourth shared terminal is set to the input port P4 used in the PIP 510, but the input port P4 is unused. .

  The bit number [0] of the function setting KFCS is an input used by the PIP 510, or the predetermined function shared terminal (fifth shared terminal) in the main control unit 41 is set to the external maskable interrupt terminal XINT connected to the CPU 505 or the like. This is an XINT connection setting indicating whether to set the port P3. In the example shown in FIG. 8B, if the bit value in the bit number [0] of the function setting KFCS is “0”, the setting of the external maskable interrupt terminal XINT in which the fifth shared terminal is connected to the CPU 505 and the like (CPU connection). On the other hand, if the bit value is “1”, the fifth shared terminal is set for the input port P3 used in the PIP 510 (CPU disconnected). In this embodiment, the bit number [0] of the function setting KFCS is set to “0”, and the fourth shared terminal is set to the external maskable interrupt terminal XINT connected to the CPU 505 or the like, so that the power interruption detection circuit 48 A voltage drop signal is input.

  The first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area indicate the initial setting of the random number circuit 509. FIG. 9A shows an example of the setting contents in the first random number initial setting KRS1. FIG. 9B shows an example of setting contents in the second random number initial setting KRS2.

  The bit number [3] of the first random number initial setting KRS1 is a random number circuit use setting indicating whether to use the random number circuit 509 or not. In the example shown in FIG. 9A, if the bit value in the bit number [3] of the first random number initial setting KRS1 is “0”, the random number circuit 509 is not used (unused), but “1”. "Is set to use the random number circuit 509 (use). In this embodiment, the random number circuit 509 is set to be usable by setting the bit number [3] of the first random number initial setting KRS1 to “1”.

  The bit number [2] of the first random number initial setting KRS1 uses the random number update clock RGK (see FIG. 12) used for updating the numerical data as the random number value in the random number circuit 509 as the internal system clock SCLK or for the random number This is a random number update clock setting indicating whether the clock RCLK is divided by two. In the example shown in FIG. 9A, if the bit value in the bit number [2] of the first random number initial setting KRS1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. If it is 1 ″, the random number clock RCLK is divided by two and used as the random number update clock RGK. In the present embodiment, the bit number [2] of the first random number initial setting KRS1 is set to “1”, and the random number clock RCLK is divided by two to be used as the random number update clock RGK.

  The bit number [1-0] of the first random number initial setting KRS1 is a random number update rule setting indicating whether or not to change the random number update rule in the random number circuit 509 and the change method in the case of the change. In the example shown in FIG. 9A, if the bit value in the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number update rule is not changed, and if it is “01”. The setting for changing the random number update rule by software is made after the second round, and if it is “10”, the random number update rule is automatically changed after the second round.

  The bit number [3-2] of the second random number initial setting KRS2 is set to a fixed bit value “00”. Note that “B” of “00B” in FIG. 9B indicates binary display. The bit number [1-0] of the second random number initial setting KRS2 indicates the setting relating to the start value in the numerical data that becomes the random value in the random number circuit 509. In the example shown in FIG. 9B, if the bit value in the bit number [1] of the second random number initial setting KRS2 is “0”, the start value is set to a predetermined default value 0001H, while “1”. Is set to a value based on an ID number, which is unique identification information given to each main control unit 41. In the example shown in FIG. 9B, if the bit value in the bit number [0] of the second random number initial setting KRS2 is “0”, the start value is not changed every time the system is reset. When it is 1 ″, the start value is changed every time the system is reset. When the start value is set to a value based on the ID number, a part or all of the calculation for performing a predetermined scramble process on the ID number and the calculation such as addition, subtraction, multiplication, and division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value. When the start value is changed at each system reset, for example, the count value of the free run counter built in the main control unit 41 is set to a predetermined internal register (random number start) provided in the main control unit 41 when the system reset occurs. Value register). Then, by using the stored value of the random number start value register as it is at the time of initial setting or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the start value is It may be determined at random. The free-run counter only needs to be backed up using a backup power source common to the backup location on the game control board 40. Alternatively, the free-run counter may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 507 or the like. In this way, the free-run counter is backed up by the backup power supply, so that the count value in the free-run counter is stored for a predetermined period even when the power supply is stopped.

  When two circuits (corresponding to the first and second channels) for generating numerical data to be random values in the random number circuit 509 are provided, the first shown in FIGS. 9A and 9B. The bit number [3-0] of the random number initial setting KRS1 and the bit number [3-0] of the second random number initial setting KRS2 are used to indicate the initial setting in the first channel. On the other hand, the bit number [7-4] of the first random number initial setting KRS1 and the bit number [7-4] of the second random number initial setting KRS2 (omitted in FIGS. 9A and 9B), the second What is necessary is just to use as a thing which shows the initial setting in a channel.

  The interrupt initial setting KIIS stored in the program management area indicates an initial setting related to handling of maskable interrupts generated in the main control unit 41. FIG. 9C shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of priority levels of maskable interrupt factors is set. In the example shown in FIG. 9C, if any of “00H” to “02H” and “06H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt from the CTC 508 A combination of priorities with the factor as the highest priority is set. On the other hand, if any one of “03H” and “07H” is designated, a combination of priorities that gives the highest priority to the maskable interrupt factor from the random number circuit 509 is set. If either “04H” or “05H” is designated, a combination of priorities with the highest priority given to the maskable interrupt factor from the serial communication circuit 511 is set. If the specified value is different even if the priority is a combination of priority with the maskable interrupt factor from the same circuit as the highest priority, the type of maskable interrupt factor with the highest priority and the priority combination in the second or lower order, etc. Is different.

  The security time setting KSES stored in the program management area is the frequency at which an abnormality is detected when monitoring the frequency of the random number clock RCLK, the time of the security mode in which the main control unit 41 starts operation (security time). ). Here, when the operation mode of the main control unit 41 is the security mode, a predetermined security check process is executed to check whether or not the contents stored in the ROM 506 have been changed. FIG. 10A shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES is a random number clock abnormality detection setting indicating a frequency at which an abnormality is detected when the frequency of random number clock RCLK is monitored. FIG. 10B shows an example of setting contents in the bit number [7-6] of the security time setting KSES. The bit number [7-6] of the security time setting KSES specifies a reference value (determination value) at which the frequency of the random number clock RCLK is detected as abnormal based on the frequency of the internal system clock SCLK. The bit number “5” of the security time setting KSES is set to a fixed bit value “0”.

  The bit number [4-3] of the security time setting KSES indicates a time setting when the security time is extended by a random time every system reset. FIG. 10C shows an example of setting contents in the bit number [4-3] of the security time setting KSES. In the example shown in FIG. 10C, if the bit value in the bit number [4-3] of the security time setting KSES is “00”, the setting is not performed at random time extension. On the other hand, if the bit value is “01”, the short mode is set, and if the bit value is “10”, the long mode is set. Here, when the short mode or the long mode is designated, for example, the count value of the free run counter built in the main control unit 41 is changed to a predetermined built-in register (variable) included in the main control unit 41 when a system reset occurs. Store in the security time register. Then, the security time can be reduced by using the stored value of the variable security time register as it is at the initial setting or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). What is necessary is just to determine the extension time at the time of extending at random. As an example, when the frequency of the internal system clock SCLK is 6.0 MHz, the extension time is randomly determined in the range of 0 to 680 μs (microseconds) in the short mode, and in the range of 0 to 348, 160 μs in the long mode. The extension time is determined at random. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 408 μs in the short mode, and in the range of 0 to 208,896 μs in the long mode. The extension time is determined at random. The free-run counter used for randomly determining the extension time for extending the security time for each system reset randomly determines the start value of the random number generated by the random number circuit 509 for each system reset. Therefore, the counter may be the same as the free-run counter used for this purpose, or may be a counter provided separately.

Bit number [2-0] of security time setting KSES indicates time setting when the security time is set to one of a plurality of pre-selectable extended times in addition to the fixed time. FIG. 10D shows an example of setting contents in the bit number [2-0] of the security time setting KSES. In the example shown in FIG. 10D, if the bit value in the bit number [2-0] of the security time setting KSES is “000”, there is no extension time added to the fixed time, and no setting is made. On the other hand, if the bit value is a value other than “000”, it is set to one of a plurality of extension times determined using the cycle T _SCLK of the internal system clock SCLK. In this case, a different extension time is set according to the designated bit value. As an example, if the bit value [2-0] of the security time setting KSES is “001” when the frequency of the internal system clock SCLK is 6.0 MHz, about 699.1 ms in addition to the fixed time. An extension time of (milliseconds) is set. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz and the bit value in the bit number [2-0] of the security time setting KSES is “001”, in addition to the fixed time An extension time of about 419.4 ms is set.

  Further, the short mode or the long mode is set by the bit value [4-3] of the security time setting KSES, and the bit value in the bit number [2-0] of the security time setting KSES is set to other than “000”. Thus, it is possible to set an extension time to be added to the fixed time. In this case, both the extension time corresponding to the bit value in the bit number [2-0] and the extension time randomly determined based on the bit value in the bit number [4-3] are fixed times. By adding, the security time for the main control unit 41 to be in the security mode is determined.

  The external bus interface 501 provided in the main control unit 41 shown in FIG. 5 includes an interface function between an external bus and an internal bus of the chip constituting the main control unit 41, a direction control function of an address bus, a data bus, and each control signal Is a bus interface. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the main control unit 41, and transmits / receives address signals, data signals, various control signals, and the like to / from these external devices. Anything to do. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to internal data of the main control unit 41 from an external device via the external bus interface 501, and stores internal data such as a game control program and fixed data stored in the ROM 506, for example. This is a circuit for limiting inappropriate external reading. Here, a circuit analysis device such as an in-circuit emulator (ICE) may be connected to the external bus interface 501 as an external device.

  As an example, according to the contents of the header KHDR stored in the program management area of the ROM 506, it is possible to switch between prohibiting or permitting reading of stored data in the ROM 506. For example, when the header KHDR is bus output mask invalid data, the ROM 506 can be read by an external device, and external reading of internal data is permitted. On the other hand, if the header KHDR is the bus output mask valid data, the ROM 506 can be read from the external device by masking the address bus output, data bus output and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that internal data cannot be read from the external device. . Further, when the header KHDR is ROM read prohibition data, the ROM 506 itself may not be read, and reading of stored data in the ROM 506 may be prevented. For example, in the ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, the bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, in the case of a mass production ROM, the bus output mask valid data is written in the header KHDR so that the CPU 505 and the like can read out the ROM 506 inside the main control unit 41 while the ROM 506 by an external device. It is only necessary to prevent reading of.

  As another example, the internal resource access control circuit 501A has requested that the internal data of the main control unit 41, such as all or part of the stored data in the ROM 506, be read from an external device connected to the external bus interface 501. Is detected. When detecting this read request, the internal resource access control circuit 501A determines whether or not the main control unit 41 is allowed to read internal data. For example, it is assumed that all or part of the stored data in the ROM 506 has been encrypted. In this case, if the read request from the external device is a read request for an encryption processing program or key data stored in the ROM 506, the internal resource access control circuit 501A rejects the read request and sets the main control unit 41. Reading of internal data is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 506 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be in an off state. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 506). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from an external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 506. When an authentication code is input from the external device, this authentication code is compared with the internally stored authentication code. If they match, a read request is accepted and the main control unit 41 is allowed to read internal data. . On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and the internal control unit 41 is prohibited from reading the internal data. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. As a result, it is possible to read out the internal data of the main control unit 41 using a correct authentication code obtained in advance by an inspection organization or the like, and to check the validity of the internal data appropriately. .

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 506 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the reading prohibition flag is in the off state, reading of the ROM 506 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. It ’s fine. That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A does not have a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read the internal data of the main control unit 41 such as the data stored in the ROM 506. At this time, if the read prohibition flag is on, the read request from the external device is rejected and the main controller 41 is prohibited from reading the internal data. On the other hand, if the read prohibition flag is off, the read request from the external device is accepted and the main controller 41 is allowed to read the internal data. With such a configuration, a provider who creates a game control program and stores it in the ROM 506 reads the program that has been debugged from the ROM 506 into an external device while the read prohibition flag is off. Can do. Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 506 can be restricted thereafter, and the ROM 506 by the user of the slot machine 1 or the like can be restricted. Can be prevented from being read. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  The read prohibition flag is not set irreversibly, but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, the external reading of the ROM 506 may be restricted by erasing the data stored in the ROM 506 (for example, flash erasure).

  The clock circuit 502 provided in the main control unit 41 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In this embodiment, the control clock CCLK generated by the control clock generation circuit 42 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 505 that control the progress of the game in the main control unit 41. The internal system clock SCLK is also supplied to the random number circuit 509 and used to monitor the frequency of the random number clock RCLK supplied from the random number clock generation circuit 43. Further, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the main control unit 41. It is desirable that the internal system clock SCLK is not output to the outside of the main control unit 41. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 505) of the main control unit 41 from the outside. In the case of updating by this, it is possible to prevent the random number update cycle from being specified externally.

  The unique information storage circuit 503 included in the main control unit 41 is a circuit that stores a plurality of types of unique information serving as internal information of the main control unit 41, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 506 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 506, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. The ID number is an 8-byte number assigned when the main control unit 41 is manufactured, and indicates a different numerical value for each chip constituting the main control unit 41. Here, it is sufficient that the chip individual number can be read from the user program while the ID number cannot be read from the user program. The unique information storage circuit 503 may be included in the ROM 506 by using a predetermined area of the ROM 506, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 505 by using a built-in register of the CPU 505, for example.

  The reset / interrupt controller 504 provided in the main control unit 41 is for controlling various resets and interrupt requests generated inside or outside the main control unit 41. The reset controlled by the reset / interrupt controller 504 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 504 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 505 is in an interrupt-disabled state. When a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port P4) for a certain period of time. An interrupt that occurs. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 505, and multiple interrupts can be executed by setting priority. The cause of maskable interrupt INT is that a low level signal is input to external maskable interrupt terminal XINT (also used as input port P3) for a certain period of time, and a timeout occurs in the timer circuit included in CTC 508. There are multiple types of interrupt factors, such as the occurrence of an interrupt factor due to data transmission in the serial communication circuit 511, and the occurrence of an interrupt factor due to the acquisition of numerical data as a random value in the random number circuit 509. What is necessary is just to be predetermined.

  The reset / interrupt controller 504 includes an interrupt mask register IMR (address 2028H), an interrupt wait monitor register IRR (address 2029H), among the built-in registers provided in the main control unit 41 as shown in FIG. Interrupt control and reset management are performed using the monitor monitor register ISR (address 202AH) and the internal information register CIF (address 208CH). The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The internal information register CIF is a register for managing the reset factor generated immediately before and recording the frequency abnormality of the random number clock RCLK.

  FIG. 11A shows a configuration example of the internal information register CIF. FIG. 11B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data CIF4 stored in the bit number [4] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCLK. In the example shown in FIG. 11B, when the frequency abnormality of the random number clock RCLK is not detected, the bit value of the internal information data CIF4 becomes “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 11B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”.

  The internal information data CIF1 stored in the bit number [1] of the internal information register CIF is a WDT timeout instruction indicating whether or not the reset factor generated immediately before is a user reset due to a watchdog timer (WDT) timeout. . In the example shown in FIG. 11B, when the immediately preceding reset factor is not a user reset due to a watchdog timer timeout (timeout has not occurred), the bit value of the internal information data CIF1 becomes “0”, while the watchdog When a user reset is caused by a timer timeout (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  The CPU 505 provided in the main control unit 41 executes processing for controlling the progress of the game in the slot machine 1 by executing the program read from the ROM 506. At this time, the CPU 505 reads out fixed data from the ROM 506, the CPU 505 writes various data to the RAM 507 and temporarily stores the data, and the CPU 505 stores various data temporarily stored in the RAM 507. The CPU 505 receives the input of various signals from the outside of the main control unit 41 via the external bus interface 501 or the PIP 510, and the CPU 505 receives the input of various signals via the external bus interface 501 or the serial communication circuit 511. A transmission operation for outputting various signals to the outside of the main control unit 41 is also performed.

  As described above, in the main control unit 41, the CPU 505 executes control according to the program stored in the ROM 506. Therefore, the main control unit 41 (or CPU 505) executes (or performs processing) below. Specifically, the CPU 505 executes control according to a program. The same applies to microcomputers mounted on boards other than the game control board 40.

  A ROM 506 provided in the main control unit 41 stores a user program for game control, fixed data, and the like. The ROM 506 stores a security check program 506A. The CPU 505 reads the security check program 506A stored in the ROM 506 when the main control unit 41 shifts to the security mode in response to the power-on of the slot machine 1 or the occurrence of a system reset, and whether the storage content of the ROM 506 has been changed. Execute security check processing to check whether or not. The security check program 506A may be stored in a built-in memory different from the ROM 506. Further, the security check program 506A may correspond to a security check process for inspecting the storage content of the external memory externally attached to the main control unit 41 via the external bus interface 501, for example.

  A RAM 507 provided in the main control unit 41 provides a work area for game control. Here, at least a part of the RAM 507 may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine is stopped, at least part of the contents of the RAM 507 is stored for a predetermined period. In this embodiment, all areas of the RAM 507 are backup RAMs, and all contents of the RAM 507 are saved for a predetermined period even when power supply to the slot machine is stopped.

  The CTC 508 provided in the main control unit 41 includes, for example, an 8-bit programmable timer built in 3 channels (PTC0 to PTC2), and includes a timer circuit capable of generating a real-time interrupt and measuring time. Each programmable timer PTC0-PTC2 has a timer value that is updated in accordance with a signal change of the count clock generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is good. In addition, the CTC 508 may incorporate, for example, an 8-bit programmable counter with 4 channels (PCC0 to PCC3). Each of the programmable counters PCC0 to PCC3 is only required to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3. The CTC 508 resets the start time of the random number generated by the free run counter used for randomly determining the extension time (variable setting time) for extending the security time for each system reset or the random number circuit 509. A free-run counter or the like that is used to randomly determine each time may be included. Alternatively, these free-run counters may be included in an internal circuit of the main control unit 41 different from the CTC 508 such as a backup area of the RAM 507, for example.

  A random number circuit 509 included in the main control unit 41 is a circuit that generates numerical data that is a random value having a predetermined update range, such as a 16-bit random number. In the present embodiment, on the game control board 40 side, numerical data indicating a random value for internal lottery to be described later is controlled to be countable. In addition, in order to improve a game effect, random numbers other than these may be used. The CPU 505 uses a random counter different from the random number circuit 509 based on the numerical data extracted from the random number circuit 509 to process or update various numerical data by software, thereby indicating numerical data indicating a random value for internal lottery. May be counted. In the following, it is assumed that numerical data indicating random numbers for internal lottery is not processed by software from numerical data extracted by the CPU 505 from the random number circuit 509 serving as hardware. The random number circuit 509 may be incorporated in the main control unit 41 or may be externally attached to the main control unit 41 as a random number circuit chip different from the main control unit 41. .

  The random number for internal lottery is a value used to determine whether or not to allow a plurality of types of winnings, and takes a value in the range of “0” to “65535” in this embodiment.

  FIG. 12 is a block diagram illustrating a configuration example of the random number circuit 509. As shown in FIG. 12, the random number circuit 509 includes a frequency monitoring circuit 551, a clock flip-flop 552, a random number generation circuit 553, a start value setting circuit 554, a random number sequence change circuit 555, a random number sequence change setting circuit 556, and a latch flip-flop. 557A, 557B, random number latch selectors 558A, 558B, and random number value registers 559A, 559B. Note that the random value register 559A and the random value register 559B are respectively a random value register R1D (address 2038H-2039H) and a random value register R2D (address) included in the built-in register of the main control unit 41 as shown in FIG. 203AH-203BH). In this embodiment, the random numbers to be acquired are only random numbers for internal lottery, and among the latch flip-flops 557A, 557B, the random number latch selectors 558A, 558B, and the random number value registers 559A, 559B, the latch flip-flop 557B, The random number latch selector 558B and the random number value register 559B are unused.

  The frequency monitoring circuit 551 is a circuit for monitoring the frequency of the random number clock RCLK generated by the random number clock generating circuit 43 and detecting the occurrence of an abnormality. For example, the frequency monitoring circuit 551 monitors an oscillation signal input to the random number external clock terminal ERC, and sets the contents of the bit number [7-6] of the security time setting KSES based on the internal system clock SCLK (FIG. 10B When the frequency abnormality according to the reference) is detected, the bit number [4] of the internal information register CIF is set to “1”. In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 is input to the random number external clock terminal ERC.

  The clock flip-flop 552 is configured using, for example, a D-type flip-flop, and the random number clock RCLK from the random number external clock terminal ERC is input to the clock terminal CK. Further, in the clock flip-flop 552, the negative phase output terminal (inverted output terminal) Q bar is connected to the D input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal) Q, while the latch clock RC0 is output from the negative phase output terminal (inverted output terminal) Q bar. In this case, when the signal state of the random number clock RCLK input to the clock terminal CK changes a predetermined state, the clock flip-flop 552 has a positive phase output terminal (non-inverted output terminal) Q and a negative phase output terminal ( Inverted output terminal) Changes the signal state in the output signal from the Q bar. For example, the clock flip-flop 552 rises when the signal state of the random number clock RCLK changes from a low level to a high level, or rises when the signal state of the random number clock RCLK changes from a high level to a low level. The input signal at the D input terminal is captured at any one of the falling timings. At this time, from the positive phase output terminal (non-inverted output terminal) Q, the input signal captured at the D input terminal is output without being inverted, while the negative phase output terminal (inverted output terminal) Q bar is output. From the input signal captured by the D input terminal is inverted and output. Thus, the random number update clock RGK having an oscillation frequency (for example, 10 MHz) that is ½ of the oscillation frequency (for example, 20 MHz) of the random number clock RCLK from the positive phase output terminal (non-inverted output terminal) Q of the clock flip-flop 552. Is output from the negative phase output terminal (inverted output terminal) Q bar, that is, the reverse phase signal (inverted signal) of the random number update clock RGK, that is, the same frequency as the random number update clock RGK and the phase of the random number update clock RGK is π. A different latch clock RC0 is output by (= 180 °).

  The random number update clock RGK output from the clock flip-flop 552 is input to the clock terminal of the random number generation circuit 553 and used for incrementing the count value in the random number generation circuit 553. The latch clock RC0 output from the clock flip-flop 552 is branched into the latch clock RC1 and the latch clock RC2 at the branch point BR1. Therefore, the latch clock RC1 and the latch clock RC2 have the same oscillation frequency, and the signal state changes with a common cycle. Here, examples of changes in the signal state in the latch clock RC1 and the latch clock RC2 include a rising edge that changes from a low level to a high level and a falling edge that changes from a high level to a low level. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A and becomes a random number acquisition clock used for generating the latch signal SL1 at the start of the game.

  The oscillation frequency of the random number clock RCLK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other, and one of the oscillation frequencies is the other oscillation frequency. It is never an integer multiple of. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCLK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clocks RC1 and RC2 are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 505. That is, the clock flip-flop 552 is based on the random number clock RCLK generated by the random number clock generation circuit 43, and the random number update clock RGK for updating the count value, or the latch clock that is used as a plurality of random number acquisition clocks. As RC1 and RC2, oscillation signals whose signal states change with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) are generated.

  The random number generation circuit 553 is composed of, for example, a 16-bit counter and the like, and based on an input such as a random number update clock RGK output from the clock flip-flop 552, a predetermined initial value within a predetermined range in which numerical data can be updated. It is a circuit that cyclically updates to a predetermined final value. For example, the random number generation circuit 553 responds to the rising edge in the random number update clock RGK that is an input signal to a predetermined clock terminal, and “65535” from the initial value set in the range from “0” to “65535”. The numerical data is counted up so that one is added at a time. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The start value setting circuit 554 sets the start value in the count value generated by the random number generation circuit 553 in accordance with the bit value (see FIG. 9B) in the bit number [1-0] of the second random number initial setting KRS2. Set. For example, the start value setting circuit 554 sets the start value to the default value “0000H” if the bit number [1-0] of the second random number initial setting KRS2 is “00”, and if it is “10”. The value is set based on the ID number. If “01”, the value is changed every time the system is reset. In this embodiment, the bit number [1-0] of the second random number initial setting KRS2 is set to “10”, and a value based on the ID number is set as the start value in the count value generated by the random number generation circuit 553. Is done.

  The random number sequence change circuit 555 is a circuit that allows the permutation, which is the update order of the numerical data, to be changed to a permutation that conforms to a predetermined random number update rule when the numerical data generated by the random number generation circuit 553 makes a round. For example, the random number sequence change circuit 555 executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553. The random number sequence change circuit 555 can change the permutation, which is the update order of the numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble process, for example.

  The random number sequence change setting circuit 556 determines the update order of the numerical data in the random number sequence change circuit 555 according to the bit value (see FIG. 9A) in the bit number [1-0] of the first random number initial setting KRS1. It is a circuit for performing the setting to change. For example, if the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number sequence change setting circuit 556 sets the random number update rule not to change after the second round, while “01” If so, the random number update rule is changed in response to a change request by software after the second round, and if it is “10”, the random number update rule is automatically changed. In this embodiment, the bit number [1-0] of the first random number initial setting KRS1 is set to “10”, and the random number update rule is automatically changed.

  When the random number update circuit 556 changes the random number update rule by software in response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, FIG. Of the built-in registers included in the main control unit 41 as shown, the random number update rule RDSC (address 2034H) is used to control the change of the random number update rule. FIG. 13A shows a configuration example of the random number sequence change register RDSC. FIG. 13B shows an example of setting contents in each bit of random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates the presence / absence of a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 13B, when the random number sequence change request is not made by software, the bit value of the random number sequence change request data RDSC0 is “0”. The bit value is “1”.

  FIG. 14 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553 is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. Then, change the random number update rule. In the operation example shown in FIG. 14, the random number sequence RSN output from the random number sequence change circuit 555 is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 505 executing the user program stored in the ROM 506.

  In response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0 and the bit value is “1”. In response to "," a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 556, according to the count value permutation RCN output from the random number generation circuit 553 reaching a predetermined final value, for example, any one of a plurality of types of random number update rules prepared in advance. The random number update rule is changed, for example, by selecting. In the operation example shown in FIG. 14, the random number sequence change circuit 555 outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence change circuit 555 outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 555 is “65535 → 65534 →... → 0”. Become.

  When the CPU 505 executes the user program stored in the ROM 506 and the bit value “1” is written again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 14, when the random number sequence change circuit 555 outputs the numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. After that, the random number sequence changing circuit 555 outputs “0 → 2 →... → 65534 → 1 →.

  FIG. 15 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553 being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 556 automatically changes the random number update rule. To change. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number change circuit 555 reaches a predetermined final value, the random number sequence change setting circuit 556 follows a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule. Alternatively, the random number sequence change setting circuit 556 may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 555 becomes “0 → 2 →... → 65534 → 1 →. In the operation example illustrated in FIG. 15, the random number sequence RSN output from the random number sequence change circuit 555 is “65534 → 0 →... → 32768” due to the third change in the random number update rule. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “4 → 3 →... → 465553”.

  The latch flip-flop 557A is configured using, for example, a D-type flip-flop. In the latch flip-flop 557A, a wiring from the input port P0 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC1 is connected to the clock terminal CK. In this embodiment, the game start signal SS1 from the start switch 7 is input to the input port P0. The latch flip-flop 557A captures the game start signal SS1 in response to the rising edge of the latch clock RC1, and outputs it as the game start latch signal SL1. Thus, in the latch flip-flop 557A, the game start signal SS1 is output as the game start latch signal SL1 in synchronization with the rising edge of the latch clock RC1.

  The game start signal SS1 is not limited to that transmitted directly from the start switch 7. As an example, the time when the output signal from the output signal from the start switch 7 is on is measured, and when the measured time reaches a predetermined time (for example, 3 ms), the game start signal SS1 is output. A timer circuit may be provided.

  The random number latch selector 558A is a circuit that takes in the game start latch signal SL1 transmitted from the latch flip-flop 557A and the software random number latch request signal, and selectively outputs either one as the random number latch signal LL1. The random number latch selector 558A controls the output of the random number latch signal LL1 by using a random value fetch register RDLT (address 2032H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. The random value acquisition register RDLT is a register used to acquire numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random value register 559A by software. The random number latch selection register RDLS has a method of taking in the numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 into the random value register 559A by software or by inputting a signal to the input port P0. It is a register to show.

  FIG. 16A shows a configuration example of the random value fetch register RDLT. FIG. 16B shows an example of the setting contents in each bit of the random number acquisition specification data stored in the random value acquisition register RDLT. The random value acquisition specification data RDLT0 stored in the bit number [0] of the random value acquisition register RDLT indicates whether or not a random value acquisition specification is given to the random value register 559A serving as the random value register R1D. In the example shown in FIG. 16B, when there is no specification of random number acquisition to the random number register R1D by software, the bit value of the random value acquisition specification data RDLT0 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included.

  FIG. 17A shows a configuration example of the random number latch selection register RDLS. FIG. 17B shows an example of setting contents in each bit of random number latch selection data stored in the random number latch selection register RDLS. The random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 17B, the bit value of the random number latch selection data RDLS0 is “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R1D in response to the signal input to the input port P0, the bit value of the random number latch selection data RDLS0 is set to “1”. In this embodiment, the bit value of the random number latch selection data RDLS0 is “1”, and numerical data that becomes a random number value is taken into the random value register R1D in response to a signal input to the input port P0.

  The random value register 559A is a register that stores numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value. 18A and 18B show a configuration example of a random value register 559A serving as the random value register R1D. 18A shows the lower byte R1D (L) of the random value register R1D, and FIG. 18B shows the upper byte R1D (H) of the random value register R1D. The random value register 559A is a 16-bit (2-byte) register, and can store a 16-bit random value.

  The random value register 559A takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL1 supplied from the random number latch selector 558A being turned on. Store with. When the register read signal RRS1 supplied from the CPU 505 is turned on, the random value register 559A is in a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS1 is in the off state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559A may be in a state in which the register read signal RRS1 cannot be received when the random number latch signal LL1 is in the ON state. Further, the random number register 559A may be configured to be in a state in which the random number latch signal LL1 cannot be received when the register read signal RRS1 is in the on state before the random number latch signal LL1 is in the on state. good.

  The random value register 559A uses a random number latch flag register RDFM (address 2033H) and a random number interrupt control register RDIC (address 2031H) among the built-in registers provided in the main control unit 41 as shown in FIG. 7B. This enables operation management and interrupt control when latching random numbers. The random number latch flag register RDFM is a register that stores a random number latch flag indicating whether or not numerical data serving as a random number value has been latched corresponding to the random value register 559A. The random number interrupt control register RDIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random value is latched in the random number value register 559A.

  FIG. 19A shows a configuration example of the random number latch flag register RDFM. FIG. 19B shows an example of setting contents in each bit of the random number latch flag data stored in the random number latch flag register RDFM. The random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 19B, when the numerical value data is not taken into the random value register R1D (no random value is taken), the bit value of the random number latch flag data RDFM0 becomes “0”, while the numerical data Is taken (with random number fetching), the bit value becomes “1”. In the state where the random number latch flag data RDFM0 is “1”, that is, in the state where the numerical data is captured in the random value register R1D, the new numerical data is stored in the random value register even when a new random number capturing request is generated. In such a state, the numerical data in the random value register R1D is read and new numerical data is captured in the random value register R1D until the random number latch flag data RDFM0 is cleared. It becomes impossible.

  FIG. 20A shows a configuration example of the random number interrupt control register RDIC. FIG. 20B shows an example of setting contents in each bit of random number interrupt control data stored in the random number interrupt control register RDIC. The random number interrupt control data RDIC0 stored in the bit number [0] of the random number interrupt control register RDIC permits an interrupt that occurs when numerical data is fetched into the random number value register 559A serving as the random number value register R1D. This shows the interrupt control setting to enable or disable. In the example shown in FIG. 20B, when interrupting at the time of fetching into the random value register R1D is prohibited (interrupt prohibited), the bit value of the random number interrupt control data RDIC0 is set to “0”, When this interrupt is permitted (interrupt permitted), the bit value is set to “1”. In the present embodiment, the bit value of the random number interrupt control data RDIC0 is set to “0”, and no interrupt is generated even if numerical data is fetched into the random value register 559A serving as the random value register R1D.

  The PIP 510 included in the main control unit 41 is, for example, a 6-bit input dedicated port, and includes an input port P0 to an input port P2 serving as a dedicated terminal and an input port P3 serving as a function shared terminal and an input port P5. . The input port P3 is also used as an external maskable interrupt terminal XINT connected to the CPU 505 or the like. The input port P4 is also used as an external non-maskable interrupt terminal XNMI connected to the CPU 505 or the like. The input port P5 is also used as the first channel reception terminal RXA used by the serial communication circuit 511. The use setting of the input port P3 to the input port P5 is instructed by the function setting KFCS stored in the program management area.

  The PIP 510 performs state management of the input port P0 to the input port P5 using the input port register PI (address 2090H) among the built-in registers included in the main control unit 41 as shown in FIG. 7B. The input port register PI is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input port P0 to the input port P5.

  FIG. 21A shows a configuration example of the input port register PI. FIG. 21B shows an example of setting contents in each bit of the input port data stored in the input port register PI. The input port data PI5 stored in the bit number [5] of the input port register PI indicates the terminal state (ON / OFF) at the input port P5 that is also used as the first channel receiving terminal RXA. The input port data PI4 stored in the bit number [4] of the input port register PI indicates the terminal state (ON / OFF) at the input port P4 that is also used as the external non-maskable interrupt terminal XNMI. The input port data PI3 stored in the bit number [3] of the input port register PI indicates the terminal state (ON / OFF) at the input port P3 that is also used as the external maskable interrupt terminal XINT. The input port data PI2 stored in the bit number [2] of the input port register PI indicates the terminal state (ON / OFF) at the input port P2. The input port data PI1 stored in the bit number [1] of the input port register PI indicates the terminal state (ON / OFF) at the input port P1. The input port data PI0 stored in the bit number [0] of the input port register PI indicates the terminal state (ON / OFF) at the input port P0.

  An address decoding circuit 512 provided in the main control unit 41 shown in FIG. 5 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. . By the chip select signal, an internal circuit of the main control unit 41 or an external device as a peripheral device is selectively operated effectively and can be accessed from the CPU 505.

  The ROM 506 provided in the main control unit 41 stores various selection data and table data used for controlling the progress of the game, in addition to the game control user program and the security check program 506A. For example, the ROM 506 stores data constituting a plurality of determination tables, determination tables, setting tables, and the like prepared for the CPU 505 to perform various determinations, determinations, and settings. The ROM 506 stores table data constituting a plurality of command tables used for the CPU 505 to transmit control signals serving as various control commands from the game control board 40.

  The RAM 507 provided in the main control unit 41 is provided with a game control data holding area 590 as an area for holding various data used for controlling the progress of the game in the slot machine 1. For example, a DRAM is used as the RAM 507, and a refresh operation is required to maintain the stored data contents. The CPU 505 has a built-in refresh register for performing this refresh operation. For example, the refresh register consists of 8 bits, and the lower 7 bits are automatically incremented each time the CPU 505 fetches an instruction from the ROM 506. Accordingly, the stored value in the refresh register is updated every execution time of one instruction in the CPU 505.

  The main control unit 41 receives the detection state of various switches connected to the game control board 40 from the input port. Then, the main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from these input ports.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, the external maskable interrupt terminal XINT is connected to the power interruption detection circuit 48 described above, and the main control unit 41 will be described later according to the input of the voltage drop signal output from the power interruption detection circuit 48. Executes power interruption processing (main). Further, the main control unit 41 executes a timer interrupt process (main), which will be described later, every time a certain time interval (about 0.56 ms in this embodiment) occurs in the timer circuit included in the CTC 508. To do.

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. In this embodiment, the interruption interrupt process (main) has a higher priority than the timer interruption process (main), and when these interruptions occur simultaneously, the interruption interrupt process (main) Prioritized execution. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be. For example, if a voltage drop signal is input during execution of the timer interrupt process (main), the power interruption interrupt process (main) is not executed at that time, but the timer interrupt process being executed When the input of the voltage drop signal is continued when (main) is completed, the power interruption interrupt process (main) is executed at that time.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a power interruption interrupt process (main) in response to the input of the voltage drop signal output from the power interruption detection circuit 48, and at a certain time interval (about 0.56 ms in this embodiment). ) Timer interrupt processing (main) is executed every time. In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  The main control unit 41 transmits various commands to the effect control board 90. A command transmitted from the game control board 40 to the effect control board 90 is sent in only one direction, and no command is sent from the effect control board 90 to the game control board 40.

  The effect control board 90 is connected to effect devices such as a liquid crystal display 51 (see FIG. 1), an effect LED 52, speakers 53 and 54, and the reel LED 55 described above, which are arranged on the front door 1b of the slot machine 1. These effect devices are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  In this embodiment, the sub-control unit 91 mounted on the effect control board 90 controls the output of the effect devices such as the liquid crystal display 51, effect effect LED 52, speakers 53 and 54, and reel LED 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer including a sub CPU 91a, ROM 91b, RAM 91c, I / O port 91d, etc., and a liquid crystal display connected to the sub control unit 91 for effect control and the effect control board 90. Display control circuit 92 for performing display control of the device 51, LED drive circuit 93 for performing drive control of the effect LED 52 and reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53 and 54, at power-on or power-off A reset circuit 95 that sometimes gives a reset signal to the sub CPU 91a, a clock device 97 that outputs time information including date information and time information, and a power supply voltage supplied to the slot machine 1 are monitored, and when a voltage drop is detected, A power interruption detection circuit 98 that outputs a voltage drop signal indicating that to the sub-control unit 91 is mounted. In response to the command transmitted from the main control unit, the sub-control unit 91 performs various controls for performing an effect, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90. Control.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the number of input system clocks reaches a certain number, that is, every certain interval. Also, one of the interrupt terminals of the sub control unit 91 is connected to the power interruption detection circuit 98, and the sub control unit 91 is turned on in response to the input of the voltage drop signal output from the power interruption detection circuit 98. Execute interrupt processing (sub).

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time. Note that command reception interrupt processing is also prohibited during the execution of power interruption interrupt processing (sub), but if an interrupt that triggers power interruption interrupt processing (sub) occurs at the same time, command reception Prioritize interrupt processing

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to a set value in an internal lottery described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 507 is displayed on the setting value display 24 as a display value, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the display returns to the setting 1). . When the start switch 7 is operated, the display value is determined as the set value. Then, when the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 507 of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In order to confirm the set value, after the game is over, the setting key switch 37 may be turned on with no bet amount set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 507 is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by turning the setting key switch 37 to the OFF state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  In the slot machine 1 of this embodiment, when the main control unit 41 detects a voltage drop signal from the power interruption detection circuit 48, a power interruption interrupt process (main) is executed. In the power interruption interrupt processing (main), a register is saved in a stack of a RAM 507, which will be described later, and data for destructive diagnosis in which any bit becomes 1 (5AH in this embodiment), that is, a specific value other than 0 In addition to storing data, the RAM parity adjustment data is calculated so that the RAM parity based on the data stored in all areas of the RAM 507 becomes 0, and the process of storing in the RAM 507 is performed. The RAM parity is a value calculated as an exclusive OR of the values stored in each bit of the corresponding area (all areas in this embodiment) of the RAM 507. For this reason, if the RAM parity based on the data stored in all areas of the RAM 507 is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 507 is 1. In this case, the RAM parity adjustment data is 1.

  The main control unit 41 calculates the RAM parity based on the data stored in all areas of the RAM 507 at the time of activation, confirms the value of the destructive diagnosis data, the RAM parity is 0, and On the condition that the value of the destructive diagnosis data is also correct, the processing state of the main control unit 41 is restored to the state before the power interruption based on the data stored in the RAM 507, but when the RAM parity is not 0 (1 If the value of the data for destructive diagnosis is not correct, it is determined that the RAM is abnormal, the RAM abnormal error code is set in the register, and the RAM abnormal error state is controlled to disable the progress of the game. ing. Unlike the normal error state, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the above-described setting change state. It will not be released until

  In this embodiment, all data stored in the RAM 507 is held by the backup power source even in the event of a power failure, and the main control unit 41 determines that the data in the RAM 507 is normal when the power is turned on. In addition, the configuration is such that the control state before power interruption is restored based on the data stored in the RAM 507. However, only the data stored in the RAM 507 that is necessary for returning to the control state in the event of a power failure is backed up and the power is turned on. It may be configured to return to the control state before power interruption based on the data backed up at the time.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player For example, it is not necessary to restore the state of all input ports to the state before power interruption.

  Further, when the sub control unit 91 detects the voltage drop signal from the power interruption detection circuit 98, the sub control unit 91 executes a power interruption interrupt process (sub). In the power interruption interrupt processing (sub), the register is saved in a stack of a RAM 91c described later, and destructive diagnosis data in which any bit is 1 is stored in the RAM 91c, and data stored in all areas of the RAM 91c. The RAM parity adjustment data is calculated so that the RAM parity based on 0 becomes 0 and stored in the RAM 91c.

  Then, the sub-control unit 91 calculates the RAM parity based on the data stored in all the areas of the RAM 91c at the time of activation, and sets the data stored in the RAM 91c on the condition that the RAM parity is 0. Based on this, the processing state of the sub-control unit 91 is restored to the state before the power interruption, but when the RAM parity is not 0 (in the case of 1), it is determined that the RAM is abnormal and the RAM 91c is initialized. . In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In this embodiment, all data stored in the RAM 91c is held by the backup power supply even in the event of a power failure, and the sub-control unit 91 determines that the data in the RAM 91c is normal when the power is turned on. In addition, the configuration is such that the control state before power interruption is restored based on the data stored in the RAM 91c, but only the data required to return to the control state during a power failure is backed up among the data stored in the RAM 91c and the power is turned on. It may be configured to return to the control state before power interruption based on the data backed up at the time.

  In addition, when returning to the control state before the power interruption when the power is turned on, it is not necessary to return all the control states to the control state before the power interruption, and the minimum control state that does not disadvantage the player It is not necessary to restore the state of the input port or the progress in the middle of the production when it is interrupted.

  Next, initialization of the RAM 507 of the main control unit 41 will be described. The storage area of the RAM 507 of the main control unit 41 is divided into an important work, a general work, a special work, a set value work, a non-saved work, an unused area, and a stack area.

  The important work is a work in which data which is inconvenient if it is initialized at the end of the BB, such as various display devices, LED display data, I / O input / output data, and game time counter. The general work is a work that stores data that can be initialized at the end of the BB, such as a stop control table, a stop symbol, the number of medals paid out, and the total number of medals paid out in the BB. The special work is a work that stores data to be initialized only before the start of setting, such as data for transmitting a command to the effect control board 90 and various software random numbers. The set value work is a work that stores a set value used when a lottery is performed in the internal lottery process. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 507 is destroyed at the time of activation. The unused area is an unused area in the storage area of the RAM 507, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the main control unit 41 is stored, and the unused stack area is one of a plurality of initialization conditions to be described later, like the unused area. However, if it is established, it will be initialized, but the in-use stack area is not initialized because the program continues.

  In this embodiment, the main control unit 41 stores the data in the RAM 507 at the time of start-up with the setting key switch 37 turned on, when a RAM error occurs, at the end of BB, and at the time of start-up with the setting key switch 37 turned off. When not being destroyed, when five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is an initialization performed when the setting key switch 37 is in an ON state at the time of startup and shifts to a setting change state, or initialization performed when a RAM abnormality error occurs. In the storage area of the RAM 507, all areas (including the unused area and the unused stack area) other than the used stack area are initialized. Initialization 2 is initialization performed at the end of the BB. In initialization 2, a general work, an unused area, and an unused stack area are initialized in the storage area of the RAM 507. Initialization 3 is initialization that is performed when the setting key switch 37 is in an OFF state at the time of startup and the data in the RAM 507 is not destroyed. In the initialization 3, non-saved work, unused area, and unused The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 507 are initialized.

  In this embodiment, initialization 1 is performed before the change of the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the change of the setting change state and at the end of the setting change state. Also good. In this case, if the set value work is initialized, the determined set value is lost. Therefore, the initialization of the set value work is not performed in the initialization at the end of the setting change state.

  In the slot machine 1 according to the present embodiment, the prescribed number of bets that can be set according to the gaming state is determined as described above, and the prescribed number of bets that are determined according to the gaming state is set. It becomes possible to start the game on the condition. In this embodiment, as will be described later, there are a regular bonus (hereinafter referred to as RB) (big bonus (hereinafter referred to as BB)) and a normal gaming state as a gaming state, of which RB (BB) is the number of bets. 2 is defined as the prescribed number of 3 and 3 is defined as the prescribed number of bets in the normal gaming state. For this reason, if the gaming state is RB (BB), the game can be started when the bet number is set to 2, and if the bet number is set to 3 in the normal gaming state, the game is started. It is possible to start. In the present embodiment, all the pay lines L1 to L5 are activated when a specified number of bets corresponding to the gaming state are set, and as RB (BB) All winning lines L1 to L5 are activated when 2 is determined, and all winning lines L1 to L5 are activated when 3 is set as the number of bets in the normal gaming state. Become.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in the present embodiment, all the pay lines are always enabled. The activated winning line is simply referred to as a winning line). When a combination of symbols called a combination is arranged on the winning line, a winning is achieved. The combination may be a combination of the same symbols or a combination including different symbols. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition of the game state. Below, a small role and a re-playing role are collectively called a general role. In order to win each winning combination determined according to the game state, it is necessary to win an internal lottery described later and set a winning flag for the winning combination in the RAM 507.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combinations permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

  As the role in the slot machine 1, as shown in FIG. 22, a special bonus is a big bonus (hereinafter referred to as a big bonus BB), a regular bonus (hereinafter, a regular bonus is referred to as RB), and a small bonus is 1 Sheets, watermelons, cherries, and bells are replayed as replay players.

  Cherry is awarded when the symbol “white cherry” is derived on any of the winning lines for the right reel in any gaming state, and one medal is paid out in any gaming state. In addition, when the symbol of “white cherry” stops at the upper or lower stage of the right reel, the combination of cherries is aligned on the two winning lines of the winning lines L2, L5 or the winning lines L3, L4. Since winning a cherry on the winning line, two medals will be paid out.

  A watermelon is awarded when a combination of “watermelon-watermelon-watermelon” or “watermelon-watermelon-BAR” is available on any of the winning lines in any gaming state, and 15 RBs (BB). Medals are paid out, and in the normal gaming state, 12 medals are paid out. Bell is awarded when the combination of “Bell-Bell-Bell” is aligned on any of the winning lines in any gaming state, and 15 medals are paid out in RB (BB). Ten medals are paid out.

  Replay is a combination of “Replay-Replay-Replay”, “BAR-Replay-Replay”, or “Black 7-Replay-Replay” in any of the winning lines in the normal gaming state. Wins when you have the right. When the replay wins, no medals are paid out, but the next game can be started without setting the number of wagers again, so that three medals corresponding to the number of wagers that are not required to be set in the next game are paid out. Is essentially the same.

  RB is won when the combination of “net 7-net 7-black 7” is aligned on any of the winning lines in the normal gaming state, and the gaming state shifts to RB. The RB is a gaming state that is advantageous to the player over other gaming states by increasing the winning probability of the small role, particularly the bell, and when the 12 games are digested after the RB starts, or an 8-game winning ( When the type of a combination is allowed), it ends either whichever comes first.

  BB is a combination of “black 7-black 7-black 7”, “net 7-net 7-net 7” or “white 7-white 7-white 7” in any of the winning lines in the normal gaming state. When the combination is complete, a prize is awarded.

  When BB wins, the gaming state shifts to BB and shifts to RB at the same time. When RB ends, if BB has not ended, it shifts to RB again and is controlled repeatedly until BB ends. The That is, during BB, it is always controlled to RB. The BB ends when the total number of medals paid out to the player in the BB exceeds 465. At the end of the BB, the RB is also ended regardless of whether or not the RB end condition is satisfied.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the numerical data latched simultaneously with the detection of the operation of the start switch 7 and stored in the random value register R1D is read and stored in the random value work assigned to the RAM 507. And, for each combination determined according to the gaming state and whether or not the special combination is carried over, the numerical data stored in the random value work and the determination of each combination determined according to the gaming state, the number of bets and the set value This is done according to the number of values.

  In the present embodiment, as shown in FIG. 22, the combination that is the subject of the internal lottery differs depending on whether the gaming state is the normal gaming state or RB (BB). Further, when the gaming state is the normal gaming state, the role to be subject to the internal lottery varies depending on whether or not the special role is being carried over.

  When the gaming state is the normal gaming state and any special combination is not carried over, BB, RB, replay, watermelon, cherry, and bell are sequentially read out as the target combination of the internal lottery.

  When the gaming state is the normal gaming state and any special combination is carried over, replay, watermelon, cherry, and bell are sequentially read out as the target combinations for the internal lottery.

  When the gaming state is RB, watermelon, cherry, and bell are sequentially read out as the subject combination of the internal lottery.

  In the internal lottery, the number of judgment values determined in accordance with the role that is the subject of the internal lottery, the current gaming state and the set value are sequentially added to the random number value for the internal lottery, and the result of addition overflows It is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the winning combination is set in the internal winning flag storage work assigned to the RAM 507. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  Next, stop control of the reels 2L, 2C, 2R will be described.

  The main control unit 41 refers to the table index and table creation data stored in the ROM 506A when the reel starts rotating and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, an index that indicates the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where the data is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of each, and it is necessary according to each status from this specified address And to be able to identify the stop control table. Even when the reel stop status and the stopped position of the stopped reel are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In this embodiment, stepping motors that make one turn at a cycle of 168 steps (0 to 167) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven for 168 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, the stop control table created by referring to the table index and the table creation data corresponds to the area number, and the area corresponding to each area number is the stop reference position (in this embodiment, the perspective window 3). Sliding frame when an operation of the stop switches 8L, 8C, 8R is detected at a timing (a timing in which the number of steps from the reel reference position is included in the range of the number of steps of each region number). It is a table with each number set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the table creation data, and the stop control table address of the unreacted reel corresponding to the stopped reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table of each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  In the table index of this embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and further, one table creation data includes one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). In other words, table creation data corresponding to one internal winning state in one gaming state and stop control tables corresponding to reel stop states (and stopped positions of stopped reels) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in this embodiment, a value of 0 to 4 is determined as the number of sliding frames, and the reel can be stopped by drawing a maximum of 4 symbols after detecting the stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In this embodiment, when any of the winning combinations is won, the winning combination is drawn to the maximum in the range of 4 frames on the winning line, and the non-winning winning combination is drawn so that it is not aligned on the winning line. A stop control table with a defined number of frames is created and reel stop control is performed. If no winning combination is selected, a stop control table with a determined number of sliding symbols that do not have any combination And stop control of the reel. As a result, when a stop operation is performed, if the winning combination can be stopped on the winning line in the drawing range of up to 4 frames, the control is performed so that the winning combination is stopped. The combination that has not been performed will be controlled to be stopped in a drawing range of a maximum of 4 frames.

  When a special role and a small role are elected at the same time, such as when a special role is elected while the special role has been carried over from before the previous game, the winning small role is the maximum in the range of 4 frames on the winning line. The number of sliding frames is fixed so that it can be drawn to the limit, and for the stop operation position where the selected small role cannot be drawn in the range of up to 4 frames in the winning line, the winning special role is in the range of 4 frames in the winning line Then, a stop control table in which the number of sliding frames is determined so as to be pulled in as much as possible is created, and reel stop control is performed. As a result, when a stop operation is performed, if it is possible to stop all the small roles that have been selected in the drawing range of up to 4 frames on the winning line and stop them, control is performed so that the winning combination is stopped. If you can't draw a small role that has been won in the drawing range of up to 4 frames on the line, if you can stop with a special role that has been won in the drawing range of up to 4 frames on the winning line, A control is performed to stop them in a uniform manner, and a winning combination that has not been won will be controlled to be stopped within a 4-frame pull-in range. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. When a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn in, and the small combination is not aligned on the winning line at the same time as the special combination.

  In this example, when a special role is elected while the special role has been carried over from before the previous game, or when a special role and a small role are simultaneously elected, the special role and the small role are won simultaneously. If the selected special role is given priority over the selected special role, the special role is controlled on the winning line only when the small role cannot be withdrawn. When winning simultaneously, priority is given to the control for aligning the special role on the winning line over the small role, and the control for aligning the small role on the winning line may be performed only when the special role cannot be drawn.

  If a special player and a replaying player are elected at the same time, such as when a replaying player is elected while the special role has been carried over from before the previous game, when the stop operation is performed, In addition, a control is performed in which the symbols of the re-gamer are aligned and stopped within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not arranged on the winning line simultaneously with the re-playing combination.

  In this embodiment, after the rotation of the reels 2L, 2C, and 2R is started, the main control unit 41 rotates the reels for which the stop operation has not been detected yet until the operation of the stop switches 8L, 8C, and 8R is detected. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In this embodiment, control is performed to stop the display result on the corresponding reel on condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the rotation of the reel is started. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  Next, a command that the main control unit 41 transmits to the effect control board 90 will be described.

  In the present embodiment, the main control unit 41 performs a BET command, a credit command, an internal winning command, a reel rotation start command, a reel stop command, a winning determination command, a payout start command, a payout end command, a game with respect to the effect control board 90. A plurality of types of commands including a status command, standby command, abort command, error command, return command, setting start command, confirmation start command, confirmation end command, and operation detection command are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The BET command is a command that can specify the number of inserted medals, that is, the number of medals used to set the bet number, and is a state from the end of the game (after setting change) to the start of the game. Sent when a medal is inserted or the bet number is set by operating the single BET switch 5 or the MAXBET switch 6 in a state where is not set. Further, since the BET command is transmitted when the betting number setting operation is performed, it is possible to specify that the betting number setting operation has been performed by receiving the BET command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The internal winning command is a command that can specify the winning status of the internal winning flag and the type of the internal winning flag established, and is transmitted when the start switch 7 is operated to start the game. Further, since the internal winning command is transmitted when the start switch 7 is operated, it is possible to specify that the start switch 7 has been operated by receiving the internal winning command.

  The reel rotation start command is a command for notifying the start of reel rotation, and is transmitted when rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, the area number of the corresponding reel stop operation position, and the area number of the corresponding reel stop position. And is transmitted each time stop control is performed in accordance with the stop operation of each reel. Since the reel stop command is transmitted when the stop switches 8L, 8C, and 8R are operated, it is possible to specify that the stop switches 8L, 8C, and 8R are operated by receiving the reel stop command. .

  The winning determination command is a command that can specify the presence / absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, and is transmitted after all the reels are stopped and the winning determination is performed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and paying out credits is completed.

  The game state command is a command that can specify the game state of the next game, and is transmitted when the setting change state ends and when the game ends.

  The standby command is a command indicating a transition to the standby state, and after one game is over, a credit (which was used for setting the bet number) is set when the transition to the standby state is made after a predetermined time without setting the bet number. (Including medals) is sent out after the medal payout is completed and the payout end command is sent.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The setting start command is a command indicating the start of the setting change state, and is transmitted when shifting to the setting change state. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting start command.

  The confirmation start command is a command indicating the start of the setting confirmation state, and is transmitted when shifting to the setting confirmation state. The confirmation end command is a command indicating the end of the setting confirmation state, and is transmitted when the setting confirmation state ends.

  The operation detection command is a command indicating the detection state (ON / OFF) of the operation switches (one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R), and is transmitted at regular intervals. Is done.

  Among these commands, a setting start command, an error command indicating a RAM error or a random number circuit error, and a return command are generated at a stage before the interrupt is permitted in the startup process, and the specific command assigned to the special work in the RAM 507 is transmitted. Stored in the trust buffer and sent immediately.

  Commands other than the setting start command, the error command indicating the RAM abnormality or the random number circuit abnormality, the return command, and the operation detection command are generated according to the progress of the game in the game process, and are sent to the normal command provided in the special work in the RAM 507. Temporarily stored in the trust buffer and transmitted in the command transmission process executed in the timer interrupt process (main).

  The operation detection command is generated every time the command transmission process is executed five times, stored in the aforementioned specific command transmission buffer, and immediately transmitted. In addition, when the operation detection command transmission time is reached with the unsent command stored in the normal command transmission buffer, priority is given to the transmission of the operation detection command and the normal command transmission buffer stores it. The untransmitted command is transmitted in the next command transmission process, and a plurality of commands are not transmitted in one command transmission process.

  Next, the control of the effect performed by the sub-control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is received unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  In particular, in this embodiment, when the betting number setting operation is performed during the execution of the effect, that is, when the sub-control unit 91 receives a BET command indicating that the bet number has been set, Is to be canceled. For this reason, if the player wants to proceed to the next game rather than seeing the production to the end, the production is canceled and the next game can be started. There is no. Further, when a credit or betting amount adjustment operation is performed during the performance, that is, after the sub-control unit 91 receives a game state command indicating the end of the game, it receives an internal winning command indicating the start of the game. When the payout start command is received before, the effect being executed is stopped. Credits and bets are settled when the game is terminated. In such a case, by terminating the performance that is being executed, there is an intention to end the game, but the performance continues unnecessarily. It is designed not to be overwhelmed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

  Next, various control contents executed by the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When the reset signal is input from the reset circuit 49, the main control unit 41 performs the startup process (main) shown in the flowchart of FIG. Since the reset signal is a signal that is output when the power is turned on and when the operation of the main control unit 41 is stagnant, the activation process (main) is performed when the main control unit 41 is activated when the power is turned on. This process is performed at the time of restart due to a malfunction of the unit 41.

  In the startup process (main), first, the CPU 505 executes the security check process shown in FIG. 24 based on the security check program 506A read from the ROM 506 (Sa1). At this time, the main control unit 41 enters the security mode, and the game control user program stored in the ROM 506 is not yet executed.

  In the security check process, as shown in FIG. 24, first, a process for determining a time (security time) for controlling to the security mode is executed. At this time, the CPU 505 reads the bit value in the bit number [2-0] of the security time setting KSES stored in the program management area of the ROM 506 (Sa101). Then, it is determined whether or not the read value is “000” (Sa102).

  If the read value is determined to be “000” in Sa102, the steady set time is set to a predetermined fixed time (Sa103). Here, the steady setting time is a constant time component of the security time regardless of the number of executions of the security check process based on the occurrence of a system reset or the like (the number of times the main control unit 41 enters the security mode). The fixed time is an invariant time component determined in advance based on the specification of the main control unit 41 in the security time, and may be a minimum value that can be set as the security time, for example.

  If it is determined in Sa102 that the read value is other than “000”, the extension time selected according to the setting contents shown in FIG. The time is set (Sa104). In this way, when the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, the security time as the execution time of the security check process can be selected in advance in addition to the fixed time. It can be set to any one of a plurality of extension times.

  After executing one of the processes of Sa103 and Sa104, the bit value in the bit number [4-3] of the security time setting KSES is read (Sa105). Then, it is determined whether or not the read value is “00” (Sa106).

  If the read value is determined to be “00” in Sa106, the steady setting time is set as the security time (Sa107). On the other hand, if it is determined that the read value is other than “00”, the variable set time determined corresponding to the read value is added to the steady set time and set as the security time (Sa108). . Here, the variable setting time is a time component that changes every time the security check process is executed, and the bit value in the bit number [4-3] of the security time setting KSES is “01” (short). Mode) or “10” (long mode), and changes in different predetermined time ranges. For example, when the count value in a predetermined free-run counter is stored in the variable security time register built in the main control unit 41 when the system reset occurs, the variable security time register is stored in the processing of Sa108. By using the value as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable set time is random within a predetermined time range at each system reset. What is necessary is just to be determined so that it may change. Thus, when the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the security time that is the execution time of the security check process is set as the security based on the occurrence of the system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  Here, the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, and the bit value in the bit number [4-3] of the security time setting KSES is other than “00”. In this case, both the extension time set in step S4 and the variable setting time set in step S8 are added to the fixed time, and the security time is determined. .

  After executing one of the processes of Sa107 and Sa108, the security code stored in the predetermined area of the ROM 506 is read (Sa109). Here, in a predetermined area of the ROM 506, a security code of a calculation result obtained by calculating the data of the stored content by a predetermined calculation formula is stored in advance. As a security code generation method, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 506, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing in step S9, the encrypted arithmetic expression is decrypted and restored (Sa1010). Thereafter, the storage code in the predetermined area of the ROM 506 is calculated by the arithmetic expression decrypted in Sa110 to specify the security code (Sa111). At this time, the storage data used for the calculation for specifying the security code is, for example, program data corresponding to all or part of the user program different from the security check program 506A among the storage data of the ROM 506, or predetermined table data May be all or a part of the fixed data constituting the. Then, the security code read in Sa109 is compared with the security code specified in Sa111 (Sa112). At this time, it is determined whether or not the security codes match in the comparison result (Sa113).

  If the security codes do not match at Sa113, it is determined that an unauthorized change has been made to the ROM 506, and the operation of the CPU 505 is shifted to the halt state (HALT). On the other hand, if the security codes match in Sa113, it is determined whether or not the security time set in the processing of Sa107 or Sa108 has passed (Sa114). At this time, if the security time has not elapsed, the process of Sa114 is repeatedly executed and waits until the security time elapses. If it is determined in Sa114 that the security time has elapsed, the security check process is terminated, and the value of the program counter built in the CPU 505 is set to the start address (address 0000H) of the user program in the ROM 506. As a result, the operation state of the main control unit 41 shifts from the security mode to the user mode, and execution of the user program stored in the ROM 506 is started.

  After the security check process of Sa1 is completed, the main control unit 41 initializes the built-in device, peripheral IC, interrupt mode, stack pointer, and the like (Sa2), then acquires detection data of the voltage drop signal from the input port, It is determined whether or not the voltage drop signal is input, that is, whether or not the voltage is stable (Sa3). If the voltage drop signal is input, whether or not the voltage drop signal is input is determined. Except for the determination, the process proceeds to a loop process in which no process is performed.

  If it is determined in step Sa3 that the voltage drop signal has not been input, the values of the I register and IY register are initialized (Sa4). By initialization of the I register and the IY register, an interrupt table address to be referred to when an interrupt occurs is set in the I register, and a reference address for referring to the storage area of the RAM 507 is set in the IY register. . These values are fixed values and are always initialized at startup.

  Next, access to the RAM 507 is permitted (Sa5), the RAM parity of all storage areas (including the unused area and the unused stack area) of the RAM 507 is calculated (Sa6), the abort switch 36, the automatic settlement switch 29 And the valid / invalid of the stop function and the automatic settlement function are set in a specific register of the main control unit 41 (Sa7).

  Next, it is determined whether or not the RAM parity calculated in the step of Sa6 is 0 (Sa8). If the power interruption interrupt process (main) is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa8, the data stored in the RAM 507 is not normal. In this case, after executing the initialization 1 for initializing all the storage areas except the used stack area in the storage area of the RAM 507 (Sa31), it is determined whether or not the setting key switch 37 is ON. (Sa32) If the setting key switch 37 is ON, the first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area are read, and the random number circuit setting process shown in FIG. 25 is executed. Thereafter (Sa26), the random number circuit abnormality inspection process shown in FIG. 26 is executed in order to inspect whether there is an operation abnormality in the random number circuit 509 (Sa27).

  In the random number circuit setting process shown in FIG. 25, first, setting for using the random number circuit 509 is performed based on the bit value in the bit number [3] of the first random number initial setting KRS1 (Sa201). In the present embodiment, the bit value in the bit number [3] of the first random number initial setting KRS1 is set to “1” in advance, and setting to use the random number circuit 509 is performed corresponding to this bit value. Subsequently, the random number update clock RGK in the random number circuit 509 is set based on the bit value in the bit number [2] of the first random number initial setting KRS1 (Sa202). In the present embodiment, the random number clock RCLK generated by the random number clock generation circuit 43 is determined in response to the bit value [2] of the first random number initial setting KRS1 being “1” in advance. Setting is performed by dividing the frequency by two to be the random number update clock RGK.

  After the setting in Sa202, the random number update rule is set in the random number circuit 509 based on the bit value [1-0] of the first random number initial setting KRS1 (Sa203). In this embodiment, “10” is set in advance as the bit value in the bit number [1-0] of the first random number initial setting KRS1, and the random number update rule in the random number sequence RSN is automatically changed after the second round. Settings are made.

  Subsequently, based on the bit value in the bit number [1] of the second random number initial setting KRS2, a start value at start-up in numerical data to be a random value is determined (Sa204). In this embodiment, “1” is set in advance as the bit value in the bit number [1] of the second random number initial setting KRS2, and the start value of the random number is set to a value based on the ID number.

  Further, based on the bit value in the bit number [0] of the second random number initial setting KRS2, it is set whether or not to change the start value of the numerical data to be a random value at every system reset (Sa205). In this embodiment, the bit value at the bit number [0] of the second random number initial setting KRS2 is set to “0” in advance, and the start value at start-up set in Sa204 is used as it is, and the start value in the random number circuit 509 is used. It is said. When the setting by the processing of Sa205 is completed, the random number circuit 509 starts a random value generation operation. When the bit value [0] of the second random number initial setting KRS2 is set to “1” in advance, the random number start value is changed every time the system is reset. In this case, for example, when the count value in a predetermined free-run counter is stored in the random number start value register built in the main control unit 41 when the system reset occurs, the random number start is performed in the processing of Sa205. By using the stored value of the value register as it is, or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the random number start value is predetermined at each system reset. (For example, a range including all or part of the numerical data included in the count value permutation RCN generated by the random number generation circuit 553) may be determined at random.

  Note that the setting by the random number circuit setting process may be performed autonomously by the random number circuit 509 based on the stored data in the program management area without the processing of the CPU 505 being involved. In this case, the random number circuit 509 may be configured not to perform initialization and not to generate a random value when the main control unit 41 is in the security mode. Then, when the CPU 505 reads the user program stored in the ROM 506 in the main control unit 41 and the user mode is started, for example, a control signal for instructing the initial setting to the random number circuit 509 is transmitted from the CPU 505. In response to the above, the random number generation operation may be started after the random number circuit 509 performs the initial setting. In particular, when the random number circuit 509 is externally attached to the main control unit 41, even when the main control unit 41 is in the security mode, the random number circuit 509 performs program management independently of the processing in the CPU 505. The random number generation operation may be started after initial setting based on the storage data of the area.

  In the random number circuit abnormality inspection process shown in FIG. 26, first, the random number clock abnormality determination counter is cleared, and the random number clock abnormality determination count value, which is the count value, is initialized to “0” (Sa301). Subsequently, the internal information data CIF4 stored in the bit number [4] of the internal information register CIF is read (Sa302). Then, it is determined whether or not the read value at Sa302 is “1”. At this time, if the frequency monitoring circuit 551 provided in the random number circuit 509 detects a frequency abnormality in the random number clock RCLK from the random number external clock terminal ERC, the bit value “1” is written as the internal information data CIF4. .

  Therefore, when the read value is determined to be “1” in Sa303, the random number clock abnormality determination count value is updated to be incremented by 1 (Sa304). At this time, it is determined whether or not the count value after the update in Sa304 has reached a predetermined clock abnormality determination value (Sa305). Here, the clock abnormality determination value may be a numerical value determined in advance in order to determine that the clock abnormality is detected when the frequency monitoring circuit 551 continuously detects the frequency abnormality of the random number clock RCLK. If the clock abnormality determination value has not been reached in Sa305, the processing returns to Sa302, and determination based on the bit value of the internal information data CIF4 is performed again.

  When the clock abnormality determination value is reached in Sa305, an error code indicating a random circuit abnormality is set in the register (Sa306), and the random circuit abnormality inspection process is terminated.

  If the read value is determined to be “0” in Sa303, the random value abnormality determination counter is cleared, and the random value abnormality determination count value that is the count value is initialized to “0” (Sa307). In the process of Sa303, it is determined that the read value is “0” when the bit value of the internal information data CIF4 read in Sa302 becomes “0” continuously for a plurality of times (for example, twice). You may do it.

  Subsequent to the processing of Sa307, a check value used for checking whether there is an abnormality in the random number value is set to an initial value “0000H” (Sa308). Then, the stored numerical data as the random value is read from the random value register 559A as the random value register R1D included in the random number circuit 509 (Sa309). For example, in the processing of Sa309, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “0”, and the random number value fetching by software is designated. Subsequently, the bit value of the random value fetch specification data RDLT0 stored in the bit number [0] of the random value fetch specification register RDLT is set to “1”, and fetching to the random value register R1D is designated. Note that setting the bit value in the bit number [0] of the random value fetch specification register RDLT to “1” outputs a latch signal instructing the random number circuit 509 to fetch (latch) numerical data from the CPU 505. It corresponds to that. Thereafter, the numerical value data to be stored as the random number value may be read by turning on the register read signal RRS1 supplied to the random number value register R1D.

  After reading the numerical data in Sa309, the read value is set as the random number inspection reference value (Sa310). Subsequently, the numerical value data to be a random number value is further read from the random value register 559A (Sa311). Note that the reading operation at Sa311 may be performed in the same procedure as the reading operation at Sa309. Further, it is preferable to provide a sufficient delay time between the reading operation at Sa309 and the reading operation at Sa311 because the numerical data in the random number sequence RSN generated by the random number circuit 509 changes. After the numerical data is read in Sa311, an exclusive OR operation between the random number inspection reference value and the read value in Sa311 is executed (Sa312). Further, a logical sum operation between the calculation result at Sa312 and the check value is executed, and the calculation result is updated to be a new check value (Sa313). For example, the check value may be stored in a predetermined area of the RAM 507, and each time the process of Sa313 is executed, the calculation result obtained by the process may be saved as a new check value. As a result, changes in all the bits in the numerical data read from the random value register 559A are recorded. If the bit has changed at least once during a plurality of readings, the corresponding bit value in the check value is “1”. "

  Therefore, it is determined whether or not the check value is “FFFFH” (Sa 314), and if it is, since a change in the bit value is recognized for all bits, it is determined that the random value has been updated normally. Then, the random number circuit abnormality inspection process ends. If it is confirmed that the random number value has been updated normally, the bit value of the random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS is set to “1”. It is set to instruct the random value fetching to the random value register R1D according to the signal input to the port P0. In this embodiment, a wiring for transmitting the game start signal SS1 from the start switch 7 is connected to the input port P0. Thereby, when the game start signal SS1 is turned on, the random number value can be taken into the random value register R1D.

  If the check value is determined to be other than “FFFFH” in Sa314, the random number abnormality determination count value is updated to be incremented by 1 (Sa315). At this time, it is determined whether or not the count value after the update in Sa315 has reached a predetermined random value abnormality determination value (Sa316). Here, if the random number circuit 509 is operating normally, the random value abnormality determination value is determined so that all the bits of the numerical data read from the random value register 559A are changed at least once. Any predetermined numerical value may be used. If the random value abnormality determination value has not been reached in Sa316, the process returns to Sa311 to perform determination for reading numerical data as a random value from the random number circuit 509 and checking for abnormality.

  If the random value abnormality determination value is reached in Sa316, an error code indicating a random circuit abnormality is set in the register (Sa317), and the random circuit abnormality inspection process is terminated.

  The random circuit abnormality inspection process of Sa314 is not limited to that executed by the CPU 505, and the random circuit abnormality inspection process may be executed by a built-in circuit in the main control unit 41 other than the CPU 505. As an example, the random number circuit 509 has a function of executing a random number circuit abnormality inspection process. When a frequency abnormality of the random number clock RCLK is detected or when an abnormality of the random number value is detected, the CPU 505 May be notified. In addition, the random number circuit abnormality inspection process is not limited to the one executed only by Sa 314. For example, every time a timer interrupt occurs in the main control unit 41, a part or all of the random number circuit abnormality inspection process is executed. You may make it.

  After the random number circuit abnormality inspection process in the step of Sa26, it is determined whether or not the random number circuit is abnormal (Sa27). Whether or not the random number circuit is abnormal is determined by whether or not an error code indicating a random number circuit abnormality is set. If it is determined in step Sa27 that the random number is abnormal, an error command indicating a random circuit error is set in the specific command transmission buffer and transmitted to the sub-control unit 91 (Sa22). (Sa23), the process proceeds to error processing, that is, a RAM abnormal error state.

  If it is determined in step Sa27 that the random number is not abnormal, a setting start command is set in the specific command transmission buffer and transmitted to the sub-control unit 91 (Sa28). Next, the interruption is permitted (Sa29), and the setting change processing, that is, the setting change state is entered.

  If the setting key switch 37 is OFF in the step of Sa31, an error code indicating RAM abnormality is set in the register (Sa32), an error command indicating RAM abnormality is set in the specific command transmission buffer, and the sub-control unit 91 is set. In response to the transmission (Sa33), the interrupt is permitted (Sa34), and the process proceeds to an error process, that is, a RAM abnormal error state.

  If the RAM parity is 0 in step Sa7, it is further determined whether or not the destructive diagnosis data is normal (Sa8). If power interruption interrupt processing (main) is performed normally, the data for destruction diagnosis should be set. If the data for destruction diagnosis is not normal in step Sa8 (data for destruction diagnosis is power interruption) Since the data in the RAM 507 is not normal also in cases other than 5A (H) stored at the time, the process proceeds to step Sa24 to execute initialization 1, and then the setting key switch 37 is turned on in step Sa31. If so, the random number circuit setting process (Sa25) and the random number circuit abnormality inspection process (Sa26) are sequentially performed. If the random number circuit is abnormal, the interrupt is permitted after the transmission of the error command indicating the random number circuit abnormality (Sa22). (Sa23), and the process proceeds to error processing. On the other hand, if the random circuit is not abnormal, after transmission of the setting start command (Sa28), the interrupt is permitted (Sa29), and the process proceeds to the setting change process. If the setting key switch 37 is OFF in step Sa31, an interrupt is permitted after setting an error code indicating a RAM abnormality (Sa32) and sending an error command indicating a RAM abnormality (S323) (Sa34). ), Go to error handling.

  If it is determined in step Sa8 that the destructive diagnosis data is normal, the data in the RAM 507 is normal, so the destructive diagnosis data is cleared (Sa9). After performing initialization 3 for initializing the used stack area (Sa10), it is determined whether the setting key switch 37 is ON (Sa11). If the setting key switch 37 is ON, the process proceeds to step Sa24. Initialization 1 is executed, the random number circuit setting process (Sa25), the random number circuit abnormality inspection process (Sa26) are sequentially performed. If the random number circuit is abnormal, after transmission of an error command indicating the random number circuit abnormality (Sa22), The interrupt is permitted (Sa23), and the process proceeds to error processing. On the other hand, if the random circuit is not abnormal, after transmission of the setting start command (Sa28), the interrupt is permitted (Sa29), and the process proceeds to the setting change process.

  If the setting key switch 37 is OFF in the step of Sa11, the same random number circuit setting process (Sa13) as the step of Sa25 and the same random number circuit abnormality inspection process (Sa14) as the step of Sa26 are executed, and whether or not the random number circuit is abnormal. Is determined (Sa15).

  If it is determined in step Sa15 that the random number circuit is abnormal, an error command indicating the random number circuit abnormality is set in the specific command transmission buffer, and transmitted to the sub-control unit 91 (Sa22). Permitted (Sa23), the process proceeds to error processing, that is, a RAM abnormal error state.

  If it is determined in step Sa15 that there is no abnormality in the random number circuit, each register is restored to the state before power interruption, that is, the state stored in the stack (Sa16), and the return command is stored in the specific command transmission buffer. It is set and transmitted to the sub-control unit 91 (Sa17). Then, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not the numerical value data is taken into the random number value register 559A (Sa18), and the random number value must be latched. If the random value is latched, the random number value for internal lottery is read from the random value register 559A (Sa19), and the process proceeds to Sa20. When a random number value for internal lottery is read from the random value register 559 in the step Sa19, the random number latch flag register is cleared and new numerical data is accepted. In the step of Sa19, the random number value for internal lottery is read, but the read random number value is not used, but a dummy value is taken in order to enable a new random value to be taken in response to the operation of the start switch 7. Is read out.

  In step Sa20, the return command is set in the specific command transmission buffer, transmitted to the sub-control unit 91, and then interrupts are permitted (Sa21). Return to.

  FIG. 27 is a flowchart showing the control content of error processing executed by the main control unit 41.

  In the error processing, first, the current display state of the game auxiliary display 12 is saved in the stack (Sb1), the error code stored in the register is displayed on the game auxiliary display 12 (Sb2), and the error code is stored in the RAM. It is determined whether or not the error code indicates an abnormal error or a random circuit error (Sb3). If the error code indicates a RAM abnormal error or a random circuit error, the process proceeds to a loop process that does not perform any process. .

  If it is determined in step Sb3 that the error code indicates neither a RAM error error nor a random circuit error, an error command indicating an error state and its type is set in the normal command transmission buffer ( Sb4). The error command set in step Sb4 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Next, it is determined whether or not the operation of the reset / setting switch 38 is detected (Sb5). If the operation of the reset / setting switch 38 is not detected, whether or not the operation of the reset switch 23 is further detected. (Sb6), and if the operation of the reset switch 23 is not detected, the process returns to the step Sb5. That is, the game waits in a state where the progress of the game is impossible until the operation of the reset / setting switch 38 or the reset switch 23 is detected.

  When the operation of the reset / setting switch 38 is detected in the step Sb5 or when the operation of the reset switch 23 is detected in the step Sb6, the error code stored in the register is cleared (Sb7 ), The display state of the game auxiliary display 12 is restored to the display state saved in the stack in the step Sb1 (Sb8), and an error command indicating that the error state is released is set in the normal command transmission buffer ( Sb9), the process returns to the original process. The error command set in Sb9 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  As described above, in the error processing, if the error processing is not due to the RAM abnormality or the random number circuit abnormality, the reset / setting switch 38 or the reset switch 23 is operated to return to the original processing even when the error state is canceled. However, in the case of error processing due to RAM abnormality or random number circuit abnormality, even if the reset / setting switch 38 or the reset switch 23 is operated, the error state is canceled and the original state is not restored.

  FIG. 28 is a flowchart showing the control content of the setting change process executed by the main control unit 41.

  In the setting change process, first, the setting value stored in the setting value work of the RAM 507 is read out, and the read value is set as a display value (Sc1), and whether or not the display value is out of a settable range (1 to 6). (Sc2), if the display value is within the settable range, the process proceeds to step Sc4. If the display value is outside the settable range, the display value is corrected to 1, and the process proceeds to step Sc5.

  In the step of Sc5, after the display value is displayed on the set value display 24, the operation waits for detection of the operation of the reset / setting switch 38 and the start switch 7 (Sc5, Sc6). In the step of Sc5, the reset / setting switch When 38 on is detected, the rising edge indicating the rising of the operation switch is cleared (Sc7), the display value is incremented by 1 (Sc8), and the process returns to the step Sc2.

  When the start switch 7 is detected to be on in the step of Sc6, the rising edge is cleared (Sc9), the value displayed on the set value display 24 is updated to 0 (Sc10), and the setting key Wait until the switch 37 is turned off (Sc11).

  When it is determined in step Sc11 that the setting key switch 37 is OFF, the display value is stored in the setting value work (Sc12), a game state command is generated, set in the command transmission buffer (Sc13), and game processing Migrate to The gaming state command set in the step of Sc13 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  FIG. 29 is a flowchart showing the control contents of the game process executed by the main control unit 41.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) are sequentially executed. When the end-time process ends, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step of Sd2, it is determined whether or not the above winning combination is allowed based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sd1. Process. In this internal lottery process, a winning flag is set in the RAM 507 based on each lottery result.

  In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R and the operation of the corresponding reel 2L, 2C, 2R in response to the operation of the stop switch 8L, 8C, 8R detected by the player are detected. A process for stopping the rotation is executed.

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process of setting a gaming state in preparation for the next game is executed.

  In the game process, a command is generated according to the progress control of the game and set in the normal command transmission buffer, so that the command set for the sub-control unit 91 in the subsequent timer interrupt process (main) Is to be sent.

  30 to 32 are flowcharts showing the control contents of the BET process executed by the main control unit 41 in step Sd1.

  In the BET process, first, the value of the BET counter in which the value of the bet amount is stored in the RAM 507 is cleared (Se1), and a specified number (3 regardless of the game state in this embodiment) is set in the RAM 507. Then, based on whether or not the replay game flag indicating that it is a replay game is set in the RAM 507, it is determined whether or not the game is a replay game (Se3).

  If it is determined in step Se3 that the game is a replay game, a BET command indicating that 3 bets have been added is set in the normal command transmission buffer (Se4), and the value of the BET counter is set to 1. Add (Se5) and refer to the prescribed number of bets set in the RAM 507 to determine whether or not the value of the BET counter is the prescribed number, that is, whether or not the bet number as a game start condition is set. If the value of the BET counter is not the specified number, the process returns to the step of Se5. If the value of the BET counter is the specified number, the insertion prohibition flag indicating that the medal cannot be inserted is set in the RAM 507 (Se7). , Go to the step of Se12. The BET command set in step Se4 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  If it is determined in step Se3 that the game is not a replay game, settings before waiting to be made are performed (Se8), and the process proceeds to step Se9. In the setting before waiting for insertion, the insertion disable flag set in the RAM 507 is cleared, and a medal can be inserted.

  In the step of Se9, it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the number of bets serving as a game start condition is set. Proceeding to the step, if the value of the BET counter is a specified number, it is further determined whether or not any of the switches has been turned OFF (Se10). In the step of Se10, it is determined whether or not any of the switches has been turned off based on whether or not a falling edge indicating the falling of any of the switches is set. Further, since the falling edge is set only when any switch is turned off and all the switches are turned off, in the step of Se10, it is determined whether any switch is turned off or not. In addition, it is also determined whether or not other switches are OFF.

  If it is determined in step Se10 that none of the switches have changed to OFF, or if any switch has changed to OFF but is still ON, the process proceeds to step Se14. If any of the switches changes to OFF and it is determined that all the switches are OFF, the falling edge is cleared (Se11) and the process proceeds to Se12.

  In the step of Se12, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not the numerical value data is taken into the random number value register 559A, and the random number value must be latched. If the random value is latched, the random number value for internal lottery is read from the random value register 559A (Se13), and the process proceeds to Se14. Note that when the random number value for internal lottery is read from the random value register 559 in the step of Se13, the random number latch flag register is cleared, and the acquisition of new numerical data is permitted. In the step of Se13, although the random number value for internal lottery is read, the read random number value is not used, but a dummy value is taken in order to make it possible to take in a new random value according to the operation of the start switch 7. Is read out. For this reason, although the number of bets serving as a game start condition is set, the switches other than the start switch 7 are operated, and the start switch 7 is in the state where the operation of the start switch 7 is invalidated. Even if the random number value is latched because it has been operated, and the acquisition of a new random number value is prohibited, all switches are turned off and latched when the operation of the start switch 7 is validated. The random number value thus read is read out as a dummy, and the random number value can be newly latched at the timing when the start switch 7 is operated thereafter.

  In step Se14, it is determined whether or not an error code is set in the register, that is, whether or not an error is detected. If an error code is set, the process proceeds to error processing shown in FIG.

  If an error code is not set in the step of Se14, it is determined whether or not a medal can be inserted based on whether or not the insertion disable flag is set in the RAM 507 (Se15). When it is determined in step Se15 that the medal can be inserted, the flow path switching solenoid 30 is turned on, and the medal can be inserted using the medal flow path as a path on the hopper tank side. (Se16), the process proceeds to step Se18, and if it is determined that the medal cannot be inserted, the flow path switching solenoid 30 is set to the off state, and the medal flow path is the path on the medal payout exit 9 side. As a result, the insertion of a new medal is prohibited (Se17), and the process proceeds to Step Se18.

  In step Se18, it is determined whether or not the setting key switch 37 is on. If the setting key switch 37 is on, it is determined whether or not the value of the BET counter is 0 (Se19). If the value of the BET counter is 0 in the step Se19, the confirmation start command is set in the normal command transmission buffer (Se20), and the setting confirmation process (Se21), that is, the setting confirmation state is entered. The confirmation start command set in step Se20 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main). Moreover, after the setting confirmation process in the step of Se21 is completed, the process returns to the step of Se9.

  If the setting key switch 37 is not on in step Se18, or if the value of the BET counter is not 0 in step Se19, the process proceeds to step Se22, and whether or not the inserted medal sensor 31 has detected passage of the inserted medal. That is, it is determined whether or not there is a inserted medal flag indicating that the passage of the inserted medal is detected. If the passage of the inserted medal is not detected in the step of Se22, the process proceeds to the step of Se33, and if the passage of the inserted medal is detected, the inserted medal flag is cleared (Se23), and the non-insertable flag is set in the RAM 507. Whether or not a medal can be inserted is determined based on whether or not a medal can be inserted (Se24). If the medal cannot be inserted, the process proceeds to Step Se33.

  If the medal can be inserted in the step of Se24, the prescribed number of bets set in the RAM 507 is referred to and it is determined whether or not the value of the BET counter is the prescribed number (Se20). If the value is not the prescribed number, a BET command indicating that the bet number is incremented by 1 is set in the normal command transmission buffer (Se26), the BET counter value is incremented by 1 (Se27), and the BET counter value is It is determined whether or not the number is a specified number, that is, whether or not the number of bets serving as a game start condition has been set (Se28). If the value of the BET counter is not the specified number, the process returns to Step Se9. The BET command set in step Se <b> 26 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Further, if the value of the BET counter is the specified number in the step of Se28, that is, if the betting number as the game start condition is set, the process returns to the step of Se12 and the betting number as the game start condition is set. If the random number value is latched before being performed, the random number value is read out in step Sa13, and a new random value can be taken in. For this reason, a random number value is latched because the start switch 7 is operated in a state where the start switch 7 is invalidated without setting the bet number as a game start condition, and a new random value Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the random number value latched when the operation of the start switch 7 is validated is read as a dummy. The random number value can be newly latched at the timing when the start switch 7 is operated after that.

  If the value of the BET counter is a prescribed number in the step of Se25, a credit command indicating the current credit counter value is set in the normal command transmission buffer (Se29), and the credit counter in which the credit value is stored in the RAM 507 is stored. The value is incremented by 1 (Se30), and it is determined whether the value of the credit counter is 50 which is the upper limit value (Se31). If the value of the credit counter is not 50, the process returns to the step of Se9, If the value is 50, the input impossible flag is set in the RAM 507 (Se32), and the process returns to the Se9 step. The credit command set in the step of Se29 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  In step Se33, it is determined whether or not an operation of the start switch 7 is detected, that is, whether or not a rising edge indicating a rising edge of the start switch 7 is set. Further, the rising edge is set only when any switch is turned on and all the switches are turned off. Therefore, in the step of Se33, in addition to whether any switch is turned on. Whether or not the other switch is OFF is also determined.

  If it is determined that the operation of the start switch 7 is not detected in the step of Se33, or if another switch for which the start switch 7 has been operated is also operated, the process proceeds to the step of Se44, and the start switch 7 If the operation is effectively detected, the rising edge is cleared (Se34), the specified number of bets set in the RAM 507 is referred to, and whether the value of the BET counter is the specified number, that is, the game start condition It is determined whether or not the bet number is set (Se35).

  If the value of the BET counter is not the specified number in the step of Se35, the process returns to the step of Se9. If the value of the BET counter is the specified number, the interrupt is prohibited (Se36), and the random number value register is operated by operating the start switch 7. Since the random interruption value (main) is executed without the random number value fetched in 559A being stored in the random number value work assigned to the RAM 507, the random number value latched before the interruption is not backed up. Then, the process proceeds to step Se37.

  In the step of Se37, it is determined whether or not the random number value is latched based on the value of the random number latch flag register, that is, whether or not the numerical value data is taken into the random number value register 559A, and the random value must be latched. For example, the interrupt prohibited in the step of Se36 is permitted (Se38), and the process returns to the step of Se9.

  If the random number value is latched in the step of Se37, the random number value for internal lottery is read from the random value register 559A (Se39), and the read random number value is stored in the random value work of the RAM 507 (40). Proceed to The random value work is a work for storing a random value used in the internal lottery, and the random value stored in the random value work in the step of Se40 is used for the internal lottery.

  In the step of Se41, the interruption prohibited in the step of Se36 is permitted, the insertion impossible flag is set in the RAM 507, the flow path switching solenoid 30 is set to the off state, and the flow path of the medal is routed on the medal payout exit 9 side. As a result, the insertion of a new medal is prohibited (Se42) and the setting at the start of the game is performed (Se43). Then, after the step of Se43, the BET process is terminated and the process returns to the flowchart of FIG.

  In the step of Se44, it is determined whether or not the operation of the single BET switch 5 is detected, that is, whether or not the rising edge indicating the rising of the single BET switch 5 is set. If the operation of the single BET switch 5 is not detected in the step of Se44, the process proceeds to the step of Se52, and if the operation of the single BET switch 5 is detected, the rising edge is cleared (Se45) and set in the RAM 507. With reference to the prescribed number of bets, it is determined whether or not the value of the BET counter is the prescribed number (Se46). If the value of the BET counter is a specified number in the step of Se46, the process returns to the step of Se9. If the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se47). If the counter value is 0, the process returns to step Se9. If the value of the credit counter is not 0 in step Se47, a BET command indicating that 1 is added to the bet number is set in the normal command transmission buffer (Se48), and 1 is subtracted from the value of the credit counter (Se49). Then, the value of the BET counter is incremented by 1 (Se50), and it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the number of bets serving as a game start condition is set (Se51). If the value of the counter is not a specified number, the process returns to step Se9. The BET command set in the step of Se48 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  Further, if the value of the BET counter is the prescribed number in the step of Se51, that is, if the betting number as the game start condition is set, the process returns to the step of Se12 and the betting number as the game start condition is set. If the random number value is latched before being performed, the random number value is read out in step Sa13, and a new random value can be taken in. For this reason, a random number value is latched because the start switch 7 is operated in a state where the start switch 7 is invalidated without setting the bet number as a game start condition, and a new random value Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the random number value latched when the operation of the start switch 7 is validated is read as a dummy. The random number value can be newly latched at the timing when the start switch 7 is operated after that.

  In the step of Se52, it is determined whether or not the operation of the MAXBET switch 6 is detected, that is, whether or not the rising edge indicating the rising of the MAXBET switch 6 is set. If the operation of the MAXBET switch 6 is not detected in the step of Se52, the process proceeds to the step of Se61. If the operation of the MAXBET switch 6 is detected, the rising edge is cleared (Se53), and the number of bets set in the RAM 507 Referring to the prescribed number, it is determined whether or not the value of the BET counter is the prescribed number (Se54). If the value of the BET counter is the specified number in the step of Se54, the process proceeds to the step of Se58, and if the value of the BET counter is not the specified number, it is determined whether or not the value of the credit counter is 0 (Se55), If the value of the credit counter is 0, the process proceeds to step Se58. If the value of the credit counter is not 0 in the step of Se55, the value of the credit counter is decremented by 1 (Se56), the value of the BET counter is incremented by 1 (Se57), and the process returns to the step of Se54. In the step of Se58, it is determined whether or not the BET counter is added. If the BET counter is not added, the process returns to the step of Se9, and if the BET counter is added, the number of bets is added by the added number. The BET command indicating that it has been set is set in the normal command transmission buffer (Se59), and the process proceeds to the step of Se60. The BET command set in the step of Se59 is transmitted to the sub-control unit 91 in the subsequent timer interrupt process (main).

  In the step of Se60, it is determined whether or not the value of the BET counter is a specified number, that is, whether or not the number of bets serving as a game start condition is set. If the value of the BET counter is not the specified number, the step of Se9 Return to. Further, if the value of the BET counter is the prescribed number in the step of Se60, that is, if the betting number as the game start condition is set, the process returns to the step of Se12 and the betting number as the game start condition is set. If the random number value is latched before being performed, the random number value is read out in step Sa13, and a new random value can be taken in. For this reason, a random number value is latched because the start switch 7 is operated in a state where the start switch 7 is invalidated without setting the bet number as a game start condition, and a new random value Even when the take-in is prohibited, a predetermined number of bets are set as a game start condition, and the random number value latched when the operation of the start switch 7 is validated is read as a dummy. The random number value can be newly latched at the timing when the start switch 7 is operated after that.

  In the step of Se61, it is determined whether or not the operation of the settlement switch 10 is detected, that is, whether or not the rising edge indicating the rising of the settlement switch 10 is set. If the operation of the settlement switch 10 is not detected in the step of Se61, the process returns to the step of Se9. If the operation of the settlement switch 10 is detected, the rising edge is cleared (Se62), and the replay game flag is set in the RAM 507. Whether or not the game is a replay game is determined based on whether or not it is played (Se63), and if the game is a replay game, the process returns to step Se9. If the game is not a replay game in the step of Se63, it is determined whether or not the value of the BET counter is 0 (Se64). If the value of the BET counter is 0, the process proceeds to the step of Se66, and the value of the BET counter is 0. Otherwise, a bet amount settlement flag indicating that the already set bet amount is to be settled is set in the RAM 507 (Se65), and the process proceeds to the step of Se66. In step Se66, the hopper motor 34 is driven to pay out medals corresponding to the value stored in the credit counter or the BET counter, that is, medals stored as credits or medals used for setting the number of bets. Checkout process is performed to control the return. Then, after the settlement process in the step of Se66, the input impossible flag set in the RAM 507 is cleared (Se67), and the process returns to the step of Se9.

  FIGS. 33 and 34 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the activation process and the game process at regular intervals (0.56 ms interval). Note that other interrupts are automatically prohibited during the execution period of the timer interrupt process (main).

  In the timer interrupt process (main), first, after saving the register in use to the stack area (Sk1), a port input process for inputting detection data of various switches from the input port is performed (Sk2).

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk3). In the step of Sk3, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, referring to the counter value for branching, it is determined whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sk4), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk8 described later and the phase signal data changed in the final stop process of Sk21 described later is executed (Sk5).

  Next, referring to the branch counter value, it is determined whether or not it is 1, that is, timer interrupt 2 (Sk7). If it is not timer interrupt 2, that is, timer interrupt 1, reel motor Reel start processing (Sk8) for controlling the step time interval when starting 32L, 32C, 32R, motor step processing (Sk8) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, the motor phase signal standby processing (Sk9) for changing the phase signal to single-phase excitation after a certain time has passed is executed sequentially, and then the register saved in the stack area at Sk1 is restored (Sk18) and interrupted Return to the previous process.

  In the case of timer interrupt 2 in the step of Sk6, LED dynamic display processing for dynamically lighting various indicators (Sk10), control signal output processing for outputting data such as lighting signals of various LEDs to the output port, etc. (Sk11), a time counter update process (Sk12) for updating various time counters, a command transmission process (Sk13) for transmitting a command or an operation detection command stored in the normal command transmission buffer to the sub-control unit 91, After sequentially executing the external output signal update process (Sk14) for updating the external output signal, the register saved in the stack area in Sk1 is restored (Sk18), and the process returns to the process before the interrupt.

  If it is timer interrupt 3 or timer interrupt 4 in the step of Sk4, it is further determined by referring to the branch counter value whether it is 3 or not, that is, timer interrupt 4 (Sk15). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. After the origin passing process (Sk16) to be validated and the switch input determination process (Sk17) for determining whether or not the switch detection state has changed are sequentially executed, the stack area is determined in Sk1. Returning the saved register (SK18), return to the process before the interrupt process.

  If the timer interrupt is 4 in the step of Sk15, the stop stored in the work on the stop reel is stored when the stop operation position is stored in the work on the stop reel with the detection of the stop switches 8L, 8C, 8R. The stop position is determined from the operation position, the stop switch process (Sk19) for calculating the number of steps after which the stop should be performed, and the number of steps until the stop calculated in the stop switch process is counted. A stop process (Sk20) for starting braking by two-phase excitation, and a final stop process (Sk21) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then saved in the stack area at Sk1. The register is restored (Sk18) and the process returns to the state before the interrupt.

  FIG. 35 is a flowchart showing the control content of the switch input determination process executed by the main control unit 41 in the timer interrupt 3 of the timer interrupt process (main) described above.

  In the switch input determination process, the input data of each switch acquired in the port input process is updated (Sk101), and it is determined whether the detection state indicated by the previous input data is the same as the detection state indicated by the current input data. If the determination is made (Sk102) and the detection state indicated by the previous input data is not the same as the detection state indicated by the current input data, the flow returns to the flowchart of FIG.

  In the step of Sk102, when the detection state indicated by the previous input data is the same as the detection state indicated by the current input data, that is, when the same detection state is indicated for 2.24 ms, the determined data of the corresponding switch. Is updated (Sk103), and the process proceeds to Step S104. In step Sk103, the current confirmed data is moved to the previous confirmed data, and the detection state indicated by the input data determined to be the same as the previous time is set as the current confirmed data.

  In the step of Sk104, it is determined whether or not the previous confirmed data after updating and the current confirmed data are the same. If the previous confirmed data and the current confirmed data are the same, the process returns to the flowchart of FIG. .

  If the previous confirmed data and the current confirmed data are not the same in the step of Sk104, it is determined whether a switch in which the previous confirmed data and the current confirmed data are different has changed from OFF to ON (Sk105). If it has changed to ON, it is further determined whether or not another switch is ON (Sk106). If the other switch is ON, the process proceeds to step Sk108, and if the other switch is not ON, the corresponding switch A rising edge is set to indicate that has changed from OFF to ON (Sk107), and the process proceeds to step S108.

  In step Sk108, it is determined whether or not a switch having different final determination data and current determination data has changed from ON to OFF. If the switch has changed from ON to OFF, it is determined whether or not other switches are ON. If the other switch is ON (S109), the process returns to the flowchart of FIG. 34. If the other switch is not ON, a falling edge indicating that the corresponding switch has changed from ON to OFF is set ( Sk110), the process returns to the flowchart of FIG.

  FIG. 36 is a flowchart showing the control contents of the power interruption interrupt process (main) executed when the main control unit 41 interrupts the activation process or the game process when the voltage drop signal from the power interruption detection circuit 48 is input. is there. It should be noted that after the interruption interrupt process (main) is started, other interrupts are automatically prohibited, and interrupts are not permitted except when returning to the original process.

  In the power interruption interrupt process (main), first, all registers that may be in use are saved in the stack area (Sm1). Note that the values of the I register and IY register described above are used, but are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, the detection data of the voltage drop signal is acquired from the input port, and it is determined whether or not the voltage drop signal is input (Sm2). At this time, if the voltage drop signal is not inputted, the register saved in the stack area in Sm1 is restored (Sm3), and the process before the interruption is returned. At this time, interruption is automatically permitted.

  If a voltage drop signal is input in step Sm2, destruction diagnosis data (5A (H) in this embodiment) is set (Sm4), and all output ports are initialized (Sm5). . Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 507 becomes 0 (Sm6), and access to the RAM 507 is performed. Prohibited (Sm7).

  Then, except for the determination of whether or not the voltage drop signal is input (Sm8, where Sm8 is the same process as Sm2), a loop process in which no process is performed is entered. That is, when the voltage decreases as it is, the operation is stopped internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted. Further, in this loop process, when the voltage recovers and the voltage drop signal is not input, the above-described startup process (main) is executed, if the RAM parity is 0 and the destructive diagnosis data is normal, It will return to the original process.

  In this embodiment, after prohibiting access to the RAM 507, the output state of the voltage drop signal is monitored, and when the voltage drop signal is not input, it is determined whether the voltage is restored, and the process goes to the start-up process (main). However, no processing is performed in the loop processing, and the voltage is recovered while the loop processing is being performed, and the activation is performed based on the input of the reset signal from the reset circuit 49. You may make it transfer to a process (main).

  The main control unit 41 in the slot machine 1 according to the present embodiment reads and executes the security check program 506A stored in the ROM 506 or the like when the power is turned on or the system is restarted after the system reset occurs. Thus, the security mode is set.

  At this time, a security check process is executed as a process corresponding to the security check program 506A. Here, the security time when the main control unit 41 enters the security mode is stored in advance in the bit number [2-0] or the bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 506. Depending on the bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, it can be selected in advance in addition to the fixed time corresponding to the setting contents shown in FIG. Any one of a plurality of extended times can be set as a time component included in the security time. If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the system reset or power-on is performed corresponding to the short mode or the long mode shown in FIG. A variable setting time that changes in a predetermined time range each time is performed can be set as a time component included in the security time.

  Until the security time set in this way elapses, the execution of the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 should not be started during the period in which the main control unit 41 is in the security mode. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the slot machine 1. In this case, the extension time of the security mode can be made different for each model of the slot machine 1, and it becomes difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time can be varied for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the slot machine 1.

  FIG. 37 is a timing chart for explaining the operation of the random number circuit 509 built in the main control unit 41. FIG. 37A shows the control clock CCLK generated by the control clock generation circuit 42 mounted on the game control board 40. FIG. 37B shows the random number clock RCLK generated by the random number clock generation circuit 43. As shown in FIGS. 37A and 37B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCLK are different from each other. It does not become an integral multiple of the other oscillation frequency.

  As shown in FIG. 37 (B), the random number clock RCLK rises from a low level to a high level at timings T10, T11, T12,. The random number clock RCLK is supplied to the random number external clock terminal ERC of the main control unit 41 and is input to the clock terminal CK in the clock flip-flop 552 provided in the random number circuit 509 shown in FIG. The clock flip-flop 552 responds to the rising edge of the random number clock RCLK input to the clock terminal CK with the latch clock RC0 fed back from the negative phase output terminal (inverted output terminal) Q bar to the D input terminal. Are taken in (latched) and output as a random number update clock RGK from the positive phase output terminal (non-inverted output terminal) Q. Thereby, as shown in FIG. 37C, the random number update clock RGK rises from the low level to the high level at the timing T10, T12, T14,..., And is half the oscillation frequency of the random number clock RCLK. The signal has an oscillation frequency. For example, if the oscillation frequency of the random number clock RCLK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Since the oscillation frequency of the random number clock RCLK is neither an integer multiple nor a fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK. Different frequency. The random number generation circuit 553 updates the numerical data in the count value permutation RCN in response to, for example, the rising edge of the random number update clock RGK. The random number sequence change circuit 555 changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553 based on the setting of the random number update rule by the random number sequence change setting circuit 556 as a random number sequence RSN. Output. Thus, the numerical data in the random number sequence RSN is updated in response to the rising edge of the random number update clock RGK, for example, as shown in FIG.

  The latch clock RC0 output from the clock flip-flop 552 is an inverted signal of the random number update clock RGK, the oscillation frequency is the same as the oscillation frequency of the random number update clock RGK, and its phase is the same as the phase of the random number update clock RGK and π It differs by (= 180 °). The latch clock RC0 is branched into a latch clock RC1 and a latch clock RC2 at a branch point BR1. Therefore, for example, as shown in FIG. 37E, each of the latch clocks RC0, RC1, and RC2 becomes an oscillation signal whose signal state changes in a common cycle. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B.

  In response to the rising edge of the latch clock RC1, the latch flip-flop 557A takes in (latches) the game start signal SS1 transmitted from the start switch 7 and supplied to the input port P0, and latches the game start signal. Output from the output terminal Q as SL1. If the fetching method in random number latch selector 558A is designated as signal input to input port P0, game start latch signal SL1 is output as random number latch signal LL1. As a result, for example, the game start signal SS1 whose signal state changes between the off state (low level) and the on state (high level) at the timing shown in FIG. 37F is the timing T11 when the latch clock RC1 rises. After being fetched into the latching flip-flop 557A at T13, T15,..., The random number latch signal LL1 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. And output from the random number latch selector 558A.

  The random value register 559A serving as the random value register R1D responds to the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 in response to the rising edge of the random number latch signal LL1 input from the random number latch selector 558A to the clock terminal. Then, the numerical data serving as stored data is updated (latched).

  For example, as shown in FIG. 37 (G), when a rising edge is generated at which the random number latch signal LL1 changes from the OFF state to the ON state at timing T11, the random number sequence change circuit 555 outputs it at this timing T11. As shown in FIG. 37H, the numerical data in the random number sequence RSN is taken into the random value register R1D and acquired as numerical data that becomes a random value. Accordingly, the random value register 559A serving as the random value register R1D can acquire and store numerical data used as a random number value based on the detection of the operation of the start switch 7.

  Further, if the bit value in the bit number [0] of the second random number initial setting KRS2 as shown in FIG. 9B is “1”, for example, numerical data that becomes a random value generated by the random number circuit 509 is displayed. The start value can be changed at every system reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, which is based on the analysis result of the program. By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent an act such as illegally winning a special role.

  As described above, in this embodiment, by setting the bit value in the bit number [4-3] of the security time setting KSES to a value other than “00”, a variable that changes in a predetermined time range every time the system is reset or the power is turned on. The set time can be set as a time component included in the security time. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  Also, by setting the bit value in the bit number [2-0] of the security time setting KSES to a value other than “000”, any one of a plurality of extension times that can be selected in advance in addition to the fixed time is set as the security time. It can be set as an included time component. This makes it difficult to specify the operation start timing of the random number circuit 509 and the numerical data to be updated from the operation start timing due to power-on, system reset, and so on. By connecting the “board” and inputting an illegal signal at a predetermined timing, it is possible to reliably prevent acts such as illegally winning a special role.

  Further, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 43 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 are different from each other. The oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. In this way, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. From the operation timing of the CPU 505, the random number circuit 509 generates the random number generation circuit 553 and the random number sequence change circuit 555. It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of the numerical data serving as the random number value in the random number circuit 509 from the operation timing of the CPU 505. Also, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. In this way, synchronization between the control clock CCLK and the internal system clock SCLK and the latch clocks RC1 and RC2 is prevented, and the random number circuit 509 takes in numeric data as a random value from the operation timing of the CPU 505. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 505.

  The random number circuit 509 built in or externally attached to the main control unit 41 outputs from the random number generation circuit 553 in response to the bit value [0] of the second random number initial setting KRS2 being “1”. The start value of the numerical data in the count value permutation RCN and the random number sequence RSN output from the random number sequence change circuit 555 can be changed every time the system is reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify the numerical data read from the random value register 559A included in the random number circuit 509, which is based on the analysis result of the program. It is possible to surely prevent an aiming signal or an illegal signal from being input by connecting a so-called “hanging board”.

  In the external bus interface 501 provided in the main control unit 41, the internal resource access control circuit 501A restricts external reading by internal components other than the internal circuit such as the CPU 505 with respect to internal data of the main control unit 41 such as data stored in the ROM 506, for example. Thereby, for example, a program for controlling a game, such as a user program stored in the ROM 506, can be prevented from being read from the outside of the main control unit 41 and provided for analysis or the like. Further, it is possible to reliably prevent aiming based on the analysis result of the game control processing program and input of an illegal signal due to connection of a so-called “hanging board”.

  In the random number circuit 509 built in or externally attached to the main control unit 41, when the frequency monitoring circuit 551 detects a frequency abnormality in the random number clock RCLK, the random number circuit 509 is stored in the bit number [4] of the internal information register CIF. The bit value of the information data CIF4 is set to “1”. When the CPU 505 determines that the number of times that the read value of the internal information data CIF4 is continuously determined to be “1” has reached the clock abnormality determination value in step S65, the random number circuit 509 It is determined that an abnormality has occurred in the operating state. If it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the game is controlled to be in an error state and the progress of the game is disabled. Thereby, it is possible to reliably prevent an illegal act by inputting an illegal signal as the random number clock RCLK.

  The CPU 505 built in the main control unit 41 writes the bit value “1” to the random value fetch specification register RDLT corresponding to the output of the latch signal to the random number circuit 509, and reads the random value register 559A a plurality of times. Then, all the bits of the read numerical data are monitored, and it is determined that an abnormality has occurred in the operation state of the random number circuit 509 based on the presence / absence of bit data that does not change. If it is determined that an abnormality has occurred in the operation state of the random number circuit 509, the game is controlled to be in an error state and the progress of the game is disabled. As a result, it is possible to reliably and easily detect that an abnormality has occurred in the operating state of the random number circuit 509 and prevent fraud. In particular, by performing the internal lottery while the numerical data is not normally updated by the random number circuit 509, that is, while the numerical data is fixed, it is possible to prevent fraud such as always winning a special combination.

  The random number circuit 509 built in or externally attached to the main control unit 41 is a numerical data that becomes a random value every time the system is reset when the bit value [0] of the second random number initial setting KRS2 is “1”. Change the start value of. At this time, for example, a start value that is changed at each system reset may be determined using a count value of a free-run counter built in the main control unit 41, for example. As a result, the initial value can be determined using different initial value determination data depending on the timing of the system reset or the like, and illegal acts due to shooting or the like can be prevented.

  In this embodiment, the extension time of the security mode is one of a plurality of extension times that can be selected in advance, corresponding to the bit value [2-0] of the security time setting KSES. Was not changed at each system reset, but the extension time added to the fixed time is determined as one of a plurality of extension times at each system reset, for example, by setting in the user program stored in the ROM 506 You may do it. In this case, the extension time is defined to be longer than the longest variable setting time. Then, after determining a rough extension time, a detailed extension time may be determined. As a result, the security time for entering the security mode at the time of power-on or system reset can be greatly changed for each system reset, and the operation start timing of the random number circuit 509 is updated or updated from the operation start timing of the slot machine 1. It becomes more difficult to specify numerical data.

  Further, the extension time of the security mode may be determined using an ID number assigned to each chip constituting the main control unit 41. As an example, an extension time corresponding to the calculated value is executed by executing a part or all of an operation for performing a predetermined scramble process on the ID number and an operation such as addition / subtraction / multiplication / division using the ID number. May be set. In this case, the extension time may be randomly determined for each system reset, for example, by changing an arithmetic expression used for determining the extension time for each system reset. Furthermore, the count value of the free run counter, the ID number, and the like, for example, the arithmetic expression for determining the extension time using the ID number is determined corresponding to the count value of the free run counter stored at the time of system reset. The extended time may be determined randomly at each system reset by using a combination of the above. In addition, when changing the start value of the random number generated by the random number circuit 509 at each system reset, the start value of the random number can be changed by using a combination of the count value of the free-run counter and the ID number. You may decide.

  In this embodiment, a random number clock having an oscillation frequency different from the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 42 by the random number clock generation circuit 43 provided outside the main control unit 41. Although RCLK is generated and supplied to the random number circuit 509, the clock signal supplied to the CPU 505 of the main control unit 41 and the clock signal supplied to the random number circuit 509 are shared by the common clock generation circuit. You may make it produce | generate using the oscillation signal produced | generated by one included oscillator. In this case, for example, a frequency divider for generating the random number clock RCLK and the control clock CCLK is provided, and the latch clocks RC0, RC1, RC2 are synchronized with the control clock CCLK or the internal system clock SCLK. What is necessary is just to set the frequency division ratio etc. in each frequency divider so that it may become difficult to produce. The control clock generation circuit 42 and the random number clock generation circuit 43 may be provided in whole or in part inside the main control unit 41 or outside the main control unit 41.

  In the present embodiment, the random number circuit 509 is supplied with the random number clock RCLK generated by the random number clock generation circuit 43, and the random number update clock RGK and the latch clock RC0 are generated by the clock flip-flop 552. However, an oscillation signal that becomes the random number update clock RGK or the latch clock RC0 may be generated outside the random number circuit 509, such as the random number clock generation circuit 43, for example. Alternatively, a circuit for generating the random number update clock RGK and a circuit for generating the latch clock RC0 may be separately provided in the random number circuit 509. As an example, while generating a random number update clock RGK by a flip-flop similar to the clock flip-flop 552, an inversion circuit for inverting the signal state of the random number update clock RGK is provided, and a signal output from the inversion circuit is latched. It may be used as the clock RC0.

  In the random number circuit 509 applied to the present embodiment, when the random number latch flag data RDFM0 is “1”, that is, when the numerical value data is captured in the random value register R1D, a new random value capture request is generated. Even in this case, new numerical data is not taken into the random value register R1D. In such a state, the numerical data in the random value register R1D is read and the random number latch flag data RDFM0 is cleared. It becomes impossible to load new numerical data into the random value register R1D.

  Therefore, as shown in FIG. 38, the game start signal SS1 is input by operating the start switch 7, the numerical data is latched, stored in the random value register R1D, and then the stored numerical data is read out. When the random number latch flag data RDFM0 becomes “1”, the stored numerical data is retained, and even if the game start signal SS1 is input during that time, the new numerical data may be overwritten. Therefore, even if noise is applied to the signal line of the game start signal SS1 due to static electricity or the like, the numerical data does not change, and even in such a case, the start switch 7 is latched at the timing when it is operated. Internal lottery is not performed using numerical data different from numerical data.

  Note that the configuration in which new numerical data is not captured in the random value register R1D while the numerical data is captured in the random value register R1D may be configured to prohibit latching of the new numerical data. In addition, although new numerical data is latched, the writing to the random value register R1D may be prohibited.

  As described above, in the present embodiment, in a state where the numerical data is taken into the random value register R1D, a configuration is adopted in which the stored numerical data is held until the stored numerical data is read out. However, in this case, even if the operation of the start switch 7 is performed during a period in which the game is not effective, the data is latched and numerical data is held in the random value register R1D. When the operation is enabled and the start switch 7 is operated, an internal lottery is performed based on numerical data latched at a timing different from the timing at which the start switch 7 was originally operated to start the game. New problems will arise.

  On the other hand, in the present embodiment, as shown in FIG. 39, when the prescribed number of bets is set in a state where the prescribed number of bets is not set and the game start condition is satisfied, It is confirmed whether or not the numerical data is latched in R1D, that is, whether or not the random number latch flag is set. If the numerical data is latched in the random value register R1D, the numerical value of the random number register R1D is dummy. Data is read out. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, the start switch 7 is operated before the specified number of bets is set, and the numerical data is stored in the random value register R1D. Even if this state is maintained, the specified number of bets is set. Since the numerical value data newly latched in the random number value register R1D can be stored at the same time as the game start condition is satisfied, the random number value is latched before the game start condition is set. The internal lottery is not performed using the numerical data held in the register R1D, that is, the numerical data latched at a timing different from the timing at which the start switch 7 is operated in a state where the game can be started.

  In the present embodiment, a predetermined number of bets are set, and whether or not the random number latch flag is set when the game start condition is satisfied, that is, latched before the predetermined number of bets is set. Whether or not numerical data is stored in the random value register R1D is checked, and the numerical data stored in the random value register R1D is read only when the random number latch flag is set. The numerical data stored in the random number register R1D may be read out uniformly when the number of bets is set and the game start condition is satisfied.

  Further, in this embodiment, as shown in FIG. 40, even if the start switch 7 is operated in a state where a prescribed number of bets satisfying the game start condition are set, switches other than the start switch 7 are operated. In this state, the start of the game is prohibited. However, although the specified number of bets is set, a switch other than the start switch 7 is operated and the start of the game is prohibited. In this state, when all the switches are turned off and the start of the game is permitted, it is confirmed whether the numerical data is latched in the random value register R1D, that is, whether the random number latch flag is set. When the numerical data is latched in the random value register R1D, the numerical data in the random value register R1D is read out as a dummy. To have. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  For this reason, although a prescribed number of bets satisfying the game start condition are set, switches other than the start switch 7 are operated, and the start switch 7 is operated in a state where the game start is prohibited. Even if the numerical data is stored in the random value register R1D and the state is maintained, all the switches are turned off and the start of the game is permitted, and at the same time, the numerical data newly latched in the random value register R1D Is stored in the random number value register R1D in a state where the start of the game is prohibited, that is, when the start switch 7 is operated in a state where the game can be started. Will not be used for internal lottery using numerical data latched at different times

  In this embodiment, although a specified number of bets satisfying the game start condition are set, a switch other than the start switch 7 is operated and the game start is prohibited. Whether or not the random number latch flag is set when all the switches are turned off and the start of the game is permitted, that is, the numerical data latched before the start of the game is permitted is stored in the random number value register R1D. The numerical data stored in the random number register R1D is read only when the random number latch flag is set. However, when the start of the game is permitted, the data is uniformly disturbed. The numerical data stored in the numerical register R1D may be read.

  In this embodiment, when the power is turned on, the control state of the main control unit 41 can be returned to the control state before the power interruption, and a prescribed number of bets satisfying the game start condition are set. In this embodiment, as shown in FIG. 41, when returning to the control state before the power interruption when the power is turned on, the start of the game is permitted. When the numerical data is latched in the random value register R1D, it is checked whether the random number latch flag is set. Thus, the numerical data of the random value register R1D is read out. As a result, the random number latch flag is cleared, and new numerical data can be taken in.

  Therefore, as shown in FIG. 41, after the power is turned on, after the reset signal is turned OFF and the main control unit 41 starts its operation, it returns to the control state before power interruption and before the start of the game is permitted. In this stage, the start switch 7 is operated to store numerical data in the random value register R1D, and even if the state is maintained, the control state is restored and the start of the game is permitted. Since the numerical data newly latched in R1D can be stored, the numerical data latched and held in the random number value register R1D after the power is turned on and before returning to the control state before power interruption, that is, An internal lottery is not performed using numerical data latched at a timing different from the timing at which the start switch 7 is operated in a state where the game can be started.

  In this embodiment, after turning on the power, whether or not the random number latch flag is set when returning to the control state before the power interruption, that is, the numerical data latched before the start of the game is permitted is the random number value. Whether or not the data is stored in the register R1D is checked, and only when the random number latch flag is set, the numerical data stored in the random value register R1D is read. The numerical data stored in the random value register R1D may be read out uniformly when the previous control state is restored.

  In addition, when returning to the control state before the power interruption after turning on the power, the numerical data stored in the random number register R1D is uniformly stored regardless of whether the return control state is a state where the game can be started. Although it is read out, it is checked whether or not the return control state is a state where the game can be started, and is stored in the random value register R1D only when the return control state is a state where the game can be started. The numerical data that has been read may be read out.

  The main control unit 41 determines whether or not the start switch 7 is operated in a state where the game can be started, based on whether or not a rising edge indicating the rising of the start switch 7 is set.

  The rising edge of the start switch 7 is detected by the start switch 7 in the switch input determination process that is executed once every four times (about 2.24 ms). It is set on condition that the confirmed data based on the state has changed from OFF to ON. Since the deterministic data is data that is updated only when the previous detection state and the current state match each time the switch input determination process is performed, the rising edge of the start switch 7 indicates that the detection state of the start switch 7 is OFF. When the switch is in the state, it is set by detecting the ON of the start switch 7 twice in succession in the switch input determination process.

  On the other hand, since the execution interval of the switch input determination process is about 2.24 ms, the start switch 7 is provided on condition that the ON is continuously detected for at least about 2.24 ms after the start switch 7 is turned on. Rising edge is set, and the operation of the start switch 7 is detected.

  Thus, in this embodiment, as shown in FIG. 42, on condition that the start switch 7 is continuously detected for a certain period (at least about 2.24 ms) in a state where the game can be started, The operation of the start switch 7 is detected and the game is started, and the game is prevented from starting even if the start switch 7 is erroneously detected due to noise such as static electricity. it can.

  In this embodiment, the operation of the start switch 7 is detected on condition that the start switch 7 is continuously turned on for a certain period (at least about 2.24 ms) in a state where the game can be started. The game is started. For example, the detection state of the start switch 7 is confirmed a plurality of times in one switch input determination process, and on the condition that all are determined to be ON, The operation may be detected and the game may be started. Even in such a configuration, the game starts even though the start switch 7 is erroneously detected due to noise such as static electricity. Can be prevented.

  Further, in the present embodiment, as shown in FIG. 42, when the rising edge of the start switch 7 is detected in a state where the game can be started, whether or not the random number latch flag is set, that is, the start switch 7 The numerical data is latched by the above operation, and it is checked whether or not the numerical data is stored in the random value register R1D, and the game is started only when the numerical data is stored in the random value register R1D. Yes.

  Therefore, the numerical value data is not stored in the random number value register R1D, that is, the random number value used for the internal lottery is not latched, but the game is started and the internal lottery is not performed. The internal lottery can be reliably performed using the numerical data latched at the timing when the switch 7 is operated.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  For example, in the above embodiment, a slot machine for setting bets using medals and credits is used. However, the present invention is not limited to this, and a slot machine for setting bets using game balls. Alternatively, it may be a complete credit type slot machine that uses only credits to set the number of bets.

  Further, in addition to the medal insertion mechanism such as the flow path switching solenoid 30 and the insertion medal sensor 31, a ball take-in device that takes in a game ball, and a take-in ball that detects a game ball taken in by the ball take-in device In addition to a medal payout mechanism, such as a hopper motor 34b and a payout sensor 34c, a ball payout device for paying out game balls, and a payout ball detection switch for detecting game balls paid out by the ball payout device It is possible to set a bet number using both medals and game balls and play a game, and the present invention may be applied to a slot machine in which medals and game balls are paid out by winning.

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main control unit 91 sub control unit 505 CPU
506 ROM
507 RAM
509 Random number circuit 559A Random value register

Claims (5)

The game can be started by setting a predetermined number of bets for one game using the gaming value, and the display result is displayed on a variable display device capable of variably displaying a plurality of types of symbols each identifiable. A slot machine in which one game is ended by being derived, and a winning can be generated according to the display result derived to the variable display device,
Start operation means operated when starting the game ,
Numerical value updating means for updating numerical data;
Game start means for starting the game by operating the start operation means in a startable state where the game can be started;
Random number extraction that extracts numerical data updated by the numerical value updating means as a random number value and stores it in the numerical data storage area regardless of whether the start operation means is operated or not . Means,
Numerical data reading means for reading numerical data stored in the numerical data storage area when the game starting means starts a game;
Data storage means for readable and writable storing data used for controlling the game;
Numerical data storage means for storing numerical data read by the numerical data reading means in the data storage means;
Pre-determining means for determining whether or not to allow the generation of a prize using the numerical data stored in the data storage means by the numerical data storage means ;
After the numerical data is stored in the numerical data storage area by the random number extraction means, until the stored numerical data is read, no new numerical data is stored by the random number extraction means. Numeric data holding means for holding stored numeric data;
The numerical data stored in the numerical data storage area is read out when the predetermined number of bets as a game start condition are set and the startable state is set, so that the numerical data stored by the numerical data holding means and hold releasing means for releasing the retention,
Data holding means for holding data in the data storage means even when power supply is stopped;
Control state return means for returning to a control state before stopping power supply based on data held by the data holding means when power supply is started;
An interruption interrupt processing means for interrupting and executing an interruption process for enabling a return by the control state restoration means when a decrease in power supply is detected;
In the startable state, when the start operation means is operated, execution of the interrupt processing by the power interruption interrupt processing means is prohibited, and the numerical data is stored in the data storage means by the numerical data storage means Interrupt processing prohibition / permission means for permitting execution of the prohibited interrupt processing,
A slot machine characterized by comprising: Storage information setting means for setting storage information indicating that numerical data is newly stored when numerical data is stored in the numerical data storage area by the random number extraction means;
The game start means is in the startable state, the operation of the start operation unit is detected, and to condition said storage information is set, according to claim 1, characterized in that to start the game Slot machine. A non-volatile memory in which an identification code assigned to each slot machine is stored;
The slot machine further includes initial numerical data generating means for generating initial numerical data based on an identification code stored in the nonvolatile memory when power supply is started,
The slot machine according to claim 1 or 2 , wherein the numerical value updating means starts updating the numerical data from the initial numerical data generated by the initial numerical data generating means when power supply is started. . Game control means for controlling the progress of the game,
The numerical data updating means according to any one of claims 1 to 3, characterized in that updating the numerical data to enter different operation clock periodicity of the operation clock for operating said game control means Slot machine. The numerical data update means inputs an operation clock of a predetermined cycle to update the numerical data,
The slot machine includes operation clock abnormality determining means for determining whether an abnormality has occurred in the operation state of the numerical value updating means based on the input state of the operation clock input to the numerical data updating means. The slot machine according to any one of claims 1 to 4 .

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