JP4961788B2 - Semiconductor integrated circuit, acoustic signal processing device, and operation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the load of a CPU required for scanning the state of a button. <P>SOLUTION: In an integrated circuit 10 having the CPU 11 and the button RAM 35 that can be accessed from the CPU 11, there are provided a scan control section 31 that accesses a button circuit 48 having a plurality of buttons except the CPU 11 for outputting an analog signal for indicating the state of each button periodically and successively; an ADC 32 for converting a signal outputted by the button circuit 48 to digital data; a change width restriction circuit; and an LPF 34. The converted digital data are written to the button RAM 35. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to a semiconductor integrated circuit having a function of detecting an operation of an operation element via an operation element circuit, an acoustic signal processing device including such a semiconductor integrated circuit, and such a semiconductor integrated circuit and an operation element circuit. It is related with the operating device provided with .

2. Description of the Related Art Conventionally, a semiconductor integrated circuit is provided with a parallel I / O (input / output unit) and an ADC (analog / digital converter) so that an operation of an external operator can be detected.
In this case, when an operator circuit composed of a plurality of operators connected in a matrix to the parallel I / O is connected, and the operator is an on / off input button or switch, a voltage signal from the operator circuit is provided. Is input to the input port of the parallel I / O as a digital signal. In the case where the operator sets a continuous value such as a slider or a dial, the voltage signal from the operator circuit is input to the ADC, and AD conversion is performed here to obtain digital data. It was.

  When the control CPU provided in the semiconductor integrated circuit detects the operation contents of the operation element, by setting the address of the operation element to be detected to the output port of the parallel I / O, the address is set in the parallel I / O. Is input to the operation element circuit, and the CPU inputs the voltage signal indicating the state of the plurality of operation elements corresponding to the address to the input port of the parallel I / O or the ADC. It was possible to obtain data indicating the child status.

In this case, it is possible to scan the states of all the operators by causing the CPU to sequentially set all the addresses having the operators to the output port of the parallel I / O. Then, in order to make the CPU always know the state of the operation element and the operation content, the CPU is made to repeat this scan periodically.
For example, Patent Document 1 is cited as a document related to such a technique.
Japanese Patent No. 2542574

  By the way, in the case of performing the above-described scanning, a signal indicating the state of a plurality of operators can be obtained immediately after the address is set for the operator for on / off input. However, for an operator that sets continuous values, after setting the address, it waits for several microseconds to several tens of microseconds until the signal voltage stabilizes, and further, one voltage signal is provided for each operator. It was necessary to perform AD conversion and import them one by one. Furthermore, since the AD conversion result often includes noise, it is necessary to perform processing such as a low-pass filter on the obtained data to remove the noise.

  For this reason, when scanning the state of the operation element, if there is an operation element that sets a continuous value in the scan target, an address is written to the output port of the parallel I / O at an appropriate time interval, and the input signal It was necessary to process one by one. The processing for this purpose is simple in itself, but there is a problem that the CPU is always restrained and becomes a burden on the CPU. For this reason, when a CPU with high processing capability is mounted, there is a problem in that it leads to an increase in cost of a semiconductor integrated circuit and, by extension, a device on which the semiconductor integrated circuit is mounted.

  The present invention solves such a problem and reduces the load on the CPU required to scan the state of the operation element, thereby reducing the cost of the semiconductor integrated circuit and the device mounting the semiconductor integrated circuit. With the goal.

In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes an output terminal for outputting an address signal to an external operation element circuit having a plurality of operation elements, and an input for inputting one analog signal from the operation element circuit. A semiconductor integrated circuit including a CPU and a storage means accessible from the CPU, wherein the operating element circuit is supplied from the semiconductor integrated circuit via the output terminal. In response to the signal, a signal indicating the state of one of the plurality of operating elements indicated by the address signal is output as an analog signal to the input terminal of the semiconductor integrated circuit, and the semiconductor integrated circuit Aside from the CPU , the circuit periodically generates the address signal for scanning each of the plurality of operators in order, and supplies the address signal to the operator circuit. And by, in the operator circuit, the address signal to sequentially output the analog signal indicating the state of the sequential shown operator, the operator circuit access unit, sequentially inputted through the input terminal from the operator circuit signals, and converting means for sequentially converted into digital data, the digital data in which the conversion means is sequentially converted, is obtained by incorporating a sequentially written write means in the storage means.
Another semiconductor integrated circuit according to the present invention includes an output terminal for outputting an address signal to an external operation element circuit having a plurality of operation element groups including a plurality of operation elements, and the same as the operation element group from the operation element circuit. In a semiconductor integrated circuit having a CPU and a storage means accessible from the CPU, the operation element circuit is provided for each of the operation element groups. In response to the address signal supplied from the semiconductor integrated circuit via the output terminal, a signal indicating the state of one of the plurality of operating elements indicated by the address signal is used as the analog signal for the semiconductor. A circuit that outputs to the input terminal of the integrated circuit, and the address signal that scans each of the plurality of operators in order, separately from the CPU, in the semiconductor integrated circuit. Is generated and supplied to the operator circuit, so that the same number of analog signals as the operator group indicating the state of the operator of each operator group sequentially indicated by the address signal are sequentially supplied to the operator circuit. The same number of analog signals as the number of manipulator groups input from the manipulator circuit via the input terminal while the manipulator circuit access means to be output and the address signal are held at a constant value are 1 Selection means for sequentially selecting one by one; conversion means for sequentially converting analog signals sequentially selected by the selection means into digital data; and writing means for sequentially writing the digital data sequentially converted by the conversion means to the storage means And built-in.

In these semiconductor integrated circuits, the access to the storage means by the writing means is prioritized over the access to the storage means by the CPU or is performed at a timing that does not overlap with the access to the storage means by the CPU. It is good to make it.
Further, the writing means is provided with limiting means for limiting the change width of the digital data converted by the conversion means , and the writing means sequentially stores the digital data whose change width is limited by the limiting means in the storage means. It is good to write .

Further, the writing means is provided with a low-pass filter that smoothes the change in the digital data converted by the converting means , and the writing means sequentially writes the digital data processed by the low-pass filter into the storage means. it may be.
Moreover, the acoustic signal processing apparatus of this invention is an acoustic signal processing apparatus provided with said semiconductor integrated circuit.
Moreover, the operating device of this invention is an operating device provided with said semiconductor integrated circuit and said operation element circuit.

According to the semiconductor integrated circuit , the acoustic signal processing device or the operation device of the present invention as described above, the load on the CPU required for scanning the state of the operation element is reduced, whereby the semiconductor integrated circuit and its semiconductor integrated circuit are reduced. It is possible to reduce the cost of the acoustic signal processing device or the operation device that is mounted.

Hereinafter, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
First, FIG. 1 shows a configuration of an embodiment of an acoustic signal processing apparatus of the present invention including an integrated circuit which is an embodiment of a semiconductor integrated circuit of the present invention.
Among these, the integrated circuit 10 includes a CPU 11, DSP 12, memory I / O (input / output units) 13, 14, internal RAM 15, waveform I / O 16, MIDI (Musical Instruments Digital Interface: registered trademark) I, as shown in FIG. / O17, timer 18, parallel port 19, and operator I / O30, and a CPU bus 21 and a DSP bus 22 for connecting necessary parts of these.

  The acoustic signal processing apparatus 40 includes the integrated circuit 10 mounted on a printed circuit board, and further includes an external ROM 41, an external RAM 42, and a memory bus 43 for connecting them to the memory I / O 14 of the integrated circuit 10. . Further, an ADC (analog / digital converter) 44, a DAC (digital / analog converter) 45, an audio input terminal 46, an audio output terminal 47, an operator circuit 48, and a switch / display circuit 49 are provided.

Among these, the CPU 11 is a control means for controlling the operation of each unit of the integrated circuit 10, and by executing a required program, setting of the contents of signal processing executed by the DSP 12, communication via the MIDII / O 17, Time measurement by the timer 18, operation detection via the parallel port 19 and the operation element I / O 30, and display control on the display are performed.
The program executed by the CPU 11 is stored in the external ROM 41. However, when executing the program, the program may be read directly from here, or may be read in advance and copied to the internal RAM 15 or the like. It may be read and executed.

  The DSP 12 is an acoustic signal processing unit that performs various operations such as mixing, equalizing, and applying effects to the acoustic signal input via the waveform I / O 16 and outputs the acoustic signal via the waveform I / O 16. The contents of the signal processing to be executed are determined by the contents of the microprogram and parameters set by the CPU 11 in the DSP 12.

  The memory I / O 13 is connected to both the CPU bus 21 and the DSP bus 22 and reads / writes data from / to the internal RAM 15 in response to a memory access request from the CPU 11 and the DSP 12 made through these buses. , And has a function of arbitrating those access requests.

The memory I / O 14 transmits an access request from the CPU 11 to the memory connected to the external memory bus 43 to the memory bus 43, and reads / writes data from / to the memory connected to the memory bus 43 in response to the access request. Has the function to perform.
The internal RAM 15 is a storage unit that is used as a work area for the CPU 11 and the DSP 12 and temporarily stores a program executed by the CPU 11.

  The waveform I / O 16 is an interface for inputting / outputting digital waveform data. The waveform data input from the external ADC 44 or the like is input to the DSP 12, and the waveform data processed by the DSP 12 is input to the external DAC 45 or the like. Has a function to output. If the acoustic signal processing device 40 has a digital audio input / output terminal, an input terminal buffer circuit, and an output terminal drive circuit, it is not necessary to input / output waveform data via the ADC 44 or the DAC 45.

  The MIDII / O 17 has a function of inputting / outputting MIDI data to / from an external circuit. Here, a function for handling MIDI data is not provided on the acoustic signal processing device 40 side. However, if an appropriate interface is provided in the acoustic signal processing device 40, MIDI data output from an electronic musical instrument, a PC (personal computer), or the like can be used. It is also possible to input to the integrated circuit 10 and cause the CPU 11 to change the contents of signal processing by the DSP 12 according to the contents of the MIDI data.

The timer 18 is a time measuring means for measuring the timing of signal processing by the DSP 12 and the detection timing of the state of the operation element by the parallel port 19 and the operation element I / O 30.
The parallel port 19 scans the switch operator included in the switch / display circuit 49 to capture the on / off state as in the case of the above-described Patent Document 1, and the parallel port 19 is connected to the display included in the switch / display circuit 49. It is an interface for supplying a signal for controlling display contents.

The operation element I / O 30 includes a scan control unit 31, an ADC 32, a change width limiting circuit 33, an LPF (low-pass filter) 34, and an operation element RAM 35. An analog signal indicating each state of a plurality of operation elements from an external circuit such as the operation element circuit 48 is received, converted into digital data, written in the operation element RAM 35, and used for processing by the CPU 11. Interface.
The operator I / O 30 functions as an operator circuit access unit, a conversion unit, and a writing unit. The function, configuration, and operation of each unit will be described later.

The external ROM 41 is a storage unit that stores programs executed by the CPU 11 and other data that does not need to be changed. The external ROM 41 may be constituted by rewritable nonvolatile storage means such as a flash memory so that these data can be updated.
The external RAM 42 is a storage means for providing a work area for the CPU 11 and can be configured by SRAM (Static RAM) or DRAM (Dynamic RAM).

The ADC 44 is a conversion unit that converts an acoustic signal input from the analog audio input terminal 46 into digital waveform data and outputs the digital waveform data to the waveform I / O 16.
The DAC 45 is conversion means that converts waveform data input from the waveform I / O 16 into an analog acoustic signal and outputs the analog acoustic signal to the audio output terminal 47.

The operation element circuit 48 is a circuit provided with operation elements such as a slider and a knob for outputting operation contents as an analog signal using a variable resistor or the like. Its function, configuration and operation will be described later.
The switch / display circuit 49 detects and outputs the operation content of the operation element that outputs the operation content as a digital signal such as whether or not the operation is pressed or on / off, such as buttons and keys, and the data received from the CPU 11 or the DSP 12. This is a circuit provided with a display circuit for displaying a message, a parameter value or the like on a display.

According to the acoustic signal processing device 40 as described above, various signal processing is performed on the acoustic signal input from the audio input terminal 46 by the DSP 12 in the integrated circuit 10, and the result is output from the audio output terminal 47. be able to. The contents of the signal processing performed by the DSP 12 can be selected by a user using an operator provided in the operator circuit 48 or the switch / display circuit 49 from options prepared in advance. It can be set similarly. Then, the CPU 11 generates a set of microprograms and parameter values for performing signal processing in accordance with the operation of the operator, and sets them in the DSP 12.
Such an acoustic signal processing device 40 can be configured as, for example, a mixer or an effector, but is not limited thereto.

  Further, the control of each part of the acoustic signal processing device 40 is generally in charge of the CPU 11 here. However, the state of the operation element provided in the operation circuit 48 is detected by the operation element I / O 30 and the result is stored in the operation element RAM 35. Then, when the CPU 11 sets the detection processing parameters in the scan control unit 31, the change width limiting circuit 33, and the LPF 34 when the integrated circuit 10 or the acoustic signal processing device 40 is started up, after that, the controller RAM 35 is simply set. The operator data indicating the state of the operator provided in the operator circuit 48 (the position of the knob, the presence or absence of pressing, etc.) can be acquired only by referring to it.

Next, the configuration of the operation element circuit 48 and the operation element I / O 30 will be described focusing on the points related to this function.
First, FIG. 2 shows the configuration of the operator circuit 48.
As shown in FIG. 2, the operation element circuit 48 includes first to fourth operation element groups 110 to 140. Each operating element group 110-140 can be provided with a total of 64 operating elements such as sliders and knobs that detect the state by using the variable resistor R, 16 in total. The subscript after the symbol R is a number indicating the number of the operator and the corresponding resistor.

In addition, all of these controls may be the same slider, for example, and may be used as a fader corresponding to 1ch (channel) to 64ch, or a combination of a slider and a knob, with a fader and pan partly provided on a ch strip, It is also conceivable to use the rest as an operator for setting the send level of the matrix mixer. It should be noted that an arbitrary number of operators may be provided in units of one operator as required up to a maximum of 64 operators.
Each variable resistor R is connected in parallel for each operator group, and a pull-up voltage AVDD is applied thereto.

  Further, the first operator group 110 will be described as a representative. The first operator group 110 is provided with analog switches 111 and 112, and the contact P of each variable resistor R that moves according to the operation of the operator is provided. The analog switches 111 and 112 are connected to the A0 to A7 terminals. Therefore, an analog voltage signal having a voltage corresponding to the state of the operation element is input to the A0 to A7 terminals of the analog switches 111 and 112 through the contact P.

  The analog switches 111 and 112 can output from the COM terminal one of the signals input to the A0 to A7 terminals according to the input signals to the EN terminal and the S terminal. The EN terminal is an enable terminal. When “1” is input to the EN terminal, output from the COM terminal is performed. When “0” is input, output from the COM terminal is not performed.

In addition, a 3-bit address signal indicating any of 0 to 7 is input to the S terminal, and the number of the A0 to A7 terminals to be output from the COM terminal is designated by the number. be able to.
Although illustration is omitted for the sake of simplicity, the second to fourth operator groups 120 to 140 are also provided with similar analog switches, and the operator groups are provided in accordance with input signals to the EN terminal and the S terminal. An analog voltage signal having a voltage corresponding to the state of any one of the operators is output.

  The scan control unit 31 of the manipulator I / O 30 outputs a 4-bit address signal SCANSW to such a manipulator circuit 48 to designate which manipulator is to be output. Of these, the lower 3 bits, SCANSW [2: 0], are input to the S terminal of each analog switch. The most significant bit SCANSW [3] is input to the EN terminal of the analog switch (analog switch 112 in the case of the first operator group 110) to which the contact P of the operator with the smaller number is connected. Further, the inverted signal of the most significant bit is used as the scan signal SCANSW [4], and the EN terminal of the analog switch (the analog switch 111 in the case of the first operator group 110) to which the contact P of the operator with the larger number is connected. To enter.

  In this way, substantially any one of the 16 operators in each operator group is selected by the 4-bit address signal SCANSW, and a voltage signal output corresponding to the state of the operator is obtained. Can do. This output is input to the ADC 32 of the operator I / O 30 through the four output signal lines ANPORT [0] to [3].

It should be noted that the same scan signal SCANSW is input to the analog switches in all the operator groups including those that are partially omitted from the drawing. Therefore, for example, when the address signal output by the scan control unit 31 is “0000”, a signal indicating the state of the first operator is output from the output signal line ANPORT [0], but other outputs are output. From the signal lines ANPORT [1] to [3], signals indicating the states of the second to fourth operators shown at the corresponding positions are output.
The ADC 32 sequentially selects the output signal lines ANPORT [0] to [3], converts the voltage signal input from the selected signal line into digital data (numerical data) by A / D conversion, and thereafter. Used for processing.

Next, FIG. 3 shows the output timing of the address signal output from the scan control unit 31 to the operator circuit 48 and the select signal output to the ADC 32.
As shown in this figure, the scan control unit 31 sequentially outputs address signals SCANSW from 0 to N−1, thereby causing the operator circuit 48 to respond to the states of the first to 4Nth operators. The voltage signal is sequentially output. This operation is a scan of the operator, and the scan control unit 31 that performs such an operation functions as an operator circuit access unit.
The value of N is a parameter that specifies the scan range of the operation element, and the CPU 11 writes and sets a value in the register in the range from 1 to 16.

  When a new address signal is input to the operation element circuit 48, the scan control unit 31 causes the ADC 32 to wait for the period indicated by the arrow A until the output of the voltage signal from the operation element circuit 48 is stabilized. Thereafter, select signals for sequentially selecting the output signal lines ANPORT [0] to [3] are output for each period indicated by the arrow B.

The ADC 32 selects a signal line designated by the select signal from the output signal lines ANPORT [0] to [3], and performs A / D conversion on a signal input from the signal line, thereby corresponding to each address signal. Numerical data indicating the state of the operator is sequentially generated, and the data is input to the change width limiting circuit 33.
The scan control unit 31 inputs the next address signal to the operator circuit 48 at the timing when all the output signal lines are selected and the signal conversion is completed.

Therefore, the time required for one scan is (A + B × 4) × N. The period indicated by the arrow A is about several microseconds to several tens of microseconds, and is 16 microseconds here. The period indicated by arrow B is about 1 to 2 microseconds.
The scan control unit 31 has a timer inside, and repeats scanning of addresses from 0 to N−1 at a time interval set by a register. Alternatively, the next scan may be started immediately upon completion of the scan.

Next, FIG. 4 shows the configuration of the change width limiting circuit 33.
This circuit is provided to alleviate sudden numerical fluctuations due to noise, etc., and the operator data indicating the state of a certain operator obtained by scanning changes from the previous operator data of that operator. When the difference is more than the width limit value, the change means limits the change width to the change width limit value.
More specifically, it includes a difference detection circuit 331, an addition / subtraction circuit 332, a comparison circuit 333, and a selector 334.

  The difference detection circuit 331 then obtains 10-bit numeric data after A / D conversion by the ADC 32, obtained by the current scan of the operator, at the timing corresponding to each operator, and the previous time of the operator. The processing up to the LPF 34 is performed on the data obtained by the scan of the previous scan, and then the upper 10 bits of the data at the previous scan (previous control data) stored in the control RAM 35 are input. The absolute value of the 8-bit difference is obtained and the difference is input to the comparison circuit 333. Further, a signal indicating which of the current data value and the previous data value is larger is input to the adder / subtractor circuit 332.

  The addition / subtraction circuit 332 is a circuit for obtaining an allowable upper limit value or a lower limit value of data acquired by the current scan. Based on the signal input from the difference detection circuit 331, it is determined which of the current data value and the previous data value is larger. If the current data is larger, the change width limit value is added to the previous data value. If the current value is smaller than the allowable upper limit value and the current value is smaller, a value obtained by subtracting the change width limit value from the previous data value is output to the selector 334 as the allowable lower limit value.

The comparison circuit 333 compares the absolute value of the difference obtained by the difference detection circuit 331 with the change width limit value at each timing corresponding to each operation element, and outputs the result to the selector 334.
If the absolute value of the difference is smaller than the change width limit value, the selector 334 outputs the data input from the ADC 32 as it is as the present digitized data because the change width is within the allowable range. Conversely, if the absolute value of the difference is larger than the change width limit value, the allowable upper limit value or the allowable lower limit value input from the adder / subtractor circuit 332 is output as the present digitized data to limit the data change width to the limit value. To do.
Note that the change width limit value can be arbitrarily set by the CPU 11 writing a value in the register. Further, by setting a specific value (for example, maximum value) as the change width limit value, the change width limit function of the change width limit circuit 33 may be disabled.

Next, FIG. 5 shows the configuration of the LPF 34.
The LPF 34 is also a circuit provided to alleviate rapid numerical fluctuations due to noise or the like, and has a function of smoothing the change in the digitized data of each operator output from the change width limiting circuit 33.
More specifically, it has multipliers 341, 343, an adder 342, and a delay circuit 344.

  The multiplier 341 multiplies the current digitized data of the operator by the filter coefficient a at each timing corresponding to each operator, and the multiplier 343 supplies the operation supplied from the delay circuit 344. The data after the previous filtering process of the child is multiplied by (1-a), and these are added by the adder 342 to obtain the data after the current filtering process. The delay circuit 344 is realized as a circuit for reading the previous operation data of the operation stored in the operation RAM 35.

  The filter coefficient a is a value between 0 and 1 and can be arbitrarily set by the CPU 11 writing a value in the register. For example, a 4-bit register can be set in units of 1/16. When a is 1, the function of the LPF 34 is invalidated, and only the number of bits of the input data is changed, and it is substantially through.

Then, the LPF 34 writes the data after the filter processing in the manipulator RAM 35 as the final value of the manipulator data which is digital data indicating the state of the manipulator obtained by the current scan.
In addition, reading and writing from the operation element RAM 35 by the change width control circuit 33 and the LPF 34 are performed at a predetermined address for each operation element. For this purpose, the change width limitation circuit 33 and the LPF 34 have the respective operation elements. At every timing, the serial number of the operation element may be received from the scan control unit 31, and an address signal for accessing the operation element data of the operation element may be generated based on the serial number.

  With the functions of the respective units as described above, the operation unit I / O 30 performs processing for reducing noise on the operation unit data indicating the state of the operation unit in the scan range among the operation units provided in the operation unit circuit 48. In this state, the data can be written into the operation element RAM 35 independently of the control by the CPU 11.

Next, processing related to the operation of the operator I / O 30 among processing related to the control of the integrated circuit 10 executed by the CPU 11 will be described.
First, FIG. 6 shows a flowchart of the operator I / O initialization process.
The CPU 11 starts the processing shown in FIG. 6 at an appropriate timing when the integrated circuit 10 or the acoustic signal processing device 40 is activated.

Then, the values of the parameters of the number of scan channels, the scan cycle, the waiting time, the change width, and the filter coefficient are set in the registers of the respective units in the operation unit I / O 30 (S11 to 15), and then the scan control unit 31 is set. An instruction to start scanning is issued (S16), and the process ends.
Note that the number of scan channels is N that defines the range in which the address signal is changed during scanning, the scan cycle is the scan start cycle, and the waiting time is the length of time indicated by arrow A in FIG. 4 is the change width limit value shown in FIG. 4 and the filter coefficient is the filter coefficient a shown in FIG.
Through the processing described above, it is possible to set a parameter value necessary for the operator I / O 30 and start scanning of the operator.

Next, FIG. 7 shows a flowchart of a DSP control process corresponding to the operation of the operator provided in the operator circuit 48.
The CPU 11 starts the processing shown in FIG. 7 at a timing at which the state of the operation element provided in the operation circuit 48 is detected, for example, every predetermined time.
First, the first operator among the operators provided in the operator circuit 48 is designated (S21), and then the operator data of the designated operator is read from the operator RAM 35 (S22). This data is automatically scanned by the operator I / O 30 and written in the operator RAM 35.

If the read operator data has changed since the previous read (S23), the value of the operation parameter of the DSP 12 is updated according to the operation content indicated by the change of the operator data (S24) and after the update. A coefficient corresponding to the value of the operation parameter is set in the DSP 12 (S25). For example, when it is detected that the position of the fader knob has been changed from the change in the operator data, the value of the fader parameter is updated according to the changed content, and the coefficient for causing the DSP 12 to process the fader For example, updating the value of.
The operation parameter is provided so that the parameter value can be displayed in a unit that can be easily recognized by the user. If the coefficient is simply set in the DSP 12, the value of the operator data is directly stored in a table or the like. A coefficient may be obtained by conversion.

After step S25, if there is a next operation element (S26), the operation element is designated (S27), and the process returns to step S22 to repeat the process. If all the operators have already been specified in step S26, the process is terminated.
If there is no change in step S23, there is no need to change the parameter value or the DSP 12 coefficient, and the process directly proceeds to step S26.
With the above processing, the CPU 11 can control the DSP 12 so as to perform an operation corresponding to the operation of the operation element provided in the operation element circuit 48.

In order to grasp the operation contents of the operation element provided in the operation element circuit 48, the contents of a specific address in the operation element RAM 35 may be simply read at an arbitrary timing, and the CPU 11 accesses the operation element circuit 48. It is not bound by the control of the interface. Further, since the operation element RAM 35 can be accessed at a higher speed than the external RAM 42, operation element data can be acquired quickly when necessary.
Therefore, it is possible to reduce the load on the CPU 11 required for scanning the state of the operation element. As a result, satisfactory processing performance can be obtained even if a CPU with a relatively low price and capability is provided in the semiconductor integrated circuit, and the cost of the semiconductor device and the device mounting the semiconductor integrated circuit can be reduced. Can do.

If the influence of noise in the raw digitized data after A / D conversion is reduced by the change width limiting circuit 33 and the LPF 34 in the operation element I / O 30, the CPU 11 reads the operation read from the operation element RAM 35. The child data can be used without performing noise removal processing, and the load on the CPU 11 can be reduced in this respect as well.
Note that the data indicating the state of the operation element provided in the switch / display circuit 49 can be acquired at high speed by transmitting and receiving digital signals via the parallel port 19, so that even if it is controlled by the CPU 11, it does not burden much. . Therefore, the CPU 11 directly controls the operation of the parallel port 19 to acquire data indicating the state of the operation element provided in the switch / display circuit 49.

As for access to the operation element RAM 35, writing by the LPF 34 and reading by the change width limiting circuit 33 are preferably performed at a timing that does not overlap with the access from the CPU 11.
This is because if the change width limiting circuit 33 or the LPF 34 waits for access to the operation element RAM 35, it is necessary to provide a wait circuit, and the configuration of the operation element I / O 30 becomes complicated.

  In order to prevent accesses from overlapping, for example, the access clock of the operation element RAM 35 is set to a frequency twice the operation clock of the CPU 11, and the timing at which the CPU 11 accesses the operation element RAM 35 within one clock of the CPU 11. It can be considered that the change width limiting circuit 33 and the LPF 34 access the operation element RAM 35 separately.

  Alternatively, arbitration means such as the memory I / O 13 may be provided to arbitrate access requests from the change width limiting circuit 33, the LPF 34, and the CPU 11 to the operation element RAM 35. Even in this case, if priority is given to the access requests from the change width limiting circuit 33 and the LPF 34, it is possible to prevent complication of the operator I / O 30 as in the above case. On the other hand, since the operator RAM 35 can be accessed at high speed, even if the access from the CPU 11 is kept waiting, there is no significant delay in the operation of the CPU 11.

This is the end of the description of this embodiment, but it goes without saying that the configuration and specific processing contents of the circuits and devices are not limited to those described in the above embodiment.
For example, in the above-described embodiment, an example in which an analog switch that selects and outputs one of eight inputs is used for the operator circuit 48 has been described. However, a switch that selects and outputs one of 16 inputs is described. It may be used. In this case, the scan signal SCANSW [4] is not necessary because it is only necessary to indicate which input is selected by a 4-bit address signal.

  In the above-described embodiment, the value of the parameter N is determined so that the number of operators scanned by the operator I / O 30 can be specified in groups of four operators. . However, the number of operators to be scanned may be designated in units of one operator. In addition, the function for designating the number of operators to be scanned may not be provided, and the maximum number of operators may be always scanned.

  FIG. 2 shows a configuration in which the voltage AVDD is always supplied to the 64 operators. However, this is not essential. For example, four operators in a column selected by the address signal SCANSW are used. Alternatively, the voltage may be supplied to only. In order to do this, a drive circuit capable of supplying the voltage AVDD to each column individually is provided, and to which column the voltage is supplied may be controlled by the address signal SCANSW. In that case, the analog switches of the respective operator groups 110 to 140 can be replaced with 16 diodes and one pull-up resistor.

In addition to this, the number of operators provided in the operator circuit 48 may be changed by changing the number of operators per operator group or changing the number of operator groups. It is. Further, a plurality of operation element circuits 48 or a plurality of operation element I / Os 30 may be provided. Further, the operation element circuit 48 may be a circuit that outputs a signal corresponding to the state of the operation element by means other than the variable resistor R.
Furthermore, it goes without saying that the present invention can be applied to a semiconductor integrated circuit including a DSP that processes an arbitrary signal in addition to a semiconductor integrated circuit that processes an acoustic signal.

As apparent from the above description, according to the semiconductor integrated circuit , the acoustic signal processing device or the operation device of the present invention, it is possible to reduce the load on the CPU required for scanning the state of the operation element. In addition, this can reduce the cost of the semiconductor integrated circuit, the acoustic signal processing device, or the operation device . Therefore, by applying the present invention, a low-cost semiconductor integrated circuit and an acoustic signal processing device can be provided.

It is a block diagram which shows the structure of embodiment of the acoustic signal processing apparatus of this invention provided with the integrated circuit which is embodiment of the semiconductor integrated circuit of this invention. It is a figure which shows the structure of the operation element circuit shown in FIG. 1 in detail. FIG. 2 is a diagram illustrating an example of an address signal and a select signal output from the scan control unit illustrated in FIG. 1. FIG. 2 is a diagram illustrating a configuration of a change width limiting circuit illustrated in FIG. 1. It is a figure which shows the structure of LPF shown in FIG. 3 is a flowchart of an operator I / O initialization process executed by a CPU shown in FIG. 1. It is a flowchart of DSP control processing according to operation of the operation element similarly provided in the operation element circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Integrated circuit, 11 ... CPU, 12 ... DSP, 13, 14 ... Memory I / O, 15 ... Internal RAM, 16 ... Waveform I / O, 17 ... MIDII / O, 18 ... Timer, 19 ... Parallel port, 21 ... CPU bus, 22 ... DSP bus, 30 ... operator I / O, 31 ... scan control unit, 32 ... ADC, 33 ... variation width limiting circuit, 34 ... LPF, 35 ... operator RAM, 40 ... acoustic signal processing device , 41 ... External ROM, 42 ... External RAM, 43 ... Memory bus, 44 ... ADC, 45 ... DAC, 46 ... Audio input terminal, 47 ... Audio output terminal, 48 ... Operator circuit, 49 ... Switch / display circuit

Claims (7)

An output terminal for outputting an address signal to an external operation element circuit having a plurality of operation elements; and at least one input terminal for inputting one analog signal from the operation element circuit ; a CPU; A semiconductor integrated circuit having storage means accessible from
The operation circuit receives a signal indicating a state of one operation element indicated by the address signal among the plurality of operation elements in response to the address signal supplied from the semiconductor integrated circuit via the output terminal. , A circuit that outputs the analog signal to the input terminal of the semiconductor integrated circuit,
The semiconductor integrated circuit is separate from the CPU,
Periodically, the address signal that sequentially scans each of the plurality of operators is generated and supplied to the operator circuit, thereby indicating the state of the operator sequentially indicated by the address signal to the operator circuit. A controller circuit access means for sequentially outputting the analog signals;
A signal for sequentially input through the input terminal from the operator circuit, and a converting means for sequentially converted into digital data,
The semiconductor integrated circuit, characterized in that said conversion means is sequentially converted digital data, a built-in and sequentially writes the write means in the storage means. An output terminal that outputs an address signal to an external operation element circuit having a plurality of operation element groups each including a plurality of operation elements; and an input terminal that inputs the same number of analog signals as the operation element group from the operation element circuit. A semiconductor integrated circuit including a CPU and storage means accessible from the CPU,
The operation element circuit is configured to perform one operation indicated by the address signal among the plurality of operation elements in response to the address signal supplied from the semiconductor integrated circuit via the output terminal for each of the operation element groups. A circuit that outputs a signal indicating a child state to the input terminal of the semiconductor integrated circuit as the analog signal;
The semiconductor integrated circuit is separate from the CPU,
Periodically, the address signal for sequentially scanning each of the plurality of operators is generated and supplied to the operator circuit, so that each of the operator groups sequentially indicated by the address signal is displayed on the operator circuit. Operator circuit access means for sequentially outputting the same number of analog signals as the operator group indicating the state of the operator,
Selection means for sequentially selecting the same number of analog signals as the operation element group input from the operation element circuit via the input terminal one by one while the address signal is held at a constant value;
Conversion means for sequentially converting analog signals sequentially selected by the selection means into digital data;
A semiconductor integrated circuit comprising a writing means for sequentially writing the digital data sequentially converted by the converting means into the storage means. The semiconductor integrated circuit according to claim 1 or 2 ,
Access to the storage unit by the writing unit is prioritized over access to the storage unit by the CPU or is performed at a timing that does not overlap with access to the storage unit by the CPU. Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 1 to 3 ,
The writing means has a limiting means for limiting a change width of the digital data converted by the converting means ;
The semiconductor integrated circuit according to claim 1, wherein the writing means sequentially writes the digital data, the change width of which is restricted by the restriction means, to the storage means . A semiconductor integrated circuit according to any one of claims 1 to 4 ,
The writing means has a low-pass filter for smoothing the change of the digital data converted by the converting means ;
The semiconductor integrated circuit according to claim 1, wherein the writing means sequentially writes the digital data processed by the low-pass filter into the storage means . Audio signal processing apparatus having a semiconductor integrated circuit according to any one of claims 1 to 5. An operating device comprising the semiconductor integrated circuit according to claim 1 and the operation element circuit.

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