JP4956688B2 - Head-separated camera device and video signal processing method - Google Patents

Description

  The present invention relates to a head-separated camera device, and more particularly, to a video signal processing method such as signal processing when a head (imaging unit) is removed and signal output to a subsequent stage.

  Camera devices using CMOS (Complementary Metal-oxide Semiconductor) image sensors are widely used. Today, heads, that is, those in which the imaging unit can be separated, or those in which the head is provided at a distance are widely put into practical use.

  Patent Document 1 discloses a video camera using an asynchronous FIFO.

JP 2006-191389 A

  Japanese Patent Application Laid-Open No. 2004-228561 is a head-integrated video camera that includes an asynchronous FIFO, writes an image signal to the FIFO based on a drive signal from a phase adjustment circuit of a drive processing unit, and a reference signal from a reference signal generation circuit of the drive processing unit To read from the FIFO based on the above.

  However, Patent Document 1 does not mention a structure that enables separation of the head (imaging unit) and signal processing characteristics resulting from the separation of the head.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a head-separated camera device and video signal processing capable of reducing the influence of jitter and skew caused by securing (resetting) a clock when the head is separated or delaying a signal from a head provided far away. Is to provide a method.

In embodiments, the control unit of the head-separated camera device and a control section for controlling the imaging section imaging unit are connected by a cable, comprises a signal processing circuit, and the FIFO memory, the video output circuit, the . In the signal processing circuit, the control unit performs signal processing on the video signal output from the imaging unit. FIFO memories are provided downstream of the signal processing circuit, and outputs the removing jitter from the output signal of the signal processing circuit. Video output circuit, the video signal output from said FIFO memory, and converts the normalized video signal amount of jitter allowed is defined output.

  One embodiment of the present invention provides skew and jitter characteristics due to variations in components mounted between the control unit and the imaging unit (camera head), or between the imaging unit and the control unit, and cable length. A head-separated camera system that is not affected can be obtained.

  In addition, jitter performance is improved and stable digital signals can be generated when generating standardized high-speed digital signals such as DVI and HD-SDI without requiring a large memory such as a frame memory. Become.

  Note that the reset signal to the FIFO when the imaging unit is separated is particularly useful in this embodiment.

Schematic which shows an example of a structure of the head separation type camera apparatus which can apply embodiment of this invention. Schematic which shows an example of the structure which changed the position of FIFO memory in the head separation type camera apparatus shown in FIG. The schematic diagram which shows an example of another structure which changed the position of FIFO memory in the head separation type camera apparatus shown in FIG. Schematic which shows an example of another structure which changed the position of the FIFO memory in the head separation type camera apparatus shown in FIG. FIG. 5 is a schematic diagram illustrating an example of reset (control example of MPU to FIFO and signal processing circuit with respect to state change) timing in the head-separated camera device shown in FIG. 4. In the head-separated camera apparatus shown in FIGS. 1 to 4, an outline for explaining reset timing related to switching of the output resolution and frame rate of the camera, or insertion / removal of a cable connecting the imaging unit and the control unit. Figure.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a head-separated camera device to which the present invention is applied. The element referred to as “module” below may be realized by hardware, or may be realized by software using a CPU (microcomputer) or the like.

  The head-separated camera device shown in FIG. 1 includes an imaging unit (head), that is, an imaging module 1, and a control unit (CCU), that is, a control module 11.

  The imaging module 1 includes a complementary metal-oxide semiconductor (CMOS) image sensor 3, a parallel-serial conversion circuit 5, and an LVDS (Low Voltage Differential Signaling) circuit 7 prepared in parallel with the parallel-serial conversion circuit 5.

  The control module 11 includes a main control block (MPU) 13, a serial-parallel conversion circuit 15, an LVDS (Complementary Metal-oxide Semiconductor) circuit 17, a signal processing unit 21, a clock switch (SW1) 23, a timing generator (TG), that is, A sensor drive signal generation circuit 25, an asynchronous FIFO memory 27, a transmitter (TR), that is, an output driver circuit 29, a clock switch (SW2) 31, a first clock module (CLKb) 33, and a second clock module (CLKa) 35, Including. In the first and second clock modules 33 and 35, when the oscillation frequency of the second clock module (CLKa) 35 is 60 Hz, the oscillation frequency of the first clock module (CLKb) 33 is 60 × 1000/1001 = 59. .94 Hz.

  The clock switch (SW1) 23 and the clock switch (SW2) 31 use the clock from the second clock module (CLKa) 35 or the first clock module (CLKb) 33 according to the CTRL (control) signal from the MPU 13. Whether to use the clock from is selected. The CTRL (control) signal is also supplied to the LVDS 17 on the control module 11 side, the LVDS 7 on the head (imaging module 1) side, and the parallel-serial conversion circuit 5 on the head side. CTRL is premised on using, for example, an i2c bus, a 3-wire serial bus, or the like.

  In the head-separated camera device shown in FIG. 1, the start of imaging by the sensor 3 is instructed by CLK1 (CLK) and CTRL (HS (horizontal synchronization), VS (vertical synchronization)) supplied through the LVDS 17 and LVDS 7. Video signal (Video), horizontal direction control data (HD), and vertical direction control data (VD).

  Video signals (Video), HD and VD from the sensor 3 are serially converted by the parallel-serial conversion circuit 5 and input to the serial-parallel conversion circuit 15 on the control module 11 side.

  The serial-parallel conversion circuit 15 receives the clock CLK1 selected by the clock switch (SW1) 23 (CLK1 selected from the clock CKLa35 or CLKb33 by the clock switch (SW2) 31 and the serial-parallel conversion circuit 15). The video signal (Video), HD, and VD are output to the signal processing unit 21 under one of the supplied CLK2s).

  The signal processing unit 21 writes the video signal (Video), HD, and VD to the asynchronous FIFO memory circuit (first-in first-out memory) 27 under the above-described CLK3.

  On the other hand, the video signal (Video), HD, and VD are output from the FIFO memory 27 to the transmitter (TR), that is, the output driver circuit 29, by CLK1 from the clock switch (SW2) 31. That is, the video signal (Video), HD, and VD read from the FIFO memory 27 to the transmitter (TR), that is, the output driver circuit 29, are different from CLK3 supplied to the signal processing unit 21, and the imaging unit drive signal generation CLK (clock) The switch (SW2) 31 reads the clock from one of CKLa35 and CLKb33, which is selected by CLK1). As a result, for example, the video signal (Video), HD, and VD supplied from the head (imaging unit) 1 are accompanied by a jitter component and a skew component due to the distance between the head 1 and the control module 11. Even in this case, the video output (Video out) output from the TR (output driver circuit) 29 is a video signal from which the jitter component or the skew component has been removed.

  More specifically, even in a general configuration without the FIFO memory 27, the sensor drive signal is generated by the control unit 11, and the video signal is processed in synchronization with the CLK signal returned through the imaging unit 1. The phase difference is generated as the length of the cable (wiring) between the imaging unit 1 and the control unit 11 becomes longer, but the CLK signal and the video signal returned from the imaging unit 1 are Since they are synchronized, there is an advantage that a phase difference that varies depending on the length of the cable can be dealt with by using the signal processing as it is.

  On the other hand, when the CLK signal generated by the control unit 11 is output from the control unit 11 and returns to the control unit 11 again through the imaging unit 1, the jitter component increases due to passing through a plurality of components. Become. In particular, in the head-separated camera device, serial transmission is performed by the parallel-serial conversion circuit 5 in order to reduce the number of cables when transmitting the imaged signal from the imaging unit 1 to the control unit 11, and the serial-parallel conversion circuit 15 In such a case, a PLL circuit that performs high-speed digital signal conversion processing in the parallel-serial conversion circuit 5 of the imaging unit 1 and the serial-parallel conversion circuit 15 of the control unit 11 is often used. Due to the interposition, the jitter component becomes large.

  Jitter components do not (directly) affect signal processing, but video signals such as the DVI (Digital Visual Interface) standard and SDI (Serial Digital Interface) standard that have been widely used in recent years are high-speed serial digital. It consists of differential signals, and the jitter amount is standardized for these signals. In order to satisfy this standard value, it is necessary to reduce jitter.

  Therefore, as described above, a FIFO memory circuit 27 (first-in first-out memory) is added after the signal processing unit 21, and the video signal (Video) is sent to the FIFO memory 27 with the CLK used for signal processing returned from the imaging unit. H (HD) / V (VD) signal, FLD (field period) signal indicating a video data period and DATA ENABLE (data enable) signal are written as necessary, and stable used for generating a sensor drive signal A video signal and an accompanying signal are read from the FIFO memory 27 using a CLK signal having the same frequency as the write CLK generated from the CLK signal, and the data is transmitted to an IC that converts the data into a DVI or SDI signal. As a result, a more stable CLK signal and video signal can be provided.

  FIG. 2 shows an example in which the signal processing in the head-separated camera device shown in FIG. 1 is modified. Asynchronous FIFO memory is provided before the signal processing unit 21 (between the serial-parallel conversion circuit 15 and the signal processing unit 21). An example of inserting 27 is shown. Note that the video output unit TX generally has a meaning as a transmitter, but is substantially the same as the TR (ie, the output driver circuit) shown in FIG. 1 (in the sense that the video output is transmitted to the subsequent stage). (Sometimes referred to as (TX)).

  One of the features in FIG. 2 is that CLK1 from the clock switch (SW2) 31, the first clock module (CLKb) 33, and the second clock module (CLKa) 35, which are simply shown as an oscillator, are sent to the FIFO memory 27. It is used as the reset clock RCLK. For example, when the distance between the head (imaging module) 1 and the CCU, that is, the control module 11 is large (the head 1 is provided at a position away), the video signal (Video), HD is sent to the signal processing unit 21. At the time when VD and VD are input, the jitter component and the skew component may be increased to a level that cannot be ignored. Therefore, the FIFO memory 27 is used to remove the jitter component in advance before input to the signal processing unit 21. Thus, the influence of the distance between the head 1 and the CCU 11 can be reduced from the video signal output to the subsequent stage. Also in this case, the CLK signal to be written to the FIFO memory 27 is a CLK signal after serial-parallel conversion, and the CLK to be read is a transmitter (clock switching) generated on the control unit side with a CLK signal having the same frequency as the CLK signal. (CLK1 from the clock (SW2) 31, the first clock module (CLKb) 33, and the second clock module (CLKa) 35).

  FIG. 3 shows an example in which the head-separated camera apparatus shown in FIG. 2 is a three-plate type imaging system (a system in which the head uses independent CMOS sensors for the respective color components of R, G, and B). .

  That is, in a three-plate imaging system (a system in which the head uses independent CMOS sensors for the respective color components of R, G, and B), in addition to the distance between the head 1 and the CCU 11, In particular, the asynchronous FIFO memory 27 is located in the preceding stage of the signal processing unit 21 (between the serial-parallel conversion circuit 15 and the signal processing unit 21), and the signal processing unit 21 It is beneficial to previously remove jitter components and skew components from the video signal input to.

  That is, in a system that receives a plurality of sensors and a plurality of serialized LVDS signals, the FIFO memory 27 is added to the input side of the signal processing of each channel, thereby causing a skew between channels that occurs when the cable is long. While the timing is shifted, signal processing can be performed at a constant timing, so that jitter and skew are reduced.

  FIG. 4 shows an example in which the signal processing in the head-separated camera device shown in FIG. 1 is further modified, and the first stage of the signal processing unit 21 (between the serial-parallel conversion circuit 15 and the signal processing unit 21) is the first. PLL (Phase Loop Lock) circuit 37 and second PLL (Phase Loop Lock) circuit 39 are provided, and one of Xtal1 (corresponding to CKLa) 35 or Xtal2 (reverse of Xtal1) 33 is controlled by a clock switch (SW2) 31. From the selected clock (supplied to TG25, PLL (1) 37, PLL (2) 39) and a clock switch (SW1) 23 provided in the previous stage of the signal processing unit 21, for example, a head (imaging unit) ) Even in the no signal (no clock) state when 1 is disconnected, the video output (Video), HD, and VD (H / V) are stabilized in the subsequent stage. It is beneficial in order to output.

  More specifically, in the head-separated camera system, a no-signal state occurs when the cable is disconnected. There are also camera systems that can capture images at a plurality of resolutions. As described above, when the output resolution and frame rate of the camera are switched, or when the cable connecting the imaging unit 1 and the control unit 11 is inserted or removed, the drive timing of the sensor (head 1) changes. For this reason, the CLK signal received by the control unit temporarily becomes unstable, there is a possibility that the FIFO memory 27 malfunctions, the frequency of the write CLK to the FIFO memory 27 and the frequency of the read CLK are disturbed, and an empty or overflow state may occur. .

  For this reason, a correct video signal may not be read from the FIFO memory 27 after such an operation is performed, and there is a possibility that the video is lost, for example, a driver IC for DVI or SDI output malfunctions.

  Here, as described above, the RESET signal is provided to the PLL circuits (1) and (2) for the CLK signal, and the signal output indicating the LOCK state is provided from the PLL circuits (1) and (2). Thereafter, the FIFO memory 27 is reset using a signal indicating the LOCK state of the oscillator (the output of Xtal (1) 35 or Xtal (2) 33 via SW (2) 31).

  As a result, for the frequency disturbance occurring at the time of switching the resolution and the frame rate and the period of the temporary no signal state due to the cable insertion / extraction, the FIFO memory 27 is set in the RESET state to stop the video output, and the PLL circuits (1), ( When 2) becomes stable, the RESET of the FIFO memory 27 is canceled and the output of the video signal is resumed.

  FIG. 5 shows a control example of the FIFO and the signal processing circuit from the MPU for the state change described in FIG. The main part (of FIG. 4) is extracted and described in FIG. 5, but the reset signal RST is supplied from the CLKi (internal clock), that is, the PLL (1) 37 to the FIFO 027 according to the cable state (whether or not the head is removed). As described above, by setting (fixing) the procedure of CLK supplied by the microcomputer (the host I / F or GPIO shown in FIG. 4 or the MPU 13 shown in FIG. 1), the CLKe input to the PLL 2 on the camera head side cannot be detected. Even if it is not stable, a stable operation can be obtained (see FIG. 5A).

  Further, as shown in FIG. 5B, the microcomputer (the host I / F shown in FIG. 4 or the host I / F shown in FIG. The step of selecting CLK from GPIO or MPU 13 in FIG. 1 becomes unnecessary. In the example of FIG. 5B, according to the attachment / detachment of the cable (from the head 1 side) (presence / absence of separation (removal) of the camera head), for example, without head: using PLL2 / with head: not using PLL2. Will be switched.

  That is, when RESET (reset) is executed, the operation is switched to the operation with a stable internal CLK (drive signal generation CLK), and then the PLL is reset (reset). Each setting is performed, the path of the internal circuit is determined, and the PLL circuit is reset again. Thereby, when the PLL circuit is stabilized, a signal indicating the LOCK state is output, and the FIFO memory 27 starts normal operation regardless of the presence or absence of the imaging unit (head) 1 and the setting, and the video signal (Video), HD, The output of VD is resumed.

  An example is shown in FIG. 6, but resetting from the MPU 13 with the presence or absence of the camera head 1 (HEAD DETECT <<< imaging unit (with HEAD → without) >>), <<< imaging unit (without HEAD → with) >>), << Frame rate (FRAME RATE) switching >>, << Resolution (RESOLUTION) switching >>, << Scanning mode (IP MODE) switching >> are notified via a control signal, and in response to this, internal The RESET processing of the PLL circuits (1) and (2) can be performed by switching the CLK signal and video signal paths of the circuit and performing RESET (reset) control from the outside.

  More specifically, in FIG. 6, in the case of HEAD DETECT <<< image pickup unit (with HEAD → no) >>, switching to the internal CLK ([11]), PLL reset ([12]), PLL stabilization wait ([ 13]), following the PLL stabilization ([14]) process, the RESET of the FIFO memory 27 may be canceled and the output of the video signal (Video), HD, and VD may be resumed.

  For HEAD DETECT <<< image pickup unit (without HEAD → present) >>>, after switching to internal CLK ([21]), PLL reset ([22]), RESOLUTION (resolution) setting ([23]) , FRAME RATE (frame rate) setting ([24]), IP MODE (scanning mode) setting ([25]), PLL reset ([26]), PLL stabilization wait ([27]), PLL stabilization Subsequent to the processing of ([28]), the reset of the FIFO memory 27 may be canceled and the output of the video signal (Video), HD, and VD may be resumed.

  For <<<< frame rate (FRAME RATE) switching >>, <<< resolution (RESOLUTION) switching >>> or << scanning mode (IP MODE) switching >>, HEAD DETECT <<< image pickup unit (without HEAD → yes) ) >> is substantially the same as the procedure in which a part of it is omitted, and detailed description thereof is omitted.

  As described above, by applying one embodiment of the present invention, it is possible to output a stable digital signal by absorbing skew and jitter caused by variations in parts and cables, so that DVI, HD-SDI, etc. Jitter at the time of generating a high-speed digital signal is improved, and a stable digital signal can be generated.

  Further, it is possible to realize a head-separated camera device that can reduce the influence of jitter and skew caused by securing (resetting) a clock when the head is separated or a signal delay from a head provided far away.

  In addition, jitter performance is improved and stable digital signals can be generated when generating standardized high-speed digital signals such as DVI and HD-SDI without requiring a large memory such as a frame memory. Become.

  In addition, this invention is not limited to each embodiment mentioned above, A various deformation | transformation or change is possible in the range which does not deviate from the summary in the stage of the implementation. In addition, the embodiments may be implemented by appropriately combining them as much as possible, or by deleting a part thereof, and in that case, various effects resulting from the combination or deletion can be obtained.

  DESCRIPTION OF SYMBOLS 1 ... Imaging module (head / camera), 3 ... CMOS (Complementary Metal-oxide Semiconductor) image sensor, 5 ... Parallel-serial conversion circuit, 7 ... LVDS (Low Voltage Differential Signaling) circuit, 11 ... Control (CCU) module, DESCRIPTION OF SYMBOLS 13 ... Main control block (MPU), 15 ... Serial-parallel conversion circuit, 17 ... LVDS circuit, 21 ... Signal processing part, 23 ... Clock switcher (SW1), 25 ... Timing generator (sensor drive signal generation circuit), 27 Asynchronous FIFO memory, 29 Transmitter (output driver circuit), 31 Clock selector (SW2), 33 First clock module (CLKb / Xtal1), 35 Second clock module (CLKa / Xtal1), 37 PLL (Phase Loop Lock) circuit (1), 39 ... PLL times Road (2).

Claims (23)

In head-separated camera device and a control section for controlling the imaging section imaging unit are connected by a cable,
The control unit includes a signal processing circuit that performs signal processing on the video signal output from the imaging unit;
Provided after the signal processing circuit, a FIFO memory for outputting to remove jitter from the output signal of said signal processing circuit,
The video signal output from said FIFO memory, and a video output circuit for converting the normalized image signal jitter is defined to allow,
A head-separated camera device comprising: The imaging unit includes an image sensor and a first conversion circuit that serially converts the output of the image sensor,
Wherein, the first conversion circuit is a signal head separation camera apparatus according to claim 1, further comprising a second conversion circuit for parallel conversion of feed. Wherein, the specific operating conditions head separation camera apparatus according to claim 1, wherein the PLL circuit that supplies a reset signal before Symbol F IFO memory provided in front of the F IFO memory when that occurred. The PLL circuit includes a head separation type camera device of the 請 Motomeko 3 wherein you output a reset signal if it becomes LOCK state. The specific operating conditions, the head separated type camera apparatus according to claim 3, wherein connection of the image pickup unit is a no-signal state caused by cut.   The head-separated camera device according to claim 3, wherein the specific operation state is switching of an output resolution or a frame rate of the imaging unit. The head-separated camera device according to claim 2, wherein the image sensor includes two or more image sensors . In head-separated camera device and a control section for controlling the imaging section imaging unit are connected by a cable,
Wherein,
A PLL circuit for supplying a reset signal when a predetermined timing or a specific operation state occurs;
And F IFO memory that controls the timing of the image pickup signal output from the imaging unit,
A signal processing circuit for performing signal processing on a video signal output from the FIFO memory;
The video signal output from the signal processing circuit, and a video output circuit for converting the normalized image signal jitter is defined to allow,
A head-separated camera device comprising: The imaging unit includes an image sensor and a first conversion circuit that serially converts the output of the image sensor,
Wherein the control unit, the head separation camera apparatus according to claim 8, wherein the first conversion circuit comprises a second conversion circuit for parallel conversion signals to supply. Wherein, when a predetermined timing or specific operating condition occurs, before Symbol F IFO head separation camera memory said PLL circuit for supplying a reset signal to the F IFO claim 8, wherein provided upstream of the memory apparatus. The PLL circuit includes a head separation type camera device of the 請 Motomeko 10 wherein you output a reset signal if it becomes LOCK state. The specific operating conditions, the head separated type camera apparatus according to claim 10, wherein the connection of the image pickup unit is a no-signal state caused by cut. The head-separated camera device according to claim 10 , wherein the specific operation state is switching of an output resolution or a frame rate of the imaging unit. 11. The head-separated camera device according to 10, wherein the image sensor includes two or more image sensors. In a video signal processing method for a head-separated camera device in which an imaging unit and a control unit that controls the imaging unit are connected by a cable.
Perform predetermined signal processing on the video signal output from the imaging unit by a signal processing circuit,
Jitter is removed by temporarily storing and reading out the video signal in a FIFO memory,
A video signal processing method for converting a video signal from which jitter has been removed into a standardized video signal in which an allowable amount of jitter is determined and outputting the signal. The video signal processing method according to claim 15, wherein when a specific operation state is detected in a stage before removing jitter, a reset signal is supplied to reset the PLL circuit. The video signal processing method according to claim 15, wherein the reset signal is output when the PLL circuit is in a LOCK state. The video signal processing method according to claim 16, wherein the detection of the specific operation state is detection of a no-signal state caused by disconnection of the image sensor. The video signal processing method according to claim 16, wherein the detection of the specific operation state is detection of switching of an output resolution or a frame rate of an image sensor. In a video signal processing method for a head-separated camera device in which an imaging unit and a control unit that controls the imaging unit are connected by a cable.
When a predetermined timing or a specific operation state is detected, a reset signal is supplied from the PLL circuit,
Jitter is removed by temporarily storing and reading out the video signal output from the imaging unit in a FIFO memory;
The signal processing circuit performs signal processing on the video signal output from the FIFO memory,
A video signal processing method for converting and outputting a video signal signal-processed by the signal processing circuit into a standardized video signal in which an allowable jitter amount is determined. 21. The video signal processing method according to claim 20, wherein the reset signal is output when the PLL circuit is in a LOCK state. 21. The video signal processing method according to claim 20, wherein the detection of the specific operation state is detection of a no-signal state caused by disconnection of the image sensor. 21. The video signal processing method according to claim 20, wherein the detection of the specific operation state is detection of switching of an output resolution or a frame rate of an image sensor.

Images