JP4956014B2 - Semiconductor light emitting element and light emitting device - Google Patents

Description

  The present invention relates to a light emitting element and a light emitting device, and more particularly to a semiconductor light emitting element and a light emitting device using a semiconductor material.

  Semiconductor light emitting elements are widely used in display devices, illumination devices, recording devices, and the like. In particular, semiconductor light emitting diodes (LEDs) that do not use stimulated emission are used as display devices because of their high luminance. As a recent new application, an attempt has been made to use an LED and a phosphor layer in combination as an illumination device (see, for example, Patent Document 1). This publication discloses a phosphor laminated structure in which two types of phosphor layers are laminated on a semiconductor light emitting element such as an LED so as to enhance color rendering, and a white light emitting device using the same. In the phosphor layer of the light emitting device, a diffusing agent, a binder resin, and a phosphor are adjusted and blended. Thereby, luminous efficiency is increased and deterioration of the phosphor layer is suppressed.

  In the light emitting device and the like described in the above publication, in a lighting device in which an LED and a phosphor layer are combined, the brightness and brightness of the lighting device are improved by devising the material and structure of the phosphor layer. The technique is not sufficient for use as a lighting device. The reason will be described below.

Compared with existing light bulbs, LEDs are superior in terms of efficiency and low heat generation, so replacement of existing light bulbs will be promoted in the future by combining LEDs with high-luminance phosphor layers. On the other hand, compared with fluorescent lamps that are widely used as lighting devices, LEDs still have many problems in terms of efficiency, heat generation, and operating power supply, and even if a high-luminance phosphor layer is used, it is enough to replace fluorescent lamps. Actually, it is difficult to obtain excellent luminous efficiency (luminous efficiency with respect to input power).
JP 2004-179644 JP

  As described above, conventional LEDs are not sufficient in terms of efficiency, heat generation, and operation power supply, and it is difficult to obtain excellent luminous efficiency enough to replace fluorescent lamps widely used as lighting devices. is there.

  According to one aspect of the present invention, a laminated portion including a light emitting layer made of a semiconductor, and first and second cladding layers made of a semiconductor provided with the light emitting layer interposed therebetween, and a lamination direction of the laminated portion A pair of first high reflection layers that have a high reflectivity with respect to the light generated in the light emitting layer provided in the first direction orthogonal to the first direction, and the first direction orthogonal to the stacking direction A low-reflection layer and a second high-reflection layer, each having a low reflectance and a high reflectance with respect to the light generated in the light-emitting layer provided across the light-emitting layer in the intersecting second direction, A featured semiconductor light emitting device is provided.

  According to another aspect of the present invention, a mounting substrate having a heat sink and a semiconductor light emitting element attached to the heat sink are provided. The semiconductor light emitting element has a light emitting layer made of a semiconductor and sandwiches the light emitting layer. And a light generated in the light emitting layer sandwiched between the light emitting layers in a first direction orthogonal to the stacking direction of the stacked portions. A pair of first high reflection layers having a high reflectance with respect to the light generated in the light emitting layer provided between the light emitting layers in a second direction perpendicular to the stacking direction and intersecting the first direction A low-reflection layer and a second high-reflection layer each having a low reflectance and a high reflectance, and the stacking direction of the stacked portion is relative to the surface of the heat sink on which the semiconductor light emitting element is disposed. Parallel A semiconductor light emitting device is provided.

  According to one aspect of the present invention, there is provided a stacked portion including a light emitting layer made of a semiconductor and first and second cladding layers made of a semiconductor provided with the light emitting layer interposed therebetween on a semiconductor substrate. Forming a plurality of resist patterns having the same size on the upper surface of the stacked portion, and forming an electrode or an insulation formed by the resist pattern along a first direction that is a cleavage direction of the semiconductor substrate. A first cleaving step in the direction in which the body openings are arranged, and a pair of first crests having high reflectivity with respect to the light generated in the light emitting layer on two opposing surfaces obtained by the first cleaving Forming a highly reflective layer, performing a second cleavage between the two adjacent electrodes or the insulator openings along a second direction intersecting the first direction, and the second Obtained by cleavage Forming a low reflection layer and a second high reflection layer each having a low reflectance and a high reflectance with respect to the light generated in the light emitting layer, on the two facing surfaces. An element manufacturing method is provided.

  According to one aspect of the present invention, there is provided a stacked portion including a light emitting layer made of a semiconductor and first and second cladding layers made of a semiconductor provided with the light emitting layer interposed therebetween on a semiconductor substrate. Forming a plurality of resist patterns having the same size on the upper surface of the stacked portion, and forming an electrode or an insulation formed by the resist pattern along a first direction that is a cleavage direction of the semiconductor substrate. A step of performing a first cleavage in a direction in which the body openings are arranged, and two opposing surfaces obtained by the first cleavage have a low reflectance and a high reflectance with respect to light generated in the light emitting layer, respectively. Forming a low-reflection layer and a first high-reflection layer, and performing a second cleavage between the two adjacent electrodes or the insulator openings along a second direction intersecting the first direction. And performing the step Forming a pair of second highly reflective layers having high reflectivity with respect to light generated in the light emitting layer on two opposing surfaces obtained by cleavage of 2; An element manufacturing method is provided.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor light-emitting element and a light-emitting device having high luminous efficiency with respect to input power.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a perspective view showing the configuration of the semiconductor light emitting device according to the first embodiment of the present invention. The semiconductor light emitting device shown in FIG. 1 includes a rectangular parallelepiped GaN-based compound semiconductor chip. This chip includes a p-type GaN contact layer 103 doped with Mg, a p-type Al _0.05 Ga _0.95 N cladding layer 104 doped with Mg, and a P-type Al _0.2 Ga _0.8 N overflow prevention layer 105 doped with Mg. An undoped GaN guide layer 106, an active layer 107 made of multiple quantum wells (MQW) with a well layer of ln _0.2 Ga _0.8 N and a barrier layer of ln _0.03 Ga _0.97 N, and an n-type GaN doped with Si The guide layer 108, the Si-doped n-type Al _0.05 Ga _0.95 N clad layer 109, and the Si-doped n-type GaN contact layer 110 are sequentially stacked.

  A P-side electrode 102 is connected to the P-type GaN contact layer 103, and an n-side electrode 101 is connected to the n-type GaN contact layer 110. The p-side electrode 102 is disposed along two surfaces of the chip, and the n-side electrode 101 is also disposed along two surfaces of the chip. The shape on the surface A side of the n-side electrode 101 is a rectangular shape as shown by the solid line. The comb shape indicated by the dotted line in the n-side electrode 101 will be described later.

  A plurality of surfaces (four surfaces A, B, C, D excluding the surface provided with the n-side electrode 101 and the surface provided with the p-side electrode 102) of the GaN-based compound semiconductor chip shown in FIG. Either a reflective layer or a low reflective layer is provided. 2A is a side view seen from the n-side electrode 101 side (E direction), and FIG. 2B is a side view seen from the p-side electrode 102 side (F direction).

  As shown in FIG. 2A, a low-reflection layer 203 is provided on the A-side surface of the GaN-based compound semiconductor chip, and a high-reflection layer 202 is provided on the B-side surface. High reflection layers 201b and 201a are provided on the C-side surface and the D-side surface, respectively. These high reflection layers 201b, 201a, and 202 and the low reflection layer 203 are omitted in FIG.

The low reflection layer 203 is made of a dielectric multilayer film or the like, and for example, SiO ₂ , SiN, Al ₂ O _3, or the like can be used. The reflectance of the low reflective layer 203 in this embodiment is, for example, 10%. The highly reflective layers 201b, 201a, and 202 are made of a dielectric multilayer film or the like, and for example, a laminated film in which TiO ₂ / SiO ₂ is repeatedly formed can be used. The film thickness of each of TiO ₂ and SiO ₂ is a thickness corresponding to 1/4 of the center wavelength of the light emitting layer (active layer 107). The number of repetitions can be, for example, a total of 10 pairs, but is not limited thereto. In the present embodiment, the reflectance of the highly reflective layer is, for example, 99%.

The high reflection layers 201a and 201b described above are the first layers orthogonal to the stacking direction of the stacked portion including the active layer 107, the n-type Al _0.05 Ga _0.95 N cladding layer 109, and the p-type Al _0.05 Ga _0.95 N cladding layer 104. It is disposed on both end faces in the direction (direction connecting C and D), and has a high reflectance with respect to light generated in the active layer 107.

  The low reflection layer 203 and the high reflection layer 202 described above are provided on both end faces across the active layer 107 in the second direction (direction connecting A and B) perpendicular to the stacking direction and intersecting the first direction. The light generated in 107 has a low reflectance and a high reflectance, respectively.

When a current is passed through the semiconductor light emitting device of FIG. 1, a waveguide structure is formed by the n-type Al _0.05 Ga _0.95 N clad layer 109 and the p-type Al _0.05 Ga _0.95 N clad layer 104, and light can be confined in the active layer 107. In addition, light can be resonated by the pair of high reflection layers 201a and 201b having high reflectivity. Since the active layer 107 has gain, it is possible to suppress light absorption due to light emitted from the active layer 107 crossing the active layer 107 again by internal reflection (multiple reflection).

  At this time, since the low reflection layer 203 and the high reflection layer 202 are provided so that light can be extracted in a direction intersecting the oscillation direction, the light emitted from the active layer 107 is extracted to the outside through the low reflection layer 203. As a result, the luminous efficiency of the device can be increased by a factor of about two.

  In the semiconductor light emitting device of this embodiment, the length in the direction (depth direction in FIG. 1, that is, the first direction) perpendicular to both the stacking direction and the second direction (direction connecting A and B) is It has an element shape longer than the length in the direction perpendicular to both the direction and the first direction (the direction connecting C and D) (the vertical direction in FIG. 1, ie, the length in the second direction). In the case of this element shape, the sectional area of the active layer 107 in the plane perpendicular to the second direction is larger than the sectional area of the active layer 107 in the plane perpendicular to the first direction. Therefore, the area of the light emitting region in the light emission direction of the element is larger than the cross-sectional area in the direction perpendicular to the radiation direction, and the length in the first direction is longer than the length in the second direction Because of the shape, even when the reflectivity is not sufficient, the oscillation threshold current is reduced, and the light emission efficiency with respect to the input power can be improved.

Furthermore, a normal laser requires a region where a wire is connected to the n-side electrode and the p-side electrode, and only a limited portion of the element is a light emitting region. According to the semiconductor light emitting device of this embodiment, the light emitting area occupied in the device can be made much larger, and the device chip can be used effectively. For this reason, the number of elements obtained from one wafer can be improved by about 20 times. .
Further, by making the reflectivity of the highly reflective layers 201a and 201b be 80% or more, preferably 95% or more, respectively, with respect to the light generated in the active layer 107, the oscillation threshold current is reduced, and the luminous efficiency with respect to the input power is reduced. Can be improved. Further, when the reflectance of the low reflection layer 203 is 10% or less with respect to the light generated in the active layer 107, the light extraction efficiency can be improved, and the light emission efficiency with respect to the input power can be improved.

  In addition, since the n-side electrode 101 that supplies current to the active layer 107 is in contact with a surface (surface A) parallel to the stacking direction of the stacked portion of the n-type GaN contact layer 110, a wide contact area on the parallel surface Can be ensured. Thereby, the contact resistance of the metal semiconductor interface can be lowered, and the operating voltage of the element can also be lowered.

  Here, when the p-side electrode 102 is in contact with a surface (surface B) parallel to the stacking direction of the stacked portion of the p-type GaN contact layer 103, the operating voltage of the element can be similarly lowered. In the present embodiment, since the length of the stacked portion in the stacking direction has an element shape longer than the length in the first and second directions described above, it is extremely easy to obtain a wide contact area.

  Furthermore, in the semiconductor light emitting device of this embodiment, since the n-side electrode 101 and the p-side electrode 102 are in contact with the device over a larger area than a normal edge emitting laser, heat dissipation is good and the current density is increased. Can do.

  Next, a method for manufacturing the semiconductor light emitting device of this embodiment will be described. FIG. 3 is a perspective view showing a method for manufacturing the semiconductor light emitting device of this embodiment.

First, an n-type GaN substrate is placed in a crystal growth apparatus. This n-type GaN substrate functions as an n-type GaN contact layer 110 doped with Si. By crystal growth using this MOCVD method on this n-type GaN substrate, a Si-doped n-type Al _0.05 Ga _0.95 N cladding layer 109, a Si-doped n-type GaN guide layer 108, and a well layer are formed as In. Active layer 107 consisting of multiple quantum wells (MQW) with _0.2 Ga _0.8 N and barrier layer In _0.03 Ga _0.97 N, undoped GaN guide layer 106, and Mg-doped p-type AI _0.2 Ga _0.8 N to prevent overflow A layer 105, a p-type Al _0.05 Ga _0.95 N cladding layer 104 doped with Mg, and a p-type GaN contact layer 103 doped with Mg are formed in this order.

Next, the n-type GaN substrate on which such crystal growth has been performed is taken out of the crystal growth apparatus, and an SiO ₂ film 401 is laminated on the p-type GaN contact layer 103 as shown in FIG. 3A.

Next, a resist pattern on the surface of the SiO ₂ film 401 by patterning the SiO ₂ film 401 by using the resist pattern, the column an opening comprising a rectangular 5 [mu] m × 80 [mu] m in the SiO ₂ film 401 on the vertical and horizontal Set up. The pitch of the plurality of openings adjacent in the longitudinal direction of the openings is 100 μm, and the pitch of the plurality of openings adjacent in the short side direction is 10 μm. For removing the SiO ₂ film 401, ammonium fluoride is used.

  Next, as shown in FIG. 3B, scribe lines are formed on the surface of the n-type GaN substrate along the direction in which the openings are arranged. For example, the <11-20> direction is used as the cleavage direction. The scribe line is performed while observing the surface of the P-type GaN contact layer 103 so that cleavage can be performed while avoiding the opening on the P-type GaN contact layer 103. Cleaving along the cleavage plane using the scribe line as a starting point, and separating into a plurality of bar-like bodies 402. The width along the short side of the bar-shaped body 402 (the width along the longitudinal direction of the opening) is 100 μm.

Next, as shown in FIG. 3C, in this state, a dielectric multilayer film 403 is deposited on the cleaved surface as the highly reflective layers 201b and 201a. The dielectric multilayer film 403 is laminated with a total of 10 pairs by repeating TiO ₂ / SiO ₂ . The reflectance of the dielectric multilayer film 403 is 99% or more with respect to the emission wavelength. During the deposition of the dielectric multilayer film 403, the thickness of each layer is adjusted so that the thickness corresponds to 1/4 of the center wavelength of the light emitting layer (active layer 107). This vapor deposition is performed on the cleaved surfaces on both sides of the bar-like body 402.

  Next, as shown in FIG. 3D, the bar-like body 402 is braked in the short direction to produce one element chip 404. Here, it is performed while observing the surface of the P-type GaN contact layer 103 so as to avoid the opening on the P-type GaN contact layer 103 and perform cleavage. The width of the element chip 404 (the width along the short direction of the opening) is 10 μm.

  Thus, by manufacturing the element chip 404 by cleavage, the volume per element can be reduced, and one wafer can be used effectively, yield can be improved, and cost can be reduced.

Next, in this state, the element chips 404 are arranged and fixed on a support substrate or a support base so that the stacking direction is horizontal. Further, as shown in FIG. 3E, a dielectric multilayer film 405 is deposited as a highly reflective layer 202 on one of the cleavage planes. The dielectric multilayer film 405 is laminated with a total of 10 pairs by repeating TiO ₂ / SiO ₂ . The reflectance of the dielectric multilayer film 405 is 99% or more with respect to the emission wavelength. During the deposition of the dielectric multilayer film 405, the thickness of each layer is adjusted so that the thickness corresponds to 1/4 of the center wavelength of the light emitting layer (active layer 107).

  Next, as shown in FIG. 3F, a metal film 406 is deposited as the P-side electrode 102 from the opening on the P-type GaN contact layer 103 to the surface on which the dielectric multilayer film 405 is formed. Here, in order to increase the contact area between the P-side electrode 102 and the P-type GaN contact layer 103, an opening is also provided on the surface of the P-type GaN contact layer 103 where the dielectric multilayer film 405 is formed. It is also possible to form the metal film 406 so as to embed the portion. The metal film 406 is patterned as necessary.

Next, as shown in FIG. 3G, the element chip 404 is transferred to another support substrate or support base, and the element chip 404 is placed so that the surface on which the dielectric multilayer film 405 is laminated is in contact with the support substrate or support base. Are fixed side by side. Further, as shown in FIG. 3G, a dielectric film 407 is deposited as a low reflection layer 203 on the opposite cleavage surface. For example, SiO ₂ is laminated as the dielectric film 407. The reflectance of the dielectric film 407 is 10% or less with respect to the emission wavelength. During the deposition of the dielectric film 407, the film thickness is adjusted so as to have a thickness corresponding to half the center wavelength of the light emitting layer (active layer 107).

Thereafter, an opening is formed on the surface of the n-type GaN contact layer 110 where the dielectric film 407 is formed (a surface parallel to the stacking direction of crystal growth). For removing the dielectric film (SiO ₂ film) 407, ammonium fluoride is used. Next, as shown in FIG. 3H, a metal film 408 is embedded as an n-side electrode 101, an opening exposing the n-type GaN contact layer 110 is embedded, and the surface provided with this opening (in the stacking direction of crystal growth). A metal film 408 is deposited over a plane adjacent to the (parallel plane) (a plane perpendicular to the stacking direction of crystal growth). A relatively large opening can be provided on the surface of the n-type GaN contact layer 110 where the dielectric film 407 is formed (a surface parallel to the stacking direction of crystal growth), and the n-side electrode 101 and the n-type GaN contact layer The contact area with 110 can be increased.

  Next, in order to prevent the active layer 107 from being covered with the metal film 408, the metal film 408 is patterned. As a patterning method, for example, a lift-off method is used. A resist pattern is formed on a region including the active layer 107 and the like, and after the metal film 408 is deposited, the resist pattern is removed with an organic solvent or the like. Can be patterned.

  As described above, in the first embodiment, after the light emitted from the active layer 107 is reciprocated in the first direction to increase the light intensity, the light can be extracted to the outside through the low reflection layer 203. Improvement can be achieved. In addition, since the cross-sectional area of the active layer in the second direction, which is the light emission direction, is larger than the cross-sectional area of the active layer in the first direction perpendicular to the light emission direction, the light emission efficiency can be further improved.

  Furthermore, since the n-side electrode 101 is in surface contact with the n-type contact layer 110 and the p-side electrode 102 is also in surface contact with the p-type GaN contact layer 103, the contact resistance can be lowered and the operating voltage of the element can be lowered. Can do. Further, since the n-side electrode 101 and the p-side electrode 102 are in contact with the element over a wide area, the heat dissipation is improved and the current density can be increased.

(Second embodiment)
FIG. 4 is a cross-sectional view showing a configuration of a light emitting device according to the second embodiment of the present invention. In the present embodiment, a light emitting device in which the semiconductor light emitting element of FIG. 1 is mounted on a heat sink will be described. As shown by a solid line in FIG. 4, a heat sink 302 is disposed in one area on the upper surface of the v-mount substrate 301, and a heat sink 305 is disposed in another area on the upper surface of the mount substrate 301 via an insulator 304. Has been. The heat sinks 302 and 305 are made of a conductor. However, the heat sinks 302 and 305 are insulated from each other.

  The semiconductor light emitting device shown in FIG. 1 is arranged on the heat sink 302 via the solder 303 so that the surface on which the highly reflective layer (dielectric multilayer film) 202 is laminated faces the heat sink 302. The solder 303 electrically connects the portion of the p-side electrode 102 extending on the dielectric multilayer film 202 and the heat sink 302.

  Further, solder 306 is formed between the n-side electrode 101 and the heat sink 305, and the n-side electrode 101 and the heat sink 305 are electrically connected by the solder 306. Instead of the solder 306, an electrical connection may be made using an Au wire. Reference numeral 307 denotes a power source that applies a voltage between the heat sink 302 and the heat sink 305. With this configuration, a voltage is applied between the n-side electrode 101 and the p-side electrode 102.

  According to the light emitting device of the second embodiment, the same effects as those described in the first embodiment can be obtained, and the n-side electrode 101 and the p-side electrode 102 that are in contact with the element over a wide area can be obtained. The heat can be released to the heat sink 305 and the heat sink 302 through the solder 306 and the solder 303, respectively. For this reason, the heat dissipation can be further improved, the temperature characteristics and reliability of the element can be improved, and operation at a high output becomes possible. In particular, the active layer 107 that generates a large amount of heat and the p-side electrode 102 can be positioned in the vicinity of the heat sink 302, thereby significantly improving the heat dissipation efficiency and enabling stable operation with high output.

(Third embodiment)
The third embodiment relates to a light emitting device that emits white light, and is an example of an illumination device that replaces a fluorescent lamp or the like. The configuration of this apparatus will be described with reference to FIG. As shown in FIG. 4, in the light emitting device of the present embodiment, in addition to the structure of the second embodiment (solid line portion in FIG. 4), members indicated by dotted lines are added. 510 is a plastic cell, and the semiconductor light emitting device shown in FIG. A phosphor layer 511 is embedded in the cell 510 on the semiconductor light emitting device, and a light extraction window 512 is provided so as to cover the phosphor layer 511.

The phosphor layer 511 is a layer in which a red phosphor, a green phosphor, and a blue phosphor are dispersed in a fluoropolymer. Red phosphors include La ₂ O ₂ S: Eu, Sm (elements after: indicate active elements; the same shall apply hereinafter), and green phosphors include lnGaN and BaMgAl ₂₇ O ₁₇ : Eu, Mn As the blue phosphor, lnGaN, (Sr, Ca, Ba) ₁₀ (PO ₄ ) ₆ Cl ₂ : Eu, or the like is used. The phosphors of these colors are excited by the light emitted from the semiconductor light emitting element to emit light, and white light can be obtained by superimposing the light emission of the phosphors of the respective colors. It is also possible to use a yellow phosphor instead of or in combination with the green phosphor. For example, (Sr, Ca, Ba) ₂ SiO ₄ : Eu or the like is used.

  The cell 510 is plastic here, but may be made of metal, ceramic, or glass. In that case, the light-emitting device has good heat dissipation and little deterioration, and provides a light-emitting device with high output and high reliability. be able to. In addition, the phosphor may be in contact with the semiconductor light emitting element, may be outside the cell 510, or may be intermediate between them.

  According to the light emitting device according to the third embodiment, in addition to obtaining the same effects as those of the first and second embodiments, it is possible to obtain a white light emitting device with excellent color rendering and high luminous efficiency. Can do. For this reason, a novel illumination system that can replace the conventional fluorescent lamp can be realized.

(Fourth embodiment)
In the fourth embodiment, in the semiconductor light emitting device of FIG. 1, instead of the n-type Al _0.05 Ga _0.95 N cladding layer 109, the thickness of each layer is AIGaN / GaN equivalent to 1/4 wavelength in terms of the optical path length of the emission wavelength. A laminated structure is used.

5A and 5B are diagrams showing the refractive index distribution of the n-type cladding layer. The horizontal axis represents the position in the film thickness direction, and the vertical axis represents the refractive index. As shown in FIG.5B, the n-type cladding layer is a laminate in which Al _0.3 Ga _0.7 N layers (503, 504) and GaN layers, which are equivalent to the thickness of the quarter wavelength in the optical path length of the emission wavelength, are alternately laminated. It has a structure. With this structure, the amount of light leaking from the active layer 107 to the n-type GaN substrate side (n-type GaN contact layer 110 side) can be reduced, and the light emission efficiency can be improved.

Here, as shown in FIG. 5A, the Al _0.3 Ga _0.7 N layer (503, 504) of FIG. 5B is composed of Al _0.65 Ga _0.35 N and GaN superlattices (501, 502), respectively, and the refractive index distribution is 2 You may make it have a heavy period. Here, the thicknesses of Al _0.65 Ga _0.35 N and GaN can be 4.6 rms and 5 mm, respectively.

  According to the fifth embodiment, the same effect as in the first embodiment can be obtained, and in the example of FIG. 5B, although the voltage increases, the light output during operation is about three times that of the conventional one. Can do. In the example of FIG. 5A, the optical output during operation can be about three times that of the conventional one, and the operating voltage can be set to a value similar to the conventional one.

Alternatively, the p-type Al _0.05 Ga _0.95 N clad layer 104 may have a laminated structure in which AIGaN layers and GaN layers, each corresponding to a quarter wavelength thickness with an optical path length of the emission wavelength, are alternately laminated. Thereby, the amount of light leaking from the active layer 107 to the p-type GaN contact layer 103 side can be reduced, and the light emission efficiency can be improved.

Only the n-type Al _0.05 Ga _0.95 N clad layer 109 may have the above-mentioned laminated structure, or only the p-type Al _0.05 Ga _0.95 N clad layer 104 may have the above-mentioned laminated structure. Also good.

(Fifth embodiment)
In the fifth embodiment, a nitride-based insulator, for example, a film made of silicon nitride is provided between the side surface of the active layer 107 and the high reflection layers 201a, 201b, 202 and the low reflection layer 203. The side surface is characterized by nitriding treatment.

  According to the element structure of the present embodiment, a nitride-based insulator is provided between the active layer 107 and the high reflection layers 201a, 201b, 202 and the low reflection layer 203 formed on the side surfaces of the active layer 107. Therefore, even when a current flows in the vicinity of the side surface of the active layer 107, the reactive current can be reduced by reducing the surface recombination by the film made of silicon nitride, and the light emission efficiency with respect to the input power can be improved. Become.

  Note that a film made of aluminum nitride or the like can be used instead of silicon nitride. These nitride-based insulators can be formed by CVD or sputtering.

Further, it is desirable to nitride the side surface of the active layer 107 before forming the high-reflection layers 201a, 201b, 202 and the low-reflection layer 203 on the side surface of the active layer 107, and by this treatment. The effects of reducing the reactive current and improving the light emission efficiency can be further improved. As the nitriding treatment, for example, it is preferable to perform discharge in a gas such as nitrogen or ammonia, thereby generating nitrogen radicals, and performing surface treatment with the nitrogen radicals. Note that only the nitriding treatment is performed, and the side surfaces of the active layer 107 may not be covered with the nitride-based insulator. .
(Sixth embodiment)
The semiconductor light emitting device of the sixth embodiment uses a p-type GaN substrate instead of the n-type GaN substrate, and is the same as the first embodiment except for this point.

FIG. 6 is a perspective view showing the configuration of the semiconductor light emitting device according to this embodiment. As shown in FIG. 6, the semiconductor light emitting device of this embodiment is composed of a rectangular parallelepiped GaN compound semiconductor chip. This chip includes a p-type GaN contact layer 603 doped with Mg, a p-type Al _0.05 Ga _0.95 N cladding layer 604 doped with Mg, a p-type Al _0.2 Ga _0.8 N overflow prevention layer 605 doped with Mg, , An undoped GaN guide layer 606, an active layer 607 composed of a multiple quantum well (MQW) in which the well layer is ln _0.2 Ga _0.8 N and the barrier layer is ln _0.03 Ga _0.97 : N, and Si-doped n-type GaN The guide layer 608, the Si-doped n-type Al _0.05 Ga _0.95 N cladding layer 609, and the Si-doped n-type GaN contact layer 610 are sequentially stacked. A p-side electrode 602 is connected to the p-type GaN contact layer 603, and an n-side electrode 601 is connected to the n-type GaN contact layer 610. The element having such a structure can be manufactured by the same process as that of the first embodiment except that the n-type GaN substrate is a p-type GaN substrate.

  The element structure of the sixth embodiment is a structure in which p and n of the layer structure in the first embodiment are interchanged, and the same operational effects as those of the first embodiment can be obtained. That is, according to the present embodiment, the contact area between the p-type GaN contact layer 603 and the p-side electrode 602 can be dramatically increased, and the contact resistance can be greatly increased in the p-side electrode 602 where the contact resistance tends to increase. Can be reduced. As a result, the operating voltage can be greatly reduced, and the heat generation of the element can be drastically reduced.

  A light-emitting device as shown in FIG. 4 can also be configured using the semiconductor light-emitting element shown in FIG. The p-side electrode 602 is electrically connected to the heat sink 305 via the solder 306 and the n-side electrode 601 is electrically connected to the heat sink 302 via the solder 303 to improve the heat dissipation efficiency and operate at high output. It becomes possible to make it.

  In addition, the p-side electrode 602 can be electrically connected to the heat sink 302 via the solder 303 and the n-side electrode 601 can be electrically connected to the heat sink 305 via the solder 306. In this case, the low reflection layer 203 and the high reflection layer 202 are exchanged so that the n-side electrode 601 does not cover the light emission surface of the active layer 607. In this case, the heat dissipation efficiency is further improved, and it is possible to operate stably at a high output.

(Seventh embodiment)
In the above-described third embodiment, the example in which the phosphor is applied around the semiconductor light emitting element to obtain white light has been described. However, the seventh embodiment described below is characterized by the method of applying the phosphor. There is something.

  FIG. 7 is a perspective view showing an example in which the semiconductor light emitting device of FIG. 1 is mounted on a wiring board. On the wiring substrate 700, an n-side wiring pattern 701 and a p-side wiring pattern 702 that are electrically connected to the n-side electrode 101 and the p-side electrode 102 of the semiconductor light emitting element are formed. The electrodes 101 and 102 and the wiring patterns 701 and 702 are joined by, for example, solder 703. Although omitted in FIG. 7, a heat sink similar to that in FIG. 4 may be connected to the semiconductor light emitting element.

  Although not shown in FIG. 7, the phosphor is applied to the entire surface of the substrate with the semiconductor light emitting element mounted on the wiring substrate 700. By applying the phosphor, the wavelength of light emitted from the semiconductor light emitting element changes, and white light is obtained.

  Phosphors are usually in the form of particles, and when this type of phosphor is applied to the top and side surfaces of a semiconductor light emitting device, color unevenness due to variation in particle size occurs. In order to prevent this, in this embodiment, the phosphor is applied directly around the active layer of the semiconductor light emitting device by sputtering. Specifically, a phosphor manufactured by the same method as usual is laminated on the surface of the semiconductor light emitting element where no electrode is formed.

  As a specific method of stacking the phosphors, for example, the phosphors are stacked by performing sputtering while rotating in a planetary manner with a heat sink attached to the semiconductor light emitting element.

  More preferably, the phosphor is laminated by laser ablation. This makes it possible to uniformly form a phosphor with good luminous efficiency without variation in particle size.

  When transmitting part of the light emitted from the device and using it as part of white light, the phosphor layer is formed thin, and when the phosphor is excited with ultraviolet light, a plurality of phosphor layers are formed as a laminated structure. To do. In addition, fine crystals can be stacked on other crystal planes in an aqueous solution such as zinc oxide. By such a method, it is possible to obtain good white light without color unevenness.

  When a lighting device is manufactured using the semiconductor light emitting element according to each of the above-described embodiments, the luminance is high only around the active layer of the semiconductor light emitting element, and glare occurs. Therefore, as shown in FIG. 8, a light guide plate 711 may be disposed around the active layer, and the light emission area may be widened by the light guide plate 711 to reduce the light density. Alternatively, instead of the light guide plate 711, as shown in FIG. 9, a reflection plate or a diffusion plate 712 may be arranged along the light emitting direction of the semiconductor light emitting element to increase the light emitting area. In the case of FIG. 9, instead of applying the phosphor to the semiconductor light emitting element, the phosphor is applied to the reflection plate or the diffusion plate. Thereby, good white color can be obtained while lowering the light density.

  The present invention is not limited to the embodiments described above. For example, in the example of FIG. 3, when manufacturing a chip of a semiconductor light emitting device, first, a surface on which a pair of highly reflective layers is formed is formed by cleaving the substrate, and the substrate is separated into a plurality of bar-shaped pieces. The surface on which the high-reflection layer and the low-reflection layer are formed by cleaving the bar-shaped piece and each bar-shaped piece is separated into a plurality of element chips, but the reverse process may be employed.

  That is, first, a scribe line is inserted in the longitudinal direction of the element, a surface for forming a high reflection layer and a low reflection layer is formed by cleavage, and the substrate is separated into a plurality of bar-shaped pieces. On the other hand, it is possible to produce a surface on which a pair of highly reflective layers are formed by cleavage, and to separate each bar-shaped piece into a plurality of element chips. In the former order of production steps, the cleavage plane can be created at a time, so that an effect of good efficiency can be obtained.In the latter order of production steps, each element is cleaved so that the cleavage plane can be accurately formed. The effect that the obtained yield is good can be obtained.

Further, in the example of FIG. 3, the elements are separated by scribing and cleaving, but may be performed by dry etching. In this case, a mask pattern is formed on the substrate surface so that the separation region of the substrate is exposed, and the substrate is dry etched using this mask pattern. When a substrate made of a Ga: N-based material is used, a metal such as SiO ₂ or Mo can be used as the mask pattern, and argon or chlorine can be used as the etching gas. In that case, since the shape corresponding to D in FIG. 3 can be formed only by etching, the number of times the elements are rearranged and stretched can be reduced.

  Further, a structure in which the n-side electrode is comb-shaped can be employed. For example, in FIG. 1, the planar shape on the surface A of the n-side electrode 101 can be a shape indicated by a dotted line. In this case, the electrode area can be reduced, light absorption due to reflection at the electrode portion can be reduced, and a decrease in light emission efficiency due to light absorption outside the light emitting layer can be further suppressed. A structure in which the P-side electrode is in a comb shape or a structure in which both the n-side electrode and the p-side electrode are in a comb shape may be employed, and similar effects can be obtained.

  In each of the embodiments described above, GaN is used as the substrate, but other substrates such as a sapphire substrate and a Sic substrate may be used. In this case, the substrate-side electrode is formed so as to be in contact with a conductive substrate or a laminated layer. For example, in the case of a sapphire substrate, since the substrate is insulative, the electrode can be in contact with the conductive semiconductor layer stacked on the substrate. The electrode may have a structure extending from the insulating substrate to the conductive semiconductor layer. In this case, heat dissipation can be improved.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a perspective view illustrating a configuration of a semiconductor light emitting element according to a first embodiment. FIG. 2 is a side view of the semiconductor light emitting device of FIG. 3A-3H are process diagrams showing a manufacturing method for manufacturing the semiconductor light emitting device of FIG. Sectional drawing which shows the structure of the light-emitting device which concerns on 2nd and 3rd embodiment. FIG. 6 is a diagram showing a configuration of a semiconductor light emitting element according to a fourth embodiment. FIG. 9 is a perspective view showing a configuration of a semiconductor light emitting element according to a sixth embodiment. The perspective view which shows the example which mounts the semiconductor light-emitting device of FIG. 1 on a wiring board. The figure which has arrange | positioned the light-guide plate around the active layer. The figure which shows the example which arrange | positions a reflecting plate and a diffusion plate along the light emission direction of a semiconductor light-emitting device.

Explanation of symbols

101 n-side electrode 102 P-side electrode 103 p-type GaN contact layer doped with Mg 104 p-type Al _0.05 Ga _0.95 N cladding layer doped with Mg 105 p-type Al _0.2 Ga _0.8 overflow prevention layer doped with Mg 106 Undoped GaN guide layer 107 Active layer made of multiple quantum well (MQW) with well layer In _0.2 Ga _0.8 N and barrier layer In _0.03 Ga _0.97 N 108 n-type GaN guide layer 109 doped with Si 109 Si doped N-type Al _0.05 Ga _0.95 N clad layer 110 Si-doped n-type GaN contact layer 201a, 201b High reflection layer 202 High reflection layer 203 Low reflection layer 301 Mount substrate 302, 305 Heat sink 303, 306 Solder 304 Insulator 307 Power supply 401 SiO ₂ film 402 Multiple bars 403 Dielectric multilayer film 404 Element chip 405 Dielectric multilayer film 406 Metal film 407 Dielectric film 408 Metal film 501, 502 Al _0.65 Ga _0.35 N and GaN superlattice 503, 504 Al _0.3 Ga _0.7 N layer 510 Cell made of plus chip 511 Phosphor layer 512 Light extraction window 601 N side electrode 602 P side Electrode 603 p-side GaN contact layer 604 Mg-doped p-type Al _0.05 Ga _0.95 N cladding layer 605 Mg-doped p-type Al _0.2 Ga _0.8 N overflow prevention layer 606 Undoped GaN guide layer 607 Well layer In _0.2 Active layer made of multiple quantum well (MQW) with Ga _0.8 N and barrier layer In _0.03 Ga _0.97 N 608 n-type GaN guide layer doped with Si 609 n-type Al _0.05 Ga _0.95 N clad layer doped with Si 610 n-type GaN contact layer doped with Si

Claims (17)

A laminated portion including a light emitting layer made of a semiconductor, and a first clad layer and a second clad layer which are provided between the light emitting layers and are made of a semiconductor and have a gain structure for the light emitting layer;
A pair of first highly reflective layers that are provided across the light emitting layer in a first direction perpendicular to the stacking direction of the stacked portion and have a high reflectance with respect to light generated in the light emitting layer;
A low reflection layer and a second reflection layer, which are provided with the light emitting layer sandwiched in a second direction perpendicular to the stacking direction and intersecting the first direction, and have a low reflectance and a high reflectance, respectively, with respect to the light generated in the light emitting layer. A highly reflective layer,
First and second layers formed on opposite sides of the first and second cladding layers from the light emitting layer, respectively.
A contact layer of
Stacked on the first and second contact layers and through the first and second contact layers
Comprising first and second electrodes for supplying current to the light emitting layer ,
The length in the stacking direction has an element shape longer than the length in the first and second directions,
The first and second electrodes are formed by stacking the stacked portions of the first and second contact layers, respectively.
A light-emitting element which is also in contact with a plane parallel to the layer direction . The first electrode is connected to the first contour through an opening formed in a part of the surface of the low reflection layer.
Is formed on the surface of the low reflection layer,
The second electrode is formed on a part of the surface of the second highly reflective layer, and the second contact layer
2. The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element is conductive and formed on a surface of the second highly reflective layer . 2. The semiconductor light emitting element according to claim 1, wherein a cross sectional area of the light emitting layer in a plane perpendicular to the second direction is larger than a cross sectional area of the light emitting layer in a plane perpendicular to the first direction. 2. The semiconductor light emitting element according to claim 1, wherein the first and second cladding layers include a pair of third high reflection layers having high reflectivity with respect to light generated in the light emitting layer. The reflectivity of the first and second highly reflective layers is 80 for the light generated in the light emitting layer, respectively.
The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element is at least%. The semiconductor light emitting element according to claim 1, wherein a reflectance of the low reflection layer is 10% or less with respect to light generated in the light emitting layer. The semiconductor light emitting element according to claim 1, wherein at least a part of a side surface of the light emitting layer is covered with a nitride-based insulator. 8. The semiconductor light emitting device according to claim 7 , wherein the nitride-based insulator is silicon nitride. The semiconductor light emitting device according to claim 1, wherein the light emitting layer is made of a nitride compound semiconductor. A mounting substrate having a heat sink;
A semiconductor light emitting element attached to the heat sink,
The semiconductor light emitting element includes a light emitting layer made of a semiconductor, and first and second cladding layers as a waveguide structure made of a semiconductor provided with the light emitting layer sandwiched between them to give gain to the light emitting layer. A laminated part;
A pair of first highly reflective layers that are provided across the light emitting layer in a first direction perpendicular to the stacking direction of the stacked portion and have a high reflectance with respect to light generated in the light emitting layer;
A low reflection layer and a second reflection layer, which are provided with the light emitting layer sandwiched in a second direction perpendicular to the stacking direction and intersecting the first direction, and have a low reflectance and a high reflectance, respectively, for the light generated in the light emitting layer. A highly reflective layer,
First and second cladding layers are formed on opposite sides of the light emitting layer, respectively.
The first and second contact layers;
Stacked on the first and second contact layers and through the first and second contact layers
Comprising first and second electrodes for supplying current to the light emitting layer ,
The length in the stacking direction has an element shape longer than the length in the first and second directions,
The first and second electrodes are formed by stacking the stacked portions of the first and second contact layers, respectively.
It is an element in contact with the plane parallel to the layer direction,
The semiconductor light emitting device according to claim 1, wherein the stacking direction of the stacked portions is disposed in parallel to a surface of the heat sink on which the semiconductor light emitting element is disposed. The light emitting device according to claim 11, further comprising a phosphor formed around the light emitting layer of the semiconductor light emitting element attached to the heat sink. The light emitting device according to claim 10, further comprising a light guide plate, a reflection plate, or a diffusion plate disposed around the light emitting layer of the semiconductor light emitting element attached to the heat sink. 11. The light emitting device according to claim 10, wherein a cross sectional area of the light emitting layer in a plane perpendicular to the second direction is larger than a cross sectional area of the light emitting layer in a plane perpendicular to the first direction. 11. The light emitting device according to claim 10, wherein the first and second cladding layers include a pair of third highly reflective layers having a high reflectance with respect to light generated in the light emitting layer. The light emitting device according to claim 10, wherein at least a part of a side surface of the light emitting layer is covered with a nitride-based insulator. A laminate including a light emitting layer made of a semiconductor and a first clad layer and a second clad layer as a waveguide structure made of a semiconductor provided with the light emitting layer sandwiched between them to give gain to the light emitting layer. Forming a first portion and a second contact layer on both sides of the laminated portion,
Forming a plurality of resist patterns having the same size on the upper surface of the laminated portion;
Performing a first cleavage in a direction in which electrodes or insulator openings formed by the resist pattern are aligned along a first direction which is a cleavage direction of the semiconductor substrate;
Forming a pair of first highly reflective layers having high reflectivity with respect to light generated in the light emitting layer on two opposing surfaces obtained by the first cleavage;
Performing a second cleavage between two adjacent electrodes or the insulator opening along a second direction intersecting the first direction;
Forming a low reflection layer and a second high reflection layer each having a low reflectance and a high reflectance with respect to light generated in the light-emitting layer on two opposing surfaces obtained by the second cleavage;
Forming an opening in a part of the surface of the low reflection layer, and forming a first electrode electrically connected to the first contact layer on the surface of the low reflection layer through the opening; Forming a second electrode formed on a part of the surface of the second highly reflective layer and electrically connected to the second contact layer;
A method for manufacturing a semiconductor light emitting device comprising:
The length in the stacking direction has an element shape longer than the length in the first and second directions,
The first and second electrodes are formed by stacking the stacked portions of the first and second contact layers, respectively.
The method of manufacturing a semiconductor light emitting element characterized that you have also contact with the plane parallel to the layer direction. On the semiconductor substrate, a laminated portion including a light emitting layer made of a semiconductor and first and second clad layers made of a semiconductor provided with the light emitting layer sandwiched therebetween is formed, and both sides sandwiching the laminated portion. Forming a first contact layer and a second contact layer;
Forming a plurality of resist patterns having the same size on the upper surface of the laminated portion;
Performing a first cleavage in a direction in which electrodes or insulator openings formed by the resist pattern are aligned along a first direction which is a cleavage direction of the semiconductor substrate;
Forming a low reflection layer and a first high reflection layer each having a low reflectance and a high reflectance with respect to light generated in the light emitting layer on two opposing surfaces obtained by the first cleavage;
Performing a second cleavage between two adjacent electrodes or the insulator opening along a second direction intersecting the first direction;
Forming a pair of second highly reflective layers having a high reflectance with respect to the light generated in the light emitting layer on two opposing surfaces obtained by the second cleavage;
Forming an opening in a part of the surface of the low reflection layer, and forming a first electrode electrically connected to the first contact layer on the surface of the low reflection layer through the opening; Forming a second electrode formed on a part of the surface of the second highly reflective layer and electrically connected to the second contact layer, comprising:
The length in the stacking direction has an element shape longer than the length in the first and second directions,
The first and second electrodes are formed by stacking the stacked portions of the first and second contact layers, respectively.
A method of manufacturing a semiconductor light emitting device, wherein the method is also in contact with a plane parallel to the layer direction .

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