JP4940605B2 - Data receiving apparatus and data transmission system - Google Patents

Description

  The present invention relates to a data receiving apparatus and a data transmission system, and more particularly to a data receiving apparatus and a data transmission system for transmitting multi-bit digital data.

  In the transmission of digital data, there are many industrial applications that require multi-bit digital transmission. However, multi-pole cables and connectors often cannot be used for transmission due to distance or mounting area / volume restrictions, and various multiplexing methods are used.

For example, a technique of multiplexing and transmitting data and a word clock as a multi-valued logic signal, particularly a transmission technique using a differential multi-valued logic signal is known (see, for example, Patent Document 1).
According to such a data transmission system, a multi-level logic signal is generated based on the data to be transmitted and the value of the word clock, and the data and the word clock are separated and demodulated by the receiving circuit.

  By the way, in recent years, it has been required to reduce the amplitude of a multi-level logic signal in order to save power and reduce radiation. As the amplitude of the multi-level logic signal is reduced, the demand for the accuracy of the threshold voltage for identifying the multi-level logic signal is increased, which imposes strong restrictions on the circuit manufacture of the transmission / reception circuit.

  As one method for avoiding this problem, a method is known in which a peak hold circuit detects the maximum amplitude from a multi-value logic signal sequence and generates an offset based on the maximum amplitude (see, for example, Patent Document 2).

However, the peak hold has a problem in accuracy such as a slow return response after erroneously recognizing the maximum amplitude to a large extent due to mixed noise.
Also known is a method of generating an offset from a signal called a frame slot with a fixed amplitude (see, for example, Patent Documents 3 and 4).

However, this has the problem that it only works after the completion of frame synchronization that identifies the frame slot from the signal sequence.
JP 2005-142872 A JP 2000-349605 A JP 61-133748 A JP-A-1-220536

In Patent Document 1 described above, a comparator is used as a method for discriminating between data and a word clock.
An absolute offset (threshold voltage) is not required for the comparator for identifying data, and data is identified from a multilevel transmission signal by determining which of the positive and negative signals has a relatively high potential. If the comparator offset is sufficiently small compared to the signal amplitude generated by the transmission circuit, this identification is always stable without being affected by the current output from the transmission circuit or the absolute value fluctuation of the termination resistance of the reception circuit. To do.

  On the other hand, the comparator that demodulates the word clock needs to accurately identify the threshold voltage of each multilevel logic signal. For example, two comparators are provided to identify a quaternary (3Io, Io, -Io, -3Io) signal, and one comparator accurately identifies the middle between the 3Io level and the Io level, that is, the 2Io level. It is necessary to have an offset, and the other comparator needs to have an offset that accurately distinguishes between the -3Io level and the -Io level, that is, the -2Io level. The offsets of these comparators are determined as a function of the output current of the transmission circuit and the termination resistance of the reception circuit, and are proportional to the transmission circuit output current having a characteristic variation factor different from that of the reception circuit. Therefore, unless the receiving circuit obtains the output current information of the transmitting circuit in any way, it is necessary to strictly manage the output current, the terminating resistance, and the absolute value of the offset of the transmitting / receiving circuit.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a data receiving apparatus and a data transmission system that can accurately identify the multilevel logic of a multilevel logic signal.

In the present invention, in order to solve the above problems, a data receiving apparatus for receiving a multi-level logic signal having a plurality of amplitude values based on a control signal for controlling the comparison voltage, the comparison voltage from the multi-value logic signal Based on the output of the comparison unit, a comparison unit that compares the difference between the multi-value logic signal and the comparison voltage with a predetermined reference signal, and the comparison voltage is the multi-value logic. The control signal is generated so as to have the maximum amplitude of the signal, the voltage control unit that outputs to the voltage generation unit, the proportional threshold generation unit that generates a threshold proportional to the comparison voltage, the threshold, There is provided a data receiving device comprising a comparator for comparing a multi-level logic signal.

  According to such a configuration, the voltage control unit controls the comparison voltage so that the maximum amplitude value of the multi-valued logic signal is obtained, so that the threshold value proportional to the comparison voltage and the multi-value logic signal are output from the comparator. The value compared with is output.

Further, in a data transmission system for transmitting a plurality of bits of data, a plurality of bits obtained by converting a plurality of bits of parallel data to be transmitted into serial data and adding a word clock indicating a word delimiter in the serial data as one bit information A data transmission device for generating and transmitting a multi-level logic signal representing the information of one symbol by one symbol, and the multi-level logic signal based on a control signal for receiving the transmitted multi-level logic signal and controlling a comparison voltage from generates voltages for the comparison, the difference of the multi-value logic signal and said comparison voltage is compared with a predetermined reference signal based on the comparison result, the comparison voltage is the largest of the multivalued logic signals controls the comparison voltage to generate the control signal such that the amplitude and the threshold value in proportion to the comparison voltage, child comparing the multi-value logic signal Provides a data transmission system comprising: a data receiving device that extracts the serial data and the word clock from the multi-level logic signal and reproduces the parallel data based on the extracted word clock Is done.

  According to such a configuration, the voltage control unit of the receiving device controls the comparison voltage so that the maximum amplitude value of the multi-value logic signal is obtained, so that the comparator has a threshold value proportional to the comparison voltage and a multi-value. The word clock is extracted by comparing with the value logic signal.

  In the present invention, the voltage control unit controls the comparison voltage so that the maximum amplitude value of the multi-value logic signal is obtained, so that the threshold value proportional to the comparison voltage is compared with the multi-value logic signal from the comparator. Therefore, the comparator can accurately identify the multi-value logic of the multi-value logic signal.

  In particular, when the ratio between the comparison voltage and the threshold is set to the ratio between the maximum amplitude value of the multi-value logic signal and the intermediate value between the two amplitude values to be identified, the comparator is accurate for each amplitude value. A simple threshold can be easily obtained.

  In addition, since the voltage control unit controls the comparison voltage so that the maximum amplitude value of the multi-level logic signal becomes the maximum, the multi-level logic can always be identified with the maximum noise margin. Improves.

Embodiments of a data receiving apparatus and a data transmission system according to the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a data transmission system according to the first embodiment.

  The data transmission system according to the first embodiment converts a plurality of bits of transmission parallel data to be transmitted into transmission serial data, and adds a transmission word clock indicating a word delimiter in the transmission serial data as 1-bit information. A data transmission device 100 that generates a quaternary (multi-value) logic signal representing bit information by one symbol and sends it to the differential transmission line 200; receives the quaternary logic signal via the differential transmission line 200; The data receiving apparatus 300 extracts the same received serial data as the transmitted serial data and the same received word clock as the transmitted word clock, and reproduces the same received parallel data as the transmitted parallel data based on the extracted word clock.

  The data transmitting apparatus 100 includes a parallel / serial conversion circuit 110 that converts 10 × 1 bit (K × N bits) transmission parallel data, which is a plurality of bits to be transmitted, into 1 (N) bit transmission serial data, The transmission bit clock necessary for the operation of the serial conversion circuit 110 is generated by multiplying the transmission data clock (the frequency is multiplied by 10 (K)), which is synchronized with the transmission parallel data, and the transmission serial clock based on the transmission data clock. A frequency multiplying circuit (frequency multiplying circuit) 130 that generates a transmission word clock indicating a word delimiter in data is included. Further, a quaternary logic signal generation circuit for generating a multi-value logic signal that represents information of 2 bits ((N + 1) bits), which is a combination of 1-bit transmission serial data and a transmission word clock as a 1-bit signal, by one symbol ( Multi-value logic signal generation circuit) 140.

Here, one symbol means a time for holding one value. For example, when converting to N = 2-bit transmission serial data, one symbol holds N + 1 = 3-bit information, that is, 2 ^{(N + 1)} = 8-value information.

The differential transmission path 200 is a differential transmission path that sends out a multilevel differential signal. Since a multi-value differential signal is transmitted, resistance to external noise applied to the differential transmission line 200 can be enhanced.
The data receiving apparatus 300 includes a cascode circuit 310 that generates a comparison signal having a magnitude corresponding to the multilevel logic signal transmitted from the data transmitting apparatus 100 via the differential transmission path 200, and a termination resistor as the differential transmission path 200. The terminal resistance adjustment circuit 320 that adjusts to the characteristic impedance of the signal, and the comparison signal is compared with the voltage value generated by the variable offset circuit, which will be described later, and the reception serial data and the reception word clock equal to the transmission serial data and the transmission word clock are A data / clock separation circuit 330 that extracts data, a frequency multiplication circuit 340 that generates a reception bit clock by multiplying the frequency of the reception word clock by 10 (K), and received serial data according to the reception bit clock and the reception data clock. A serial-parallel conversion circuit 360 for converting to reception parallel data; And a phase adjustment circuit 350 that adjusts the received bit clock phase capturing signals serial data.

The operation of the data transmission system of FIG. 1 will be briefly described below.
In the data transmission apparatus 100, when 10 × 1 bit transmission parallel data is input to the parallel-serial conversion circuit 110, the frequency 10 multiplication circuit 130 increases the frequency of the transmission data clock to which the transmission parallel data is synchronized by 10 times. The transmission bit clock is generated, and a load signal for determining the output timing of the parallel / serial conversion circuit 110 is generated. In addition, a transmission word clock equivalent to the transmission data clock is generated.

  The parallel / serial conversion circuit 110 converts the transmission parallel data of 10 × 1 bits into 1-bit transmission serial data according to the transmission bit clock and the load signal, and sends it to the quaternary logic signal generation circuit 140.

  The quaternary logic signal generation circuit 140 converts all 2-bit data including the input 1-bit transmission serial data and the 1-bit transmission word clock into a multi-level logic signal having four levels per symbol. The data is converted and sent to the differential transmission line 200.

  When the data receiving device 300 receives a multilevel logic signal from the data transmitting device 100 via the differential transmission line 200, the cascode circuit 310 creates a comparison signal having a magnitude corresponding to the multilevel logic signal. At this time, the termination resistance adjustment circuit 320 adjusts the termination resistance to the characteristic impedance of the differential transmission path 200. The data / clock separation circuit 330 quantizes the level of the comparison signal by comparing it with a plurality of voltage values, and extracts reception serial data and reception word clock equal to transmission serial data and transmission bit clock.

  The frequency multiplying circuit 340 generates a reception bit clock obtained by multiplying the frequency of the reception word clock by 10 and a reception data clock equivalent to a reception word clock in which the reception parallel data is synchronized.

  The serial / parallel conversion circuit 360 generates 10 × 1 bits of reception parallel data and outputs 1 bit of reception serial data according to the reception bit clock and the reception data clock.

FIG. 2 is a circuit diagram of a parallel / serial conversion circuit of the data transmission apparatus.
The parallel-serial conversion circuit 110 is a circuit that converts 10-bit transmission parallel data into 1-bit transmission serial data.

  The parallel / serial conversion circuit 110 is a circuit that converts parallel data D0 to D9 to be transmitted into serial data S0 to be transmitted. Ten D flip-flops (hereinafter referred to as D-FF) 111, 112,... , 120 and nine selectors 121, 122,.

D-FFs 111, 112,..., 120 are connected in 10 stages in series via selectors 121, 122,.
Data D0 is input to the input terminal of the D-FF 111, data D1 is input to one input terminal of the selector 121, and data D2 is input to one input terminal of the selector 122. Similarly, each data is input to one input terminal of the corresponding selector, and data D9 is input to one input terminal of the selector 129.

  The output terminal of the D-FF 111 is connected to the other input terminal of the selector 121. The output terminal of the selector 121 is connected to the input terminal of the D-FF 112. The output terminal of the D-FF 112 is connected to the other input terminal of the selector 122. Similarly, the output terminal of each selector is input to the input terminal of the corresponding D-FF, and the output terminal of D-FF 119 is connected to the other input terminal of the selector 129. The output terminal of the selector 129 is connected to the input terminal of the D-FF 120. From the D-FF 120, 1-bit transmission serial data S0 is output.

  The data D0 to D9 are taken into the D-FFs 111 to 120 according to the transmission bit clock input to the clock terminals of the D-FFs 111 to 120. When the load signal input to the selectors 121 to 129 becomes, for example, an H (High) level, the output of the preceding FF is sequentially taken into the subsequent stage according to the transmission bit clock, and 1 bit is output from the D-FF 120. Is output as transmission serial data S0.

FIG. 3 is a circuit diagram of a frequency 10 multiplication circuit of the data transmission apparatus.
The frequency multiplying circuit 130 includes a phase comparator PFD (Phase Frequency Detector) 131, a LPF (Low Pass Filter or Loop Filter) 132, a VCO (Voltage Controlled Oscillator) 133, and D-FFs 134, 135, 136, 137, 138 and an AND circuit 139.

  The PFD 131 receives a transmission word clock and a transmission data clock that are output from the D-FF 138, compares the phase of each signal, and inputs the output to the VCO 133 via the LPF 132. The VCO 133 generates a transmission bit clock having a frequency 10 times that of the transmission data clock and outputs the transmission bit clock from the frequency 10 multiplication circuit 130. The generated transmission bit clock is input as a clock signal for the D-FFs 134, 135, 136, 137, and 138. A circuit in which the D-FFs 134, 135, 136, 137, and 138 are connected in series functions as a 1 / 10-fold frequency dividing circuit, and the output of the frequency dividing circuit, that is, the transmission word clock that is the output of the D-FF 138 is It is input to one input terminal of the preceding D-FFs 134 to 137 and the PFD 131. By configuring such a phase-locked loop (PLL), a transmission word clock having no frequency or phase shift from the input transmission data clock is generated and output from the frequency 10 multiplication circuit 130.

  An output signal of the D-FF 137 and a signal obtained by inverting the output signal of the D-FF 138 are input to the AND circuit 139, and the output of the AND circuit 139 is output from the frequency 10 multiplication circuit 130 as a load signal.

FIG. 4 is a circuit diagram of a quaternary logic signal generation circuit.
The quaternary logic signal generation circuit 140 is a circuit that inputs 1-bit transmission serial data and a 2-bit transmission word clock to generate a quaternary signal.

  In quaternary logic signal generation circuit 140, transmission serial data S0 is input to the gate of n-channel MOSFET (hereinafter referred to as nMOS) 143 via inverters 141 and 142, and input to the gate of nMOS 145 via inverter 144. . The source terminals of the nMOSs 143 and 145 are connected to the current source 146, and the current 2Io flows.

  The transmission serial data is input to one input terminal of the EX-NOR circuit 147, and the transmission word clock is input to the other input terminal. The output of the EX-NOR circuit 147 is input to the gate of the nMOS 150 via the inverters 148 and 149 and input to the gate of the nMOS 152 via the inverter 151. The source terminals of the nMOSs 150 and 152 are connected to the current source 153, and the current Io flows. Further, the drain terminal of the nMOS 150 is connected to the drain terminal of the nMOS 143 and a NEG terminal (not shown) for sending a NEG signal of a quaternary differential signal. The drain terminal of the nMOS 152 is connected to the drain terminal of the nMOS 145 and a POS terminal (not shown) for sending a POS signal of a quaternary differential signal.

  With such a circuit configuration, a multi-level logic signal is generated that has correspondence between transmission serial data and 2-bit (ie, four-value) information of the transmission word clock in one symbol in the relationship shown in the following figure. .

FIG. 5 is a diagram showing the correspondence between quaternary logic and transmission data.
Here, the correspondence between the input signal of the quaternary logic signal generation circuit of the data transmission apparatus shown in FIG. 4 and the output signal will be described. The receiving side will be described later.

  As shown in this figure, the POS terminal current and the NEG terminal current each have four values depending on the values of the transmission serial data and the transmission word clock input to the quaternary logic signal generation circuit 140. For example, when the transmission serial data and the transmission word clock are both “1”, the POS terminal current is 0, the NEG terminal current is 3Io, the transmission serial data is “1”, and the transmission word clock is “0”. The POS terminal current is Io and the NEG terminal current is 2Io. When the transmission serial data and the transmission word clock are both “0”, the POS terminal current is 2Io, the NEG terminal current is Io, the transmission serial data is “0”, and the transmission word clock is “1”. The POS terminal current is 3Io, and the NEG terminal current is 0.

FIG. 6 is a diagram showing a quaternary differential signal generated from a quaternary logic signal generation circuit.
In this figure, the quaternary differential signal is indicated by a POS signal-NEG signal (current value). Here, the POS signal-NEG signal has a large amplitude when the transmission word clock is at the H level, and has a small amplitude when the transmission word clock is at the L level. Thus, when the POS signal-NEG signal is 3Io, the transmission serial data is "0" and the transmission word clock is "1". When the POS signal-NEG signal is Io, both the transmission serial data and the transmission word clock are When "0", the POS signal -NEG signal is -Io, the transmission serial data is "1", the transmission word clock is "0", and when the POS signal -NEG signal is -3Io, the transmission serial data and transmission Both word clocks indicate “1”, which means that one symbol holds 2 bits and 4 values.

Such a signal is transmitted from the data transmission device 100 to the data reception device 300 via the differential transmission path 200.
However, at this time, the actual current flows from the data receiving device 300 to the data transmitting device 100.

  In the following, a section in which the POS signal-NEG signal has a large amplitude due to the word clock is referred to as a time mark. In FIG. 6, the ratio of time marks in one word clock cycle (hereinafter referred to as “mark rate”) is 5/10, but can be set to an arbitrary ratio of 1/10 to 9/10. Even if the ratio is set, the data and the word clock can be multiplexed and transmitted.

This mark rate is preset to one value (5/10 in the present embodiment) as a protocol for communication between the data transmitting apparatus 100 and the data receiving apparatus 300 at the time of transmission.
FIG. 7 is a circuit diagram showing a cascode circuit and a termination resistance adjusting circuit.

The cascode circuit 310 includes nMOSs 311 and 312, pMOSs 313 and 314, and resistors Rt 1 and Rt 2.
In the cascode circuit 310, the source terminal of the nMOS 311 is connected to the current source 315, and the drive current Iidol flows. The source terminal of the nMOS 312 is also connected to the current source 316, and the drive current Iidol flows. The drain terminal of the nMOS 311 is connected to the drain terminal of the pMOS 313 via the resistor Rt1. The drain terminal of the nMOS 312 is connected to the drain terminal of the pMOS 314 via the resistor Rt2. The gate of the nMOS 311 is connected to the drain terminal of the pMOS 314, and the gate of the nMOS 312 is connected to the drain terminal of the pMOS 313. Power is supplied to the source terminals of the pMOSs 313 and 314. A signal from the termination resistance adjustment circuit 320 is input to the gates of the pMOSs 313 and 314.

  The POS signal, which is a quaternary differential signal, is input to the source terminal of the nMOS 311 and the NEG signal is input to the source terminal of the nMOS 312. The signal VP of the cascode circuit 310 corresponding to the POS signal is output from the drain terminal of the nMOS 311, and the signal VM of the cascode circuit 310 corresponding to the NEG signal is output from the drain terminal of the nMOS 312. That is, the cascode circuit 310 converts the POS signal-NEG signal (current value) into comparison signals (voltages) VP and VM. Here, the signal VP corresponds to the POS signal, and the signal VM corresponds to the NEG signal.

  The termination resistance adjustment circuit 320 is a replica of the front end of the cascode circuit 310 and has the same circuit configuration as that of the cascode circuit 310 and is connected to the nMOSs 321 and 322 and the pMOSs 323 and 324. The source terminal of the nMOS 321 is connected to the current source 325 and the drive current Iidol flows. The source terminal of the nMOS 322 is connected to the current source 326 and the drive current Iidol + current Io flows. Source outputs of the nMOS 321 and the nMOS 322 are input to the differential amplifier 327. The output of the differential amplifier 327 is compared with the output of the differential amplifier 328 to which the reference voltage Vo is input by the differential amplifier 329, and the output is input to the pMOSs 323 and 324 and the pMOSs 313 and 314 of the cascode circuit 310. The

  With such a cascode circuit 310 and a termination resistance adjusting circuit 320, the input resistance can be adjusted to a relatively small transmission line characteristic impedance by feedback, and the voltage amplitude at the transmission receiving end can be amplified with a relatively large load resistance. A large received signal amplitude can be obtained inside the circuit.

The extracted signals VP and VM are output to the data / clock separation circuit 330.
Hereinafter, the data clock separation circuit 330 will be described. First, the data clock separation circuit 30 for explaining the principle of the data clock separation circuit 330 will be described, and then the data clock separation circuit of the present embodiment. 330 will be described.

FIG. 8 is a principle diagram showing the principle of the data / clock separation circuit according to the first embodiment.
The data / clock separation circuit 30 is a circuit that correctly identifies the thresholds of the signals VP and VM, separates and extracts the received serial data and the received word clock from the signals VP and VM, and is capable of changing the offset. Circuits (offset voltage adjustment circuits) 31, 32, 38, 39, differential amplifiers 33, 34, an adder 35, an LPF 36, an error amplifier 37, comparators 40, 41, 42, and a selector 43 are included.

  The variable offset circuit (voltage control unit) 31 has one end connected to the input terminal in1 to which the signal VP is input and the other end connected to the inverting input terminal of the differential amplifier (voltage generation unit) 33. The variable offset circuit (voltage control unit) 32 has one end connected to the input terminal in2 to which the signal VM is input and the other end connected to the inverting input terminal of the differential amplifier 34.

The non-inverting input terminal of the differential amplifier 33 is connected to the input terminal in2, and the non-inverting input terminal of the differential amplifier (voltage generating unit) 34 is connected to the input terminal in1.
The output terminals of the differential amplifiers 33 and 34 are connected to the adder 35, respectively.

The output terminal of the adder 35 is connected to the non-inverting input terminal of the error amplifier 37 through the LPF 36.
A reference voltage V _REF equal to the midpoint potential output (power supply voltage / 2) of the differential amplifiers 33 and 34 is applied to the inverting input terminal of the error amplifier 37. The output terminal of the error amplifier 37 is connected to the variable offset circuits 31, 32, 38, and 39.

The variable offset circuits 31 and 32, the differential amplifiers 33 and 34, the adder 35, the LPF 36, and the error amplifier 37 form a negative feedback loop system.
The variable offset circuit (proportional threshold value generator) 38 has one end connected to the input terminal in2 and the other end connected to the inverting input terminal of the comparator 40. The variable offset circuit 38 is adjusted to output an offset that is 2/3 times the offset output from the variable offset circuit 31.

  The variable offset circuit (proportional threshold value generation unit) 39 has one end connected to the input terminal in 1 and the other end connected to the inverting input terminal of the comparator 41. The variable offset circuit 39 is adjusted so as to output an offset that is 2/3 times the offset output from the variable offset circuit 32.

The non-inverting input terminal of the comparator 40 is connected to the input terminal in1, and the non-inverting input terminal of the comparator 41 is connected to the input terminal in2.
The output terminals of the comparators 40 and 41 are connected to the selector 43, respectively.

The inverting output terminal of the comparator 42 is connected to the input terminal in2, and the non-inverting output terminal is connected to the input terminal in1.
Next, the operation of the data / clock separation circuit 30 will be described.

  First, when the signal VP is input to the input terminal in1 and the signal VM is input to the input terminal in2, the signal VP is input to the non-inverting input terminal of the differential amplifier 33, and the variable offset circuit 31 is input to the inverting input terminal. The offset from is input. Further, the signal VM is input to the non-inverting input terminal of the differential amplifier 34, and the offset from the variable offset circuit 32 is input to the inverting input terminal.

The outputs of the differential amplifiers 33 and 34 are input to the adder 35, and the input values are added and output to the LPF 36.
The LPF 36 removes noise from the input signal and outputs it to the error amplifier 37.

The error amplifier 37 compares the signal output from the LPF 36 with a value obtained by multiplying the reference voltage V _REF by the time mark ratio, amplifies the error of the signal, and outputs the amplified signal to the variable offset circuits 31, 32, 38, 39. To do.

  Based on the output of the error signal, the variable offset circuits 31 and 32 operate so as to cancel the error. Specifically, the variable offset circuit 31 operates so that the offset of the differential amplifier 33 is equal to the maximum amplitude of the signal VM, and the variable offset circuit 32 has the offset of the differential amplifier 34 having the maximum of the signal VP. Operates to be equal to the amplitude. This operation process will be described in detail later.

  As a result, the voltage (error) output from the error amplifier 37 is reduced, and the variable offset circuit 38 receives an offset for identifying a voltage of 2/3 of the maximum amplitude of the signal VP, that is, a received word clock. The correct threshold voltage for reproduction is input, and the variable offset circuit 38 has an offset for identifying the voltage of 2/3 of the maximum amplitude of the signal VM, that is, the correct threshold voltage for reproducing the received word clock. Is entered.

  The comparator 40 compares the signal VP with the voltage input from the variable offset circuit 38 and outputs it to the selector 43. The comparator 41 compares the signal VM with the voltage input from the variable offset circuit 39 and outputs it to the selector 43.

The comparator 42 reproduces the received serial data from the input signals VP and VM.
The selector 43 selects one of the output signals of the comparators 40 and 41 based on the output signal from the comparator 42 and regenerates the received word clock.

Next, the operation by the negative feedback loop system will be described.
FIG. 9A to FIG. 9C are diagrams illustrating the operation of the differential amplifier with respect to the differential signal.
Hereinafter, the differential amplifiers 33 and 34 will be described. Since the configurations of the differential amplifiers 33 and 34 are the same, the differential amplifier 34 will be typically described.

  As shown in FIGS. 9A to 9C, the output of the differential amplifier 34 when the signal VP has the maximum amplitude decreases as the offset of the differential amplifier 34 increases. Therefore, whether or not the offset is equal to the maximum amplitude of the signal VP can be determined by examining the magnitude of the output waveform of the differential amplifier 34.

Specifically, when the magnitude of the output waveform of the differential amplifier 34 is larger than the magnitude of the reference voltage V _REF (FIG. 9A), the output value of the error amplifier 37 becomes positive, so that the variable offset The circuit 32 determines that the offset is too small for the maximum amplitude, and increases the output voltage. When the output waveform of the differential amplifier 34 is smaller than the reference voltage V _REF (FIG. 9C), the output value of the error amplifier 37 becomes negative. The offset is determined to be too large for the maximum amplitude, and the output voltage is reduced.

That is, the variable offset circuit 32 operates so as to converge the offset of the differential amplifier 34 to the maximum amplitude.
As a result, as shown in FIG. 9B, the offset becomes equal to the maximum amplitude of the signal VP. At this time, the output signal of the differential amplifier 34 appears as a pulse in which the midpoint potential output has the mark ratio of the time mark.

  Further, when the size of the output waveform is equal to the size of the predetermined reference voltage, the size of the offset is equal to the size of the input maximum amplitude, so that the offset is given to the comparator 40. By doing so, a correct threshold value can be obtained.

FIG. 10 is a diagram illustrating a change in output sum with respect to a change in offset.
In the data / clock separation circuit 30, the input polarities of the differential amplifiers 33 and 34 corresponding to the signals VP and VM are inverted and provided in parallel, and the adder 35 takes the sum of the outputs. When the polarities of the signals VP and VM are positive or negative and the absolute value is maximum, that is, the differential amplifiers 33 and 34 can obtain an output corresponding to the offset and the signal amplitude during reception of the time mark. It will be.

  If an offset equal to the signal amplitude is obtained in this way, the comparators 40 and 41 having offsets that are a multiple of the constant are discriminators having ideal threshold values for the multilevel logic signal. Since the signals VP and VM are four-value information, for example, if the amplitude is ± V, ± 2V / 3 is a threshold value that distinguishes the maximum value and the minimum value from the other two levels.

  By inputting the output of the error amplifier 37 to the variable offset circuits 38 and 39 that maintain a constant ratio with the variable offset circuits 31 and 32, the offset values of the comparators 40 and 41 are controlled. Therefore, the comparators 40 and 41 operate as ideal discriminators for quaternary signals when the negative feedback loop converges and stabilizes.

Next, the data / clock separation circuit 330 will be described.
FIG. 11 is a circuit diagram showing the data / clock separation circuit according to the first embodiment.
The data / clock separation circuit 330 includes differential amplifiers 1 and 2, error amplifier 3, comparators 5 and 6, a comparator and a selector for reproducing received serial data from input signals VP and VM.

In FIG. 11, the functions and configurations of the comparator and the selector are the same as the functions and configurations of the comparator 42 and the selector 43, respectively.
The differential amplifier 1 includes an nMOS (current mirror) 11, a differential amplifier circuit 12, an operational amplifier 13, and a resistor Rf1 connected between the output terminal and the inverting input terminal of the operational amplifier 13. .

The nMOS 11 constitutes a current source through which 2 × I _OFF (offset current) flows.
The nMOS 11 and the differential amplifier circuit 12 constitute a voltage-current conversion circuit (transconductance circuit) that converts a voltage difference between the signals VP and VM into a current difference.

  The differential amplifier circuit 12 includes pMOSs 14 and 15, n-type transistors (hereinafter simply referred to as transistors) 16 and 17, a resistor Rm 1, and two current sources that each output a current (constant current) Io. The source of the pMOS 14 is connected to the power supply, and the drain is connected to the collector of the transistor 16. The source of the pMOS 15 is connected to the power supply, and the drain is connected to the collector of the transistor 17. The gates of the pMOS 14 and pMOS 15 are connected to the drain of the pMOS 14, respectively.

The base of the transistor 16 is connected to the input terminal in11 for inputting the signal VP, and the base of the transistor 17 is connected to the input terminal in12 for inputting the signal VM.
Further, the emitter of the transistor 16 and the emitter of the transistor 17 are respectively connected to separate constant current sources.

The emitter of the transistor 16 and the emitter of the transistor 17 are connected to each other via a resistor Rm1.
The nMOS 11 has a drain connected to the emitter of the transistor 17 and is provided in parallel with the current source.

An output current I1 of the differential amplifier circuit 12 output from between the drain of the pMOS 15 and the collector of the transistor 17 is input to the inverting input terminal of the operational amplifier 13.
A resistor Rf1 is connected between the output terminal and the inverting input terminal of the operational amplifier 13, and the operational amplifier 13 and the resistor Rf1 convert a current I1 into a voltage V1 and output a current-voltage conversion circuit (transimpedance circuit). It is composed. The voltage VC is input to the non-inverting input terminal of the operational amplifier 13.

  The differential amplifying unit 2 includes an nMOS (current mirror) 21, a pMOS 24 and 25, transistors 26 and 27, a resistor Rm2, a differential amplifier circuit 22 including a current source, an operational amplifier 23, and a resistor Rf2. ing.

The nMOS 21 constitutes a current source through which 2 × I _OFF (offset current) flows.
The nMOS 21 and the differential amplifier circuit 22 constitute a voltage-current conversion circuit (transconductance circuit) that converts the voltage difference between the signals VP and VM into a current difference.

  The differential amplifier circuit 22 includes pMOSs 24 and 25, transistors 26 and 27, a resistor Rm2 having a resistance value equal to that of the resistor Rm1, and two current sources each outputting a current Io. The source of the pMOS 24 is connected to the power supply, and the drain is connected to the collector of the transistor 26. The source of the pMOS 25 is connected to the power supply, and the drain is connected to the collector of the transistor 27. The gates of the pMOS 24 and pMOS 25 are connected to the drain of the pMOS 24, respectively. The base of the transistor 26 is connected to the input terminal in12 for inputting the signal VM, and the base of the transistor 27 is connected to the input terminal in11 for inputting the signal VP.

The emitter of the transistor 26 and the emitter of the transistor 27 are connected to separate constant current sources, respectively.
The emitter of the transistor 26 and the emitter of the transistor 27 are connected to each other via a resistor Rm2.

The nMOS 21 has a drain connected to the emitter of the transistor 27 and is provided in parallel with the constant current source.
The output current I2 of the differential amplifier circuit 22 output from between the drain of the pMOS 25 and the collector of the transistor 27 is input to the inverting input terminal of the operational amplifier 23.

  A resistor Rf2 having a resistance value equal to the resistor Rf1 is connected between the output terminal and the inverting input terminal of the operational amplifier 23, and the operational amplifier 23 and the resistor Rf2 convert the current I2 into the voltage V2 and output it. A circuit (transimpedance circuit) is configured. The voltage VC is input to the non-inverting input terminal of the operational amplifier 23.

The error amplifying unit 3 includes resistors R3 and R4, an operational amplifier 24, a resistor Rf3, and a capacitor C1.
The voltage V1 output from the operational amplifier 13 is connected to the inverting input terminal of the operational amplifier 24 through the resistor R3. On the other hand, the voltage V2 output from the operational amplifier 23 is connected to the inverting input terminal of the operational amplifier 24 through the resistor R4. That is, the connection point between the resistor R3 and the resistor R4 and the inverting input terminal of the operational amplifier 24 are connected to each other.

A resistor Rf3 and a capacitor C1 are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 24, respectively.
The output terminal of the operational amplifier 24 is connected to the gates of the nMOSs 11 and 21.

The comparator 5 includes an nMOS 51, a comparator (differential amplifier circuit) 52, and an inverter inv1.
The nMOS 51 constitutes a current source through which a current of 4/3 × I _OFF flows.

The nMOS 51 and an nMOS 61 to be described later constitute a current source through which a current mirror output 2 * I _OFF · k having a predetermined ratio with respect to the nMOSs 11 and 21 flows. The coefficient k varies depending on the number of differential signal divisions. In this embodiment, since a four-value differential signal is used, it is necessary to divide into four (1, 1/3, −1/3, −1), and k = 2/3 is set.

The comparator 52 includes pMOSs 54 and 55, transistors 56 and 57, a resistor Rm5, and two constant current sources that output currents Io, respectively.
The comparator 52 is the same as the differential amplifier circuit 12 in its configuration and the constants of each element, and detailed description thereof is omitted.

The pMOS 51 is connected to the emitter of the transistor 57 in parallel with the constant current source.
The comparator 52 receives the signal VP from the transistor 56 and the signal VM from the transistor 57.

The comparator 52 outputs Hi when the potential difference between the signal VP and the signal VM is larger than Rm5 × I _OFF × 2/3, and outputs Lo when the potential difference is small.
The inverter inv1 outputs a voltage (Hi or Lo signal) obtained by inverting the polarity of the current output from the comparator 52 to the selector.

The comparator 6 includes an nMOS 61, a comparator (differential amplifier circuit) 62, and an inverter inv2.
The comparator 62 includes pMOSs 64 and 65, transistors 66 and 67, a resistor Rm6, and two constant current sources that output currents Io, respectively.

The comparator unit 6 has the same configuration and constants for each element as the comparator unit 5, and a detailed description thereof will be omitted.
The comparator 62 receives the signal VP from the transistor 67 and VM from the transistor 66.

The comparator 62 outputs Hi when the potential difference between the signal VP and the signal VM is larger than Rm6 × I _OFF × 2/3, and outputs Lo when the potential difference is small.
The nMOS 11 of the data / clock separation circuit 330 corresponds to the variable offset circuit 31 of the data / clock separation circuit 30. Similarly, the differential amplifier circuit 12 corresponds to the differential amplifier 33, the nMOS 11 corresponds to the variable offset circuit 31, the differential amplifier circuit 22 corresponds to the differential amplifier 34, the resistors R3, R4, and the operational amplifier 24. Is connected to the inverting input terminal of the inverting input terminal, the operational amplifier 24, the resistor Rf3, and the capacitor C1 are equivalent to the LPF 36 and the error amplifier 37, the nMOS 51 is equivalent to the variable offset circuit 31, and the comparator 52 is the comparator 40. The nMOS 61 corresponds to the variable offset circuit 39, and the comparator 62 corresponds to the comparator 41.

Next, the operation of the data / clock separation circuit 330 will be described.
Since the transconductance of the nMOS 11 and the differential amplifier circuit 12 is approximately Rm1, the offset voltage is Rm1 · I _OFF , and the output current I1 is expressed by the equation (1).
_{I1 = (VP-VM-Rm1} · I OFF) / Rm1 ··· (1)
Further, the output voltage V1 of the operational amplifier 13 is expressed by Expression (2).
V1 = (VP−VM−Rm1 · I _OFF ) · Rf1 / Rm1 + VC (2)
However, Expression (2) is established only in the linear region, and the output for an excessive input (VP-VM-Rm1 · I _OFF ) is saturated as shown in FIG.

The output current I2 and the output voltage V2 can be derived in the same manner.
The output voltages V1 and V2 from the differential amplifiers 1 and 2 are added by the operational amplifier 13 and compared with the reference voltage _VREF to detect an error and apply an LPF. As a result, the voltage V3 output from the operational amplifier 24 is supplied to the gates of the nMOSs 11 and 21 (controls the current mirror circuit), thereby forming a negative feedback loop. By this loop, the data / clock separation circuit 330 operates so as to reduce the magnitude of the voltage V3, and the offset voltages Rm1 · I _OFF and Rm2 · I _OFF both converge near the maximum amplitude values of the signals VP and VM. To do.

Since the nMOS 51 and the nMOS 61 of the comparators 5 and 6 constitute current sources through which a current of 4/3 × I _OFF flows, the offset voltage of the comparator 5 is the maximum amplitude value of the signals VP and VM. The value becomes 2/3 times (hereinafter referred to as a threshold signal). Thereby, as described above, the comparator 5 inputs the signals VP and VM, outputs Hi when a signal equal to or higher than the threshold signal 2/3 is input, and inputs a signal less than the threshold signal 2/3. When it is done, Lo is output. The comparator 6 receives the signals VP and VM, outputs Hi when a signal equal to or lower than the threshold signal −2/3 is input, and receives a signal larger than the threshold signal −2/3. Output Lo.

Next, the frequency multiplication circuit 340 and the phase adjustment circuit 350 will be described.
FIG. 12 is a circuit diagram of the frequency multiplication circuit and the phase adjustment circuit.
The frequency multiplying circuit 340 includes a PFD 341, a charge pump circuit 342, an LPF 343, and a VCO 344, and FFs 345, 346,..., 349 functioning as 1/10 frequency dividing circuits. The phase adjustment circuit 350 is connected between the charge pump circuit 342 and the LPF 343.

  Here, when the UP signal is input from the PFD 341, the charge pump circuit 342 turns on the switch SW1, and charges the capacitor of the LPF 343 with the charge pump current Icp. When the DOWN signal is input from the PFD 341, the switch SW2 is turned on, the capacitor of the LPF 343 is discharged, and the charge pump current Icp is supplied.

  The phase adjustment circuit 350 has a function of generating an offset current Icp · α / 10 and adding this to the charge pump current Icp to lock the reception bit clock with a fixed time lag with respect to the reception word clock. ing. In the serial / parallel conversion circuit 360, the reception bit clock for converting the reception serial data to the reception parallel data is usually aligned with the edge of the reception serial data, and the conversion may be inaccurate. The phase adjustment circuit 350 generates a time lag and makes it possible to set the edge of the reception bit clock to the noise margin maximum point where the eye pattern of the reception serial data is most stably opened.

  This adjustment is performed using the property that the ratio between the received word clock period and the time lag is equal to the ratio between the charge pump current and the offset current. Since the receive word clock period is a constant multiple of the symbol rate and is equal to 1 bit time of serial data, appropriate setting of the ratio of charge pump current and offset current is accurate and stable at the time with the largest noise margin of received serial data It is possible to adapt to. Furthermore, as disclosed in Japanese Patent No. 3395818, the phase can be adjusted with higher accuracy by applying this offset current on the pulse.

FIG. 13 is a circuit diagram of a serial / parallel conversion circuit of the data receiving apparatus.
The serial-parallel conversion circuit 360 shown here is a circuit for reproducing 10-bit reception parallel data equal to transmission parallel data from 1-bit reception serial data.

  The serial / parallel conversion circuit 360 is a circuit that converts the received serial data S0 into parallel data D0 to D9 (received parallel data), and the ten D-FFs 361, 362, 363,. 370 and ten D-FFs 371, 372, 373,..., 380 constituting a parallel register.

  The D-FFs 361 to 370 constituting the shift register are connected in series, and the received serial data S0 is input to the first-stage D-FF 361. The reception bit clock is supplied as a shift trigger to the clock terminals of the D-FFs 361 to 370.

  Outputs of the D-FFs 361 to 370 are input to input terminals of the D-FFs 371 to 380 constituting the parallel register, respectively, and a reception data clock is input to the clock terminal to be triggered. The reception parallel data that is the same as the transmission parallel data can be reproduced by correctly sampling the received serial data flowing through the shift register by this trigger. This is because the word clock determines the parallel / serial conversion timing in the data transmission apparatus, and therefore, the MSB, which means the word clock, is continuously changed from the L (Low) level to the H level in the quaternary symbols transmitted continuously. This is because it is possible to make a rule so that the rising edge becomes the beginning of a word in the serial / parallel conversion circuit 360.

With such a configuration, the received serial data S0 is captured according to the received bit clock, and the data D0 to D9 are output in parallel according to the received data clock.
As described above, according to the data transmission system of the present embodiment, by providing the data / clock separation circuit 330, the offset used to identify the quaternary differential signal is the maximum value of the signal actually received. (Automatically) so that the maximum value is always obtained regardless of individual differences between the data transmitting apparatus 100 and the data receiving apparatus 300, fluctuations due to changes in operating temperature, operating voltage, etc. This makes it possible to discriminate with a noise margin, thereby improving the transmission reliability.

  In addition, since the multilevel logic signal can be identified stably even when the amplitude of the transmission signal is relatively small, it is possible to reduce the power consumption of the transmitter by reducing the amplitude of the signal. Unwanted radiation from the transmission line 200 can be suppressed.

  In addition, in order to obtain the maximum amplitude value of the quaternary signal, the maximum value detection accuracy is reduced due to sudden noise superposition compared to, for example, a separate circuit for generating an identification offset using peak hold. And a stable offset can always be generated. As a result, highly reliable four-value identification becomes possible.

  Further, in this case, the circuit manufacturing of the data transmission device 100 and the data reception device 300 is remarkably facilitated, so that the data transmission device 100 and the data reception device 300 with high productivity can be manufactured.

  Furthermore, even if the frame synchronization required in the general method for detecting the amplitude of the frame slot is not established, the quaternary signal can be stably identified, so that the preamble signal for frame synchronization can be identified. A processing system is not required, or quaternary signals can be identified independently of frame synchronization. Thereby, various communication procedures can be realized.

  In addition, since a multi-valued logic signal is used to convolve a word clock as clock information together with data into a transmission path, clock extraction and reproduction in the receiving apparatus can be configured by a comparator and a frequency multiplication circuit. This is a general clock superposition method, which is more stable than the clock recovery PLL required in the method of transmitting the clock phase at the transmission signal transition time, and is a harmonic lock phenomenon that extracts a frequency different from the clock. Does not occur.

  In addition, the clock information superimposed on the data using the multi-level logic signal is a word clock indicating the position of the beginning of the word when the data is serial-converted. There is no need for complicated processing such as transmitting a special signal for indicating the head. This simplifies the configuration of the transmitter / receiver, and when the operation of the serial / parallel converter circuit of the receiver is disturbed due to noise or the like, the word clock is always transmitted without waiting for the transmission of the next special signal. It has the advantage of being able to quickly return to normal operation.

  In the present embodiment, the comparators 5 and 6 are provided to separate the word clock from the quaternary logic signal. However, the comparator accords with the number of threshold levels of the received multilevel logic signal. A plurality (minimum of two) are provided.

  For example, if the maximum amplitude is a 7-value logic signal of −3 Vo to 3 Vo, it has −2.5 Vo, −1.5 Vo, −0.5 Vo, 0.5 Vo, 1.5 Vo, 2.5 Vo as threshold values 6 Two comparators are provided.

Next, a second embodiment of the data transmission system will be described.
FIG. 14 is a configuration diagram of a data transmission system according to the second embodiment.
Hereinafter, the data transmission system according to the second embodiment will be described with a focus on differences from the data transmission system according to the first embodiment described above, and description of similar matters will be omitted.

The data transmission system of the second embodiment is the same as the first embodiment except for the configuration of the data / clock separation circuit.
FIG. 15 is a circuit diagram showing a data / clock separation circuit according to the second embodiment.

In the data receiving device 300a, the data / clock separation circuit 330a includes nMOSs 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, and 22a, pMOSs 19a, 20a, and 21a, and resistance values are R _X (Ω), respectively. There are certain resistors R1a, R2a, R3a, R4a, R5a, R6a, a capacitor C, comparators 23a, 24a, and comparators and selectors for reproducing the received serial data from the signals VP and VM.

  In FIG. 15, the functions and configurations of the comparator and the selector are the same as the functions and configurations of the comparator 42 and the selector 43 shown in FIG.

  The nMOS 11a constitutes a source follower. When the signal VP is input to the gate, the nMOS 11a supplies a voltage proportional to the gate voltage to the resistor R1a. The nMOS 12a also constitutes a source follower. When the signal VN is input to the gate, a voltage proportional to the gate voltage is supplied to the resistor R4a.

  The resistors R1a, R2a, and R3a are connected in series in this order. The opposite side of the resistor R3a from the resistor R2a is connected to the drain of the nMOS 13a. The resistors R4a, R5a, and R6a are also connected in series in this order. The side of the resistor R6a opposite to the resistor R5a is connected to the drain of the nMOS 14a.

The gate of the nMOS 13a and the gate of the nMOS 14a are connected to each other. Thereby, when the gate of the nMOS 13a and the gate of the nMOS 14a are ON, the same current _IOFFa flows through the drains of the nMOS 13a and the nMOS 14a.

The nMOS 15a and the nMOS 16a constitute a differential amplifier, and outputs a current proportional to the difference between the voltages input from the gates from the drain of the nMOS 16a.
The gate of the nMOS 15a is connected between the source of the nMOS 11a and the resistor R1a. The gate of the nMOS 16a is connected between the resistor R6a and the drain of the nMOS 14a.

The source of the nMOS 15a and the source of the nMOS 16a are connected to a current source through which the constant current I1 flows.
The nMOS 17a and the nMOS 18a also constitute a differential amplifier, and outputs a current proportional to the difference between the voltages input from the gates from the drain of the nMOS 18a.

  The gate of the nMOS 17a is connected between the resistor R3a and the drain of the nMOS 13a. The gate of the nMOS 18a is connected between the source of the nMOS 12a and the resistor R4a.

The source of the nMOS 17a and the source of the nMOS 18a are connected to a current source through which the constant current I1 flows.
The drain of the nMOS 16a and the drain of the nMOS 17a are connected to each other, and the drain current of the nMOS 16a and the drain current of the nMOS 17a are added at the node X. That is, the node X constitutes an adding unit.

The pMOS 19a and the pMOS 20a operate as a current mirror circuit, and a constant current I1 / 4 flows through the drain of the pMOS 20a. This constant current I1 / 4 corresponds to the reference voltage _VREF of the first embodiment, and acts as a reference current for determining the reference voltages of the comparators 23a and 24a.

The node X and the drain of the pMOS 20a are connected to each other at the node Y, and the current of the node X and the drain current of the pMOS 20a are added at the node Y.
The capacitor C corresponds to the current-voltage conversion circuit / LPF of the first embodiment.

Capacitor C is charged when the current at node Y is equal to or greater than I / 4, and capacitor C is discharged when the current at node Y is less than I / 4.
The pMOS 21a has a source connected to the power supply VDD, a gate connected to the node Y, and a drain connected to the drain of the nMOS 22a.

  In the nMOS 22a, the source is connected to the GND, and the drain and the gate are connected to each other. The gate of the nMOS 22a is connected to the gates of the nMOSs 13a and 14a. As a result, a current mirror circuit in which the drain current of the nMOS 22a is proportional to the drain currents of the nMOSs 13a and 14a is obtained.

The non-inverting input terminal of the comparator 23a is connected between the source of the nMOS 12a and the resistor R4a, and the inverting input terminal is connected between the resistor R2a and the resistor R3a.
The non-inverting input terminal of the comparator 24a is connected between the source of the nMOS 11a and the resistor R1a, and the inverting input terminal is connected between the resistor R5a and the resistor R6a.

Next, the operation of the data / clock separation circuit 330a will be described.
When the signals VP and VM are input, the source follower output of the signal VP is applied to the gate of the nMOS 15a, and the signal obtained by lowering the source follower output of the signal VM by a fixed potential of 3Rx · I _OFF is applied to the gate of the nMOS 16a. Is done. This fixed potential corresponds to the offset of the nMOS 15a and nMOS 16a when the signals VP and VM are input. A source follower output of the signal VM is applied to the gate of the nMOS 18a, and a signal obtained by lowering the source follower output of the signal VP by a fixed potential of 3Rx · I _OFF is applied to the gate of the nMOS 17a. This fixed potential corresponds to an offset between the nMOS 17a and the nMOS 18a when the signals VP and VM are inputted.

  When this offset is equal to the maximum amplitude of signal VP, the voltages applied to the gates of nMOS 17a and nMOS 18a are equal, and the drains of nMOS 17a and nMOS 18a draw current I1 / 2, which is the midpoint of the constant current. On the other hand, when the offset is equal to the maximum amplitude of signal VM, the voltages applied to the gates of nMOS 15a and nMOS 16a are equal, and the drains of nMOS 15a and nMOS 16a draw current I1 / 2, which is the midpoint of the constant current, respectively. .

  Therefore, when these outputs are added, the current I1 / 2 is drawn when the absolute value of the input differential voltage becomes maximum, that is, during reception of the time mark. Therefore, the time average value of the output current at the node X is a value obtained by multiplying I1 / 2 by 1/2 (mark rate). Therefore, the time average value of the output current is I1 / 4.

The constant current flowing through the drain of the pMOS 20a is set to be equal to this time average value.
Here, when the offset does not reach the absolute value of the input differential voltage, the time average value of the output current at the node X becomes larger than I1 / 4 as shown in FIG. When the absolute value exceeds the time average value, the time average value at the node X is smaller than I1 / 4 as shown in FIG.

At node Y, the output current from node X is compared with the drain current of pMOS 20a.
When the output current from the node X is larger than I1 / 4, the capacitor C is charged and the negative voltage input to the gate of the pMOS 21a becomes small, so that the drain voltage of the pMOS 21a decreases. As a result, the gate voltages of the nMOSs 13a and 14a are reduced, the drain currents of the nMOSs 13a and 14a are reduced, and the output current of the node X is reduced.

  On the other hand, when the output current from the node X is smaller than I1 / 4, the capacitor C is discharged and the negative voltage input to the gate of the pMOS 21a increases, so that the drain voltage of the pMOS 21a increases. As a result, the gate voltages of the nMOSs 13a and 14a increase, the drain currents of the nMOSs 13a and 14a increase, and the output current of the node X increases.

Thus, the offset 3Rx · I _OFF is controlled so as to converge to a large amplitude (maximum absolute value) of the input differential voltage by negative feedback.
By the way, since the offset 3Rx · I _OFF becomes equal to the maximum absolute value of the quaternary differential voltage, the voltage value between the resistors R2a and R3a and the voltage value between the resistors R5a and R6a are respectively Rx · I _OFF. That is, 1/3 of the maximum absolute value. Since this voltage value is applied to the non-inverting input terminals of the comparators 23a and 24a, the comparators 23a and 24a accurately output the quaternary differential signal with a threshold of 1/3 of the maximum absolute value of the input differential voltage. Can be identified.

According to the data transmission system of the second embodiment, the same effect as the data transmission system of the first embodiment can be obtained.
According to the data transmission system of the second embodiment, since the configuration of the data / clock separation circuit can be simplified, the entire system can be simplified and reduced in size.

  As described above, the data receiving apparatus and the data transmission system of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary one having the same function. It can be replaced with that of the configuration. Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
In each of the embodiments described above, a quaternary logic signal is used as a multi-value logic signal. However, the present invention is not limited to this, and can be applied to a logic signal having an arbitrary value.

  In the above description, in the data receiving apparatuses 300 and 300a, the comparison unit has been described as being configured by a plurality of comparators that extract the reception bit clock and the reception word clock from the multilevel logic signal. May be.

  For example, the present invention can be applied to digital transmission to a high-definition color liquid crystal monitor of a computer.

It is a block diagram of the data transmission system of 1st Embodiment. It is a circuit diagram of the parallel-serial conversion circuit of a data transmitter. It is a circuit diagram of the frequency 10 multiplication circuit of a data transmitter. It is a circuit diagram of a quaternary logic signal generation circuit. It is a figure which shows a response | compatibility with 4-value logic and transmission data. It is a figure which shows the quaternary differential signal generated from a quaternary logic signal generation circuit. It is a circuit diagram which shows a cascode circuit and a termination resistance adjustment circuit. It is a principle figure which shows the principle of the data clock separation circuit of 1st Embodiment. (A)-(c) is a figure which shows operation | movement of the differential amplifier with respect to a differential signal. It is a figure which shows the change of the output sum with respect to the change of an offset. 1 is a circuit diagram showing a data / clock separation circuit according to a first embodiment; FIG. It is a circuit diagram of a frequency multiplication circuit and a phase adjustment circuit. It is a circuit diagram of the serial-parallel conversion circuit of a data receiver. It is a block diagram of the data transmission system of 2nd Embodiment. It is a circuit diagram which shows the data clock separation circuit of 2nd Embodiment.

Explanation of symbols

12, 22... Differential amplifier circuit 31, 32, 38, 39... Variable offset circuit (offset voltage adjustment circuit), 33, 34... Differential amplifier, 37 .. Error amplifier, 40, 41. , 100... Data transmission device, 110... Parallel / serial conversion circuit, 130... Frequency multiplying circuit, 140... Quaternary logic signal generation circuit, 200. Device, 330, 330a ... Data / clock separation circuit, 340 ... Frequency multiplier, 360 ... Serial / parallel conversion circuit

Claims (8)

In a data receiving apparatus that receives a multi-value logic signal having a plurality of amplitude values,
Based on the control signal for controlling the comparison voltage, and a voltage generator for generating a voltage for the comparison from the multi-value logic signals,
A comparator for comparing a difference between the multi-value logic signal and the comparison voltage with a predetermined reference signal;
Based on the output of the comparison unit, a voltage control unit that generates the control signal so that the comparison voltage has the maximum amplitude of the multilevel logic signal, and outputs the control signal to the voltage generation unit ;
A proportional threshold value generator for generating a threshold value proportional to the comparison voltage;
A comparator that compares the threshold and the multi-valued logic signal;
A data receiving apparatus comprising:   The data receiving apparatus according to claim 1, wherein a magnitude of the comparison voltage is equal to a maximum amplitude value among the plurality of amplitude values.   The data receiver according to claim 1, wherein the comparator is provided corresponding to the number of the amplitude values. The voltage generation unit includes a differential amplifier circuit that amplifies and outputs a differential multilevel logic signal by offsetting the comparison voltage,
The data receiving apparatus according to claim 1, wherein the voltage control unit is configured to control an offset of the differential amplifier circuit. The multi-level logic signal has a POS signal with a positive polarity and a NEG signal with a negative polarity;
5. The data receiving apparatus according to claim 4, wherein the differential amplifier circuit is provided with an offset corresponding to the POS signal and the NEG signal. The multi-level logic signal is a signal in which information of a plurality of bits obtained by adding a word clock for each bit representing a word delimiter in serial data to be transmitted is expressed by one symbol.
2. The data receiving apparatus according to claim 1, wherein the comparator outputs a signal corresponding to the word clock from the multilevel logic signal.   7. The data receiving apparatus according to claim 6, wherein the maximum amplitude of the multilevel logic signal is an amplitude of a portion corresponding to a word clock of the multilevel logic signal. In a data transmission system that transmits multi-bit data,
Converts multi-bit parallel data to be transmitted into serial data, and generates a multi-value logic signal representing one-symbol multi-bit information by adding a word clock indicating a word delimiter in the serial data as one-bit information A data transmission device for sending
Receives the sent the multi-level logic signal, and generates the comparison voltage from the multi-value logic signal on the basis of a control signal for controlling the comparison voltage, the difference between the multi-value logic signal and the comparison voltage compared with a predetermined reference signal based on the comparison result, together with the comparison voltage for controlling the maximum of the comparison voltage and generates the control signal such that the amplitude of the multi-value logic signal, the comparison The serial data and the word clock are extracted from the multi-level logic signal by comparing a threshold proportional to the voltage for use with the multi-level logic signal, and the parallel data is extracted based on the extracted word clock. A data receiving device to be reproduced;
A data transmission system comprising:

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