JP4936009B2 - Semiconductor device, semiconductor module and manufacturing method thereof - Google Patents

Semiconductor device, semiconductor module and manufacturing method thereof Download PDF

Info

Publication number
JP4936009B2
JP4936009B2 JP2008051967A JP2008051967A JP4936009B2 JP 4936009 B2 JP4936009 B2 JP 4936009B2 JP 2008051967 A JP2008051967 A JP 2008051967A JP 2008051967 A JP2008051967 A JP 2008051967A JP 4936009 B2 JP4936009 B2 JP 4936009B2
Authority
JP
Japan
Prior art keywords
wirings
resin protrusion
semiconductor substrate
electrodes
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008051967A
Other languages
Japanese (ja)
Other versions
JP2009212204A (en
Inventor
直也 佐藤
明仁 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2008051967A priority Critical patent/JP4936009B2/en
Publication of JP2009212204A publication Critical patent/JP2009212204A/en
Application granted granted Critical
Publication of JP4936009B2 publication Critical patent/JP4936009B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Description

本発明は、半導体装置並びに半導体モジュール及びその製造方法に関する。   The present invention relates to a semiconductor device, a semiconductor module, and a manufacturing method thereof.

半導体チップに長尺状の樹脂突起を形成し、その上に複数の配線を形成して、弾力性を有する端子を形成することが知られている（特許文献１）。しかし、特許文献１には、複数の配線間で、配線を構成する金属が移動して絶縁不良を起こすマイグレーションの対策について開示されていない。
特開２００７−４２８６７号公報 It is known that a long resin protrusion is formed on a semiconductor chip and a plurality of wirings are formed thereon to form a terminal having elasticity (Patent Document 1). However, Patent Document 1 does not disclose a countermeasure against migration that causes insulation failure due to movement of a metal constituting a wiring between a plurality of wirings.
JP 2007-42867 A

本発明は、マイグレーションの発生を抑制することを目的とする。   An object of the present invention is to suppress the occurrence of migration.

（１）本発明に係る半導体モジュールは、
集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
前記複数の配線の前記樹脂突起上の部分にそれぞれ接触する複数のリードと、
前記複数のリードが形成された弾性基板と、
前記半導体基板の前記前記樹脂突起が形成された面と、前記弾性基板の前記複数のリードが形成された面と、の間で間隔を保持する接着剤と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記端部が前記溝内に入るように、前記複数の配線が屈曲している。本発明によれば、複数の配線が、隣同士に対向する端部が溝内に入るように屈曲しているので、隣同士の配線間の間隔が広くなり、マイグレーションの発生を抑制することができる。
（２）本発明に係る半導体モジュールの製造方法は、
半導体装置を、複数のリードが形成された弾性基板に搭載する工程を含み、
前記半導体装置は、
集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記工程で、
前記複数のリードを、前記複数の配線の前記樹脂突起上の部分に対向させ、
前記半導体装置と前記弾性基板の間に押圧力を加えて、前記複数の配線の前記樹脂突起上の部分を前記複数のリードに押圧し、
前記押圧力によって、前記弾性基板を弾性変形させて、前記弾性基板の一部によって前記複数の配線の前記端部を前記複数の溝内に押圧して、前記複数の配線を、前記端部が前記溝に入り込むように屈曲させる。本発明によれば、複数の配線を、隣同士に対向する端部が溝内に入るように屈曲させるので、隣同士の配線間の間隔を広くして、マイグレーションの発生を抑制することができる。
（３）本発明に係る半導体装置は、
集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記端部は、前記溝内に突出している。本発明によれば、複数の配線を、隣同士に対向する端部が溝内に入るように屈曲させると、隣同士の配線間の間隔を広くすることができるので、これによりマイグレーションの発生を抑制することができる。 (1) A semiconductor module according to the present invention comprises:
A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
A plurality of leads each contacting a portion on the resin protrusion of the plurality of wirings;
An elastic substrate on which the plurality of leads are formed;
An adhesive that maintains a gap between the surface of the semiconductor substrate on which the resin protrusions are formed and the surface of the elastic substrate on which the leads are formed;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
The plurality of wirings are bent so that the end portion enters the groove. According to the present invention, since the plurality of wirings are bent so that the end portions facing each other enter the groove, the interval between the adjacent wirings is widened, and the occurrence of migration can be suppressed. it can.
(2) A method for manufacturing a semiconductor module according to the present invention includes:
Including a step of mounting a semiconductor device on an elastic substrate on which a plurality of leads are formed,
The semiconductor device includes:
A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
In the process,
The plurality of leads are opposed to portions on the resin protrusions of the plurality of wirings,
Applying a pressing force between the semiconductor device and the elastic substrate, pressing the portions on the resin protrusions of the plurality of wirings against the plurality of leads,
The elastic substrate is elastically deformed by the pressing force, the end portions of the plurality of wirings are pressed into the plurality of grooves by a part of the elastic substrate, and the end portions of the plurality of wirings are It is bent so as to enter the groove. According to the present invention, the plurality of wirings are bent so that the ends facing each other enter the groove, so that the interval between the adjacent wirings can be widened to suppress the occurrence of migration. .
(3) A semiconductor device according to the present invention includes:
A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
The end protrudes into the groove. According to the present invention, if a plurality of wirings are bent so that the ends facing each other are in the groove, the interval between the adjacent wirings can be widened. Can be suppressed.

（半導体装置）
図１は、本発明の実施の形態に係る半導体装置を示す平面図である。図２は、図１に示す半導体装置のII-II線断面図であり、図３は、図１に示す半導体装置のIII-III線断面図である。 (Semiconductor device)
FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II of the semiconductor device shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of the semiconductor device shown in FIG.

半導体装置１は、半導体基板１０を有する。半導体基板１０は、図１では半導体チップであるが、変形例として半導体ウエハであってもよい。半導体チップである半導体基板１０は、矩形の面を有している。半導体基板１０には、集積回路１２（トランジスタ等）が形成されている。半導体基板１０には、集積回路１２に電気的に接続されるように、複数の電極１４が形成されている。複数の電極１４は、１列又は複数列（平行な複数列）に並んでいる。電極１４は、半導体基板１０の矩形の面の辺（例えば長方形の長辺）に沿って（平行に）並んでいる。半導体基板１０が半導体ウエハであれば、複数の集積回路１２が形成され、それぞれの集積回路について複数の電極１４が形成される。電極１４は、内部配線（図示せず）を介して集積回路１２に電気的に接続されている。半導体基板１０には、電極１４の少なくとも一部が露出する様に、電極１４上に位置する開口を有する絶縁膜１６（例えばパッシベーション膜）が形成されている。絶縁膜１６は、例えば、ＳｉＯ２やＳｉＮ等の無機材料のみで形成されていてもよい。絶縁膜１６は、集積回路１２の上方に形成されている。 The semiconductor device 1 has a semiconductor substrate 10. The semiconductor substrate 10 is a semiconductor chip in FIG. 1, but may be a semiconductor wafer as a modification. The semiconductor substrate 10 which is a semiconductor chip has a rectangular surface. An integrated circuit 12 (transistor or the like) is formed on the semiconductor substrate 10. A plurality of electrodes 14 are formed on the semiconductor substrate 10 so as to be electrically connected to the integrated circuit 12. The plurality of electrodes 14 are arranged in one row or a plurality of rows (a plurality of parallel rows). The electrodes 14 are arranged along (in parallel with) a side of a rectangular surface of the semiconductor substrate 10 (for example, a long side of the rectangle). If the semiconductor substrate 10 is a semiconductor wafer, a plurality of integrated circuits 12 are formed, and a plurality of electrodes 14 are formed for each integrated circuit. The electrode 14 is electrically connected to the integrated circuit 12 via internal wiring (not shown). An insulating film 16 (for example, a passivation film) having an opening located on the electrode 14 is formed on the semiconductor substrate 10 so that at least a part of the electrode 14 is exposed. The insulating film 16 may be formed of only an inorganic material such as SiO 2 or SiN. The insulating film 16 is formed above the integrated circuit 12.

半導体基板１０（絶縁膜１６上）には、樹脂突起１８が設けられている。半導体基板１０の矩形の面の辺（例えば長方形の長辺）に沿って（平行に）延びる樹脂突起１８が示されており、複数の樹脂突起１８が平行に配列されている。樹脂突起１８は弾性体からなる。樹脂突起１８の材料としては、例えばポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）、アクリル樹脂、シリコーン樹脂、フェノール樹脂等を用いてもよい。   Resin protrusions 18 are provided on the semiconductor substrate 10 (on the insulating film 16). A resin protrusion 18 extending (parallel) along a side (for example, a long side of the rectangle) of the rectangular surface of the semiconductor substrate 10 is shown, and a plurality of resin protrusions 18 are arranged in parallel. The resin protrusion 18 is made of an elastic body. Examples of the material of the resin protrusion 18 include polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), acrylic resin, silicone resin, and phenol. A resin or the like may be used.

樹脂突起１８は長尺状に形成されている。樹脂突起１８は、その延長方向に沿った軸ＡＸ（図１参照）に直交する断面が、図２に示すように弓形（円の弧とその両端を結ぶ弦によってできる図形）をなしている。樹脂突起１８は、その断面において、弓形の弦が絶縁膜１６上に配置されている。樹脂突起１８の表面（半導体基板１０とは反対側を向く面）は、凸曲面になっている。樹脂突起１８の表面は、樹脂突起１８の長手軸を回転軸として、回転軸の周囲に平行に位置する直線を回転させて描かれる回転面である。樹脂突起１８の表面は、円柱を中心軸に平行な平面で切断して得られた形状の曲面（円柱の回転面の一部）の形状をなしている。樹脂突起１８は、上面よりも下面が広くなるように、末広がりの形状になっている。   The resin protrusion 18 is formed in a long shape. As shown in FIG. 2, the cross section of the resin protrusion 18 perpendicular to the axis AX (see FIG. 1) along the extending direction forms an arcuate shape (a figure formed by a circular arc and a string connecting both ends thereof). The resin protrusion 18 has an arcuate string disposed on the insulating film 16 in its cross section. The surface of the resin protrusion 18 (surface facing away from the semiconductor substrate 10) is a convex curved surface. The surface of the resin protrusion 18 is a rotation surface drawn by rotating a straight line positioned in parallel around the rotation axis with the longitudinal axis of the resin protrusion 18 as a rotation axis. The surface of the resin protrusion 18 has a curved surface shape (a part of the rotating surface of the cylinder) obtained by cutting the cylinder along a plane parallel to the central axis. The resin protrusion 18 has a divergent shape so that the lower surface is wider than the upper surface.

半導体基板１０には、複数の配線２０が形成されている。配線２０の材料として、Ａｕ、Ｔｉ、ＴｉＷ、Ｗ、Ｃｒ、Ｎｉ、Ａｌ、Ｃｕ、Ｐｄ又は鉛フリーはんだ等を使用することができる。複数の配線２０は、電極１４上から樹脂突起１８上に至るように形成されている。複数の配線２０は、隣同士の間隔をあけて樹脂突起１８の上面に形成されている。１つの樹脂突起１８上に複数の配線２０が形成されている。配線２０は、樹脂突起１８の延長方向に沿った軸ＡＸ（図１参照）に交差するように延びる。配線２０は、電極１４上から、絶縁膜１６上を通って、樹脂突起１８上に至る。樹脂突起１８上では、配線２０の表面は、樹脂突起１８の表面に従った曲面になっている。配線２０と電極１４は直接接触していてもよいし、両者間に導電膜（図示せず）が介在していてもよい。配線２０は、樹脂突起１８の、電極１４とは反対側の端部を越えて、絶縁膜１６上に至るように形成されている。   A plurality of wirings 20 are formed on the semiconductor substrate 10. As a material for the wiring 20, Au, Ti, TiW, W, Cr, Ni, Al, Cu, Pd, lead-free solder, or the like can be used. The plurality of wirings 20 are formed from the electrode 14 to the resin protrusion 18. The plurality of wirings 20 are formed on the upper surface of the resin protrusion 18 with an interval between adjacent ones. A plurality of wirings 20 are formed on one resin protrusion 18. The wiring 20 extends so as to intersect the axis AX (see FIG. 1) along the extending direction of the resin protrusion 18. The wiring 20 extends from the electrode 14 to the resin protrusion 18 through the insulating film 16. On the resin protrusion 18, the surface of the wiring 20 is a curved surface according to the surface of the resin protrusion 18. The wiring 20 and the electrode 14 may be in direct contact, or a conductive film (not shown) may be interposed between them. The wiring 20 is formed so as to reach the insulating film 16 beyond the end of the resin protrusion 18 opposite to the electrode 14.

図３に示すように、樹脂突起１８の表面には、軸ＡＸに交差する方向に複数の溝１９が形成されている。複数の溝１９は、間隔をあけて形成されている。樹脂突起１８の複数の溝１９は、複数の配線２０が延びる方向に沿って形成されている。隣同士の配線２０の間に１つの溝１９が形成されている。複数の配線２０は、それぞれ、隣の配線２０に対向する端部２１を有する。複数の溝１９は、それぞれ、配線２０の端部２１の下に至るまで形成されている。言い換えると、配線２０の端部２１は、溝１９内（溝１９の上方）に突出し、溝１９上で浮いた状態になっている。   As shown in FIG. 3, a plurality of grooves 19 are formed on the surface of the resin protrusion 18 in a direction intersecting the axis AX. The plurality of grooves 19 are formed at intervals. The plurality of grooves 19 of the resin protrusion 18 are formed along the direction in which the plurality of wirings 20 extend. One groove 19 is formed between the adjacent wirings 20. Each of the plurality of wirings 20 has an end portion 21 that faces the adjacent wiring 20. Each of the plurality of grooves 19 is formed to reach under the end portion 21 of the wiring 20. In other words, the end 21 of the wiring 20 protrudes into the groove 19 (above the groove 19) and floats on the groove 19.

図４は、本実施の形態の溝の形成方法を説明する図である。例えば、樹脂突起１８をその上面が平坦になるように形成し、その上に配線２０を形成する。そして、配線２０をマスクとして、樹脂突起１８をエッチング（例えばドライエッチング）する。エッチングは、樹脂突起１８の配線２０からの露出面に対して垂直に進行するが、さらにエッチングが進むと配線２０の端部２１の下方に向けてサイドエッチングが進む。これによって、図３に示す溝１９を形成することができる。   FIG. 4 is a diagram for explaining the groove forming method of the present embodiment. For example, the resin protrusion 18 is formed so that the upper surface thereof is flat, and the wiring 20 is formed thereon. Then, the resin protrusion 18 is etched (for example, dry etching) using the wiring 20 as a mask. The etching proceeds perpendicularly to the exposed surface of the resin protrusion 18 from the wiring 20, but as the etching proceeds further, side etching proceeds toward the lower side of the end portion 21 of the wiring 20. Thereby, the groove 19 shown in FIG. 3 can be formed.

（半導体モジュールの製造方法）
図５（Ａ）〜図６（Ｄ）は、本発明の実施の形態に係る半導体モジュールの製造方法を説明する図である。本実施の形態では、上述した半導体装置１（半導体基板１０は半導体チップである。）を、接着剤２２を介して、弾性基板２４に搭載する。弾性基板２４は、樹脂などからなるフレキシブル基板であり、弾性変形する性質を有する。弾性基板２４には、リード２６が形成されている。リード２６の延長方向（図５（Ｂ）で紙面の表裏面方向）に直交する幅Ｗ１は、配線２０の延長方向に直交する幅Ｗ２よりも狭い。 (Semiconductor module manufacturing method)
FIG. 5A to FIG. 6D are diagrams illustrating a method for manufacturing a semiconductor module according to an embodiment of the present invention. In the present embodiment, the above-described semiconductor device 1 (the semiconductor substrate 10 is a semiconductor chip) is mounted on the elastic substrate 24 via the adhesive 22. The elastic substrate 24 is a flexible substrate made of resin or the like and has a property of elastic deformation. Leads 26 are formed on the elastic substrate 24. The width W 1 perpendicular to the extension direction of the lead 26 (the front and back direction of the paper in FIG. 5B) is narrower than the width W 2 perpendicular to the extension direction of the wiring 20.

図５（Ａ）〜図５（Ｂ）に示すように、複数のリード２６を、複数の配線２０の樹脂突起１８上の部分に対向させ、リード２６を配線２０の樹脂突起１８上の部分に接触させる。なお、リード２６は、樹脂突起１８の延長方向に沿った軸ＡＸに交差して延びるように配置する。   As shown in FIG. 5A to FIG. 5B, the plurality of leads 26 are opposed to the portions on the resin protrusions 18 of the plurality of wires 20, and the leads 26 are placed on the portions on the resin protrusions 18 of the wires 20. Make contact. The lead 26 is arranged so as to extend across the axis AX along the extending direction of the resin protrusion 18.

図６（Ａ）に示すように、半導体装置１と弾性基板２４の間に押圧力を加える。押圧力によって、複数の配線２０の樹脂突起１８上の部分を複数のリード２６に押圧する。そして、樹脂突起１８を弾性変形させて、配線２０の一部及びリード２６をくい込ませる。さらに、押圧力を加えて、図６（Ｂ）に示すように、リード２６及び配線２０をさらに樹脂突起１８にくい込ませ、配線２０のリード２６に対向する部分の隣接部分を弾性基板２４に接触させる。さらに、図６（Ｃ）に示すように、配線２０のリード２６に対向する部分及びこれに隣接する部分（隣同士の溝１９の間の部分）を介して、樹脂突起１８から弾性基板２４に押圧力を加えて、弾性基板２４を弾性変形させて、弾性基板２４の一部によって、複数の配線２０の端部２１を複数の溝１９内に押圧する。これにより、複数の配線２０を、その端部２１が溝１９に入り込むように屈曲させる。なお、押圧力によって、接着剤２２を、樹脂突起１８の溝１９内で流動させる（例えば排出する）。   As shown in FIG. 6A, a pressing force is applied between the semiconductor device 1 and the elastic substrate 24. The portions on the resin protrusions 18 of the plurality of wirings 20 are pressed against the plurality of leads 26 by the pressing force. Then, the resin protrusion 18 is elastically deformed so that a part of the wiring 20 and the lead 26 are inserted. Further, a pressing force is applied so that the lead 26 and the wiring 20 are further inserted into the resin protrusion 18 and the adjacent portion of the wiring 20 facing the lead 26 is brought into contact with the elastic substrate 24 as shown in FIG. 6B. Let Further, as shown in FIG. 6 (C), the resin protrusion 18 is connected to the elastic substrate 24 through a portion facing the lead 26 of the wiring 20 and a portion adjacent thereto (portion between adjacent grooves 19). The elastic substrate 24 is elastically deformed by applying a pressing force, and the end portions 21 of the plurality of wirings 20 are pressed into the plurality of grooves 19 by a part of the elastic substrate 24. Accordingly, the plurality of wirings 20 are bent so that the end portions 21 enter the grooves 19. The adhesive 22 is caused to flow (for example, discharged) in the groove 19 of the resin protrusion 18 by the pressing force.

図６（Ｄ）に示すように、押圧力を緩めて、樹脂突起１８の弾性力（復元力）によって、樹脂突起１８にくい込んだ配線２０及びリード２６を押し出して、配線２０と弾性基板２４の間に隙間を形成してもよい。ただし、樹脂突起１８が完全に復元しない程度の押圧力は加えておく。そして、熱によって接着剤２２が硬化するまで押圧力を維持する。接着剤２２が硬化したら押圧力を解除する。こうして、半導体モジュールを製造する。   As shown in FIG. 6D, the pressing force is loosened and the wiring 20 and the lead 26 which are hard to be inserted into the resin protrusion 18 are pushed out by the elastic force (restoring force) of the resin protrusion 18 so that the wiring 20 and the elastic substrate 24 are A gap may be formed between them. However, a pressing force is applied so that the resin protrusion 18 is not completely restored. The pressing force is maintained until the adhesive 22 is cured by heat. When the adhesive 22 is cured, the pressing force is released. In this way, a semiconductor module is manufactured.

本実施の形態によれば、複数の配線２０を、隣同士に対向する端部２１が溝１９内に入るように屈曲させるので、隣同士の配線２０間の間隔Ｄ（図６（Ｄ）参照）を広くして、マイグレーションの発生を抑制することができる。   According to the present embodiment, the plurality of wirings 20 are bent so that the end portions 21 facing each other enter the groove 19, so that the interval D between the adjacent wirings 20 (see FIG. 6D). ) Can be widened to suppress the occurrence of migration.

（半導体モジュール）
半導体モジュールは、上述した半導体装置１と、弾性基板２４と、を有する。弾性基板２４は、リード２６の樹脂突起１８とは反対側を支持する。樹脂突起１８の溝１９と弾性基板２４との間と、配線２０のリード２６に対向する部分を除いた部分と弾性基板２４との間には隙間が形成されている。この隙間には、接着剤２２が介在している。接着剤２２は、半導体基板の樹脂突起１８が形成された面と、弾性基板２４の複数のリード２６が形成された面と、の間で間隔を保持する。接着剤２２は硬化収縮している。接着剤２２は、硬化時の収縮による残存ストレスを内在している。 (Semiconductor module)
The semiconductor module includes the semiconductor device 1 described above and the elastic substrate 24. The elastic substrate 24 supports the side of the lead 26 opposite to the resin protrusion 18. A gap is formed between the groove 19 of the resin protrusion 18 and the elastic substrate 24 and between the portion of the wiring 20 excluding the portion facing the lead 26 and the elastic substrate 24. An adhesive 22 is interposed in the gap. The adhesive 22 maintains a gap between the surface of the semiconductor substrate on which the resin protrusions 18 are formed and the surface of the elastic substrate 24 on which the plurality of leads 26 are formed. The adhesive 22 is cured and contracted. The adhesive 22 contains residual stress due to shrinkage during curing.

樹脂突起１８の表面には、複数の配線２０が延びる方向に沿って複数の溝１９が形成されている。隣同士の配線２０の間に１つの溝１９が配置され、複数の配線２０は、それぞれ、隣の配線２０に対向する端部２１を有している。複数の溝１９は、それぞれ、端部２１の下に至るまで形成されている。端部２１が溝１９内に入るように、複数の配線２０が屈曲している。   A plurality of grooves 19 are formed on the surface of the resin protrusion 18 along the direction in which the plurality of wirings 20 extend. One groove 19 is disposed between the adjacent wirings 20, and each of the plurality of wirings 20 has an end portion 21 that faces the adjacent wiring 20. Each of the plurality of grooves 19 is formed to reach under the end portion 21. The plurality of wirings 20 are bent so that the end 21 enters the groove 19.

本実施の形態によれば、複数の配線２０が、隣同士に対向する端部２１が溝１９内に入るように屈曲しているので、隣同士の配線２０間の間隔Ｄ（図６（Ｄ）参照）が広くなり、マイグレーションの発生を抑制することができる。なお、半導体モジュールを有する電子機器として、ノート型パーソナルコンピュータ又は携帯電話などが挙げられる。   According to the present embodiment, since the plurality of wirings 20 are bent so that the end portions 21 that face each other enter the groove 19, the distance D between the adjacent wirings 20 (FIG. 6D (D )) Is widened, and the occurrence of migration can be suppressed. Note that an electronic device having a semiconductor module includes a notebook personal computer or a mobile phone.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明の実施の形態に係る半導体装置を示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. 図２は、図１に示す半導体装置のII-II線断面図である。2 is a sectional view of the semiconductor device shown in FIG. 1 taken along the line II-II. 図３は、図１に示す半導体装置のIII-III線断面図である。3 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line III-III. 図４は、溝の形成方法を説明する図である。FIG. 4 is a diagram for explaining a groove forming method. 図５（Ａ）〜図５（Ｂ）は、本発明の実施の形態に係る半導体モジュールの製造方法を説明する図である。FIG. 5A to FIG. 5B are diagrams illustrating a method for manufacturing a semiconductor module according to an embodiment of the present invention. 図６（Ａ）〜図６（Ｄ）は、本発明の実施の形態に係る半導体モジュールの製造方法を説明する図である。6 (A) to 6 (D) are diagrams illustrating a method for manufacturing a semiconductor module according to an embodiment of the present invention.

符号の説明Explanation of symbols

１…半導体装置、 １０…半導体基板、 １２…集積回路、 １４…電極、 １６…絶縁膜、 １８…樹脂突起、 １９…溝、 ２０…配線、 ２１…端部、 ２２…接着剤、 ２４…弾性基板、 ２６…リード   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 16 ... Insulating film, 18 ... Resin protrusion, 19 ... Groove, 20 ... Wiring, 21 ... End part, 22 ... Adhesive, 24 ... Elasticity Board, 26 ... Lead

Claims (3)

集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
前記複数の配線の前記樹脂突起上の部分にそれぞれ接触する複数のリードと、
前記複数のリードが形成された弾性基板と、
前記半導体基板の前記前記樹脂突起が形成された面と、前記弾性基板の前記複数のリードが形成された面と、の間で間隔を保持する接着剤と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記端部が前記溝内に入るように、前記複数の配線が屈曲している半導体モジュール。 A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
A plurality of leads each contacting a portion on the resin protrusion of the plurality of wirings;
An elastic substrate on which the plurality of leads are formed;
An adhesive that maintains a gap between the surface of the semiconductor substrate on which the resin protrusions are formed and the surface of the elastic substrate on which the leads are formed;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
A semiconductor module in which the plurality of wirings are bent so that the end portion enters the groove. 半導体装置を、複数のリードが形成された弾性基板に搭載する工程を含み、
前記半導体装置は、
集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記工程で、
前記複数のリードを、前記複数の配線の前記樹脂突起上の部分に対向させ、
前記半導体装置と前記弾性基板の間に押圧力を加えて、前記複数の配線の前記樹脂突起上の部分を前記複数のリードに押圧し、
前記押圧力によって、前記弾性基板を弾性変形させて、前記弾性基板の一部によって前記複数の配線の前記端部を前記複数の溝内に押圧して、前記複数の配線を、前記端部が前記溝に入り込むように屈曲させる半導体モジュールの製造方法。 Including a step of mounting a semiconductor device on an elastic substrate on which a plurality of leads are formed,
The semiconductor device includes:
A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
In the process,
The plurality of leads are opposed to portions on the resin protrusions of the plurality of wirings,
Applying a pressing force between the semiconductor device and the elastic substrate, pressing the portions on the resin protrusions of the plurality of wirings against the plurality of leads,
The elastic substrate is elastically deformed by the pressing force, the end portions of the plurality of wirings are pressed into the plurality of grooves by a part of the elastic substrate, and the end portions of the plurality of wirings are A method for manufacturing a semiconductor module, wherein the semiconductor module is bent so as to enter the groove. 集積回路が形成された半導体基板と、
前記半導体基板に形成され、前記集積回路に電気的に接続された複数の電極と、
前記複数の電極上に位置する複数の開口を有して前記半導体基板上に形成された絶縁膜と、
前記絶縁膜上に配置された、長尺状をなす樹脂突起と、
前記複数の電極上から、前記樹脂突起が延びる方向に沿った軸に交差して延び、前記樹脂突起上に至る複数の配線と、
を有し、
前記樹脂突起の表面には、前記複数の配線が延びる方向に沿って複数の溝が形成され、隣同士の前記配線の間に１つの前記溝が配置され、
前記複数の配線は、それぞれ、隣の前記配線に対向する端部を有し、
前記複数の溝は、それぞれ、前記端部の下に至るまで形成され、
前記端部は、前記溝内に突出している半導体装置。 A semiconductor substrate on which an integrated circuit is formed;
A plurality of electrodes formed on the semiconductor substrate and electrically connected to the integrated circuit;
An insulating film having a plurality of openings located on the plurality of electrodes and formed on the semiconductor substrate;
An elongated resin protrusion disposed on the insulating film;
A plurality of wirings extending from above the plurality of electrodes, intersecting an axis along a direction in which the resin protrusion extends, and reaching the resin protrusion;
Have
On the surface of the resin protrusion, a plurality of grooves are formed along a direction in which the plurality of wirings extend, and one groove is disposed between the adjacent wirings.
Each of the plurality of wirings has an end facing the adjacent wiring,
Each of the plurality of grooves is formed to reach under the end,
The semiconductor device in which the end protrudes into the groove.
JP2008051967A 2008-03-03 2008-03-03 Semiconductor device, semiconductor module and manufacturing method thereof Active JP4936009B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008051967A JP4936009B2 (en) 2008-03-03 2008-03-03 Semiconductor device, semiconductor module and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008051967A JP4936009B2 (en) 2008-03-03 2008-03-03 Semiconductor device, semiconductor module and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009212204A JP2009212204A (en) 2009-09-17
JP4936009B2 true JP4936009B2 (en) 2012-05-23

Family

ID=41185090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008051967A Active JP4936009B2 (en) 2008-03-03 2008-03-03 Semiconductor device, semiconductor module and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4936009B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4145902B2 (en) * 2005-07-19 2008-09-03 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2009212204A (en) 2009-09-17

Similar Documents

Publication Publication Date Title
JP4535295B2 (en) Semiconductor module and manufacturing method thereof
JP4572376B2 (en) Semiconductor device manufacturing method and electronic device manufacturing method
JP4352279B2 (en) Semiconductor device and manufacturing method thereof
JP4645832B2 (en) Semiconductor device and manufacturing method thereof
JP4488254B2 (en) Semiconductor module
JP3642414B2 (en) Semiconductor device and manufacturing method thereof
JP4936009B2 (en) Semiconductor device, semiconductor module and manufacturing method thereof
JP5088488B2 (en) Semiconductor module and manufacturing method thereof
JP4936010B2 (en) Semiconductor module and manufacturing method thereof
JP5105103B2 (en) Semiconductor device
JP5088489B2 (en) Semiconductor module and manufacturing method thereof
JP5019060B2 (en) Manufacturing method of semiconductor device
JP5263485B2 (en) Manufacturing method of semiconductor module
JP5077540B2 (en) Manufacturing method of semiconductor device
JP2009212209A (en) Semiconductor module and manufacturing method thereof
JP5217299B2 (en) Semiconductor device and electronic device
JP2009049189A (en) Electronic device
JP2006303169A (en) Semiconductor device
JP6459690B2 (en) Electronic component and manufacturing method thereof
JP2007042805A (en) Wiring board, its manufacturing method, and semiconductor device
JP2006313832A (en) Semiconductor device
JP2009049188A (en) Semiconductor device, its manufacturing method and electronic device
JP2016100533A (en) Electronic component and manufacturing method of the same
JP2009043830A (en) Semiconductor device
JP2012209312A (en) Mounting structure body of electronic component

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120126

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120207

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150302

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4936009

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250