JP4929003B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective for use in a semiconductor integrated circuit device used for RFID (Radio Frequency IDentification) such as a wireless IC tag, a non-contact IC card, and the like.

As an example in which a magnetic field or electromagnetic wave is received by a coil or an antenna like a data carrier or a non-contact IC card, and is rectified and stabilized by a stabilizing voltage circuit, JP-A-2005-202721, JP-A-2003-085506 Japanese Laid-Open Patent Publication Nos. 2002-288615 and 2000-348152.
JP 2005-202721 A JP 2003-085506 A JP 2002-288615 A JP 2000-348152 A

  In an example using a Zener diode as in Patent Document 4, when the power supply voltage exceeds the Zener voltage, a current flows through the Zener diode, and the load of the rectifier circuit is increased to control the power supply voltage. Usually, the breakdown voltage of a Zener diode can only be set to 5V or more.

  For this reason, it cannot be applied to a fine CMOS process (power supply voltage 1.8 V or less). Also, there is a method in which the reference voltage and the power supply voltage are compared, and when the power supply voltage exceeds the reference voltage, a current driving MOSFET (Metal Oxide Field Effect Transistor) is turned on to adjust the load current.

  In this method, an arbitrary power supply voltage can be set, but the actual one can only have a slow feedback loop delay (time constant). This is because of the capacity for countermeasures against oscillation. For this reason, when an ASK modulated signal is received, the power supply voltage fluctuation of the internal circuit becomes large without following the fluctuation of the signal.

  FIG. 33 shows a simplified diagram of a rectifier circuit (rectenna circuit) previously examined by the inventors of the present application. This rectifier circuit includes a two-stage boosting charge pump circuit and an antenna. FIG. 34 shows a circuit diagram of the boost charge pump circuit. FIG. 35 shows a schematic operation timing chart thereof.

  The input voltage Vin is shown in the form of a pulse signal for simplification of the drawing, but is actually a sine wave. In this circuit, a first phase in which the input terminal LA becomes higher than the ground potential VSS (0 V) of the circuit by the input voltage Vin by the radio wave received from the antenna, and the input voltage Vin lower than the ground potential VSS (LB). The second phase is repeated at about 900 MHz corresponding to the received radio wave.

  As shown in FIG. 35, during the second phase, the diode D1 is turned on and -Vin is charged on the input terminal LA side of the capacitor C1. In the next first phase, the diode D1 is turned off, the diode D2 is turned on, and + Vin of the input terminal LA and + Vin held in the capacitor C1 are added to charge 2Vin to the capacitor C2 (node n1).

  In the next second phase, the diode D2 is turned off, the diode D1 is turned on again, and the capacitor C1 is charged with -Vin again. At the same time, the diode D3 is turned on, and the capacitor C3 is charged with -Vin-2Vin (-3Vin).

  In the next first phase, the diodes D1 and D3 are turned off, the diodes D2 and D4 are turned on, and + Vin of the input terminal LA and + Vin held in the capacitor C1 are added to add 2Vin to the capacitor C2 (node n2). ), + Vin of the input terminal LA and + 3Vin held in the capacitor C3 are added to charge 4Vin to the capacitor C4 (node n4).

  By repeating this, a voltage of 4 Vin is generated at the output node n4. When the diodes D1 to D4 are in the ON state, a level loss is generated by the forward voltage Vf. Therefore, actually, a voltage of 4Vin-4Vf is generated at the output node n4.

  The boosting charge pump circuit has a circuit structure in which a voltage four times the input terminal LA-VSS (antenna) voltage Vin is generated at the output node n4-VSS. When the output node n4 becomes equal to or higher than VDD (= 1.5V), a current is supplied from the output node n4 through the resistor R to VDD. When the supply current reaches the chip operating current, normal operation is performed.

  The MOSFETs M1 to M4 clamp the potential of the output node n4 with Vgs voltages corresponding to four N-channel MOSFETs. The reason why the diode-connected MOSFETs of the MOSFETs M1 to M4 are stacked in four stages is that current is not drawn from the output node n4 at the minimum operating power.

  The minimum operating power is that the potential of the output node n4 is about 1.8V. The N-channel MOSFETs are stacked in four stages, so that the potential of the clamp operation minimum output node n4 of the MOSFETs M1 to M4 is set to 0.7V × 4 = 2.8V.

  When the threshold voltage Vth of the MOSFET varies to 0.5V, it becomes 0.5V × 4 = 2V. Even if the threshold voltage Vth varies up to 0.5V, the current is not drawn from the output node n4 unless the voltage is not less than 2V if four stages are stacked.

  If the clamp MOSFET has three stages, 0.5V × 3 = 1.5V, and the output node n4 draws a current from 1.5V, and the chip operation minimum input power increases. The output voltage of the step-up charge pump circuit is an operating voltage of an internal stabilization power supply circuit (not shown) via a resistor R. In consideration of the voltage drop at the resistor R, the output node n4 is 1.5V. However, 1.5V cannot be secured as the operating voltage of the internal circuit.

  Thus, in order to set the operating voltage of the internal circuit to about 1.5 V, the clamp MOSFET needs to have at least four stages.

  The technical problem of the above circuit is that the clamp capability of the potential of the output node n4 is insufficient when a large power is input. Due to insufficient clamping capability, the potential of the output node n4 becomes high, and a MOS breakdown voltage violation of the MOSFET M1 occurs.

  That is, a large voltage is applied to the gate and channel (substrate gate; VSS) of MOSFET M1 to cause dielectric breakdown, or a large voltage to the drain and channel (substrate gate; VSS) is applied to cause junction breakdown.

  Since the current is drawn by the four-stage stacked MOSFETs M1 to M4 and the potential of the output node n4 is clamped, the drawing current is limited by 4 Vgs (gate-source voltage) of the MOSFETs M1 to M4.

  That is, Vgs = Vth + Vov, and the current flowing through the MOSFETs M1 to M4 is determined corresponding to Vov. Here, Vth is a threshold voltage of the MOSFETs M1 to M4. It is necessary to increase the extraction current only when the input power is large, without extracting the current when the input power is small.

  In order to increase the extraction current only at a large input power, it is necessary to increase the size (W / L ratio) of the MOSFETs M1 to M4 so that a large current flows with respect to Vov, and the RFID chip size increases. Problem arises.

  An object of the present invention is to provide a semiconductor integrated circuit device for an RFID capable of efficient and stable operation from a small power input to a large power input with a simple configuration.

  Another object of the present invention is to provide a semiconductor integrated circuit device that ensures a withstand voltage in a rectifier circuit directed to an RFID.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One embodiment in the present application is as follows. That is, the propagated energy is input to the input terminal in the form of an electrical signal. The electric signal at the input terminal is rectified by a rectifier circuit to generate a DC voltage.

  The output voltage output from the output terminal of the rectifier circuit is restricted from rising exceeding a predetermined voltage. The voltage limiting circuit includes a plurality of MOSFETs connected in series that flow current toward a reference potential point when the output voltage exceeds the predetermined voltage, and the reference potential point of the plurality of MOSFETs And a voltage limiting MOSFET that is in the form of a current mirror and that supplies a current that limits the rise in output voltage to the reference potential point.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A large voltage limiting extraction current can be efficiently passed by the voltage limiting MOSFET.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a circuit diagram showing one embodiment of a boost charge pump circuit provided in an RFID according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate by a known semiconductor manufacturing technique.

  The step-up charge pump circuit includes the following circuit elements. One ends of capacitors C1 and C3 are connected to the input terminal LA to which the antenna is connected. The other end of the capacitor C1 is connected to the circuit node n2. Between the circuit node n1 and the ground potential VSS of the circuit, a diode D1 is provided for flowing a current from the ground potential VSS toward the circuit node n1. A diode D2 is provided for flowing a current from the circuit node n1 to the circuit node n2.

  A capacitor C2 is provided between the circuit node n2 and the ground potential. The other end of the capacitor C3 is connected to the circuit node n3. Between the circuit node n3 and the circuit node n2, there is provided a diode D3 for flowing a current from the circuit node n2 toward the circuit node n3. A diode D4 is provided for flowing a current from the circuit node n3 to the output node n4. A capacitor C4 is provided between the output node n4 and the ground potential VSS. The output node n4 is connected to a power supply voltage VDD of an internal circuit (not shown) via a resistor R.

  The following voltage clamp circuit is provided for the output node n4. N-channel MOSFETs M1 to M4 are connected in series (vertically stacked) to output node n4 and circuit ground potential VSS.

  The ground potential VSS of the circuit is connected to the other input terminal (LB) to which the antenna is connected. That is, the radio wave received by the antenna is input in the form of a voltage signal between the input terminal LA and the ground potential VSS (LB).

  The MOSFETs M1 to M4 are each in the form of a diode with the gate and drain connected. The gate and drain of the MOSFET M1 are connected to the output node n4, and the ground potential VSS of the circuit is applied to the source of the MOSFET M4. Although not restricted in particular, the MOSFETs M1 to M4 have a circuit ground potential VSS applied to their substrate gates (channels).

  In this embodiment, an N-channel MOSFET M5 having a drain-source path connected between the output node n4 and the ground potential VSS is provided. The MOSFET M5 is connected to the MOSFET M4 in the form of a current mirror by connecting the gate to the gate and drain of the MOSFET M4.

  Similar to FIGS. 33 and 34, the first phase in which the input terminal LA becomes higher than the circuit ground potential VSS (LB) by the input voltage Vin by the radio wave received from the antenna, and the input voltage Vin higher than the ground potential VSS. The second phase, which is only lower, repeats at about 900 MHz as a voltage signal corresponding to the received radio wave.

  As a result, as in FIG. 35, during the second phase, the diode D1 is turned on and the capacitor C1 is charged with -Vin. In the next first phase, the diode D1 is turned off, the diode D2 is turned on, and + Vin of the input terminal LA and + Vin held in the capacitor C1 are added to charge 2Vin to the capacitor C2.

  In the next second phase, the diode D2 is turned off, the diode D1 is turned on again, and the capacitor C1 is charged with -Vin again. At the same time, the diode D3 is turned on, and the capacitor C3 is charged with -Vin-2Vin (-3Vin).

  In the next first phase, the diodes D1 and D3 are turned off, the diodes D2 and D4 are turned on, and + Vin of the input terminal LA and + Vin held in the capacitor C1 are added to charge 2Vin to the capacitor C2. + Vin of the terminal LA and + 3Vin held in the capacitor C3 are added to charge the capacitor C4 with 4Vin. By repeating this, a voltage of 4 Vin is generated at the output node n4 in the same manner as described above.

  In the step-up charge pump circuit, the output voltage actually obtained at the output node n4 is not 4Vin, but a voltage loss occurs by the forward voltage Vf (threshold voltage) of the diodes D1 to D4, resulting in 4Vin-4Vf. Voltage.

  In this embodiment, although not particularly limited, a Schottky barrier diode (SBD) having a small voltage loss (Vf) and excellent high-speed switching characteristics is used as the diodes D1 to D4 in order to achieve high efficiency.

  If the efficiency of the rectified voltage is good, in other words, if the voltage loss (4Vf) is not a problem, the diodes D1 to D4 can be PN junction diodes or MOSFETs in the form of diodes.

  In this embodiment, the MOSFET M4 can draw a current that is m times the current drawn by the MOSFETs M1 to M4 by current mirroring the MOSFET M4. Although not particularly limited in this embodiment, the W / L of the MOSFET M4 is set smaller than those of the MOSFETs M1 to M3.

  By reducing the W / L of the MOSFET M4, it becomes easy to increase the W / L ratio of the MOSFETs M5 and M4. Since only the W / L of the MOSFET M4 is reduced, the drawing currents of the MOSFETs M1 to M4 are slightly smaller than those in the case where the MOSFETs M1 to M4 have the same size.

  When the threshold voltages of the MOSFETs M1 to M4 are Vth and the overdrive voltages of the MOSFETs M1 to M4 are Vov1 to Vov4, the clamp voltage Vn4 of the output node n4 is Vn4 = 4Vgs = Vth + Vov1 + Vth + Vov2 + Vth + Vov3 + Vth + Vov4. If the sizes of the MOSFETs M1 to M4 are the same, Vov1 = Vov2 = Vov3 = Vov4 and Vn4 = 4Vth + 4Vov1.

  On the other hand, in order to reduce only the size of the MOSFET M4 as described above and cause the same current as the current flowing through the MOSFETs M1 to M3 to flow through the MOSFET M4 thus reduced in size, Vov4 ′> Vov1 ′. It is necessary to be.

  In this case, Vn4 = 4Vth + 3Vov1 ′ + Vov4 ′, and the increase in the overdrive voltage Vov4 ′ of the MOSFET M4 may be borne by the decrease (ΔV) of the three overdrive voltages 3Vov1 ′ of the MOSFETs M1 to M3. Therefore, as described above, the current flowing through the MOSFETs M1 to M4 can be made somewhat small.

  Since a current that is m times larger than the current flowing through the MOSFETs M1 to M4 can be extracted from the MOSFET M5, when considering the entire circuit, a current that is approximately m times that of FIGS. 33 and 34 can be extracted. Since MOSFET M5 is a current mirror of MOSFET M4, current does not flow unless MOSFET M4 flows current, so there is no fear of drawing current from output node n4 at the time of small input power.

  The circuit according to this embodiment does not draw a current when the input power is small and can multiply the draw current by m times only when the power is high. As a result, the potential of the node n4 can be lowered even when the power is high, and the withstand voltage violation is eliminated.

  FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

  An electromagnetic wave including a signal component received by the antenna ANT is rectified by a charge pump circuit (rectifier circuit) as shown in FIG. 1 to form a DC voltage. This DC voltage is limited by the MOSFETs M1 to M5 as described above.

  That is, when the DC voltage exceeds the threshold voltage 4Vth of the MOSFETs M1 to M4, a current flows through the MOSFETs M1 to M4 and M5 to limit the increase of the DC voltage. This DC voltage is transmitted as an operating voltage VDD (internal power supply voltage) via a resistor R. The capacitor C is for stabilization and includes a parasitic capacitance of the internal circuit.

  The current consumed in the internal circuit is i1, the set voltage in the voltage limiting circuit is VL, and the resistance value of the resistor R is also R. If the voltage required for the internal circuit is VDD, a voltage drop of VL-VDD can be generated in the resistor R by selecting the value of the resistor as R = (VL-VDD) / i1.

  By utilizing this, the following stabilized power supply circuit is provided in parallel with the internal circuit under the condition that the set voltage VL of the voltage limiting circuit is larger than the internal voltage VDD (VL> VDD).

  That is, the MOSFET M0 is provided in parallel with the internal circuit, and the current i2 flowing through the MOSFET M0 is divided by the reference voltage Vref by the silicon band gap (BGR) or the like and the resistors R1 and R2 of VDD (VDD × R2 / (R1 + R2)). So that the gate voltage of the MOSFET M0 is controlled by the differential amplifier circuit AMP.

  As a result, the change in the operating current i1 of the internal circuit is canceled by the change in the current i2, and the current (i1 + i2) flowing through the resistor R2 is made constant. As a result, the internal power supply voltage VDD is kept within the standard voltage range without being affected by fluctuations in the operating current i1 of the internal circuit.

  The RFID ASK reception signal receives, for example, a radio wave of a predetermined frequency when a logic 1 is input, and does not receive a radio wave when a logic 0 is input. Alternatively, the amplitude modulation is performed so that the logic 1 of the signal amplitude of the input radio wave is large and when the logic is 0, the logic is greatly reduced.

  For this reason, when the logic 0 is input, the output voltage of the rectifier circuit is substantially zero from the viewpoint of securing the operating voltage of the internal circuit. Therefore, it is necessary for the internal circuit to secure the operating current i1 with the charge held in the power supply capacitor.

  However, no current is supplied from the rectifier circuit, and when the internal power supply voltage VDD decreases, the differential amplifier circuit AMP detects it and turns off the MOSFET M0 to cut off the current i2. An operation delay occurs and the MOSFET M0 continues to pass the current i2, and the power supply voltage VDD is lowered during this delay time.

  In order to avoid the influence of the decrease in the internal power supply voltage VDD due to the delay of the switching operation of the MOSFET M0, it is necessary to increase the capacity value of the power supply capacity in anticipation of the current i2 from the MOSFET M0. This increases the chip area.

  In this embodiment, the current i2 flowing through the MOSFET M0 is set to be small in order to reduce the capacitance value of the power supply capacitance. However, if the current flowing through MOSFET M0 is reduced, the amount of fluctuation of internal power supply voltage VDD by the stabilized power supply circuit becomes large as it is conventionally.

  In particular, since the output voltage of the rectifier circuit becomes large when high power is input, it is necessary to increase the voltage drop in the resistor R. Therefore, as in the embodiment of FIG. 1, by adding the MOSFET M5, the voltage is efficiently limited so that the output voltage of the rectifier circuit does not increase even when the high power is input.

  By stabilizing the output voltage of the rectifier circuit, the internal stabilization power supply circuit of the RFID can reduce the voltage fluctuation compensation range by the MOSFET M0, and can sufficiently stabilize even if the maximum current i2 is reduced. Can do.

  As a result, it is possible to stabilize the internal operation at the time of ASK reception while using a power supply capacity having a relatively small capacity value (small size).

  The MOSFET M0 operates with an internal power supply voltage VDD as low as 1.5V. On the other hand, the MOSFETs M1 to M5 constituting the charge pump circuit have a high breakdown voltage by forming a gate insulating film thicker than the MOSFET M0, the differential amplifier circuit AMP and the MOSFET constituting the internal circuit. .

  That is, the MOSFETs M1 to M5 have a gate insulating film that is higher than the MOSFET M0 that operates at the internal power supply voltage VDD so that the gate insulating film, the drain, and the substrate are not broken with respect to the operating voltage as described above. It is formed thick.

  FIG. 3 shows a block diagram of an embodiment of an RFID to which the present invention is applied.

  A rectifier circuit (charge pump circuit), a modulation circuit, and a demodulation circuit as shown in FIG. 1 are provided for the antenna or the coil. The rectifier circuit rectifies a received signal in the form of an electric signal by an antenna to form a DC voltage.

  This DC voltage is transmitted to a power supply voltage control circuit (stabilized power supply circuit) as described with reference to FIG. 2, where an internal voltage VDD is formed. The demodulation circuit demodulates the ASK reception signal into digital data.

  The clock component included in the demodulated signal is transmitted to the clock oscillation circuit included in the reception logic circuit, and the synchronized clock is reproduced. The receiving logic circuit receives the received data using the regenerated clock.

  The memory stores stored data. The control circuit performs the entire control operation. The transmission system logic circuit forms a transmission signal and transmits it to the modulation circuit. The modulation circuit modulates the transmission signal and outputs it through the antenna. The internal circuit of FIG. 2 includes the control circuit, transmission system circuit, reception system circuit, and memory. The modulation circuit and the demodulation circuit are omitted in FIG. 2, but will be described later with reference to FIG.

  Although not particularly limited, the memory includes a non-volatile memory having a stacked gate structure including a control gate and a floating gate. As will be described later, the capacitors C1 and C3 shown in FIG. 1 use MIM structure capacitive elements having two metal wiring layers as both electrodes and an interlayer insulating film formed therebetween as a dielectric.

  On the other hand, the capacitors C2 and C4 are capacitive elements in which the control gate and the floating gate constituting the memory element are both electrodes, and an insulating film provided therebetween is a dielectric. In addition, a MOSFET gate capacitance, a PN junction capacitance element, or a combination thereof can be used as a capacitance element constituting the capacitor. This also applies to the power supply capacity shown in FIG.

  FIG. 4 is a circuit diagram showing another embodiment of the boost charge pump circuit provided in the RFID according to the present invention. In this embodiment, the drain of the MOSFET M5 is connected to the internal node n3. Other configurations are the same as those of the embodiment of FIG.

  In this embodiment, when the potential of the circuit node n3 is lowered due to the circuit structure, the potential of the output node n4 is also lowered. Not only the element connected to the output node n4 but also the breakdown voltage violation of the element such as the capacitor C3 connected to the circuit node n3 can be eliminated.

  FIG. 5 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention. In this embodiment, the drain of the MOSFET M5 is connected to the internal node n2. Other configurations are the same as those of the embodiment of FIG.

  In this embodiment, when the potential of the circuit node n2 is lowered due to the circuit structure, the potentials of the circuit node n3 and the output node n4 are also lowered. Not only the elements connected to the output node n4 but also the breakdown of voltage resistance of the elements such as the capacitors C1 to C3 connected to the circuit nodes n2 and n3 can be eliminated.

  FIG. 6 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention. In this embodiment, the drain of the MOSFET M5 is connected to the internal node n1. Other configurations are the same as those of the embodiment of FIG.

  In this embodiment, when the potential of the circuit node n1 is lowered due to the circuit structure, the potentials of the circuit nodes n2, n3 and the output node n4 are also lowered. Not only the elements connected to the output node n4 but also the breakdown of the breakdown voltage of the elements such as the capacitors C1 to C3 connected to the circuit nodes n1 to n3 can be eliminated.

  FIG. 7 shows a circuit diagram of still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of the MOSFET M5 is connected to the input terminal LA. Other configurations are the same as those of the embodiment of FIG. In this embodiment, when the input voltage at the input terminal LA is lowered due to the circuit structure, the potentials at the circuit nodes n1 to n3 and the output node n4 are also lowered accordingly.

  Not only the elements connected to the output node n4 but also the breakdown of the breakdown voltage of the elements such as the capacitors C1 to C3 connected to the input terminal LA and the circuit nodes n1 to n3 can be eliminated. The waveform of the input signal Vin when the input terminal LA is pulled out by the MOSFET M5 is close to the pulse state, and the operation waveforms of the nodes n1 to n4 at that time are similar to those shown in FIG.

  FIG. 8 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of MOSFET M5 is connected to the interconnection point of MOSFETs M1 and M2. Other configurations are the same as those of the embodiment of FIG. Rather than clamping the output node n4 by the MOSFET M5, the drain potential of the MOSFET M2 is lowered by clamping the drain potential of the MOSFET M2.

  Due to the circuit structure, when the drain potential of the MOSFET M2 is lowered, the potential of the output node n4 is also lowered correspondingly. This configuration is useful for applications that perform good ASK demodulation.

  In other words, when the amplitude modulation is performed so that the signal amplitude of the input radio wave is large when the logic is 1 and greatly reduced when the logic is 0, if the potential change of the output node n4 is strongly suppressed during high power input, the ASK input Since it becomes impossible to distinguish between the logic 1 and the logic 0 of the signal, it operates so as to relax it.

  FIG. 9 shows a circuit diagram of still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of MOSFET M5 is connected to the interconnection point of MOSFETs M2 and M3. Rather than clamping the output node n4 by the MOSFET M5, the drain potential of the MOSFET M3 is lowered by clamping the drain potential of the MOSFET M3.

  Due to the circuit structure, when the drain potential of the MOSFET M3 is lowered, the potential of the output node n4 is also lowered correspondingly. This configuration is also useful for applications in which ASK demodulation is performed satisfactorily as described above.

  FIG. 10 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, diode-type MOSFETs M6 to M8 are provided at the circuit node n2. The MOSFET M8 is smaller in size than the MOSFETs M6 and M7.

  That is, the MOSFETs M6 and M7 correspond to the MOSFETs M1 to M3 in FIG. 1, and the MOSFET M8 corresponds to the MOSFET M4. In this embodiment, since the voltage of the circuit node n2 at which the double boosted voltage is obtained is monitored, the MOSFETs M6 to M8 are stacked in three stages.

  The MOSFET M8 and MOSFET M5 have a current mirror configuration, and the output node n4 is clamped by the MOSFET M5. That is, the MOSFETs M1 to M4 in FIG. 1 are replaced with MOSFETs M6 to M8. In this embodiment, the MOSFETs M1 to M4 having the same size are left, but this can be omitted.

  The circuit node n2 potential is about half of the output node n4 potential. Since the diode-connected MOSFETs M6 to M8 are stacked in three stages at the circuit node n2, the input power at which the MOSFETs M6 to M8 start drawing current is larger than the clamp voltage by the MOSFETs M1 to M4.

  Therefore, the MOSFET M5 does not operate unless the power is higher than the clamp voltage by the MOSFETs M1 to M4. MOSFET M5 draws a large current from the potential of output node n4. Therefore, the potential of the output node n4 is controlled to a low voltage when the power is high. The potential of the circuit node n2 remains at a relatively high voltage because current is drawn only with a small current of the MOSFETs M6 to M8. Therefore, when the power is high, it is possible to draw a large current from the output node n4 by making a current mirror with reference to the potential of the circuit node n2.

  That is, in the embodiment of FIG. 1, the current flowing through the MOSFET M5 is controlled by the voltage rise at the output node n4 suppressed by the operation of the MOSFET M5, so that the increase in current at the time of high power input is reduced.

  On the other hand, in the embodiment of FIG. 10, the change in the input radio wave is detected by detecting the potential change of the circuit node n2 that reacts more directly to the high power input and controlling the current flowing through the MOSFET M5. The control sensitivity corresponding to can be increased.

  Further, since the current can be extracted in two stages, that is, the diode connection stage of the MOSFETs M1 to M4 and the current extraction circuit of the MOSFETs M6 to M8 and M5, the extraction current can be easily adjusted by design.

  In the charge pump circuit, when the number of charge pump stages is further increased to three or more stages, not the boosted voltage of the output node but the stable circuit node n2 (n4) before the output node as described above. However, the current mirror current generation MOS diode connection stage (M6 to M8, etc.) may be configured anywhere.

  FIG. 11 is a circuit diagram showing another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of the MOSFET M5 is connected to the internal node n3. Other configurations are the same as those of the embodiment of FIG. In this embodiment, when the potential of the circuit node n3 is lowered due to the circuit structure, the potential of the output node n4 is also lowered. Not only the element connected to the output node n4 but also the breakdown voltage violation of the element such as the capacitor C3 connected to the circuit node n3 can be eliminated.

  FIG. 12 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of the MOSFET M5 is connected to the internal node n2. Other configurations are the same as those of the embodiment of FIG. In this embodiment, when the potential of the circuit node n2 is lowered due to the circuit structure, the potentials of the circuit node n3 and the output node n4 are also lowered. Not only the elements connected to the output node n4 but also the breakdown of voltage resistance of the elements such as the capacitors C1 to C3 connected to the circuit nodes n2 and n3 can be eliminated.

  FIG. 13 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of the MOSFET M5 is connected to the internal node n1. Other configurations are the same as those of the embodiment of FIG. In this embodiment, when the potential of the circuit node n1 is lowered due to the circuit structure, the potentials of the circuit nodes n2, n3 and the output node n4 are also lowered. Not only the elements connected to the output node n4 but also the breakdown of the breakdown voltage of the elements such as the capacitors C1 to C3 connected to the circuit nodes n1 to n3 can be eliminated.

  FIG. 14 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of the MOSFET M5 is connected to the input terminal LA. Other configurations are the same as those of the embodiment of FIG. In this embodiment, when the input voltage at the input terminal LA is lowered due to the circuit structure, the potentials at the circuit nodes n1 to n3 and the output node n4 are also lowered accordingly. Not only the elements connected to the output node n4 but also the breakdown of the breakdown voltage of the elements such as the capacitors C1 to C3 connected to the input terminal LA and the circuit nodes n1 to n3 can be eliminated.

  The waveform of the input signal Vin when the input terminal LA is pulled out by the MOSFET M5 is close to the pulse state, and the operation waveforms of the nodes n1 to n4 at that time are similar to those shown in FIG.

  FIG. 15 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of MOSFET M5 is connected to the interconnection point of MOSFETs M1 and M2. Other configurations are the same as those of the embodiment of FIG. Instead of clamping the output node n4 as shown in FIG. 10 by the MOSFET M5, the drain potential of the MOSFET M2 is lowered by clamping the drain potential of the MOSFET M2.

  Due to the circuit structure, when the drain potential of the MOSFET M2 is lowered, the potential of the output node n4 is also lowered correspondingly. This configuration is useful for applications that perform good ASK demodulation. In other words, when the amplitude modulation is performed so that the signal amplitude of the input radio wave is large when the logic is 1 and greatly reduced when the logic is 0, if the potential change of the output node n4 is strongly suppressed during high power input, the ASK input Since it becomes impossible to distinguish between the logic 1 and the logic 0 of the signal, it operates so as to relax it.

  FIG. 16 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the drain of MOSFET M5 is connected to the interconnection point of MOSFETs M2 and M3. Instead of clamping the output node n4 by the MOSFET M5 as shown in FIG. 10, the drain potential of the MOSFET M3 is lowered by clamping the drain potential of the MOSFET M3.

  Due to the circuit structure, when the drain potential of the MOSFET M3 is lowered, the potential of the output node n4 is also lowered correspondingly. This configuration is also useful for applications in which ASK demodulation is performed satisfactorily as described above.

  10 to 16, the MOSFETs M6 to M8 are connected to the circuit node n2 in three stages of diode connection of N-channel MOSFETs. The diode-connected three stages of these N-channel MOSFETs M6 to M8 can be changed to four stages or two stages depending on the MOSFET conditions and the input power to be extracted due to the circuit structure.

  Further, the MOSFETs M6 to M8 can be changed to P-channel MOSFETs other than the MOSFET M8 (which is a current mirror).

  FIG. 17 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, a P-channel MOSFET M9 having a die auto connection is provided between the drain of the MOSFET M5 and the output node n4. Other configurations are the same as those of the embodiment of FIG. In this embodiment, the drain-source voltage withstand voltage of the MOSFET M5 can be improved.

  At the time of high power input, the largest voltage is applied to the drain-source voltage of the MOSFET M5. The breakdown voltage of the drain-source voltage of the MOSFET M5 becomes a problem. Therefore, MOSFET M9 is provided.

  As a result, the drain-source voltage of the MOSFET M5 is reduced by the gate-source voltage Vgs of the MOSFET M9. If the potential of the circuit node n5 (the drain voltage of the MOSFET M5) is high even when the MOSFET M9 is added, the diode-connected MOSFET M9 may be replaced with an m-stage stacked diode-connected P-channel MOSFET. MOSFET M9 may be an N-channel MOSFET.

  FIG. 18 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the full-wave rectification system is made by using two charge pump circuits (D11 to D31 and C11 to C31 and D12 to D32 and C12 to C32) of FIG. 1 in parallel. At this time, diodes D51 and D52 are added between the circuit ground potential VSS and the antenna terminals LA and LB. By changing the connection in this way, the breakdown voltage of the rectifier circuit can be improved.

  That is, when changing to the full-wave rectification method, the antenna terminal LA-VSS, for each half cycle is compared with the half-wave rectification method in which the antenna terminal LB is fixedly connected to VSS as shown in FIGS. An input voltage is applied between the antennas LB and VSS. Therefore, each potential is lowered to half that of the half-wave method (LA-LB), and the withstand voltage in the rectifier circuit can be improved. And of course, the ripple can also be improved.

  In this full-wave rectification method, the first phase in which the input terminal LA is relatively higher than the input terminal LB and the input terminal LA is relatively lower than the input terminal LB in response to the radio wave received from the antenna. The second phase is repeated. During the first phase, the input terminal LA is at a high level.

  As a result, the diode D21 is turned on, and the high level of the input terminal LA and the voltage held in the capacitor C11 are input to the capacitor C21. The ground potential VSS in the first phase is clamped to a voltage that is higher than the LB by the forward voltage Vf because the diode D52 is turned on by the low level of the input terminal LB. The low level of the input terminal LB is transmitted to the input side electrode of the capacitor C12, but the other electrode of the capacitor C12 becomes lower than the ground potential VSS by the forward voltage of the diode D12. Becomes zero.

  In the second phase, the input terminal LA changes to a relatively low level and the input terminal LB changes to a relatively high level. Due to the high level of the input terminal LB, the diode D22 is turned on, and the high level of the input terminal LB and the voltage held in the capacitor C12 are input to the capacitor C22.

  As described above, since the holding voltage of the capacitor C12 is almost zero, the capacitor C22 is charged with a high level corresponding to the input terminal LB. The ground potential VSS of the circuit in the second phase is clamped to a voltage higher than the input terminal LA by the forward voltage Vf, with the diode D51 being turned on from the low level of the input terminal LA.

  The low level of the input terminal LA is transmitted to the input side electrode of the capacitor C11, but the other electrode of the capacitor C11 is lower than the circuit ground potential VSS by the forward voltage of the diode D11. The voltage is almost zero. The diode D31 is turned on by the low level of the input terminal LA and the holding voltage of the capacitor C21 to charge up the capacitor C31.

  In the first phase again, the diode D21 is turned on as described above, and the high level of the input terminal LA and the voltage held in the capacitor C11 are input to the capacitor C21. Since the input side electrode of the capacitor C31 is set to the high level according to the input terminal LA, a boosted voltage obtained by adding the holding voltage of the capacitor C31 is formed at the circuit node n31, and the capacitor C4 is charged up through the diode D41. Let

  The ground potential VSS of the circuit in the first phase is clamped to a voltage higher than the input terminal LB by the forward voltage Vf because the diode D52 is turned on by the low level of the input terminal LB. Similarly to the above, the voltage between both electrodes of the capacitor C12 becomes almost zero. The diode D32 is turned on by the low level of the input terminal LB and the holding voltage of the capacitor C22 to charge up the capacitor C32.

  In the second phase again, the diode D22 is turned on as described above, and the high level of the input terminal LB and the voltage held in the capacitor C12 are input to the capacitor C22. Since the input side electrode of the capacitor C32 is set to the high level according to the input terminal LB, a boosted voltage obtained by adding the holding voltage of the capacitor C32 is formed at the circuit node n32, and the capacitor C4 is charged up through the diode D42. Let

  The ground potential VSS of the circuit in the second phase is turned on by the diode D51 by the low level of the input terminal LA, and is clamped to a voltage higher than the LA by the forward voltage Vf. The diode D31 is turned on by the holding voltage of the capacitor C21 to charge up the capacitor C31.

  By repeating the first phase and the second phase as described above, when the input voltage of the input terminal LA-LB is Vin, the voltage of the output node n4 is finally expressed as Vin × 2 = 2Vin. The boosted voltage is half that of the half-wave rectification method such as 1 or the like. However, in this description, the voltage loss due to the forward voltage Vf of the diode is ignored as described above.

  FIG. 19 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, in the full-wave rectification type charge pump circuit shown in FIG. Capacitors C11 and C12 and diodes D11 and D12, which are no longer charged with voltage and no longer play a substantial role in the circuit, are omitted. The operation of the rectifier circuit is the same as in FIG. In this embodiment, the area can be reduced by reducing the number of elements.

  FIG. 20 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the capacitors C21 and C22 are shared as the capacitor C2 in the full-wave rectification type charge pump circuit of FIG. The operation of the rectifier circuit is the same as in FIG. In this embodiment, the area can be reduced by further reducing the number of elements.

  FIG. 21 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, diode-connected MOSFETs M10 and M11 are additionally connected between the input terminals LA and LB and the output node n4 in the embodiment of FIG. By providing such MOSFETs M10 and M11, the ESD resistance of the input terminals LA and LB (VSS) can be improved.

  When a large voltage is applied to the input terminals LA and VSS (LB) due to static electricity during handling and transportation of the RFID, a large current (discharge current) flows through the MOSFETs M10 and M11, and the withstand voltages of the dielectric films of the capacitors C1 and C3 Destruction can be prevented. Therefore, the capacitors C1 and C3 are not easily broken, and the ESD resistance as RFID is increased.

  When performing circuit operation as an RFID, the potential of the output node n4 of the charge pump circuit is the highest voltage in the circuit, so that the diode-connected MOSFETs M10 and M11 can always be turned off.

  Thus, in this embodiment, the MOSFETs M10 and M11 provided to increase the ESD resistance do not become an obstacle when performing circuit operation as RFID.

  FIG. 22 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, resistors R3 and R4 are additionally connected between the MOSFET M10 and the input terminal LB (VSS) and between the MOSFET M11 and the input terminal LA in the embodiment of FIG.

  By adding such resistors R3 and R4, it is possible to prevent the MOSFETs M10 and M11 from being destroyed by an inrush current generated when discharging static electricity. Thereby, ESD tolerance as RFID becomes strong.

  FIG. 23 is a circuit diagram showing still another embodiment of the boost charge pump circuit provided in the RFID according to the present invention.

  In this embodiment, the connection location of the resistors R3 and R4 is changed in the embodiment of FIG. That is, resistors R3 and R4 are connected between MOSFET M10 and circuit node n4 and between MOSFET M11 and circuit node n4, respectively.

  By adding such resistors R3 and R4, it is possible to prevent the MOSFETs M10 and M11 from being destroyed by the inrush current generated when discharging static electricity as in FIG. Thereby, ESD tolerance as RFID becomes strong.

  FIG. 24 shows a schematic element structure sectional view of one embodiment of the MOSFET M11 of FIG.

The antenna pad (LA) is led to the source and drain regions (p ⁺ ) constituting the MOSFET M11 by the uppermost metal wiring layer M3 and the lower metal wiring layer M2, and the lower metal wiring layer M1, The second polysilicon layer SG and the first polysilicon layer FG are connected to the source and drain regions (p ⁺ ) through contact holes connecting the wiring layers. The other source / drain region (p ⁺ ) of the MOSFET M11 is connected to the first metal wiring layer M1 through FG-SG.

  The first metal wiring layer M1 is extended toward the circuit node n4. In the MOSFET M11, the first polysilicon layer FG on the well (channel) n-well sandwiched between the pair of source and drain regions serves as a gate electrode, and the first polysilicon layer SG is interposed through the first polysilicon layer SG. It is connected to the layer metal wiring layer M1.

  The film thickness tox of the gate insulating film provided between the well (channel) n-well and the gate electrode FG is thicker than that of the MOSFET operating at the internal power supply voltage VDD as described above.

  FIG. 25 shows a schematic element structure sectional view of an embodiment of the MOSFET M11 and the resistor R4 of FIG.

The antenna pad (LA) is led to the source and drain regions (p ⁺ ) constituting the MOSFET M11 by the uppermost metal wiring layer M3 and the lower metal wiring layer M2, and the lower metal wiring layer M1, The second polysilicon layer SG and the first polysilicon layer FG are connected to the source and drain regions (p ⁺ ) through contact holes connecting the wiring layers. Other configurations are the same as those in FIG.

  FIG. 26 shows a schematic element structure sectional view of another embodiment of the MOSFET M11 and the resistor R4 of FIG.

  The antenna pad (LA) is connected to one end side of the second polysilicon layer SG constituting the resistance element R4 by the uppermost metal wiring layer M3 and the lower metal wiring layers M2 and M1. The other end of the second polysilicon layer SG is connected to one end of the upper metal wiring layer M2 via the first metal wiring layer M1.

The other end side of the metal wiring layer M2 is led to the source and drain regions (p ⁺ ) constituting the MOSFET M11. Similarly to the above, the lower metal wiring layer M1, the second polysilicon layer SG, and the first layer poly-silicon are connected. The silicon layer FG is connected to the source / drain regions (p ⁺ ) through contact holes connecting the wiring layers.

The other source / drain region (p ⁺ ) of the MOSFET M11 is connected to the first metal wiring layer M1 through FG-SG. The other end of the first metal wiring layer M1 is connected to one end of a resistance element R4 composed of the second polysilicon layer SG below the first metal wiring layer M1.

  The other end of the second polysilicon layer SG is connected to one end of the first metal wiring layer M1, and the other end is extended toward the circuit node n4. Other configurations are the same as those in FIG.

  FIG. 27 shows a circuit diagram of an embodiment of the RFID according to the present invention.

  In this embodiment, the ASK circuit and the backscatter MOSFET M12 are connected to the circuit node n2. The ASK circuit (demodulation circuit) is generally connected to the input terminals LA and VSS (LB) as shown in FIG.

  Further, the backscatter MOSFET M12 constituting the modulation circuit is generally connected to the circuit node n1 and VSS. However, in this way, the input capacitance of the ASK circuit is connected as a parasitic capacitance to the input terminals LA and LB (VSS). Similarly, the drain parasitic capacitance of MOSFET M12 is connected to circuit node n1.

  Further, the wiring resistance due to the wiring for connecting these circuits also increases. The input terminals LA and LB and the circuit node n1 are portions where voltage changes occur according to input radio waves. In the configuration in which the parasitic capacitance of the portion where the voltage fluctuates is connected in this way, the charge pump / discharge current with respect to the parasitic capacitance acts to reduce the potential change of the input terminals LA and LB and the circuit node n1, thereby charge pump. The operation efficiency is deteriorated, and the power loss due to the parasitic resistance is increased to cause deterioration of the rectification efficiency.

  In the embodiment of FIG. 27, the circuit node n2 is a portion where the double boosted voltage is formed, and when the charge pump circuit operates stably, its potential fluctuation is extremely small. Therefore, when the capacitors C1 and C3 are precharged, the loss due to the parasitic capacitance caused by the ASK circuit and the backscatter MOSFET M12 is substantially zero when the charge is transferred from the capacitor C1 to the capacitor C2, and the rectification efficiency can be improved. .

  The ASK circuit detects an AM-modulated input signal and reproduces input data and a clock. The backscatter MOSFET M12 causes a load fluctuation to the radio wave transmission source due to the on / off of the backscatter MOSFET M12, and transmits the transmission signal to the transmission source (reading device). The ASK circuit and backscatter MOSFET M12 shown in FIG. 27 can be similarly applied to the circuit of the embodiment other than FIG.

  FIG. 28 is a circuit diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

  An electromagnetic wave including a signal component received by the antenna ANT is rectified by a full-wave rectification type charge pump circuit as shown in FIG. 20 to form a DC voltage. This DC voltage is limited by the MOSFETs M1 to M5 as described above.

  That is, when the DC voltage exceeds the threshold voltage 4Vth of the MOSFETs M1 to M4, a current flows through the MOSFETs M1 to M4 and M5 to limit the increase of the DC voltage. This DC voltage is transmitted as an operating voltage VDD (internal power supply voltage) via a resistor R.

  The capacitor C is for stabilization and includes a parasitic capacitance of the internal circuit. As in FIG. 2, a stabilized power supply circuit including a MOSFET M0, a differential amplifier circuit AMP, and a silicon band gap BGR is provided in parallel with the internal circuit. As described above, the internal circuit includes a memory, a control circuit (digital circuit), an analog circuit, and the like.

  FIG. 29 shows a schematic element cross-sectional view of one embodiment of the resistance element used in the rectifier circuit.

As the resistor R, a polysilicon layer P ⁺ poly introduced with a p ⁺ impurity component formed in the element isolation insulating layer SGI is used. n-well is an n-type well region, and p-well is a p-type well region. P-sub is a p-type semiconductor substrate.

  FIG. 30 is a schematic element cross-sectional view of one embodiment of a capacitor used in the rectifier circuit.

  The capacitor includes a first-layer polysilicon layer FG that constitutes a MOSFET gate electrode or a floating gate of a nonvolatile memory element, and a second-layer polysilicon layer that constitutes a control gate of the nonvolatile memory element formed thereon. SG is used as both electrodes, and an insulating film formed therebetween is configured as a dielectric.

  n-well is an n-type well region, and p-well is a p-type well region. Similarly to the above, SGI is an element isolation insulating layer, and p-sub is a p-type semiconductor substrate.

  FIG. 31 shows a schematic element cross-sectional view of another embodiment of the capacitor used in the rectifier circuit.

The capacitor uses the gate capacitance of the MOSFET. That is, the source and drain regions (p ⁺ ) constituting the P-channel MOSFET are used as one electrode, and the gate electrode (FG) of the MOSFET is used as the other electrode. Similarly to the above, SGI is an element isolation insulating layer, and p-sub is a p-type semiconductor substrate.

  FIG. 32 shows a schematic element plan view of another embodiment of the capacitor used in the rectifier circuit. The capacitor is composed of an Al wiring 1 and an Al wiring 2 that are extended in parallel using any one of the metals M1 to M3 (such as aluminum).

  In addition, a capacitor may be configured using different wiring layers such as M1 and M2 or M2 and M3.

  Although not particularly limited in FIG. 1 and the like, capacitors C1 and C3 having the MIM structure as shown in FIG. 32 are used. Capacitors C2 and C4 use polysilicon capacitors or MOS capacitors as shown in FIG. These capacitors C2 and C4 also improve the rectification efficiency when using MIM capacitors with small parasitic resistance and parasitic capacitance.

  In the half-wave rectification method as shown in FIG. 1, the capacitance values of the capacitors C1 and C3 are, for example, 0.5 pF to 2 pF, the capacitor C2 is 0.5 pF to 5 pF, and the capacitor C4 is 0, although it varies depending on the application of RFID. .5 pF to 10 pF. The resistance R is set to 1 KΩ to 100 KΩ. As the diodes D1 to D4, Schottky barrier diodes (SBD) having a small forward voltage Vf are used as described above.

  Although the invention made by the present inventors has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

  As described above, the charge pump circuit may have three or more stages in order to increase the necessary boosted voltage. Corresponding to such a boosted voltage, the number of stages of the diode-connected MOSFETs M1 to M4 and M6 to M8 may be increased corresponding to the threshold voltage. Further, the number of MOSFETs M1 to M4 and M6 to M8 may be appropriately selected in accordance with the internal power supply voltage VDD.

  The present invention can be applied to RFID and non-contact type IC cards. Further, for example, the propagated energy may be light or sound. That is, the present invention can be similarly applied to a device that converts light into an electric signal and thereby forms a power supply voltage, or converts sound into an electric signal and rectifies it to form a power supply voltage.

  That is, the present invention can be similarly applied to an optical response IC tag, a voice response IC tag, and the like. The present invention can be widely used in semiconductor integrated circuit devices having internal circuits that operate by generating a power supply voltage by receiving the propagated energy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to RFID and non-contact type IC cards. Further, for example, the propagated energy may be light or sound. That is, the present invention can be similarly applied to a device that converts light into an electric signal and thereby forms a power supply voltage, or converts sound into an electric signal and rectifies it to form a power supply voltage. That is, the present invention can be similarly applied to an optical response IC tag, a voice response IC tag, and the like. The present invention can be widely used in semiconductor integrated circuit devices having internal circuits that operate by generating a power supply voltage by receiving the propagated energy.

It is a circuit diagram which shows one Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a block diagram which shows one Example of the semiconductor integrated circuit device based on this invention. It is a block diagram which shows one Example of RFID with which this invention is applied. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. It is a circuit diagram which shows another Example of the pressure | voltage rise charge pump circuit provided in RFID which concerns on this invention. FIG. 22 is a schematic cross-sectional view of an element structure showing an embodiment of MOSFET M in FIG. 21. FIG. 23 is a schematic cross-sectional view of an element structure showing one embodiment of a MOSFET M and a resistor of FIG. 22. FIG. 24 is a schematic cross-sectional view of an element structure showing another embodiment of the MOSFET M and the resistor of FIG. It is a circuit diagram which shows one Example of RFID which concerns on this invention. It is a circuit diagram which shows another Example of the semiconductor integrated circuit device based on this invention. It is an outline element sectional view showing one example of a resistance element used in a rectifier circuit concerning the present invention. It is a schematic element sectional drawing which shows one Example of the capacitor currently used in the rectifier circuit which concerns on this invention. It is a schematic element sectional drawing which shows another Example of the capacitor currently used in the rectifier circuit based on this invention. It is a schematic element top view which shows another Example of the capacitor currently used in the rectifier circuit based on this invention. It is the simplification figure of the rectifier circuit examined previously by the present inventors. FIG. 34 is a circuit diagram of the boost charge pump circuit of FIG. 33. FIG. 35 is a schematic operation timing chart of FIG. 34.

Explanation of symbols

ANT antenna LA, LB input terminal (antenna terminal)
D1-D4, D11-D51 Diodes R, R1, R2 Resistors C1-C4, C11-C32 Capacitors M0-M12 MOSFET
AMP differential amplifier circuit

Claims (15)

An input terminal through which the propagated energy is input in the form of an electrical signal;
A rectifier circuit that rectifies the electrical signal at the input terminal to generate a DC voltage;
A voltage limiting circuit for limiting an increase in output voltage output from the output terminal of the rectifier circuit exceeding a predetermined voltage;
The voltage limiting circuit is:
A plurality of MOSFETs in the form of diodes connected in series so that a current flows toward a reference potential point when the output voltage exceeds the predetermined voltage;
A MOSFET provided at the reference potential point among the plurality of MOSFETs in the diode form and a voltage limiting MOSFET connected to the current mirror form and flowing a current for restricting an increase in the output voltage to the reference potential point. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1.
The voltage limiting MOSFET and the diode-shaped MOSFET in the form of a current mirror have an element size ratio set so that a larger current flows through the voltage-limiting MOSFET than the diode-shaped MOSFET. Integrated circuit device. The semiconductor integrated circuit device according to claim 2.
2. The semiconductor integrated circuit device according to claim 1, wherein the diode-shaped MOSFET in the form of a current mirror has a smaller element size than other diode-shaped MOSFETs connected in series with the MOSFET. The semiconductor integrated circuit device according to claim 3.
Resistance means for transmitting the DC voltage formed by the rectifier circuit;
A voltage stabilizing circuit that forms a stabilizing voltage smaller than the DC voltage via the resistance means;
An internal circuit that operates at a stabilized voltage formed by the voltage stabilizing circuit;
And further comprising capacitive means provided in parallel with the internal circuit,
The voltage stabilization circuit includes:
MOSFET provided in parallel with the internal circuit,
A differential amplifier circuit that compares a reference voltage and a divided voltage of the stabilization voltage to form a gate voltage of the MOSFET;
A semiconductor integrated circuit device, wherein a current flowing through the MOSFET is controlled so that a voltage drop in the resistance means falls within a specified voltage of the stabilization voltage. The semiconductor integrated circuit device according to claim 4.
The semiconductor integrated circuit device according to claim 1, wherein the propagated energy is an electromagnetic wave that is intermittently input corresponding to a received signal component. The semiconductor integrated circuit device according to claim 5.
The rectifier circuit is
A semiconductor integrated circuit device comprising a charge pump circuit that forms a boosted rectified voltage with respect to a voltage of the electrical signal. The semiconductor integrated circuit device according to claim 6.
The plurality of diode-shaped MOSFETs connected in series are provided between an output terminal of the charge pump circuit and a reference potential point of the circuit,
The drain of the voltage limiting MOSFET is connected to the output terminal of the charge pump circuit. The semiconductor integrated circuit device according to claim 6.
The plurality of diode-shaped MOSFETs connected in series are provided between an output terminal of the charge pump circuit and a reference potential point of the circuit,
The drain of the voltage limiting MOSFET is connected to one of circuit nodes forming a boosted voltage in the charge pump circuit excluding the output terminal of the charge pump circuit. The semiconductor integrated circuit device according to claim 6.
The diode-connected MOSFETs connected in series are provided between a reference potential point of a DC voltage node lower than an output voltage of the output terminal in the charge pump circuit,
The drain of the voltage limiting MOSFET is connected to the output terminal of the charge pump circuit. The semiconductor integrated circuit device according to claim 6.
The diode-connected MOSFETs connected in series are provided between a reference potential point of a DC voltage node lower than an output voltage of the output terminal in the charge pump circuit,
The drain of the voltage limiting MOSFET is connected to one of circuit nodes forming a boosted voltage in the charge pump circuit excluding the output terminal of the charge pump circuit. The semiconductor integrated circuit device according to claim 6.
A semiconductor integrated circuit device further comprising an ASK demodulation circuit and an ASK modulation MOSFET for a DC voltage node that is lower than an output voltage of the output terminal in the charge pump circuit and has no voltage change due to a charge pump operation. The semiconductor integrated circuit device according to claim 6.
Having a first terminal and a second terminal connected to the antenna;
The input terminal is the first terminal,
The semiconductor integrated circuit device, wherein the second terminal is connected to the reference potential point. The semiconductor integrated circuit device according to claim 6.
Having a first terminal and a second terminal connected to the antenna;
The input terminals are the first terminal and the second terminal;
The charge pump circuit is provided corresponding to the first terminal and the second terminal,
Between the reference potential point and the first terminal and the second terminal, there is provided a rectifying diode that performs a full-wave rectification operation of a voltage corresponding to the electric signals of the first terminal and the second terminal, respectively. A semiconductor integrated circuit device. An input terminal through which the propagated energy is input in the form of an electrical signal;
A charge pump circuit that forms a boosted rectified voltage with respect to the voltage of the electrical signal;
2. A semiconductor integrated circuit device comprising: a diode-type MOSFET for passing a current from the input terminal to the output terminal between the input terminal and an output terminal for outputting a rectified voltage of the charge pump circuit. The semiconductor integrated circuit device according to claim 14.
A voltage limiting circuit for limiting an increase in output voltage output from the output terminal of the rectifier circuit exceeding a predetermined voltage;
The voltage limiting circuit is:
A plurality of MOSFETs in the form of diodes connected in series so that a current flows toward a reference potential point when the output voltage exceeds the predetermined voltage;
A MOSFET provided at the reference potential point among the plurality of MOSFETs in the diode form and a voltage limiting MOSFET connected to the current mirror form and flowing a current for restricting an increase in the output voltage to the reference potential point. A semiconductor integrated circuit device.

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