JP4918929B2 - Light-emitting diode controller - Google Patents

Description

  The present invention relates to a light emitting diode control device. Specifically, the present invention relates to a light emitting diode control device that controls light emission of a light emitting diode using a voltage source circuit and a current source circuit.

Patent Document 1 discloses an LED (Light Emitting Diode) display device.
The LED display device of Patent Document 1 includes a panel in which a plurality of LEDs (hereinafter referred to as light emitting diodes) are arranged in a matrix, a common driver connected to the plurality of light emitting diodes by line lines, a plurality of light emitting diodes, A constant current driver (constant current source) connected by a line (see FIG. 1).
A power supply voltage is supplied from the common driver to the light emitting diode selected by the line line and the row line, and a constant current preset by the constant current driver is supplied.

The luminance of the light emitting diode to which a voltage is applied in this way can be controlled by the magnitude (amplitude) of the current value passed through the light emitting diode or the energization time.
Therefore, for example, by energizing the light emitting diode connected to the constant current source according to the duty, the light emitting diode can emit light with the luminance according to the duty.

The light emitting diode emits light when a current flows in a forward direction from the anode to the cathode. At this time, the light emitting diode causes a voltage drop in the forward direction. Therefore, in order to cause the light emitting diode to emit light with a luminance corresponding to the magnitude of the current value or the energization time, it is necessary to apply a voltage equal to or higher than the forward voltage drop generated in the light emitting diode.
In addition, when a plurality of light emitting diodes are connected in series, it is necessary to apply a voltage equal to or higher than the sum of forward drop voltages generated in the plurality of light emitting diodes.

JP-A-9-292860

The voltage drop of the light emitting diode varies depending on the actually manufactured element due to manufacturing variations. In addition, the temperature characteristics of the light emitting diodes are different for each actually manufactured element.
Therefore, a forward voltage drop is reduced in some light emitting diodes, and a forward voltage drop is increased in other light emitting diodes.

  As a result, in the LED display device actually manufactured, it is assumed that the forward voltage drop is the largest, and a power supply voltage higher than the assumed voltage is supplied from the common driver to the light emitting diode.

On the other hand, in an LED display device that is actually manufactured, the forward voltage drop of the light emitting diode may be smaller than the assumed voltage.
When the forward drop voltage of the light emitting diode actually used is small, an unnecessarily large voltage is applied to the light emitting diode.
In addition, this unnecessarily large voltage consumes more power than necessary. Excess heat is generated in the LED display device.
The following formula 1 is an extra power calculation formula. In Equation 1, P (Loss) is extra power consumption, Vf (max) is the maximum value of the forward drop voltage of the light emitting diode due to manufacturing variation, etc., Vf (min) is the minimum value of the forward drop voltage of the light emitting diode, N is the number of light emitting diodes connected in series, and I is the value of the current passed through the light emitting diodes.

  P (Loss) = (Vf (max) −Vf (min)) × N × I Equation 1

  An object of the present invention is to provide a light emitting diode control device capable of reducing wasteful power consumption due to manufacturing variations of light emitting diodes or temperature characteristics.

  The light emitting diode control device of the present invention includes a voltage source circuit for supplying voltage to the anode of the light emitting diode, a current source circuit for selectively supplying current to the cathode of the light emitting diode, and light emission connected to the current source circuit. A first voltage detection circuit for comparing the cathode voltage of the diode and the first reference voltage; a second voltage detection circuit for comparing the cathode voltage and a second reference voltage lower than the first reference voltage; A voltage control circuit for controlling a voltage value of a voltage supplied by the voltage source circuit. The voltage control circuit controls the voltage source circuit so that the voltage supplied from the voltage source circuit is between the first reference voltage and the second reference voltage.

  In the present invention, it is possible to reduce wasteful power consumption due to manufacturing variations of light emitting diodes or temperature characteristics.

1 is a schematic block diagram of a light-emitting diode control device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of a DA converter and a voltage source circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a current source circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a circuit of a control value generation system in FIG. 1. It is a timing chart which shows the signal waveform of each part in FIG. It is a timing chart which shows an example of the anode voltage control in the light emitting diode control apparatus of FIG. It is a schematic block diagram of the light emitting diode control apparatus which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows an example of the circuit of the control value generation system in FIG. It is a schematic block diagram of the principal part of the light emitting diode control apparatus which concerns on 3rd Embodiment of this invention. FIG. 10 is a timing chart showing an example of signal waveforms at various parts in FIG. 9. FIG. 11 is a timing chart illustrating an example of signal waveforms of respective units corresponding to FIG. 10 in the light emitting diode control device of FIG. 1. It is a schematic block diagram of the principal part of the light emitting diode control apparatus which concerns on 4th Embodiment of this invention. It is a schematic block diagram of the principal part of the light emitting diode control apparatus which concerns on 5th Embodiment of this invention. It is a schematic block diagram which shows an example of the data interface circuit in FIG. It is a system block diagram which shows an example of the light emission system using multiple light emitting diode control apparatuses of FIG. FIG. 16 is a system configuration diagram illustrating a modification of the light emitting system of FIG. 15. It is a schematic block diagram of the principal part of the modification of the light emitting diode control apparatus of FIG. It is the schematic block diagram which rewritten the light emitting diode control apparatus of FIG. 1 focusing on a power supply system. It is a schematic block diagram of the principal part of the light emitting diode control apparatus which concerns on 6th Embodiment of this invention. It is a schematic block diagram of the principal part of the light emitting diode control apparatus which concerns on 7th Embodiment of this invention. It is a schematic block diagram of the light emitting diode control apparatus which concerns on 8th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The present invention is not limited to the following embodiment. Further, the following embodiments may be appropriately combined.

<First Embodiment>
FIG. 1 is a schematic block diagram of a light emitting diode control device 10 according to the first embodiment of the present invention. 1 includes an integrated circuit 11, a power supply 12, and a plurality of, for example, n light emitting diodes 13a (1) to 13a (n), 13b (1) to 13b (n), and 13c (1). ~ 13c (n). Here, n is a natural number of 1 or more.

The integrated circuit 11 includes, as input / output terminals, a power supply terminal 21, a ground terminal 22, an anode terminal 23, three cathode terminals 24a, 24b, 24c, a transfer data input terminal (SIN) 26, and a transfer clock input terminal (SCKIN) 27. , A transfer data output terminal (SOUT) 28 and a transfer clock output terminal (SCKOUT) 29.
The transfer data input terminal 26, the transfer clock input terminal 27, the transfer data output terminal 28, and the transfer clock output terminal 29 may be configured by a pair of terminals, and a differential signal may be input to the pair of terminals.

  The power supply 12 is connected between the power supply terminal 21 and the ground terminal 22. Then, the power supply 12 applies a power supply voltage Vcc as a DC voltage of, for example, 24 V (volts) to the power supply terminal 21. The power supply voltage Vcc may be 12V, 48V, or the like.

The plurality of light emitting diodes 13a (1) to 13a (n) are connected in series. The plurality of light emitting diodes 13b (1) to 13b (n) and the plurality of light emitting diodes 13c (1) to 13c (n) are also connected in series. As a result, three light emitting diode rows 14a, 14b, and 14c in which n light emitting diodes are connected in series are formed.
In the light emitting diode row 14a, the anode at the upper end of the row is connected to the anode terminal 23, and the cathode at the lower end of the row is connected to the cathode terminal 24a.
In the light emitting diode row 14b, the anode at the upper end of the row is connected to the anode terminal 23, and the cathode at the lower end of the row is connected to the cathode terminal 24b.
In the light emitting diode row 14c, the anode at the upper end of the row is connected to the anode terminal 23, and the cathode at the lower end of the row is connected to the cathode terminal 24c.

Hereinafter, the light emitting diodes 13a (1) to 13a (n), 13b (1) to 13b (n), and 13c (1) to 13c (n) are collectively referred to as the light emitting diode 13.
The light emitting diode rows 14a, 14b, and 14c are collectively referred to as the light emitting diode row 14.
The cathode terminals 24a, 24b, and 24c are collectively referred to as the cathode terminal 24.

The plurality of light emitting diodes 13 used in the light emitting diode rows 14a, 14b, and 14c may emit light in the same color or in different colors. For example, the three light emitting diode rows 14a, 14b, and 14c may be a combination of a row that emits red light, a row that emits blue light, and a row that emits green light. In addition, the light emitting diodes 13 of a plurality of colors may be combined in one light emitting diode row 14.
Further, the number n of the light emitting diodes 13 in each light emitting diode row 14 may be the same or different between the light emitting diode rows 14a, 14b, and 14c.

Moreover, the anode terminal 23 of the integrated circuit 11 may be two or more.
The cathode terminal 24 may be one, two, or four or more.
Further, the number of the light emitting diode rows 14 connected between one anode terminal 23 and one cathode terminal 24 may be two or more.
Further, the light emitting diode array 14 may be connected to a part of the three cathode terminals 24, and the light emitting diode array 14 may not be connected to the remaining cathode terminals 24.

  Further, one light emitting diode 13 may be connected between the anode terminal 23 and the cathode terminal 24.

  The integrated circuit 11 includes, as internal circuits, a power supply circuit 31, a DA (Digital to Analog) converter (DAC) 32, a voltage source circuit (VA_SOURCE) 33, a current source circuit 34, an output voltage control unit (VA_CTRL) 35, and an adjustment voltage detection. A circuit 36, a lower limit voltage detection circuit 37, a data interface unit (DATA_I / F) 41, a display timing control unit (T_CTRL) 42, an oscillator (OSC) 43, and a reset circuit (RST) 44 are provided.

The power supply circuit 31 is connected to the power supply terminal 21. The power supply circuit 31 generates an internal power supply voltage Vdd from the power supply voltage Vcc input to the power supply terminal 21.
The internal power supply voltage Vdd includes a DA converter 32, a current source circuit 34, an output voltage control unit 35, an adjustment voltage detection circuit 36, a lower limit voltage detection circuit 37, a data interface unit (I / F unit) 41, and a display timing control unit. 42, an oscillator 43, and a reset circuit 44.

  FIG. 2 is a circuit diagram showing an example of the DA converter (DAC) 32 and the voltage source circuit (VA_SOURCE) 33 in FIG.

The DA converter (DAC) 32 includes a voltage generation circuit 51, m resistance elements 52-1 to 52-m, m transistors 53-1 to 53-m, and a selector 54. Here, m is a natural number of 2 or more.
The m resistance elements 52-1 to 52-m are connected in series. Also, the entire m resistive elements 52-1 to 52-m are connected to the voltage generation circuit 51.
A plurality of nodes N1 to Nm between the voltage generation circuit 51 and the plurality of resistance elements 52 are connected to sources of m transistors 53-1 to 53-m.
The gates of the m transistors 53-1 to 53-m are connected to the selector 54.
The drains of the m transistors 53-1 to 53-m are connected together as a node Nout. The voltage level of the node Nout becomes the voltage level of the output signal S32 of the DA converter 32.

Then, the voltage generation circuit 51 of the DA converter 32 generates the reference voltage V51.
The m resistance elements 52-1 to 52-m connected in series divide the reference voltage V51 by the ratio of the resistance values. Thereby, the plurality of nodes N2 to Nm become voltages obtained by dividing the reference voltage V51.
The control value D35 is input to the selector 54. The control value D35 is a command value of the anode voltage VA generated by the output voltage control unit 35 as will be described later.
The selector 54 controls one of the plurality of transistors 53-1 to 53-m to the on state according to the control value D35, and sets all the remaining transistors 53-1 to 53-m to the off state. Control. The selector 54 selects one node from the plurality of nodes N1 to Nm.
Thereby, the DA converter 32 outputs the voltage of the node selected by the selector 54 based on the control value D35 as an analog voltage. This analog voltage is input to the voltage source circuit 33 as the reference voltage Vref.

The voltage source circuit (VA_SOURCE) 33 is a switching power supply, and includes a switching control circuit 61, a transistor 62, a coil 63, a diode 66, a capacitor 64, and two voltage dividing resistance elements 65-1 and 65-2. The voltage source circuit 33 outputs the anode voltage VA to the anode terminal 23.
The drain of the transistor 62 is connected to the power supply terminal 21, and the source is connected to one terminal of the coil 63 and the cathode of the diode 66.
The anode of the diode 66 is connected to the ground terminal 22.
The other terminal of the coil 63 is connected to the anode terminal 23.
The capacitor 64 is connected between the anode terminal 23 and the ground terminal 22.
The two voltage dividing resistance elements 65-1 and 65-2 are connected in series with each other. The whole is connected between the anode terminal 23 and the ground terminal 22.
The switching control circuit 61 controls the gate of the transistor 62.

  In the voltage source circuit 33, the anode voltage VA is divided by the two voltage dividing resistance elements 65-1 and 65-2. A node N65 between the two voltage dividing resistance elements 65-1 and 65-2 is a voltage V65 obtained by dividing the anode voltage VA.

The switching control circuit 61 compares the divided voltage V65 of the node N65 with the voltage (reference voltage Vref) of the output signal S32 of the DA converter 32, and performs switching control of the gate of the transistor 62 according to the comparison result.
For example, when the divided voltage V65 is lower than the voltage (reference voltage Vref) of the output signal S32 of the DA converter 32, the ON / OFF duty ratio of the transistor 62 is controlled so that the current supplied to the anode terminal 23 increases. To do.
On the other hand, when the divided voltage V65 is higher than the voltage (reference voltage Vref) of the output signal S32 of the DA converter 32, the ON / OFF duty ratio of the transistor 62 is controlled so that the current supplied to the anode terminal 23 is reduced. .

Thus, the voltage source circuit 33 charges the capacitor 64 so that the voltage V65 obtained by dividing the anode voltage VA becomes equal to the output voltage (reference voltage Vref) of the DA converter 32.
Then, the voltage source circuit 33 outputs the anode voltage VA of the following formula 2 to the anode terminal 23. In the following formula 2, R1 is a resistance value of the voltage dividing resistor element 65-1, R2 is a resistance value of the voltage dividing resistor element 65-2, and V65 is a divided voltage V65.

  VA = (R1 + R2) × V65 ÷ R2 Equation 2

FIG. 3 is a circuit diagram showing an example of the current source circuit 34 in FIG.
The current source circuit 34 is connected to the three cathode terminals 24 a, 24 b, 24 c and the display timing control unit 42.

As shown in FIG. 3, the current source circuit 34 is basically configured as a current mirror circuit, and has one NPN transistor 71, three NPN transistors 72 to 74 as current output transistors, and transistors 72 to 74 turned on. Three on transistors 75-1, 75-2, 75-3, and three off transistors 76-1, 76-2, 76-3 that turn off the transistors 72-74.
That is, the current source circuit 34 is a current source circuit 34 with an on / off function. The number of current output transistors 72 to 74 may be the same as the number of cathode terminals 24.

  The transistor 71 has a collector connected to the current source I, an emitter connected to the ground terminal 22, and a base connected to the collector. Therefore, the transistor 71 functions as a diode.

The transistors 72 to 74 have their collectors connected to the three cathode terminals 24a, 24b, and 24c, their emitters connected to the ground terminal 22, and their respective bases as the drains of the three on transistors 75-1 to 75-3. Connected to.
The sources of the on transistors 75-1 to 75-3 are connected to the node N71 to which the base of the transistor 71 functioning as a diode is connected.
The off transistors 76-1 to 76-3 are connected to nodes N 72, N 73, and N 74 whose drains are connected to the bases of the transistors 72 to 74, and their sources are connected to the ground terminal 22.

Therefore, for example, the gate of the on-transistor 75-1 is controlled to the high level to turn on the on-transistor 75-1, and the gate of the off-transistor 76-1 is controlled to the low level to turn off the transistor 76--. When 2 is turned off, the base N72 of the transistor 72 is connected via the on transistor 75 to the base N71 of the transistor 71 functioning as a diode.
Thereby, a current mirror circuit of the transistor 72 and the transistor 71 is formed.
Then, the same current Ia as the collector current Iref of the transistor 71 functioning as a diode, or the current Ia obtained by multiplying the collector current Iref flows through the collector and cathode terminal 24a of the transistor 72.

Conversely, the gate of the on-transistor 75-1 is controlled to a low level to turn off the on-transistor 75-1, and the gate of the off-transistor 76-1 is controlled to a high level to turn off the transistor 76--. When 1 is turned on, the base N72 of transistor 72 is pulled down through off transistor 76-1.
By this pull-down, the transistor 72 is turned off.
Further, the current Ia does not flow through the collector of the transistor 72 and the cathode terminal 24a.

The relationship between the on / off control state of the on-transistor 75-2 and off-transistor 76-2 and the current Ib of the collector and cathode terminal 24b of the transistor 73, and the on-transistor 75-3 and off-transistor 76- The relationship between the ON / OFF control state 3 and the current Ic of the collector of the transistor 74 and the cathode terminal 24c is the same.
Thus, the constant current source circuit 34 functions as constant current sources 34a, 34b, and 34c configured as three sets of current mirrors.

  Further, the voltage source circuit 33 is connected to the anode of the light emitting diode 13a (1) at the upper end of the light emitting diode row 14, and the current source circuit 34 with an on / off function is connected to the cathode of the light emitting diode 13a (n) at the lower end. Since the current flowing through the light-emitting diode 13 can be turned on and off stably and at high speed, the light-emitting diode 13 can be stably blinked at high speed.

FIG. 4 is a circuit diagram showing an example of a circuit of the control value generation system in FIG.
4, the adjustment voltage detection circuit (VH_DTCT) 36, the lower limit voltage detection circuit (VL_DTCT) 37, and the output voltage control unit (VA_CTRL) 35 in FIG. 1 are drawn.

  The adjustment voltage detection circuit (VH_DTCT) 36 includes a voltage generation circuit 81, three comparators 82-1, 82-2, 82-3, and an AND circuit 83.

  The voltage generation circuit 81 of the adjustment voltage detection circuit 36 is, for example, more than the base voltages (hereinafter also referred to as voltages of control terminals (nodes N72 to N74)) V71, V72, V73 of the transistors 71, 72, 73 of the current source circuit 34. A slightly higher voltage may be generated. The voltage of the control terminals N72 to N74 during energization is, for example, about 0.7V. Therefore, the voltage generation circuit 81 may generate an adjustment reference voltage V81 of 1.1V, for example.

The number of comparators 82-1 to 82-3 of the adjustment voltage detection circuit 36 may be the same as the number of cathode terminals 24a to 24c.
The inverting input terminals of the comparators 82-1 to 82-3 are connected to the voltage generation circuit 81 in common. The non-inverting input terminal is connected to separate cathode terminals 24a to 24c.
The comparators 82-1 to 82-3 output a high level signal when the cathode voltages VKa to VKc input to the comparators 82-1 to 82-3 are higher than the adjustment reference voltage V81, and output a low level signal when the cathode voltages VKa to VKc are low.

The comparators 82-1 to 82-3 of the adjustment voltage detection circuit 36 are connected to the AND circuit 83.
The AND circuit 83 outputs a high level signal when all the output signals of the three comparators 82-1 to 82-3 are at a high level, and outputs a low level signal otherwise.

Therefore, the adjustment voltage detection circuit 36 outputs a high-level signal S36 when all of the three cathode voltages VKa to VKc are higher than the adjustment reference voltage V81 (eg, 1.1 V).
The adjustment voltage detection circuit 36 outputs a low-level signal S36 when any one of the three cathode voltages VKa to VKc is lower than the adjustment reference voltage V81 (eg, 1.1 V).

  The lower limit voltage detection circuit (VL_DTCT) 37 includes a voltage generation circuit 91, three comparators 92-1, 92-2, 92-3, and an OR circuit 93.

The voltage generation circuit 91 of the lower limit voltage detection circuit 37 may generate the voltage V91 that is between, for example, the voltages V72 to V74 of the control terminal of the current source circuit 34 and the adjustment reference voltage V81.
The voltages V72 to V74 at the control terminal of the current source circuit 34 when energized are, for example, about 0.7V.
The adjustment reference voltage V81 is about 1.1V, for example.
In this case, the voltage generation circuit 91 may generate a lower limit reference voltage V91 of 0.9V, for example.

The number of comparators 92-1 to 92-3 of the lower limit voltage detection circuit 37 may be the same as the number of cathode terminals 24a to 24c.
The non-inverting input terminals of the comparators 92-1 to 92-3 are commonly connected to the voltage generation circuit 91. The inverting input terminals are connected to the cathode terminals 24a to 24c, respectively.
Each of the comparators 92-1 to 92-3 outputs a high level signal when the cathode voltages VKa to VKc are lower than the lower limit reference voltage V91, and outputs a low level signal when the cathode voltages VKa to VKc are higher.

The comparators 92-1 to 92-3 of the lower limit voltage detection circuit 37 are connected to the OR circuit 93.
The OR circuit 93 outputs a low level signal when all the output signals of the three comparators 92 are at a low level, and outputs a high level signal otherwise.

For this reason, the lower limit voltage detection circuit 37 outputs a high-level signal S37 when at least one of the three cathode voltages VKa to VKc is lower than the lower limit reference voltage V91 (for example, 0.9 V).
The lower limit voltage detection circuit 37 outputs a low level signal S37 when all of the three cathode voltages VKa to VKc are higher than the lower limit reference voltage V91 (for example, 0.9 V).

  The output voltage control unit (VA_CTRL) 35 includes a standard value register 101 and an up / down counter 102.

The standard value register 101 stores a control value.
The control value stored in the standard value register 101 is a value corresponding to the anode voltage VA that allows the currents Ia to Ic necessary for light emission to flow through all the light-emitting diode arrays 14.
In particular, the control value stored in the standard value register 101 allows the currents Ia to Ic necessary for light emission to flow even if the drop voltage fluctuates due to manufacturing variations of the light emitting diode 13 and the environmental temperature (or operating temperature range). The value may correspond to the anode voltage VA that can be
Specifically, for example, the standard value register 101 corresponds to the anode voltage VA obtained by adding the voltages V72 to V74 of the control terminal of the current source circuit 34 to the maximum voltage drop generated in the three light emitting diode rows 14. What is necessary is just to memorize | store the control value to perform.
A control value corresponding to a voltage obtained by adding a voltage margin to the anode voltage VA may be stored in the standard value register 101.

The maximum voltage drop generated in one light emitting diode array 14 can be calculated by, for example, Equation 3 below.
In Equation 3, Vf (max) is the maximum value of the voltage drop of the light emitting diode 13 in consideration of manufacturing variations and environmental temperature (operating temperature range), n is the number of light emitting diodes 13 connected in series, and Vf (total) is This is the maximum voltage drop that occurs in one light-emitting diode array 14.

  Vf (total) = Vf (max) × n Equation 3

  By storing the control value corresponding to Vf (total) in Equation 3 in the standard value register 101, even if the maximum voltage drop Vf (max) occurs in the three light emitting diode rows 14, three rows of light emitting diodes A necessary voltage can be applied to the column 14 to cause the currents Ia to Ic to flow through the plurality of light emitting diodes 13.

When the reset signal S44 is input, the up / down counter 102 reads the control value read from the standard value register 101 as an initial value. Further, when the start signal S42D is input, the up / down counter 102 outputs the control value D102 read from the standard value register 101 to the DA converter 32.
Therefore, the output value of the up / down counter 102 becomes the control value D35 output by the output voltage control unit 35.

Then, after the start signal is input, when the down input D from the adjustment voltage detection circuit 36 becomes high level, the up / down counter 102 decreases the control value in synchronization with the clock signal S42E.
Further, when the up input U from the lower limit voltage detection circuit 37 becomes high level, the up / down counter 102 increases the control value in synchronization with the clock signal S42E.

FIG. 5 is a timing chart showing signal waveforms at various parts in FIG.
5A is a signal waveform of the detection signal S36 of the adjustment voltage detection circuit 36, FIG. 5B is a waveform of the detection signal S37 of the lower limit voltage detection circuit 37, and FIG. 5C is input to the up / down counter 102. 5D shows a waveform corresponding to the control value D35 output from the up / down counter 102. FIG.

In the period in which the detection signal S36 of the adjustment voltage detection circuit 36 in FIG. 5A is at a high level, the up / down counter in FIG. 5D is input each time the clock signal S42E in FIG. The control value D35 of 102 decreases by one step.
Further, in the period in which the detection signal S37 of the lower limit voltage detection circuit 37 in FIG. 5B is at a high level, the up / down counter 102 in FIG. 5D is input every time the clock signal S42E in FIG. The control value D35 increases by one step.
The width of one step may be 1 or 2 or more.
Further, by appropriately setting the cycle of the clock signal S42E, this feedback control system can be prevented from oscillating.

  Next, overall light emission control of the light emitting diode control device 10 according to the first embodiment having the configuration shown in FIGS. 1 to 4 will be described.

FIG. 6 is a timing chart showing an example of anode voltage control in the light emitting diode control device 10 of FIG.
6A shows the waveform of the start signal S42D output from the display timing control unit 42 to the up / down counter 35, FIG. 6B shows the waveform corresponding to the control value D35 output from the up / down counter 102, and FIG. ) Is the waveform of the anode voltage VA, FIG. 6D is the waveform of the detection signal S36 of the adjustment voltage detection circuit 36, and FIG. 6E is the waveform of the detection signal S37 of the lower limit voltage detection circuit 37.
And the timing chart of FIG. 6 is a timing chart when the lighting control for making the light emitting diode 13 light-emit with fixed brightness | luminance is started.

When the light emitting diode 13 is caused to emit light, the display timing control unit 42 outputs a start signal S42D to the up / down counter 35 as shown in FIG.
When the start signal S42D is input, the up / down counter 102 outputs a control value D35 to the DA converter 32 as shown in FIG. The control value D35 at the start of light emission is the control value D35 stored in the standard value register 101.
The DA converter 32 outputs an analog voltage corresponding to the control value D35. The voltage source circuit 33 uses the analog voltage as a reference voltage Vref, and generates an anode voltage VA corresponding to the reference voltage as shown in FIG. 6C.

Further, the display timing control unit 42 outputs duty constant current on / off signals S42a to S42c corresponding to the luminance for each control period.
In the current source circuit 34, the on transistors 75-1 to 75-3 are turned on and the off transistors 76-1 to 76-3 are turned off by the input of the constant current on / off signals S42a to S42c. Three sets of current mirror circuits are configured in the current source circuit 34, and the current source circuit 34 is in an energizable state.

Thus, at the start of lighting, the anode voltage VA based on the control value D35 stored in the standard value register 101 is applied to the three light emitting diode rows 14. Further, current mirror circuits for the constant current sources 34a to 34c are formed in the current source circuit 34 by the constant current on / off signals S42a to S42c.
As a result, currents Ia to Ic flow through the three light emitting diode rows 14. The plurality of light emitting diodes 13 emit light.

Thereafter, when the duty period corresponding to the luminance elapses in the first control period, the display timing control unit 42 controls the constant current on / off signals S42a to S42c to a low level.
As a result, the on transistors 75-1 to 75-3 of the current source circuit 34 are turned off, and the off transistors 76-1 to 76-3 are turned on. A current mirror circuit is not formed in the current source circuit 34.
Therefore, although the anode voltage VA is applied to the three light emitting diode rows 14, no current flows through the plurality of light emitting diodes 13. The plurality of light emitting diodes 13 are turned off.

After that, the display timing control unit 42 controls the constant current on / off signals S42a to S42c to a high level in a duty period corresponding to the luminance for each control period. In the current source circuit 34, current mirror circuits for the constant current sources 34a to 34c are formed.
Thereby, the plurality of light emitting diodes 13 emit light in a period corresponding to the duty for each control period. As a result, the plurality of light emitting diodes 13 are subjected to PWM (Pulth Width Modulation) control for each control period, and emit light with luminance corresponding to the duty.
Note that light emission of the plurality of light emitting diodes 13 is controlled for each of the light emitting diode rows 14a to 14c. For example, the data interface unit 41 in FIG. 1 may receive the duty information at this time as transfer data from another light emitting diode control device 10 not shown.

  In this way, the display timing control unit 42 outputs the clock signal S42E to the up / down counter 102 while executing the control of causing the plurality of light emitting diodes 13 to emit light with the brightness of the transfer data. Specifically, the display timing control unit 42 outputs the clock signal S42E to the up / down counter 102 only during a lighting period (duty period) in which the light emitting diode 13 emits light, for example.

When the anode voltage VA is high and the detection signal S36 of the standard voltage detection circuit 36 is at a high level as shown in FIG. 6D, the up / down counter 102 receives the clock signal S42E every time the clock signal S42E is input. As shown in B), the control value D35 is decreased.
When the control value D35 decreases, as shown in FIG. 6C, the anode voltage VA generated by the voltage source circuit 33 also decreases accordingly.
By this control, the cathode voltages VKa to VKc are controlled so that all of them do not become 1.1 V or more, for example.
Therefore, the potential difference between the cathode voltages VKa to VKc and the voltages V72 to V73 of the control terminals of the current source circuit 34 is reduced.

When the anode voltage VA is low and the detection signal S37 of the lower limit voltage detection circuit 37 becomes high level as shown in FIG. 6 (E), the up / down counter 102 receives the clock signal as shown in FIG. 6 (B). Each time S42E is input, the control value D35 is increased.
When the control value D35 increases, as shown in FIG. 6C, the anode voltage VA generated by the voltage source circuit 33 also increases accordingly.
By controlling the anode voltage VA, the cathode voltages VKa to VKc are controlled so that none of them becomes 0.9 V or less, for example.
Therefore, a minimum potential difference can be secured as a potential difference between the cathode voltages VKa to VKc and the voltages V72 to V73 of the control terminal of the current source circuit 34.
As a result, currents Ia, Ib, and Ic flow in the light emitting diode rows 14a to 14c, and the light emitting diode rows 14a to 14c can emit light with a desired luminance.

As described above, in the first embodiment, the output voltage generation unit 35 generates the control value D35 whose value is updated according to the detection of the adjustment voltage detection circuit 36. The DA converter 32 converts the control value D35 into the analog voltage Vref. The voltage regulator transistor 62 of the voltage source circuit 33 generates an anode voltage VA corresponding to the analog voltage Vref. Then, the voltage source circuit 33 decreases the anode voltage VA.
Therefore, in the first embodiment, even if manufacturing variation occurs in the characteristics of the plurality of light emitting diodes 13, the anode voltage is adjusted in accordance with the forward voltage drop determined according to the combination of the plurality of light emitting diodes 13 actually used. VA can be lowered.
That is, in the first embodiment, the anode voltage VA can be lowered so that the adjustment voltage detection circuit 36 does not detect that all of the cathode voltages VKa to VKc are equal to or higher than the adjustment reference voltage V81.
In the first embodiment, the potential difference between the voltage V72 to V74 of the control terminal of the current source circuit 34 and the cathode voltage VKa to VKc is reduced to suppress useless power consumption, and the power consumption is suppressed. The plurality of light emitting diodes 13 can emit light with a desired luminance.

In the first embodiment, when at least one of the cathode voltages VKa to VKc is equal to or lower than the lower limit reference voltage V91, the voltage source circuit 33 increases the anode voltage VA.
Therefore, in the voltage source circuit 33 of the first embodiment, a potential difference can be ensured between the cathode voltages VKa to VKc detected by the lower limit voltage detection circuit 37 and the voltages V72 to V74 of the control terminals of the current source circuit 34. Thus, the node voltage VA can be adjusted.
Therefore, in the first embodiment, the currents Ia to Ic flowing through the light emitting diode 13 can be secured, and the luminance of the light emitting diode 13 can be prevented from being insufficient.

In the first embodiment, by these controls, at least one of the cathode voltages VKa to VKc can be controlled to an optimum voltage within a range of 0.9 to 1.1 V, for example.
Further, in the first embodiment, wasteful power loss in the current source circuit 34 can be minimized even though the voltage drop of the light emitting diode 13 is not constant due to manufacturing variations, temperature fluctuations, and the like.
In the first embodiment, the control value D35 is digitally updated in synchronization with the clock signal S42E. Therefore, in the first embodiment, as in the case of the analog feedback control, the anode voltage VA can be prevented from oscillating and not becoming unstable or unstable.

In the first embodiment, the detection results of the cathode voltages VKa, VKb, and VKc are fed back only during the period when the light emitting diode 13 is turned on, and the anode voltage VA is controlled to be maintained when the light is turned off. Accordingly, in the first embodiment, the necessary anode voltage VA can be applied immediately after the start of lighting to quickly turn on and quickly turn off. Moreover, in 1st Embodiment, the light emitting diode 13 can be blinked at high speed.
On the other hand, unlike the present embodiment, for example, when the anode voltage VA is controlled by monitoring the current Ia of the light emitting diode 13, it takes time until the anode voltage VA becomes a necessary voltage. Therefore, with this control method, it is possible to turn on quickly and turn off quickly.

In addition, the display timing control unit 42 according to the first embodiment supplies currents Ia to Ic from the current source circuit 34 to the light emitting diode rows 14 a to 14 c with a duty according to data received by the data interface unit 41.
In the first embodiment, the display of the light emitting diode rows 14a to 14c can be changed according to data.

<Second Embodiment>
FIG. 7 is a schematic block diagram of the light emitting diode control device 10 according to the second embodiment of the present invention. The light emitting diode control device 10 of FIG. 7 differs from the light emitting diode control device 10 of FIG. 1 in that an abnormal voltage detection circuit 111 is added.

FIG. 8 is a circuit diagram showing an example of a circuit of the control value generation system in FIG.
The abnormal voltage detection circuit (VHMAX_DTCT) 111 includes a voltage generation circuit 112, three comparators 113-1, 113-2, and 113-3, and an OR circuit 114.

The voltage generation circuit 112 of the abnormal voltage detection circuit 111 may generate a voltage V112 that is greater than the adjustment reference voltage V81, for example. The voltage generation circuit 112 may generate an abnormality detection voltage V112 of about 4.0V, for example.
The voltage difference between the drop voltage Vf of the high brightness green light emitting diode and the drop voltage Vf of the high brightness blue light emitting diode is, for example, about 1.5V.
Therefore, in the three light emitting diode rows 14, when the specification is such that two red light emitting diodes, two blue light emitting diodes and two green light emitting diodes can be connected in series, the voltage drop difference between the three light emitting diode rows 14. Therefore, it is necessary to allow a voltage difference of 3V at a minimum.
The current source circuit 34 requires a voltage of about 1.0 V, for example.
Therefore, in the case of such a specification, the abnormality detection voltage V112 needs to be 4.0 V or more, for example.

The voltage generation circuit 112 is connected to the inverting input terminals (−) of the comparators 113-1 to 113-3 of the abnormal voltage detection circuit 111. Cathode terminals 24a to 24c are connected to the non-inverting input terminal (+).
The comparators 113-1 to 113-3 output a high level signal when the voltage at the cathode terminals 24a to 24c is higher than the abnormality detection voltage V112, and output a low level signal when the voltage is low.

The comparators 113-1 to 113-3 of the abnormal voltage detection circuit 111 are connected to the OR circuit 114.
The output signal S114 of the OR circuit 114 becomes a low level when all the output signals of the three comparators 113-1 to 113-3 are at a low level, and otherwise becomes a high level.

Therefore, the abnormal voltage detection circuit 111 outputs a high-level signal S111 when at least one of the three cathode voltages VKa to VKc is higher than the abnormality detection voltage V112 (for example, 4.0 V).
The abnormal voltage detection circuit 111 outputs a low level signal S111 when all of the three cathode voltages VKa to VKc are lower than the abnormality detection voltage V112 (for example, 4.0 V).

As shown in FIG. 8, the output voltage control unit 35 includes an AND circuit 104 in addition to the standard value register 101 and the up / down counter 102.
One of the two input terminals of the AND circuit 104 is an inverting input terminal.
The abnormal voltage detection circuit 111 is connected to the inverting input terminal of the AND circuit 104. A lower limit voltage detection circuit 37 is connected to the other input terminal. The AND circuit 104 is connected to the up input U of the up / down counter 102.

Therefore, the AND circuit 104 of the output voltage control unit 35 supplies the output signal S37 of the lower limit voltage detection circuit 37 to the up input U of the up / down counter 102 when the output signal S111 of the abnormal voltage detection circuit 111 is at a low level. . The up / down counter 102 counts up the control value D35 in synchronization with the clock signal S42E.
Further, when the output signal of the abnormal voltage detection circuit 111 is at a high level, the AND circuit 104 maintains the up input U of the up / down counter 102 at a low level. For example, even if the lower limit voltage detection circuit 37 detects that any one of the three cathode voltages VKa to VKc is low, the output signal S114 of the AND circuit 104 is forcibly controlled to a low level.
As a result, the up input U of the up / down counter 102 is maintained at a low level. Even when the clock signal S42E is input, the up / down counter 102 does not count up the control value D35. The control value D35 output from the up / down counter 102 does not increase, and the anode voltage VA and the cathode voltages VKa to VKc also do not increase.

As described above, in the second embodiment, even if the lower limit voltage detection circuit 37 detects that any one of the cathode voltages VKa to VKc is low, if the abnormal voltage detection circuit 111 detects an abnormality, the control value D35 is Will not Increase. Further, the anode voltage VA and the cathode voltages VKa to VKc do not increase. Therefore, in the second embodiment, the anode voltage VA and the cathode voltages VKa to VKc can be prevented from rising excessively.
For example, when a part of the three light emitting diode rows 14a to 14c connected to the three cathode terminals 24a to 24c is disconnected, or when a malfunction such as disconnection occurs in some of the light emitting diode rows 14a to 14c, The lower limit voltage detection circuit 37 detects this and the control value D35 increases.
As a result of this detection, the anode voltage VA increases as the control value D35 increases, and the cathode voltages VKa to VKc of the remaining normal light emitting diode arrays 14a, 14b, 14c also increase. The cathode voltages VKa to VKc are high voltages.
When the cathode voltages VKa to VKc of the normal light emitting diode array 14 exceed 4.0 V, for example, the abnormal voltage detection circuit 111 detects an abnormality.
Thereafter, the control value D35 does not increase. Further, the anode voltage VA and the cathode voltage VKa˜ do not increase any more.

<Third Embodiment>
FIG. 9 is a schematic block diagram of a main part of the light emitting diode control device 10 according to the third embodiment of the present invention.
The light emitting diode control device 10 according to the third embodiment shown in FIG. 9 includes an adder (ADDR) 121 and a selector (SEL) 122 in the output voltage control unit 35 when compared to the light emitting diode control device 10 of FIG. It differs in that it has been added.

  The adder (ADDR) 121 adds a preset value (+ N, for example, +2) to the control value D102 of the up / down counter 102 to obtain an added value D121.

The selector (SEL) 123 selects one of the control value D102 of the up / down counter 102 and the addition value D121 of the adder 121 and supplies the selected value to the DA converter 32.
Therefore, in this embodiment, the value selected by the selector 123 becomes the control value D35 of the output voltage control unit 35.

The schematic block diagram of FIG. 9 differs from the schematic block diagram of FIG.
In FIG. 9, the light emitting diode control device 10 includes various signal terminals 21 to 29, a power supply circuit 31, light emitting diode rows 14a to 14c, a data interface unit 41, a reset circuit 44, an oscillator 43, a current source circuit 34, and the like. Omitted or simplified.

The voltage source circuit 33 (not shown) includes a switching voltage controller (VSW_CTRL) 125, an output stage circuit 126, and a capacitor 64.
The output stage circuit 126 may be composed of, for example, an FET (Field Effect Transistor), a coil, a rectifier diode, or the like.

Further, the display timing control unit 42 includes a gradation control circuit (GR_CTRL) 127 and a gradation data register (GR_REG) 128.
The gradation data register 128 stores gradation data received by the data interface unit 41, for example. The gradation data may be 36 bits, for example.
The gradation control circuit 127 causes the plurality of light emitting diodes 13 to emit light with a duty corresponding to the value of the gradation data register 128 every time the gradation control timing clock signal GTCLK is input.
Note that the gradation control timing clock signal GTCLK is a signal for setting the start timing for each control period in FIG. 6, for example. The gradation control timing clock signal GTCLK may be generated by a controller (not shown) and supplied to the gradation control circuit 127, for example.

FIG. 10 is a timing chart showing an example of a signal waveform of each part in FIG.
10A shows the waveform of the gradation control timing clock signal GTCLK input to the gradation control circuit 127, FIG. 10B shows the waveform of the switching signal S127F output from the gradation control circuit 127 to the selector 122, and FIG. 10 (C) is a waveform of the anode voltage VA, FIG. 10 (D) is a waveform of the cathode voltage VKa, and FIG. 10 (E) is a waveform showing an on / off control state of the light emitting diodes 13a (1) to 13a (n). FIG. 10F shows the waveform of the current Ia of the light emitting diodes 13a (1) to 13a (n).

When the timing clock signal GTCLK in FIG. 10A is input, the gradation control circuit 127 outputs a high-level switching signal S127F to the selector 122 as shown in FIG. 10B.
Then, the selector 122 selects the addition value D121 instead of the control value D102 and supplies it to the DA converter 32.
The DA converter 32 generates an analog voltage Vref corresponding to the added value D121.
The switching voltage controller 125 performs a switching operation according to the potential difference between the detection voltage V65 of the output voltage VA and the analog voltage Vref.
The output stage circuit 126 charges the capacitor 64.
As a result, as shown in FIG. 10C, the anode voltage VA rises from a voltage corresponding to the control value D102 to a voltage corresponding to the added value D121. As shown in FIG. 10D, the cathode voltage VKa also increases with the anode voltage VA. The cathode voltage VKa and the anode voltage VA are preboosted.

After outputting the high level switching signal S127F to the selector 122, the gradation control circuit 127 controls the current source circuit 34 to be in an ON state. For example, the gradation control circuit 127 may control the current source circuit 34 to be in an on state after 3 to 16 cycles of the clock signal GTCLK after controlling the switching signal S127F to a high level.
Accordingly, as shown in FIG. 10E, the control state of the light emitting diode 13 is switched from the off state to the on state.
At this time, the high anode voltage VA corresponding to the added value D121 is already applied to the plurality of light emitting diodes 13.
Therefore, as shown in FIG. 10F, the plurality of light emitting diodes 13 include currents Ia (, Ib, Ic) to be drawn into the current source circuit 34 immediately after switching the control state of the light emitting diodes 13 to the on state. Flows.

After controlling the current source circuit 34 to the on state, the gradation control circuit 127 returns the switching signal S127F from the high level to the low level. For example, the gradation control circuit 127 may return the switching signal S127F from the high level to the low level after several cycles of the clock signal GTCLK after controlling the current source circuit 34 to the on state.
Thereby, the selector 122 selects the control value D102 instead of the addition value D121 and supplies it to the DA converter 32.
The DA converter 32 generates an analog voltage corresponding to the control value D102.
The switching voltage controller 125 performs a switching operation according to the potential difference between the detection voltage V65 of the anode voltage VA and the analog voltage Vref.
The output stage circuit 126 attempts to charge the capacitor 64 to a voltage corresponding to the control value D102.
Further, the accumulated charge of the capacitor 64 is consumed by the light emission of the light emitting diode 13.
As a result, as shown in FIG. 10C, the anode voltage VA drops from a voltage corresponding to the addition value D121 to a voltage corresponding to the control value D102.
Further, as shown in FIG. 10D, the cathode voltage VKa also drops together with the anode voltage VA.

In a period in which this series of control is executed, as shown in FIG. 10E, after the control state of the light emitting diode 13 is switched from the off state to the on state, as shown in FIG. 10C and FIG. Thus, the anode voltage VA and the cathode voltage VKa decrease instantaneously.
This is because the inrush current of the plurality of light emitting diodes 13 is larger than the current for charging the capacitor 64 by the voltage source circuit 33 having the switching voltage controller 125 and the output stage circuit 126.
Further, the switching voltage controller 125 and the output stage circuit 126 have a control response delay or the like, so that the insufficient current cannot be compensated instantaneously.

However, in the third embodiment, before the control state of the light emitting diode 13 is switched from the off state to the on state, the cathode voltage VKa is boosted as shown in FIG.
Therefore, even if the cathode voltage VKa temporarily decreases, the cathode voltages VKa, VKb, and VKc do not become lower than the voltages V72, V73, and V74 of the control terminal of the current source circuit 34.
Therefore, as shown in FIG. 10F, currents Ia, Ib, and Ic drawn by the current source circuit 34 flow in the light emitting diode 13 immediately after the control state of the light emitting diode 13 is switched from the off state to the on state. .

On the other hand, in the light emitting diode control device 10 of FIG. 1, for example, the voltage difference between the cathode voltages VKa, VKb, VKc and the control terminal voltages V72, V73, V74 of the current source circuit 34 is the minimum necessary voltage difference. The anode voltage VA is controlled so that
Therefore, in the light emitting diode control device 10 of FIG. 1, the cathode voltages VKa, VKb, and VKc are applied to the control terminals N72, V73, and V74 of the current source circuit 34 immediately after switching the control state of the light emitting diode 13 from the off state to the on state. There is a risk that the voltage will drop to a voltage below this value.
In this case, the currents Ia, Ib, and Ic set in the current source circuit 34 do not flow through the light emitting diode 13.
This will be described in detail below.

FIG. 11 is a timing chart showing an example of signal waveforms of the respective parts corresponding to FIG. 10 in the light emitting diode control device 10 of FIG.
11A shows the waveform of the anode voltage VA based on the control value D102, FIG. 11B shows the waveform of the cathode voltage VKa, and FIG. 11C shows on / off of the light emitting diodes 13a (1) to 13a (n). FIG. 11D shows the waveform of the current Ia of the light emitting diode 13.

As shown in FIGS. 11A and 11B, also in the light emitting diode control device 10 of FIG. 1, the anode voltage VA and the cathode voltage VKa are temporarily reduced immediately after the light emitting diode 13 is switched to the ON state. To do.
In addition, in the light emitting diode control device 10 of FIG. 1, the cathode voltage VKa that has temporarily decreased falls to a voltage lower than the voltage V72 of the control terminal of the current source circuit 34.
Therefore, as shown in FIG. 11D, even when the control state of the light emitting diode 13 is switched from the off state to the on state, the period until the cathode voltage VKa returns to the voltage of the control terminal N72 of the current source circuit 34 or higher. In A, the set current Ia does not flow through the light emitting diode 13.
As a result, the amount of light emitted from the light emitting diode 13 per control period is reduced. Further, the light emitting diode 13 cannot emit light with a desired luminance.

As described above, in the third embodiment, the command value D35 (the control value D102 and the addition value D121 supplied to the DA converter 32 before and after the timing at which the light emitting diode 13 is controlled from the off state to the on state. , The same) is temporarily increased to boost the anode voltage VA.
Therefore, in the third embodiment, even when the light emitting diode 13 is switched from the off state to the on state, the cathode voltages VKa, VKb, and VKc are reduced to voltages V72, V73, and V74 of the control terminal of the current source circuit 34. The light emitting diode 13 can be made to emit light with the correct luminance.

Moreover, in the third embodiment, the command value D35 supplied to the DA converter 32 is temporarily increased to obtain the effect of causing the light emitting diode 13 to emit light with the correct luminance.
Therefore, in the third embodiment, for example, it is not necessary to constantly increase the command value D35 supplied to the DA converter 32. The steady command value D35 supplied to the DA converter 32 can be a value corresponding to the anode voltage VA that can effectively reduce wasted power.
Further, in the third embodiment, it is not necessary to increase the capacity of the capacitor 64 so that the voltage does not easily fluctuate even with an inrush current. In the third embodiment, the cost can be reduced and the space can be saved by using the capacitor 64 having a small capacity. In the third embodiment, the capacity of a capacitor (not shown) on the power supply side can be reduced, and an inexpensive power supply 12 with a low response speed can be used.

<Fourth embodiment>
FIG. 12 is a schematic block diagram of a main part of the light emitting diode control device 10 according to the fourth embodiment of the present invention.
When the light emitting diode control device 10 according to the fourth embodiment shown in FIG. 12 is compared with the light emitting diode control device 10 of FIG. 9, the output voltage control unit 35 has a first adder (ADDR) instead of the first adder (ADDR). The difference is that a plurality of adders (ADDR) 121-1 to 121-p (p is a natural number) up to x-th (x is a natural number) are included.

The adders (ADDR) 121-1 to 121-p add the set values (+ N,..., + Np) to the control value D102 of the up / down counter 102 and add values D121 (1) to D121 (p) is obtained.
Note that all of the values set in the adders 121-1 to 121-p may be different or may be the same.

  Then, the selector 122 controls the control value D102 of the up / down counter 102 and the plurality of addition values D121 (1) to D121 of the adders 121-1 to 121-p according to the switching signal S127F from the gradation control circuit 127. One value is selected from (p) and output to the DA converter 32 as a command value D35.

  In the case of such a configuration, the gradation control circuit 127 can perform the following control, for example.

For example, a value that is incremented by 1 in order is set for the adders 121-1 to 121 -p. In the timing chart shown in FIG. 10, the gradation control circuit 127 sends the adders 121-1 to 121-1 to the selector 122. A switching signal S127F that continuously switches 121-p can be output.
Thereby, for example, the command value D35 supplied to the DA converter 32 increases stepwise and decreases stepwise.
Therefore, the anode voltage VA increases and decreases slowly. Further, when the anode voltage VA has a ramp waveform and the anode voltage VA and the cathode voltage VKa are changed, it is possible to suppress high frequency components (or harmonic components) contained therein.
As a result, the adjustment voltage detection circuit 36, the lower limit voltage detection circuit 37, or the abnormal voltage detection circuit 111 is erroneous even if the cathode voltages VKa, VKb, and VKc are distorted because they contain high frequency components (or higher harmonic components). It becomes difficult to detect.
Further, by changing the command value D35 stepwise over time as described above, a capacitor (not shown) on the power supply side can be reduced. As the capacitor on the power supply side, an inexpensive capacitor with a slow response speed can be used.

In addition to this, for example, in the first control period, the gradation control circuit 127 causes the selector 122 to select the adder 121-1 that adds + N to the control value D102, and as a result, the cathode voltage VKa becomes the current source. When the voltage at the control terminal N72 of the circuit 34 is interrupted and the lower limit voltage detection circuit 37 outputs a high level detection signal S37, another adder 121 that adds + 2N to the control value D102 in the next control period. -2 can be selected by the selector 122.
Further, the gradation control circuit 127 can switch the adder selected by the selector 122 between the adders 121-1 to 121-p until it is not detected by the lower limit voltage detection circuit 37.
As a result, even during a period in which the light emitting diode 13 is periodically turned on, the anode voltage VA becomes a minimum voltage at which the cathode voltage VKa does not interrupt the voltage V72 of the control terminal of the current source circuit 34. As a result, wasteful power consumption can be suppressed.

  Further, the gradation control circuit 127 can use the adders 121-1 to 121-p properly depending on, for example, the mode.

As described above, in the fourth embodiment, the adders 121-1 to 121-p add a preset value to the control value D102 generated by the up / down counter 102, and the selector 122 Then, one of the control value D102 and the addition values D121 (1) to D121 (p) is selected and supplied to the DA converter 32.
As a result, the gradation control circuit 127 supplies the light-emitting diode 13 to the light-emitting diode 13 with the current source circuit 34 in a state where the selector 122 selects any one of the addition values D121 (1) to D121 (p) and increases the anode voltage VA. Current supply can be started.
Therefore, even if the anode voltage VA decreases due to the inrush current at the start of lighting of the light emitting diode 13, the cathode voltages VKa to VKc do not become lower than the voltages V72 to V74 of the control terminal of the current source circuit 34.
As a result, in the fourth embodiment, immediately after the current supply to the light emitting diode 13 by the current source circuit 34 is started, the currents Ia to Ic can be supplied to the light emitting diode 13 to emit light.

<Fifth Embodiment>
FIG. 13 is a schematic block diagram of a main part of the light emitting diode control device 10 according to the fifth embodiment of the present invention.
The light emitting diode control device 10 according to the fifth embodiment shown in FIG. 13 differs from the light emitting diode control device 10 of FIG. 7 in that an abnormal voltage detection circuit 111 is connected to the data interface unit 41.

FIG. 14 is a schematic block diagram showing an example of the data interface unit 41 in FIG.
The data interface unit 41 includes an n-bit shift register (SHIFT_REG) 131, a selector (SEL) 132, an output circuit 133, and a clock buffer (CLK_BUFF) 134.

The transfer data input terminal (SIN) 26 and the transfer clock input terminal (SCKIN) 27 are connected to the shift register 131.
The shift register 131 and the abnormal voltage detection circuit 111 are connected to the selector 132.
The selector 132 is connected to the output circuit 133.
The output circuit 133 is connected to the transfer data output terminal (SOUT) 28.
The transfer clock input terminal 27 is connected to the clock buffer 134.
The clock buffer 134 is connected to the transfer clock output terminal (SCKOUT) 29.

The shift register 131 stores q-bit data. Note that q is a natural number and may be 40, for example.
The shift register 131 outputs the most significant bit MSB data DOFL of the q-bit data to be stored to the selector 132.
Further, when the transfer clock signal is input from the transfer clock input terminal 27, the shift register 131 latches data input from the transfer data input terminal 26. After the latch operation, the shift register 131 bit-shifts a plurality of bits of data stored before the latch operation from the lower bit to the upper bit, and stores the latched data as the least significant bit LSB.

The selector 132 selects one of the voltage level of the output data DOFL of the shift register 131 and the abnormal voltage detection signal S111 of the abnormal voltage detection circuit 111 and outputs the selected voltage level to the output circuit 133.
Specifically, the selector 132 selects the output data DOFL of the shift register 131 and outputs it to the output circuit 133 when the abnormal voltage detection signal S111 is at a low level.
In addition, when the abnormal voltage detection signal S111 is at a high level, the selector 132 selects the voltage level of the abnormal voltage detection signal S111 and outputs it to the output circuit 133.

  When the transfer clock signal is input from the transfer clock input terminal 27, the output circuit 133 latches the output data of the selector 133 and outputs it to the transfer data output terminal 28. The output data of the output circuit 133 becomes transfer data SOUT.

The abnormal voltage detection circuit 111 controls the abnormal voltage detection signal S111 to a high level when any one of the cathode voltages VKa, VKb, and VKc becomes, for example, 4.0 V or higher. In other cases, the abnormal voltage detection circuit 111 controls the abnormal voltage detection signal S111 to a low level.
Therefore, in a normal state where the abnormal voltage detection circuit 111 does not detect an abnormality, the abnormal voltage detection signal S111 is at a low level. In this case, the output data DOFL of the shift register 131 is supplied to the output circuit 133. When the transfer clock signal is input, the output circuit 133 latches the output data DOFL and outputs it to the transfer data output terminal 28.
Therefore, an overflow data signal that is no longer stored in the shift register 131 due to the input of the transfer clock signal is output from the transfer data output terminal 28.

When the abnormal voltage detection circuit 111 detects an abnormality, the abnormal voltage detection signal S111 is at a high level. In this case, the voltage level (high level) of the abnormal voltage detection signal S111 is supplied to the output circuit 133. When the transfer clock signal is input, the output circuit 133 latches this voltage level (high level) and outputs it to the transfer data output terminal 28.
Therefore, a high level signal is output from the transfer data output terminal 28.

FIG. 15 is a system configuration diagram showing an example of a light emitting system 1 using a plurality of light emitting diode control devices 10 of FIG.
The light emitting system 1 of FIG. 15 includes a plurality of light emitting diode rows 14, r light emitting diode control devices 10, a controller (CTRL) 2, and a power source 12. The display unit 4 is formed by the plurality of light emitting diode rows 14. Here, r is a natural number.
In addition, the display part 4 should just be installed in the outer wall of a building, a square in a building, etc., for example. The display unit 4 displays a full color image by RGB (Red-Green-Blue) and the like, and can be used as a message board or the like.

A plurality of light emitting diode rows 14 are connected to the light emitting diode control device 10.
Unlike FIG. 15, for example, a plurality of light emitting diode control devices 10 may be connected to one light emitting diode row 14. As a result, a large current can be supplied by supplying a current from a plurality of light emitting diode control devices 10 to one light emitting diode array 14.
In addition, for example, the anode of the light emitting diode row 14 of another light emitting diode control device 10 may be connected to the anode terminal 23 of one light emitting diode control device 10.

The controller 2 and the r light emitting diode control devices 10 are connected in series by a signal cable 3.
Specifically, the transfer data output terminal (SOUT) 28 and the transfer clock output terminal (SCKOUT) 29 of the controller 2 are connected to the transfer data input terminal (SIN) 26 of the first light emitting diode controller 10 by the signal cable 3. And a transfer clock input terminal (SCKIN) 27.
The transfer data output terminal (SOUT) 28 and the transfer clock output terminal (SCKOUT) 29 of the first light emitting diode control device 10 are connected to the transfer data input terminal (SIN) of the second light emitting diode control device 10 by the signal cable 3. ) 26 and a transfer clock input terminal (SCKIN) 27.
Further, the transfer data output terminal (SOUT) 28 and the transfer clock output terminal (SCKOUT) 29 of the r-th last light emitting diode control device 10 are connected to the transfer data input terminal 26 (SIN) of the controller 2 by the signal cable 3. A transfer clock input terminal (SCKIN) 27 is connected.

With this connection, the transfer data serially output from the transfer data output terminal (SOUT) 28 by the controller 2 is sequentially transmitted among the r light emitting diode control devices 10 in synchronization with the transfer clock signal SCK output by the controller 2. Transferred.
Specifically, the transfer data serially output by the controller 2 is the shift register 131 of the first light-emitting diode control device 10, the shift register 131 of the second light-emitting diode control device 10,. The data is transferred by the shift register 131 of the light emitting diode control device 10 of the second stage, and returns to the controller 2.
When the shift register 131 of the light emitting diode control device 10 is q bits, the transfer data serially output by the controller 2 after q × r clock pulses returns to the controller 2.

For example, in the second light emitting diode control device 10, when one light emitting diode row 14 is disconnected or when one light emitting diode row 14 is disconnected, the detection signal of the abnormal voltage detection circuit 111 is at a high level. It becomes. The output signal SOUT of the second light emitting diode control device 10 is maintained at a high level.
Therefore, the value after the first q bits in the q × r bit data returned to the controller 2 is changed to a high level value (for example, 1).
Therefore, the controller 2 compares the q × r-bit data transferred by itself with the received q × r-bit data, so that the second unit of the r light-emitting diode control devices 10 connected in series is connected. It is easy to recognize that an abnormality has occurred.
Therefore, the controller 2 can execute exception processing such as display control in accordance with the detected abnormality.

In FIG. 15, among the r light emitting diode control devices 10 connected in series, the transfer clock input terminal (SCKIN) 27 of the second and subsequent light emitting diode control devices 10 is the preceding light emitting diode control device 10. The transfer clock output terminal (SCKOUT) 29 is connected.
In addition, for example, as shown in FIG. 16, the transfer clock output terminals (SCKIN) 29 of all r light emitting diode control devices 10 may be connected to the transfer clock output terminal (SCKOUT) 29 of the controller 2. Good.
Furthermore, for example, r light emitting diode control devices 10 are grouped into a plurality of units, and the transfer clock input terminal 27 of the first light emitting diode control device 10 in each group is connected to the controller 2 as shown in FIG. 15 and the transfer clock input terminal 27 of the second and subsequent light-emitting diode control devices 10 in the group is connected to the transfer clock output terminal 29 of the preceding light-emitting diode control device 10 in the group as shown in FIG. The output terminal 29 may be connected.

As described above, each light emitting diode control device 10 of the fifth embodiment controls the light emission of the light emitting diode 13 using the light emission control data received from the controller 2.
In addition, each light-emitting diode control device 10, when the abnormal voltage detection circuit 111 detects an abnormality (disconnection or disconnection of the light-emitting diode array 14), sends data indicating this from the data interface unit 41 to another light-emitting diode control device. 10 and the controller 2.
Therefore, each light emitting diode control device 10 and the controller 2 can detect the occurrence of an abnormality based on the abnormality information notified from the other light emitting diode control devices 10 and can execute an arbitrary abnormality sequence.

  In the fifth embodiment, the abnormal voltage detection circuit 111 is directly connected to the data interface unit 41 as shown in FIG. 13, but the output voltage control unit 35 is connected to the data interface as shown in FIG. The unit 41 may be connected.

In the case of the connection shown in FIG. 17, the output voltage control unit 35 may buffer the output of the abnormal voltage detection circuit 111 and output the buffered signal as a signal S35 to the selector 132 of the data interface unit 41, for example. .
As a result, when the abnormal voltage detection circuit 111 detects an abnormality, for example, disconnection or disconnection of the light emitting diode array 14, the data interface unit 41 sends a signal SOUT indicating the abnormality to the other light emitting diode control devices 10 and the controller 2. Can be sent.

In the case of the connection shown in FIG. 17, for example, the output voltage control unit 35, for example, the control value D102 of the up / down counter 102 reaches the maximum value or the control value D102 reaches a preset upper limit value. In this case, the abnormality detection signal S35 may be output to the selector 132 of the data interface unit 41.
Thus, when the control value D102 of the up / down counter 102 reaches the maximum value, or when the control value D102 reaches a preset upper limit value, the output voltage control unit 35 generates the abnormality detection signal S35. By outputting to the selector 132 of the data interface unit 41, the data interface unit 41 outputs a signal SOUT indicating the abnormality to another light emitting diode control even when all the light emitting diode rows 14 are abnormal. It can be transmitted to the device 10 and the controller 2.
In other words, the output voltage control unit 35 has an abnormality in all the light emitting diode rows 14 as well as an abnormality in some of the light emitting diode rows 14, for example, when the light emitting diode rows 14 are disconnected or disconnected. Even when the data is present, the abnormality is detected, and the data interface unit 41 can notify the abnormality to the other light emitting diode control device 10 and the controller 2.

<Sixth Embodiment>
FIG. 18 is a schematic block diagram in which the light emitting diode control device 10 of FIG. 1 is rewritten mainly in the power supply system.
In the schematic block diagram of FIG. 18, the light-emitting diode control device 10 of FIG. 1 includes various signal terminals 21 to 29 of the integrated circuit 11, the number of light-emitting diode rows 14, a DA converter 32, an output voltage control unit 35, and an adjustment voltage detection. The circuit 36, the lower limit voltage detection circuit 37, the reset circuit 44, the oscillator 43, and the like are omitted.

The voltage source circuit 33 of the light emitting diode control device 10 includes a switching voltage controller (VSW_CTRL) 125, an output stage circuit 126, and a capacitor 64.
The data interface unit 41 includes an input buffer (IN_BUFF) 141, a gradation data register (GR_REG) 128, and an output buffer (OUT_BUFF) 143.
The display timing control unit 42 includes a gradation control circuit (GR_CTRL) 127.

In addition, the power supply circuit 31 of the light emitting diode control device 10 includes a linear regulator (LRGTR) 145.
The regulator voltage Vreg generated by the linear regulator 145 includes, as an internal power supply voltage Vdd, a data interface unit 41, an LED driver unit 144 (display timing control unit 42 and current source circuit 34), a DA converter 32, an output voltage control unit 35, The voltage is supplied to the adjustment voltage detection circuit 36, the lower limit voltage detection circuit 37, the reset circuit 44, and the oscillator 43.
Therefore, the internal circuits other than the voltage source circuit 33 in the integrated circuit 11 of the light emitting diode control device 10 operate with the regulator voltage Vreg.

As described above, in the light emitting diode control device 10 of FIG. 18, the voltage source circuit 33, the data interface unit 41, and the LED driver unit 144 are integrated in one integrated circuit 11.
Therefore, the power consumed by the internal circuits other than the voltage source circuit 33 in the integrated circuit 11 is expressed by the following formula 4.
In Equation 4, P is power consumption, Vcc is a power supply voltage supplied to the integrated circuit 11, and I (sum) is a total value of current consumed by internal circuits other than the voltage source circuit 33 in the integrated circuit 11.

  P = Vcc × I (sum) (4)

As apparent from Equation 4, the power consumption of internal circuits other than the voltage source circuit 33 in the integrated circuit 11 increases as the power supply voltage Vcc increases.
When an internal circuit other than the voltage source circuit 33 in the integrated circuit 11 can operate at a voltage of, for example, 5 V, the power consumed by supplying a voltage higher than that is wasted power.
In addition, wasteful power is consumed inside the integrated circuit 11 and the package of the integrated circuit 11 is heated.
As a result, a protection circuit (not shown) in the integrated circuit 11 frequently operates.
In the light emitting diode control device 10, the protection circuit of the integrated circuit 11 is provided together with the temperature sensor in the output stage circuit 126 of the voltage source circuit 33, for example.
In this case, when the package of the integrated circuit 11 generates heat, the protection circuit is activated and the current flowing through the light emitting diode 13 is limited.

  Therefore, in the light emitting diode control device 10 according to the sixth embodiment, the power supplied to the internal circuit other than the voltage source circuit 33 in the integrated circuit 11 is generated from the anode voltage VA. Thereby, in 6th Embodiment, consumption of electric power can be suppressed.

FIG. 19 is a schematic block diagram of a main part of the light emitting diode control device 10 according to the sixth embodiment of the present invention.
The light emitting diode control device 10 of FIG. 19 differs from the light emitting diode control device 10 of FIG. 18 in that it includes a switching reference voltage generation circuit 151, a switching comparator 152, and a switching switch (SW) 153.

The switching reference voltage generation circuit 151 is connected to the inverting input terminal of the switching comparator 152.
The voltage source circuit 33 is connected to the non-inverting input terminal of the switching comparator 152.
The changeover comparator 152 is connected to the changeover switch 153.
A voltage source circuit 33, a power supply terminal 21 and a linear regulator 145 are connected to the changeover switch 153.

The switching reference voltage generation circuit 151 generates a switching reference voltage V151.
The switching reference voltage V151 is a reference voltage for determining that the voltage supplied to the linear regulator 145 is switched between the anode voltage VA of the voltage source circuit 33 and the power supply voltage Vcc of the power supply terminal 21.
For this reason, the switching reference voltage V151 may be a voltage equal to or higher than a voltage required for the operation of the internal circuit other than the voltage source circuit 33 in the integrated circuit 11, for example. For example, the switching reference voltage V151 may be the same as the internal power supply voltage Vdd (for example, 7V) generated by the linear regulator 145.

The changeover comparator 152 compares the anode voltage VA and the changeover reference voltage V151 and outputs a changeover signal S152 to the changeover switch 153.
Specifically, when the anode voltage VA is lower than the switching reference voltage V151, the switching signal S152 is at a low level. Further, when the anode voltage VA is higher than the switching reference voltage V151, the switching signal S152 is at a high level.

The changeover switch 153 selects one of the voltage source circuit 33 and the power supply terminal 21 according to the changeover signal S152 and connects it to the linear regulator 145.
Specifically, when the switch signal S152 is at a low level, the switch 153 selects the power supply terminal 12 and connects it to the linear regulator 145.
In this case, the power supply voltage Vcc is supplied to the linear regulator 145. The regulator voltage Vreg generated from the power supply voltage Vcc is supplied to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.
When the switching signal S152 is at a high level, the changeover switch 153 selects the voltage source circuit 33 and connects it to the linear regulator 145.
In this case, the anode voltage VA is supplied to the linear regulator 145. The regulator voltage Vreg generated from the anode voltage VA is supplied to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.

Next, the operation of the light emitting diode control device 10 according to the sixth embodiment will be described.
When the power supply 12 is connected to the integrated circuit 11 of FIG. 19, the internal circuit of the integrated circuit 11 starts to operate. For example, the voltage source circuit 33 generates the anode voltage VA from the power supply voltage Vcc.
However, since the voltage source circuit 33 charges the capacitor 64 by a switching operation, the anode voltage VA does not become a desired voltage immediately after the power source 12 is turned on, but becomes a desired voltage after a while has passed. .

Therefore, immediately after the power supply 12 is turned on, the anode voltage VA is lower than the switching reference voltage V151 generated by the switching reference voltage generation circuit 151.
Then, the switching comparator 152 outputs a low level output signal S152. The changeover switch 153 selects the power supply terminal 21.
As a result, the power supply voltage Vcc is supplied to the linear regulator 145. The regulator voltage Vreg generated from the power supply voltage Vcc is supplied to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.
In this case, the power consumed by the internal circuits other than the voltage source circuit 33 in the integrated circuit 11 is the power calculated by Equation 4 above.

When time elapses after the power is turned on, the capacitor 64 is charged and the anode voltage VA increases. The anode voltage VA is higher than the switching reference voltage V151.
As a result, the output signal S152 of the switching comparator 152 is switched from the low level to the high level. The changeover switch 153 selects the voltage source circuit 33.
As a result, the regulator voltage Vreg generated from the anode voltage VA of the voltage source circuit 33 is supplied to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.

In this case, the power consumed by the internal circuits other than the voltage source circuit 33 in the integrated circuit 11 is the power calculated by replacing Vcc in Equation 4 with the anode voltage VA.
The anode voltage VA is a voltage generated by the voltage source circuit 33 based on the power supply voltage Vcc, and is lower than the power supply voltage Vcc.

  As a result, in the sixth embodiment, power consumed by internal circuits other than the voltage source circuit 33 in the integrated circuit 11 can be suppressed. In the sixth embodiment, wasteful power consumption can be reduced and the power consumption of the entire integrated circuit 11 can be suppressed. Moreover, in the sixth embodiment, by reducing power consumption, it is possible to suppress an increase in the package temperature of the integrated circuit 11 and prevent a protection circuit not shown from operating frequently.

In the sixth embodiment, the changeover switch 153 switches the voltage supplied to one linear regulator 145 between the power supply voltage Vcc and the anode voltage VA.
In addition, for example, the changeover switch 153 may switch a regulator voltage supplied to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.

FIG. 20 is a schematic block diagram of a main part of the light emitting diode control device 10 according to a modification of the sixth embodiment.
The light-emitting diode control device 10 according to the modification of the sixth embodiment has a startup linear regulator (Vcc_LRGTR) 161 and a regular linear regulator (VA_LRGTR) instead of the linear regulator 145, as compared with the light-emitting diode control device 10 of FIG. ) 162.

The startup linear regulator 161 is connected to the power supply terminal 21. The startup linear regulator 161 generates a startup power supply voltage Vreg1 based on the power supply voltage Vcc.
The normal linear regulator 162 is connected to the voltage source circuit 33. The normal linear regulator 162 generates the normal power supply voltage Vreg2 based on the anode voltage VA.
The starting linear regulator 161 and the regular linear regulator 162 may generate regulator voltages having the same voltage level or regulator voltages having different voltage levels.
The changeover switch 153 is connected to internal circuits other than the startup linear regulator 161, the regular linear regulator 162, and the voltage source circuit 33 in the integrated circuit 11. The changeover switch 153 selects one of the starting power supply voltage Vreg1 and the normal power supply voltage Vreg2 and supplies the selected power supply voltage to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.

In the light emitting diode control device 10 of FIG. 20, the changeover switch 153 selects the startup power supply voltage Vreg1 and supplies it to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11 at startup.
Further, when time elapses from the start, the changeover switch 153 selects the normal power supply voltage Vreg2 and supplies it to an internal circuit other than the voltage source circuit 33 in the integrated circuit 11.
As a result, even with the configuration of FIG. 20, power consumption can be reduced.

As described above, the data interface unit 41 and the LED driver unit 144 integrated in the single integrated circuit 11 together with the voltage source circuit 33 are based on the anode voltage VA in the steady state after the integrated circuit 11 is activated. Operates with the generated regulator voltage.
Therefore, the data interface unit 41 and the LED driver unit 144 can be operated in the steady state after the integrated circuit 11 is started, compared with the case where the integrated circuit 11 is continuously operated with the regulator voltage generated based on the power supply voltage Vcc. Power consumption can be reduced.

<Eighth Embodiment>
FIG. 21 is a schematic block diagram of the light emitting diode control device 10 according to the eighth embodiment of the present invention. The light emitting diode control device 10 of FIG. 21 has a current register (C_REG) 171 and a current controller (C_CTRL) for controlling the current values of the output currents Ia to Ic, as compared with the light emitting diode control device 10 of FIG. The difference is that 172 is added.

The current register 171 is connected to the data interface unit 41.
The current register 171 stores the data received by the data interface unit 41 as set values of the output currents Ia to Ic.
The current register 171 may store 7-bit data or 21-bit data, for example.

The current controller 172 is connected to the display timing control unit 42, the current register 171, and the current source circuit 34.
The current controller 172 changes the currents Ia to Ic flowing through the constant current sources 34a to 34c.

When the display timing control unit 42 outputs the constant current on / off signals S42a to S42c, the current source circuit 34 forms the constant current sources 34a to 34c.
Further, the current controller 172 changes the currents Ia to Ic flowing through the constant current sources 34 a to 34 c according to the values stored in the current register 171.
Thereby, in 8th Embodiment, the brightness of the some light emitting diode 13 can be changed according to the data which the data interface part 41 received.
In the eighth embodiment, when there is a variation in brightness among the plurality of light emitting diode rows 14a to 14c, the variation can be suppressed and the brightness can be unified.
A plurality of current registers 171 may be provided, and one of the plurality of current registers 171 may be selected by a selector and connected to the current controller 172.

  The above embodiment is a preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications or changes are possible.

DESCRIPTION OF SYMBOLS 10 ... Light emitting diode control apparatus, 13 ... Light emitting diode, 32 ... DA converter (a part of voltage control circuit), 33 ... Voltage source circuit, 34 ... Current source circuit, 35 ... Output voltage generator (part of the voltage control circuit) 36... Adjustment voltage detection circuit (first voltage detection circuit) 37 37 Lower limit voltage detection circuit (second voltage detection circuit) 41 ..Data interface section, 42... Display timing control section (light emission control section), 72, 73, 74... Current output transistor (current detection element), 82-1, 82-2, 82-3 ..Comparator (detection circuit), 92-1, 92-2, 92-3 ... Comparator (detection circuit), 102 ... Up / down counter (control value generation unit), 111 ... Abnormal voltage detection circuit (Third voltage detection circuit), 12 ... adder (adding unit), 122 ... selector

Claims (8)

A voltage source circuit for supplying a voltage to the anode of the light emitting diode;
A current source circuit for selectively supplying current to the cathode of the light emitting diode;
A first voltage detection circuit for comparing a cathode voltage of a light emitting diode connected to the current source circuit and a first reference voltage;
A second voltage detection circuit for comparing the cathode voltage with a second reference voltage lower than the first reference voltage;
A third voltage detection circuit for comparing the cathode voltage with a third reference voltage higher than the first reference voltage;
A voltage control circuit for controlling the voltage value of the voltage supplied by the voltage source circuit;
Including
The current source circuit includes a plurality of current supply elements that respectively supply current to the plurality of light emitting diodes,
The first voltage detection circuit includes a plurality of detection circuits that respectively detect cathode voltages of a plurality of light emitting diodes connected to the current source circuit,
The second voltage detection circuit includes a plurality of detection circuits that respectively detect the plurality of cathode voltages,
The third voltage detection circuit includes a plurality of detection circuits that respectively detect the plurality of cathode voltages,
The voltage control circuit is configured to reduce the supply voltage of the voltage source circuit when the first voltage detection circuit detects that all of the plurality of cathode voltages are higher than the first reference voltage. The voltage source circuit is controlled, and when the second voltage detection circuit detects that any of the plurality of cathode voltages is lower than the second reference voltage, the supply voltage of the voltage source circuit is increased. When the third voltage detection circuit detects that any one of the plurality of cathode voltages is higher than the third voltage, the second voltage detection circuit detects the second voltage detection circuit. Ignore results,
Light emitting diode control device. A data interface unit connected to another light emitting diode control device and transmitting data to the other light emitting diode control device;
When the third voltage detection circuit detects that the cathode voltage is higher than the third reference voltage, the data interface unit transmits data indicating that.
The light emitting diode control device according to claim 1. The voltage source circuit adjusts the supply voltage after starting the lighting of the light emitting diode with a preset supply voltage,
The light emitting diode control device according to claim 1. The voltage control circuit is
A control value generator for generating a control value whose value is updated according to the detection result of the first voltage detection circuit;
A DA converter for converting the control value into an analog voltage;
Including
The voltage source circuit supplies a voltage corresponding to the analog voltage;
The light emitting diode control device according to claim 1. The voltage control circuit is
An addition unit that obtains an addition value by adding a preset value to the control value generated by the control value generation unit;
A selector that selects one of the control value of the control value generation unit and the addition value of the addition unit and supplies the selected value to the DA converter;
Further including
The light emitting diode control device according to claim 4. A light emission control unit for controlling the current supply of the current source circuit;
The light emission control unit causes the current source circuit to start supplying current with the selector selecting the addition value.
The light emitting diode control device according to claim 5. The light emission control unit causes the current source circuit to supply a current with a duty according to the received light emission control data.
The light emitting diode control device according to claim 6. The voltage control circuit is
A plurality of addition units that obtain an addition value by adding a preset value to the control value generated by the control value generation unit;
A selector that selects one of the control value of the control value generation unit and the plurality of addition values of the plurality of addition units and supplies the selected value to the AD converter;
Further including
The light emitting diode control device according to claim 4.

Images