JP4917960B2 - Power monitoring circuit - Google Patents

Description

  The present invention relates to a power supply monitoring circuit that monitors the power supply of a driver that controls on / off of a switching element.

  Half-bridge consisting of one arm in which switching elements such as field effect transistors are connected in series to the DC power supply, and single-phase full bridge, three-phase full bridge, multi-phase full bridge, etc. consisting of two or more arms When the load is a DC motor and forward / reverse control is performed, the full bridge configuration is applied. When the load is a single phase motor, the half bridge or full bridge configuration is applied, and the polyphase In the case of a motor, a multiphase full bridge configuration is applied. When a field effect transistor is used as the switching element, a gate driver is provided to turn on the gate of the field effect transistor by applying a gate voltage.

  For example, in the conventional full-bridge switching power supply shown in FIG. 8, Q1 to Q4 are field effect transistors as switching elements, GD1 to GD4 are gate drivers, C1 to C3 are capacitors, and L1 and L2 are chokes. Coils, R1 and R2 are resistors, D1 and D2 are Zener diodes, PI1 and PI2 are photocouplers, SP1 and SP2 are power supply monitoring circuits, LD is a motor load, DCV is a DC power supply, + Vcc and -Vcc are DC power supply voltages , VH1 and VH2 are high-side power supplies, VL is a low-side power supply, and the high-side and low-side power supply voltages can be, for example, 15V. Further, the power sources VH1 and VH2 on the high side have different systems because the potential with respect to the ground potential fluctuates in response to the on / off of the field effect transistors Q1 to Q4. A control circuit for controlling the gate drivers GD1 to GD4 is not shown.

  The high-side field effect transistor Q1 and the low-side field effect transistor Q4 are set as one set, and the high-side field-effect transistor Q3 and the low-side field effect transistor Q2 are set as the other set and are not shown. By controlling the gate drivers GD1 to GD4 from the control circuit and alternately turning on and off one set and the other set, a single-phase AC voltage can be applied to the load LD. The choke coils L1 and L2 and the capacitor C3 function as a filter for removing a switching frequency component generated by switching, and the DC power source DCV rectifies and smoothes an AC voltage by a rectifier circuit and a smoothing circuit. In general, the DC voltage can be supplied.

  Also, Zener diodes D1 and D2, resistors R1 and R2, and light emitting elements (light emitting diodes) of photocouplers PI1 and PI2 are connected in series and connected in parallel with gate drivers GD1 and GD3. ) And power supply monitoring circuits SP1 and SP2 are connected in series, the power supply monitoring circuit SP1 monitors the state of the power supply VH1 of the gate driver GD1, and the power supply monitoring circuit SP2 monitors the state of the power supply VH2 of the gate driver GD3. . For example, when the power supply VH1 of the gate driver GD1 is normal, a current flows through the light emitting element of the photocoupler PI1 via the Zener diode D1 and the resistor R1, and light is emitted, and the power supply VL is supplied to the power supply monitoring circuit SP1 through the light receiving element. Therefore, the power supply monitoring circuit SP1 determines that the power supply VH1 of the gate driver GD1 is normal. When the voltage of the power supply VH1 decreases and becomes equal to or lower than the Zener voltage of the Zener diode D1, the photocoupler PI1 is turned off, and the power supply monitoring circuit SP1 determines that the power supply VH1 of the gate driver GD1 is abnormal, and a control circuit not shown The power supply abnormality detection signal is input to, and the drive control of each of the gate drivers GD1 to GD4 is stopped. The same operation is performed for monitoring the power supply VH2 by the power supply monitoring circuit SP2.

Also, in order to reduce the on-resistance of the high-side MOS transistor of the full bridge connection, the first booster circuit that boosts and applies the gate voltage applied to the gate and the power supply voltage of the first booster circuit are monitored. When the power supply voltage is low, the gate voltage applied to the gate of the protection MOS transistor for inputting the power supply voltage to the first booster circuit is boosted to reduce the on-resistance of the protection MOS transistor. 2 and a power supply voltage monitoring circuit that monitors the power supply voltage, stops the operation of the second booster circuit when the power supply voltage is high, and operates the second booster circuit when the power supply voltage is low (For example, refer patent document 1). It also monitors the voltage applied to the DC motor and the booster circuit for applying the gate voltage to the gate of the high-side MOS transistor of the full-bridge MOS transistor that performs forward / reverse control and speed control of the DC motor. Means for performing fault detection have also been proposed (see, for example, Patent Document 2).
JP-A-8-84055 JP 2000-125586 A

  The power supply for the gate driver on the high side of the conventional half-bridge connection, full-bridge connection, and multi-phase full-bridge connection is the same as the ground potential when the low-side switching element is turned on and off. Since the potential changes, the power supply for the high-side gate driver is provided independently. Therefore, as shown in FIG. 8, the power supply monitoring circuits SP1 and SP2 must be provided corresponding to the power supplies VH1 and VH2 of the high-side gate drivers GD1 and GD3. Therefore, there is a problem that the cost is increased.

  An object of the present invention is to solve the above-described conventional problems, and a plurality of power supplies can be monitored by a single power supply monitoring circuit with a relatively simple configuration.

The power supply monitoring circuit of the present invention is a power supply monitoring circuit for monitoring the power supply of the driver corresponding to the switching element on the high side and the low side, wherein the power supply of the driver corresponding to the switching element on the high side is the monitored power supply. , to charge through a resistor from a power source different from the monitored power supply, via said resistor and diode when a voltage drop of the monitored power supply, wherein the capacitor to discharge to the monitored power supply side, the terminal voltage and the reference of the capacitor by comparing the value, the terminal voltage and comparing means for outputting an alarm signal when lower than the reference value.

Also the power supply for charging to charge through the first resistor to the capacitor, and connected via a second resistor, the shunt regulator constituting the comparing means, the resistance of the terminal voltage of the capacitor of the second It may comprise a configuration including a third resistor a series circuit divide input to the reference of the shunt regulator with.

  In addition, a discharge resistor and a diode are connected to the high side power source of the high side driver for the high side driver corresponding to the switching element of the high side side and the low side side and the low side power source for the low side driver. It is possible to provide a configuration in which the low-side power supply is connected to the capacitor via a charging resistor.

  Also, a plurality of high-side power sources corresponding to switching elements of a plurality of high-side sides and a plurality of low-side sides and a plurality of high-side power sources of a low-side power source are connected to the capacitors via discharge resistors and diodes, respectively. It is possible to provide a configuration in which a plurality of the low-side power sources are commonly used as a power source for charging the capacitor.

  It is possible to monitor a high-side power source and a low-side power source as monitored power sources with the same power monitoring circuit, and a plurality of high-side power sources as monitored power sources, respectively. In addition, a plurality of high-side power sources and a plurality of low-side power sources can be monitored as monitored power sources, respectively, and an abnormal state in which the monitored power source voltage drops economically can be monitored. It is possible to detect.

  The power supply monitoring circuit of the present invention will be described with reference to FIG. 1. A power supply monitoring circuit VP for monitoring the power supplies VH1, VL of the drivers GD1, GD2 corresponding to the switching elements (Q1, Q2) on the high side and the low side. In this case, the capacitor is charged via the resistor R11 from a power source (VL) different from the monitored power source (VH1), and discharged to the monitored power source side via the diode D10 and the resistor R1 when the voltage of the monitored power source drops. C11 and comparison means (CMP) for comparing the terminal voltage of the capacitor C11 with a reference value and outputting an alarm signal when the terminal voltage falls below the reference value.

  FIG. 1 is an explanatory diagram of the main part of Embodiment 1 of the present invention, showing a case of half-bridge connection, Q1 and Q2 are field effect transistors as switching elements, GD1 and GD2 are gate drivers, D10 is a diode, VP Is a power supply monitoring circuit, DCV is a DC power supply, + Vcc and -Vcc are DC power supply voltages, VH1 is a high-side power supply, VL is a low-side power supply, R1, R11 to R13 are resistors, and C1, C2, and C11 are capacitors. CMP represents a comparison circuit, Vref represents a reference voltage, and ALM represents an alarm signal. Note that a load for supplying a single-phase AC voltage and a control circuit for controlling the gate drivers GD1 and GD2 are not shown.

  The power supply monitoring circuit VP mainly includes resistors R11 to R13, a capacitor C11, and a comparison circuit CMP. The power supply monitoring circuit VP applies the voltage of the power supply VL to the series circuit of the resistors R11 to R13, and the capacitor C11 is parallel to the resistors R12 and R13. And the capacitor C11 is charged via the resistor R11 with the voltage of the power supply VL. When the charging voltage of the capacitor C11 is reduced in the voltage of the high-side power supply VH1 of the monitored power supply, the high-side power supply VH1 The connection point between the resistors R11 and R12 and the high-side power supply VH1 are connected via the resistor R1 and the diode D10 so as to discharge in the direction. Further, the terminal voltage of the capacitor C11 is divided by resistors R12 and R13 and compared with the reference voltage Vref by the comparison circuit CMP. The diode D10 has a polarity to which a reverse polarity voltage is applied when the high-side power supply VH1 is normal, and the resistance R1 serving as a discharge resistance is smaller than the resistance R11 serving as a charging resistance with respect to the capacitor C11. To do. That is, the discharge time constant is made smaller than the charge time constant.

  When the high-side power supply VH1 of the monitored power supply is normal, when the high-side field effect transistor Q1 is on, the low-side field effect transistor Q2 is off, and the high-side field effect transistor Q1 is off, In any state when the low-side field effect transistor Q2 is on, the potential of the power source VH1 is higher than the potential at the connection point of the resistors R11 and R12, and a reverse polarity voltage is applied to the diode D10. Thus, the power supply monitoring circuit VP is disconnected from the high-side power supply VH1 by the diode D10. The comparison circuit CMP as a comparison means for comparing the terminal voltage of the capacitor C11 with the reference value compares the voltage across the resistor R13 obtained by dividing the charging voltage of the capacitor C11 with the resistors R12 and R13 with the reference voltage. When the high-side power supply VH1 is normal, the capacitor C11 is charged to the voltage across the resistors R12, R13 of the series circuit of the resistors R11, R12, R13, and is divided by the resistors R12, R13. The voltage across the resistor R13 is compared with a preset reference voltage Vref by the comparison circuit CMP. If the voltage is higher than the reference voltage, the alarm signal ALM is not output.

  When the voltage drops due to an abnormality in the high-side power supply VH1, when the high-side field effect transistor Q1 is on and the low-side field effect transistor Q2 is off, the potential of the high-side power supply VH1 is at least the DC power supply DCV When the high-side field effect transistor Q1 is off and the low-side field effect transistor Q2 is on, the potential of the high-side power supply VH1 is relative to the low-side potential −Vcc. When the voltage is lower than that in the normal case and falls below the terminal voltage of the capacitor C11, a forward voltage is applied to the diode D10, and the voltage is increased from the capacitor C11 through the resistor R1 and the diode D10. A discharge current flows through the side power supply VH1. In this case, when the discharge time constant of the capacitor C11 is smaller than the charge time constant, the terminal voltage of the capacitor C11 is reduced by the discharge current, and the voltage across the resistor R13 divided by the resistors R12 and R13 is also reduced. When the voltage falls below the reference voltage, an alarm signal ALM is sent from the comparison circuit CMP. This alarm signal ALM stops the control of the gate drivers GD1 and GD2 by being sent to a control circuit or the like (not shown).

  When the voltage of the power supply VL of the power supply monitoring circuit VP is lowered, the terminal voltage of the capacitor C11 is also lowered accordingly, and the voltage at both ends of the resistor R13 is also lowered. Therefore, an alarm signal ALM is transmitted from the comparison circuit CMP. become. Accordingly, by making the power supply VL of the power supply monitoring circuit VP and the power supply VL of the low side gate driver GD2 common, the power supply monitoring circuit VP can use both the high side power supply VH1 and the low side power supply VL. It can be monitored as a monitored power source. In principle, the comparison circuit CMP of the power supply monitoring circuit VP is not configured to compare the voltage divided by the resistors R12 and R13 with the reference voltage, but the terminal voltage of the capacitor C11 (the series circuit of the resistors R12 and R13). It is also possible to compare the voltage at both ends) with the reference voltage. The logic level of the alarm signal ALM can be selected to be low level or high level corresponding to the configuration of the control circuit (not shown). The power supply monitoring circuit VP may be configured to include a diode D10 and a resistor R1.

  FIG. 2 is an explanatory diagram of a main part of the second embodiment of the present invention, where the same reference numerals as those in FIG. 1 denote the same names, R14 denotes a resistor, and M11 denotes a shunt regulator. The shunt regulator M11 of the power supply monitoring circuit VP according to the second embodiment is turned off when the terminal voltage of the capacitor C11 is lowered, similarly to the function of the comparison circuit CMP according to the first embodiment, and a high level alarm signal is output. When ALM is output and the power supplies VH1 and VL are normal, the shunt regulator M11 is turned on by the voltage divided by the resistors R11 and R12, indicating a low-level normal state. Also in the second embodiment, the voltage input to the reference of the shunt regulator M11 can be used as the terminal voltage of the capacitor C11 without being divided by the resistors R12 and R13 according to the characteristics of the shunt regulator M11. . It is also possible to monitor the high-side power source VH1 and the low-side power source VL as monitored power sources.

  FIG. 3 is an explanatory diagram of a main part of the third embodiment of the present invention. In FIG. 1 and FIG. 2, the same reference numerals indicate the same names, and PC indicates a photocoupler. The field effect transistors Q1 and Q2 in FIG. 1 and FIG. 2 are shown as switch configurations, and the diode in parallel therewith indicates a parasitic diode of the field effect transistor. The diode D10 and the resistor R1 can be included in the configuration of the power supply monitoring circuit VP. Further, the value of the resistor R1 for discharging is made smaller than the value of the resistor R11 for charging the capacitor C11. When the field effect transistor Q1 is on and the field effect transistor Q2 is off, the output current flows in the direction of the arrow for the load (not shown). Conversely, the field effect transistor Q1 is off and the field effect transistor Q2 is on. The case where the output current flows in the direction opposite to the arrow at this time will be described.

  The power supply monitoring circuit VP has a configuration in which a photocoupler PC is provided in series with the shunt regulator M11 in FIG. 2, and the high-side power supply VH1 and the low-side power supply VL are monitored power supplies, both of which are normal. In this case, the charging current i1 flows through the resistor R11 due to the voltage of the power supply VL to the capacitor C11. However, when the voltage of the high-side power supply VH1 decreases, the discharging current flows from the capacitor C11 through the resistor R1 and the diode D10. i2 flows. When the power supplies VH1 and VL are normal, current flows to the shunt regulator M11 through the resistor R14, the photocoupler PC is turned on, the alarm signal ALM is low level, indicating a normal state, but an abnormal state of voltage drop. In this case, since the shunt regulator M11 is turned off, the photocoupler PC is also turned off, and a high-level alarm signal ALM is input to a control circuit or the like not shown, and the control of the gate drivers GD1 and GD2 is stopped. . As shown in the figure below, regarding the voltages v1 to v5 and the alarm signal (alarm signal) ALM, the on / off operation of the field effect transistors Q1 and Q2, the normal time and the low voltage of the power sources VH1 and VL This will be described with reference to FIGS. 4, 5, and 6.

  FIG. 4 shows voltage v1 to v4 of each part and an alarm signal ALM when the output current flows in the direction of the arrow when the high-side field effect transistor Q1 is on, and the field effect transistors Q1 and Q2 are turned on and off. Accordingly, the states (1), (2), (3) when the power source VH1 is normal, and the states (1x) when the voltage of the power source VH1 corresponding to these states (1), (2), (3) is lowered, (2x) and (3x) are shown. State (1) and state (1x) indicate that the high-side field effect transistor Q1 is on and the low-side field effect transistor Q2 is off, as indicated by Q1-ON and Q2-OFF. (2x) indicates that the field effect transistors Q1 and Q2 on the high side and the low side are off, and states (3) and (3x) indicate the electric field on the high side as indicated by Q1-OFF and Q2-ON. This shows the case where the effect transistor Q1 is off and the low-side field effect transistor Q2 is on, and shows the voltage relationship of each part in each state.

  In the state (1), since the high-side field effect transistor Q1 is on and the low-side field effect transistor Q2 is off, the voltage v1 with respect to the ground potential GND at the connection point of the field effect transistors Q1 and Q2 is DC power supply DCV Voltage Vcc. The voltage v2 across the gate driver GD1 due to the voltage of the high-side power supply VH1 is maintained at a predetermined value. The voltage v3 with respect to the ground potential GND (0 V) on the power supply VH1 side of the gate driver GD1 is v1 + v2. The voltage v4 across the capacitor C11 of the power supply monitoring circuit VP is charged by the charging current i1 through the resistor R11 by the voltage v5 of the low-side power supply VL and maintained at a constant normal level. The alarm signal ALM indicates a normal state at a low level because the photocoupler PC is turned on.

  In the state (2), since the field effect transistors Q1 and Q2 are off, the voltage v1 becomes the ground potential GND (0V) due to the parasitic diode of the field effect transistor Q2, and the voltage v3 becomes the voltage v2. Almost equal. The voltages v2 and v4 and the alarm signal ALM continue the previous state. In the state (3), since the field effect transistor Q1 is off and the field effect transistor Q2 is on, the same voltages v1 to v4 and alarm signal ALM as in the state (2) are continued.

  In the state (3x) in which the voltage v2 of the high-side power supply VH1 starts to decrease, when v3 <v4, a forward voltage is applied to the diode D10, so that the resistor R1 and the diode D10 are connected from the capacitor C11. Through which discharge current i2 flows. At this time, the charging current i1 of the capacitor C11 flows from the power source VL via the resistor R11. However, by setting the discharge time constant to be small, the terminal voltage v4 of the capacitor C11 is lowered, and the threshold of the shunt regulator M11. In the following cases, the photocoupler PC is turned off, and the alarm signal ALM is in a high level alarm state.

  In the next state (2x), the same state continues. In the next state (1x), the voltage v3 increases by the voltage Vcc of the DC power source DCV, so that the discharge current of the capacitor C11 is increased. i2 cannot flow, the voltage v4 rises due to the charging current i1 due to the voltage v5 of the low-side power supply VL, the shunt regulator M11 is temporarily turned on, the photocoupler PC is turned off, and the alarm signal ALM becomes low level. However, in the next state (2x), since the field effect transistor Q1 is turned off, the voltage v4 is lowered again by the discharge current i2 of the capacitor C11, the shunt regulator M11 is turned off, and the photocoupler PC is turned off. Thus, the alarm signal ALM becomes a high level alarm state. When the control of the gate drivers GD1 and GD2 is stopped by the alarm signal ALM being at a high level, the states (2x) and (1x) after the start of the voltage drop of the power supply VH1 do not occur. The alarm signal ALM never goes low.

  FIG. 5 shows a case in which the current flows from a load (not shown) in the direction opposite to the output current of FIG. 3, and this field effect is obtained when the high-side field effect transistor Q1 is off and the low-side field effect transistor Q2 is on. When a current flows from the load through the transistor Q2, and on the contrary, when the high-side and low-side field effect transistors Q1 and Q2 are off, the high-side field effect transistor Q1 passes through the parasitic diode from the load. In the case where the current flows from the load via the field effect transistor Q1 when the high-side field-effect transistor Q1 is on and the low-side field-effect transistor Q2 is off, the field-effect transistor In the states (1) to (3) and the states (1x) to (3x) according to the on / off states of Q1 and Q2. It shows changes in the respective portions of the voltage v1~v4 an alarm signal ALM that.

  When the high-side power supply VH1 is normal, the output current flows in the opposite direction to that shown in FIG. 3, so that the high-side field effect transistor Q1 is off and the low-side field effect transistor Q2 is on (Q1-OFF). , Q2-ON) in the state (1), since the field effect transistor Q2 on the low side is on, the voltage v1 becomes the ground potential GND (0 V). The voltage v3 is the voltage v2 of the high side power supply VH1. The terminal voltage v4 of the capacitor C11 is maintained at a normal level. Therefore, the alarm signal ALM becomes a low level indicating a normal state.

  In the state (2), the field effect transistors Q1 and Q2 are off, and the voltage v1 becomes the voltage Vcc of the DC power supply DCV and the voltage v3 becomes v2 + Vcc due to the parasitic diode of the field effect transistor Q1. In the state (3), the voltage state of the state (2) is continued by the field effect transistor Q1 on and the field effect transistor Q2 off (Q1-ON, Q2-OFF), and the high side power supply VH1 is normal. If the voltage v4 is constant, the alarm signal ALM continues to be in the low level normal state.

  In the state (3x) when the voltage of the high-side power source VH1 starts to decrease, even if the voltage v3 does not decrease below the terminal voltage v4 of the capacitor C11, the diode D10 has a forward direction. Since no voltage is applied, the discharge current i2 from the capacitor C11 does not flow. Therefore, the voltage v4 does not decrease. In the next state (2x), the same state continues, and in the next state (1x), the field effect transistor Q2 is turned on, so that the voltage v3 corresponds to the decrease in the voltage v2. When the voltage decreases and falls below the terminal voltage v4 of the capacitor C11, the discharge current i2 of the capacitor C11 flows through the diode D10, and the terminal voltage v4 decreases. When the terminal voltage v4 falls below the threshold value, the shunt regulator M11 is turned off, the photocoupler PC is also turned off, and the alarm signal ALM enters a high level alarm state. As described above, it is possible to detect a voltage drop of the high-side power supply VH1 regardless of the direction of the output current.

  FIG. 6 is an operation explanatory diagram when the voltage v5 of the low-side power supply VL is lowered, and shows the voltage v5, the terminal voltage v4 of the capacitor C11, and the alarm signal ALM. When the power supply VL is normal, the voltages v5 and v4 are kept constant, the shunt regulator M11 is turned on, and the photocoupler PC is also kept on accordingly. Therefore, the alarm signal ALM is in a low level normal state. continue. When the voltage of the low-side power source VL decreases and the terminal voltage v4 decreases due to a decrease in the charging current i1 of the terminal voltage v4 of the capacitor C11. When the terminal voltage v4 falls below the threshold, the shunt regulator M11 is turned off and the photocoupler PC is also turned off. Thus, the alarm signal ALM becomes a high level alarm state. As described above, the voltage monitoring circuit VP can monitor the voltages of the high-side power supply VH1 and the low-side power supply VL, and can send an alarm signal ALM when the voltage drops.

  FIG. 7 is an explanatory diagram of a main part of a fourth embodiment of the present invention, showing a power supply monitoring circuit for commonly monitoring a drive power supply in a switching power supply having a multiphase full bridge configuration. The same reference numerals as those in FIG. 1 indicate the same name, VH1, VH2, VH3,... Are high side power supplies, VL1, VL2, VL3,... Are low side power supplies, Q1, Q2, Q3,. Q4, Q5, Q6,... Are field effect transistors as switching elements, GD1, GD2, GD3, GD4, GD5, GD6,... Are gate drivers, R1, R2, R3,. , D11, D12,... Represent diodes. The power supply monitoring circuit VP has the same configuration as the power supply monitoring circuit of the embodiment shown in FIG.

  In the power supply monitoring circuit VP, the capacitor C11 is charged through the resistor R11 by the voltage of the power supply VL, the divided voltage by the resistors R12 and R13 is applied to the reference of the shunt regulator M11, the shunt regulator M11 is turned on, and normal It becomes a low level alarm signal ALM indicating the state. In this case, the terminal voltage of the capacitor C11 is set so as to be lower than the voltages of the high-side power sources VH1, VH2, VH3,..., So that the diodes D10, D11, D12,. A voltage of reverse polarity is applied, and the power supply monitoring circuit VP is disconnected from the power supplies VH1, VH2, VH3,.

  When the voltage of any one or more of the high-side power sources VH1, VH2, VH3,... Falls and falls below the terminal voltage of the capacitor C11, a discharge current flows from the capacitor C11 via the diode. The terminal voltage of the capacitor C11 also decreases, and the shunt regulator M11 is turned off. As a result, the alarm signal ALM indicates a high level alarm state, and the control circuit (not shown) stops the control of the gate driver. That is, a plurality of high-side power supplies can be monitored by a single power supply monitoring circuit VP, each being a monitored power supply. The low side power supplies VL1, VL2, VL3,... Can be shared because the potential does not fluctuate. In this case, the low side power supplies VL1, VL2, VL3,. It is also possible to monitor as a monitored power source.

It is principal part explanatory drawing of Example 1 of this invention. It is principal part explanatory drawing of Example 2 of this invention. It is principal part explanatory drawing of Example 3 of this invention. It is operation | movement explanatory drawing of Example 3 of this invention. It is operation | movement explanatory drawing of Example 3 of this invention. It is operation | movement explanatory drawing of Example 3 of this invention. It is principal part explanatory drawing of Example 4 of this invention. It is explanatory drawing of a prior art example.

Explanation of symbols

Q1, Q2 Field effect transistor GD1, GD2 Gate driver C1-C3, C11 Capacitor L1, L2 Choke coil R1, R11-R14 Resistor D10 Diode VP Power supply monitoring circuit DCV DC power supply VH1 High-side power supply VL Low-side power supply CMP Comparison circuit M11 Shunt regulator

Claims (4)

In the power supply monitoring circuit that monitors the power supply of the driver corresponding to the switching element on the high side and the low side,
Power of the high-side switching element corresponding to the driver and the monitored power supply, said the monitored power supply through a different source resistance charging, the object via said resistor and diode when a voltage drop of the monitored power supply A power source comprising: a capacitor to be discharged to a monitoring power source side; and a comparison unit that compares a terminal voltage of the capacitor with a reference value and outputs an alarm signal when the terminal voltage falls below the reference value. Supervisory circuit. To a charging source for charging via a first resistor to the capacitor, and connected via a second resistor, and a shunt regulator constituting the comparing means, and said second resistor terminal voltage of said capacitor The power supply monitoring circuit according to claim 1, further comprising: a third resistor that is divided by a series circuit and input to a reference of the shunt regulator. The high-side power source for the high-side driver corresponding to the switching element on the high-side side and the low-side side and the low-side power source for the low-side driver are connected to the high-side power source via a discharge resistor and a diode. The power supply monitoring circuit according to claim 1, wherein the power supply monitoring circuit is connected to the capacitor and connected to the capacitor via a charging resistor to the low-side power supply.   Connected to the capacitor via a discharge resistor and a diode, respectively, to a plurality of high-side power sources of a high-side power source and a low-side power source corresponding to switching elements of a plurality of high-side sides and a plurality of low-side sides The power supply monitoring circuit according to claim 1, wherein a plurality of the low-side power supplies are commonly used as a power supply for charging the capacitor.

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