JP4915047B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, an electro-optical device, and an electronic device.

  Transistors such as thin film transistors (hereinafter referred to as TFTs) are widely used in electronic devices such as display devices and drive circuits for various devices. Response is required.

FIG. 10 is a diagram showing a configuration of a general TFT.
As shown in FIG. 10, the TFT includes a semiconductor film 1 in which a channel region 1c, a source region 1s and a drain region 1d are formed, a gate insulating film 2 covering the semiconductor film 1, and a channel region 1c on the gate insulating film 2. A gate electrode 3, an interlayer insulating film 4, and a source electrode 5s and a drain electrode 5d connected to the source region 1s and the drain region 1d through the contact holes h (for example, , See Patent Document 1 below).

JP 11-2265001 A

By the way, when forming the contact hole h, two kinds of films, an interlayer insulating film (silicon oxide film) 4 and a gate insulating film (silicon oxide film) 2 formed by silicon oxide (SiO ₂ ) are etched. Will be. Although not shown, a contact hole (not shown) must be formed in the interlayer insulating film 4 for forming the extraction electrode for the gate electrode 3 as well. As described above, the contact hole is formed at two locations, that is, a portion where the interlayer insulating film 4 and the gate insulating film 2 are etched and a portion where only the interlayer insulating film 4 is etched. . For this reason, one of the two contact holes is liable to cause contact failure due to insufficient etching, and the other contact hole has a problem that the contact hole becomes abnormally large due to over-etching. Furthermore, depending on the degree of etching at the time of forming the contact hole, the semiconductor film 1 formed of a silicon film becomes unnecessarily thin, and contact resistance with the source electrode 5s and the drain electrode 5d increases, resulting in contact failure. There was a problem such as.

  The present invention has been made in view of the circumstances described above, and is a semiconductor device capable of suppressing contact failure between a semiconductor film and a source electrode and a drain electrode and controlling the size of a contact hole opened to the gate electrode. The purpose is to provide manufacturing technology.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor film in which a part of a source region and a part of a drain region are thicker than other parts, and the source Exposing a part of the region and a part of the drain region while forming a first insulating film covering the other part, forming a gate electrode on the first insulating film, and exposing the exposed part Forming a source electrode and a drain electrode connected to a part of the source region and a part of the drain region.

  According to this manufacturing method, the film thickness of both ends (a part of the source region and a part of the drain region) of the semiconductor film connected to the source electrode and the drain electrode is formed to be thicker than the film thickness of other parts. . Therefore, even if both ends are slightly etched when forming a contact hole or the like, the semiconductor film does not become unnecessarily thin, and contact failure can be suppressed.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor film in which a part of the source region and a part of the drain region are thicker than a part of the other part, and a part of the source region and the part of the source region Forming a first insulating film covering a portion of the drain region while covering the other portion; forming a gate electrode on the first insulating film; and a portion of the source region and the drain Forming a second insulating film covering a portion of the region and the gate electrode; forming a contact hole on each of the source region and the drain region of the second insulating film; Forming a source electrode and a drain electrode connected to a part of the source region and a part of the drain region through the contact holes, respectively. It is characterized in. In this way, the source and drain electrodes may be directly connected to both ends of the semiconductor film.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor film in which a part of the source region and a part of the drain region are thicker than a part of the other part, and a part of the source region and the part of the source region Forming a first insulating film covering a part of the drain region while covering the other part, and each intermediate covering a part of the source region and a part of the drain region on the first insulating film; A step of forming an electrode and a gate electrode; a step of forming a second insulating film covering each of the intermediate electrodes and the gate electrode; and any of the intermediate electrodes and the gate electrode of the second insulating film Forming a contact hole on the gate electrode, a part of the source region and a part of the drain region, and any one of the gate electrodes via the contact hole. A source electrode and a drain electrode that, as well as comprising a step of forming one of the take-out electrode of the gate electrode. In this manner, the source and drain electrodes and both ends of the semiconductor film may be connected via the intermediate electrode.

  Here, in the above manufacturing method, the intermediate electrode is formed of a material containing impurity ions and is performed prior to the step of forming the second insulating film, and the intermediate electrode is formed from the intermediate electrode. An embodiment that further includes a step of diffusing the impurity ions to both ends is preferable.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that the gate electrode and each intermediate electrode are formed separately.

  In the manufacturing method, it is preferable that the method further includes a step of implanting impurity ions into the semiconductor film using the gate electrode as a mask, the step being performed prior to the step of forming the intermediate electrode.

  In any one of the above manufacturing methods, a partition that defines an end on the source region side and an end on the drain region side is formed prior to the step of forming the semiconductor film. The aspect which further includes the process to perform is preferable. Furthermore, it is preferable that the gate insulating film is formed of a liquid material.

  The semiconductor device according to the present invention is a semiconductor device having a semiconductor film, a gate insulating film, a gate electrode, a source electrode and a drain electrode on a substrate, the semiconductor film having a source region and a drain region, A thickness of a part of the source region and a part of the drain region is formed to be thicker than that of the other part, and the gate insulating film exposes a part of the source region and a part of the drain region, A part of the source region and a part of the drain region formed so as to cover the portion and exposed from the gate insulating film are connected to the source electrode and the drain electrode formed on the gate insulating film, respectively. It is characterized by.

  Such a semiconductor device may be applied to an electro-optical device or an electronic device. Here, the electro-optical device is, for example, a device including a liquid crystal element, an electrophoretic element having a dispersion medium in which electrophoretic particles are dispersed, an EL element, and the like, and an apparatus in which the semiconductor device is applied to a drive circuit or the like Say. The electronic device refers to a general device having a certain function provided with the semiconductor device according to the present invention, and includes, for example, an electro-optical device and a memory. The configuration is not particularly limited, but for example, an IC card, a mobile phone, a video camera, a personal computer, a head-mounted display, a rear-type or front-type projector, a fax machine with a display function, a digital camera finder, a portable TV, A DSP device, PDA, electronic notebook, electronic bulletin board, advertising display, etc. are included.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

A. First Embodiment FIGS. 1 and 2 are process diagrams showing a manufacturing process of a TFT (semiconductor device) according to a first embodiment. 1C is a cross-sectional view taken along line AA ′ in FIG. 3, and FIG. 2D is a cross-sectional view taken along line BB ′ in FIG. Further, in all the following drawings, the film thickness and ratio of dimensions of each component are appropriately changed for easy viewing.

(Partition formation process)
First, as shown in FIG. 1A, a partition wall 20 is formed at a predetermined position of a substrate 10 such as a glass substrate. This partition wall 20 is a raised material that functions as a member that defines both end portions of a semiconductor film to be described later (an end portion 30s on the source region side of the semiconductor film 30 and an end portion 30d on the drain region side; see FIG. 3). It is formed using a resin material (resist material or the like). The partition wall 20 can be formed using a CVD method or the like, but of course may be formed using another method (a coating method such as a spin coating method).

(Semiconductor film formation process)
Next, as shown in FIG. 1B, after a liquid material for forming a semiconductor film is disposed in a region defined by the partition wall 20 using a droplet discharge method (inkjet method), heat treatment is performed. As a result, the semiconductor film 30 made of an amorphous silicon film in which the film thickness of both end portions 30s and 30d is thicker than the film thickness of the other portions as shown in FIG.
The formation process of the semiconductor film 30 will be described in detail. First, a liquid material is dropped onto a region defined by the partition wall 20. When the dripped liquid begins to dry, its volume gradually decreases, and along with this, the contact position between the liquid surface and the partition wall 20 gradually moves downward (see FIG. 1B). At this time, the shape of the liquid surface of the contact portion TP1 is determined by the contact angle between the liquid and the surface of the partition wall 20.

  As the liquid further dries, solid precipitation (so-called pinning) begins. When solid precipitation starts, the volume of the liquid further decreases. However, since the solidification proceeds from the contact portion TP2 when the solid precipitation starts, the liquid surface becomes lower than the contact portion TP2. (See FIG. 1 (c)). Finally, the semiconductor film 30 is formed in which both end portions 30s and 30d are thicker than the other flattened portion (hereinafter, flat portion) 30c. The film thickness of the semiconductor film 30 can be controlled by the arrangement position of the partition wall 20 and parameters (baking time, baking temperature, baking profile, etc.) relating to the drying of the liquid material. In this embodiment, the film at both end portions 30s and 30d. Control is performed so that the thickness Ts0 is about 350 nm and the thickness Ts1 of the flat portion 30c is about 50 nm (see FIG. 1C).

  After the semiconductor film 30 is formed in this way, the partition wall 20 is then removed from the substrate 10 using wet processing or the like (see FIG. 1D). Here, when the heat resistance of the partition wall 20 is high, it can be fired at a sufficiently high temperature in the above process, but when the heat resistance of the partition wall 20 is low, it cannot be fired at a high temperature. Therefore, in such a case, after baking within the heat-resistant range of the partition 20, the partition 20 may be removed from the substrate 10 and then fired at a high temperature. Note that the semiconductor film 30 is not limited to an amorphous silicon film, and may be a semiconductor film including an amorphous structure such as a microcrystalline semiconductor film or a polycrystalline semiconductor film. Alternatively, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

Subsequently, a crystallization process such as a laser annealing method or a rapid heating method (for example, a lamp annealing method or a flash annealing method) is performed on the semiconductor film 30 to crystallize the semiconductor film 30 into a polysilicon film. In the laser annealing method, a line beam having a beam length of 400 nm is used, for example, with an excimer laser, and the output intensity is set to 400 mJ / cm ² , for example. Note that the second harmonic or the third harmonic of the YAG laser may be used. For the line beam, it is preferable to scan the line beam so that a portion corresponding to 90% of the peak value of the laser intensity in the short dimension direction overlaps for each region. Thereby, an island-shaped semiconductor film 30 corresponding to the size of the TFT as shown in FIG. 3 is formed.

(Gate insulating film formation process)
Next, as shown in FIG. 1E, a gate insulating film (first insulating film) 40 that exposes both end portions 30s and 30d of the semiconductor film 30 and covers the flat portion 30c by using a coating method. Form. Specifically, first, a coating liquid (a liquid material containing polysilazane) in which polysilazane is mixed with xylene is spin-coated on a substrate, and prebaking is performed at a processing temperature of 100 ° C. for 5 minutes. Thereafter, the gate insulating film 40 having a film thickness of about 100 nm is formed by performing heat treatment at a processing temperature of 350 ° C. for 60 minutes in a WET O 2 atmosphere. By performing the heat treatment in a WET O2 atmosphere in this way, the nitrogen component in the insulating film that causes polarization can be reduced. In order to ensure the exposure of both end portions 30s and 30d, the entire surface may be lightly etched after the gate insulating film 4 is formed.

(Intermediate electrode and gate electrode formation process)
Next, as shown in FIG. 2A, intermediate electrodes 50s and 50d covering both end portions 30s and 30d and gate electrode 50g are formed by the same material and the same process. Here, the intermediate electrode 50 s is an electrode that connects the end 30 s on the source region side of the semiconductor film 30 and a source electrode (described later), and the intermediate electrode 50 d is connected to the end 30 d on the drain region side of the semiconductor film 30. This is an electrode for connecting a drain electrode (described later).

  The formation method of the intermediate electrodes 50s and 50d and the gate electrode 50g will be described in detail. First, an electrode layer doped with a large amount of impurity ions such as boron and phosphorus is formed by using a CVD method or the like. Patterning is appropriately performed according to (see FIG. 2A). Then, by annealing the patterned electrode layer, impurities are diffused and selectively grown in the silicon at the end 30s and the end 30d to form a source region and a drain region (see FIG. 2B). Impurities are introduced into the source and drain regions between the intermediate electrode and the gate electrode by ion implantation using the gate electrode as a mask. In the present embodiment, an example in which the doped silicon film is used as the intermediate electrode and the gate electrode is illustrated, but a metal material such as Al may be used. As is well known, Al forms an alloy with silicon by performing a heat treatment at about 300 ° C., so that an ohmic connection with the source region and the drain region can be obtained.

(Interlayer insulation film formation process)
Next, an interlayer insulating film (second insulating film) 50 that covers the intermediate electrodes 50s and 50d and the gate electrode 50g is formed (see FIG. 2C). Specifically, a single-layer or multilayer interlayer insulating film 50 including a silicon oxide film or a silicon oxynitride film is formed using a CVD method or the like. Alternatively, an SOG (spin on glass) film using polysilazane or the like may be used.

(Source electrode, drain electrode, gate wiring formation process)
Then, a contact hole CH is formed at a position corresponding to the source electrode, the drain electrode, and the gate wiring by using a photolithography method or the like (see FIG. 2D), and then aluminum is formed by using a sputtering method or the like. A conductive film such as a film, a chromium film, or a tantalum film (eg, a thickness of 200 nm to 800 nm) is formed. Then, a patterning mask (not shown) or the like is formed at the position where the source electrode, the drain electrode, and the gate wiring are formed, and patterning is performed, thereby forming the source electrode 60s, the drain electrode 60d, and the gate wiring 60g at the same time (FIG. 4). And FIG. 2 (d)). Through the process described above, a top gate type TFT is formed on the substrate 10.

  As described above, according to the present embodiment, the intermediate electrode that connects the source / drain electrodes and the source / drain regions is formed, and the contact hole that opens to the intermediate electrode is formed (FIG. 2D). reference). Accordingly, it is not necessary to form a contact hole that opens to the semiconductor film in which the source / drain regions are formed as in the prior art, so that problems such as contact failure with the source / drain electrodes can be suppressed. .

  In the present embodiment, a contact hole formed to connect the source / drain electrode and the source / drain region and a contact hole formed to connect the gate wiring and the gate electrode are simultaneously formed under the same conditions. (See FIG. 2D). Therefore, process conditions for forming contact holes can be easily set, and a process margin can be increased even when other process conditions vary.

  In this embodiment, the intermediate electrode can be formed in the same process as the gate electrode without adding a special process. Further, the contact resistance can be suppressed by forming both end portions of the semiconductor film forming part of the source / drain regions thick.

  In addition, since it is not necessary to form contact holes on the semiconductor film in which the source / drain regions are formed, the source / drain electrodes and the gate electrodes can be arranged with a minimum size and high density. Further, the intermediate electrode can be used as a wiring for electrically connecting a plurality of adjacent TFTs. For example, an intermediate electrode connected to the gate electrode of one TFT and the drain region of the other can be connected as a wiring.

B. Second Embodiment In the above-described first embodiment, the electrode layer doped with impurities is annealed, and the source region and the drain region are formed by diffusing and selectively growing the impurities in the semiconductor film. The source region and the drain region may be formed by performing ion implantation.

FIG. 5 is a process diagram showing a manufacturing process of the TFT according to the second embodiment, and corresponds to FIGS. 2 (a) and 2 (b). Since other steps can be described in the same manner as in the first embodiment described above, illustration and the like are omitted.
As in the first embodiment, when the gate insulating film 40 in which both end portions 30s and 30d of the semiconductor film 30 are exposed is formed, a gate electrode 50g is formed on the gate insulating film 40 as shown in FIG. To do. Then, ion implantation of impurities such as phosphorus is performed using the gate electrode 50g as a mask (see FIGS. 5A and 5B).

FIG. 6 is a diagram for explaining an ion implantation process.
As shown in the figure, in this embodiment, ion implantation is performed twice while changing the energy. Specifically, after ion implantation is performed with low energy (for example, 20 keV; see the dashed line in FIG. 6), ion implantation is performed with high energy (for example, 80 keV; see the solid line in FIG. 6). Thereby, ions can be efficiently implanted into both end portions 30 s and 30 d exposed from the gate insulating film 40 and the semiconductor film 30 covered with the gate insulating film 40. The ion implantation energy may be appropriately set according to the peak position of the ion concentration to be implanted (see P1 and P2 shown in FIG. 6). Further, instead of performing ion implantation a plurality of times, it may be performed only once.

  When the source region and the drain region are formed by performing such ion implantation, intermediate electrodes 50s and 50d made of aluminum, tantalum, or the like covering both end portions 30s and 30d of the semiconductor film 30 are formed using a sputtering method or the like. Since the subsequent steps are the same as those in the first embodiment described above, description thereof will be omitted.

  In each of the embodiments described above, the source / drain electrode and the source / drain region are connected via the intermediate electrode, but may be connected without the intermediate electrode. Specifically, as shown in FIG. 7, contact holes CH are formed on both end portions 30s and 30g of the semiconductor film 30, and a conductive film is formed and patterned in the contact holes CH and the like, whereby the source electrode 60s and the drain are formed. The electrode 60d may be formed.

C. Third Embodiment FIG. 8 is a connection diagram of an organic EL device 100 which is a kind of electro-optical device according to a third embodiment.
A pixel circuit formed in each pixel region includes a light emitting layer OELD that can emit light by an electroluminescence effect, and TFTs 111 to 114 that constitute a control circuit for driving the light emitting layer OELD. On the other hand, each of the drive circuits 101 and 102 formed in the drive circuit region includes a plurality of TFTs (not shown) having the above configuration. From the drive circuit 101, the scanning line Vsel and the light emission control line Vgp are supplied to the corresponding pixel circuits, and from the drive circuit 102, the data line Idata and the power supply line Vdd are supplied to the corresponding pixel circuits. By controlling the scanning line Vsel and the data line Idata, light emission by the corresponding light emitting units OELD can be controlled. The drive circuit is an example of a circuit in the case where an electroluminescent element is used as a light emitting element, and other circuit configurations are possible.

D. Fourth Embodiment FIG. 9 is a diagram illustrating an electronic device according to a fourth embodiment.
FIG. 9A shows a mobile phone manufactured by the manufacturing method of the present invention. The mobile phone 330 includes an electro-optical device (display panel) 100, an antenna unit 331, an audio output unit 332, an audio input unit 333, and An operation unit 334 is provided. The present invention is applied to the manufacture of a semiconductor device that constitutes a pixel circuit and a drive circuit in the display panel 100, for example. FIG. 9B shows a video camera manufactured by the manufacturing method of the present invention. The video camera 340 includes an electro-optical device (display panel) 100, an image receiving unit 341, an operation unit 342, and an audio input unit 343. ing. The present invention is applied to the manufacture of a semiconductor device that constitutes a pixel circuit and a drive circuit in the display panel 100, for example.

  FIG. 9C shows an example of a portable personal computer manufactured by the manufacturing method of the present invention. The computer 250 includes an electro-optical device (display panel) 100, a camera unit 351, and an operation unit 352. . The present invention is applied to the manufacture of a semiconductor device that constitutes the display panel 100, for example.

  FIG. 9D shows an example of a head mounted display manufactured by the manufacturing method of the present invention. The head mounted display 360 includes an electro-optical device (display panel) 100, a band unit 361, and an optical system storage unit 362. I have. The present invention is applied to the manufacture of a semiconductor device that constitutes the display panel 100, for example. FIG. 9E shows an example of a rear projector manufactured by the manufacturing method of the present invention. The projector 370 includes an electro-optical device (light modulator) 100, a light source 372, a combining optical system 373, a mirror 374, 375 is provided in the housing 371. The present invention is applied to the manufacture of a semiconductor device that constitutes a pixel circuit and a drive circuit in the optical modulator 100, for example. FIG. 9F shows an example of a front type projector manufactured by the manufacturing method of the present invention. The projector 380 includes an electro-optical device (image display source) 100 and an optical system 381 in a housing 382, and an image is displayed. Can be displayed on the screen 383. The present invention is applied to the manufacture of a semiconductor device constituting a pixel circuit and a drive circuit in the image display source 100, for example.

  The present invention is not limited to the above example and can be applied to the manufacture of all electronic devices. For example, the present invention can also be applied to a fax machine with a display function, a finder for a digital camera, a portable TV, a DSP device, a PDA, an electronic notebook, an electric bulletin board, a display for advertisement announcement, an IC card, and the like. The present invention is not limited to the above-described embodiments, and various modifications and changes can be made within the scope of the gist of the present invention. In the above-described embodiment, a TFT (thin film transistor) is illustrated as an example of a circuit element. However, it is needless to say that the present invention may be applied to other circuit elements.

It is process drawing which shows the manufacturing process of TFT which concerns on 1st Embodiment. FIG. 4 is a process drawing showing a manufacturing process of the TFT according to the same embodiment. FIG. 6 is a drawing for explaining the manufacturing process of the TFT according to the embodiment. FIG. 6 is a drawing for explaining the manufacturing process of the TFT according to the embodiment. It is process drawing which shows the manufacturing process of TFT concerning 2nd Embodiment. It is a figure for demonstrating the ion implantation process which concerns on the same embodiment. FIG. 4 is a process drawing showing a manufacturing process of the TFT according to the same embodiment. FIG. 10 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment. It is the figure which illustrated each electronic device concerning a 4th embodiment. It is a figure which shows the structure of a general TFT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... TFT, 10 ... Substrate, 20 ... Partition, 30s, 30d ... End, 30c ... Flat part, 30 ... Semiconductor film, 40 ... Gate insulating film, 50s , 50d: intermediate electrode, 50g: gate electrode, 50 ... interlayer insulating film, 60s ... source electrode, 60d ... drain electrode, 60g ... gate electrode.

Claims (2)

Forming a partition defining an end on the source region side and an end on the drain region side;
Forming a semiconductor film having a thickness of a part of the source region and a part of the drain region in contact with the partition in a region defined by the partition ;
Removing the partition;
Forming a first insulating film that exposes a portion of the source region and a portion of the drain region while covering the other portion;
Forming a gate electrode on the first insulating film;
Forming a second insulating film covering a portion of the source region and a portion of the drain region, and the gate electrode;
Forming contact holes on a part of the source region and a part of the drain region of the second insulating film,
Forming a source electrode and a drain electrode connected to a part of the source region and a part of the drain region through the contact holes, respectively. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film is formed of a liquid material.

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