JP4906146B2 - Semiconductor integrated circuit including an A / D converter composed of a bandpass ΔΣ modulator - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including an A / D converter composed of a bandpass ΔΣ modulator, and more particularly to an S / N of an A / D converter composed of a bandpass ΔΣ modulator for a digital IF receiver. It relates to a technology that is useful for improving the ratio.

  In mobile communication represented by a mobile phone, an RF (radio frequency) signal is received from a base station. The reception system suitable for the mobile phone receiver is classified into a single-stage system and a multi-stage system for RF signal down-conversion.

≪Superheterodyne receiver≫
A multi-stage superheterodyne receiver has a large number of passive elements and is not suitable for integration.

≪Direct down conversion receiver≫
In a direct down-conversion receiver that is a one-stage system, an RF reception signal is directly converted into a DC component by a quadrature RF modulator. Compared to superheterodyne receivers, direct downconversion receivers have the advantage of high integration levels.

≪Low IF receiver≫
In a low IF receiver similar to direct downconversion, the RF received signal is downconverted to an intermediate frequency of several hundred KHz instead of a DC frequency by orthogonal RF downconversion. The image removal filter can be integrated and the advantages of direct down-conversion are maintained, but a high-performance A / D converter is required for image removal. After A / D conversion, the digital signal from the A / D converter is digitally down-converted to a DC component before digital filtering.

≪Digital IF receiver≫
As described in Non-Patent Document 1 below, in a digital IF receiver, an RF reception signal is first down-converted to a first intermediate frequency by an RF modulator. The first intermediate frequency signal is A / D converted into a digital signal by a bandpass ΔΣ modulator that performs high resolution A / D conversion of the narrowband high frequency signal. According to digital signal processing, different functions are implemented by software, so the digital IF receiver is flexible. Furthermore, since orthogonal mixing and filtering for channel selection are performed in the digital domain, it is advantageous and flexible. The bandpass ΔΣ modulator is a strong candidate for direct IF digitization because it performs high resolution analog-to-digital (A / D) conversion of narrowband high frequency signals.

≪ΔΣ modulator≫
In a ΔΣ modulator that uses an oversampling ratio where a sampling frequency much higher than the Nyquist frequency is used, the quantization noise spectrum is shaved by a feedback loop. Therefore, compared to the traditional Nyquist ratio A / D converter, the oversampling ΔΣ modulator is insensitive to the non-ideal characteristics of the analog circuit. In a low-pass (LP) ΔΣ modulator using a loop filter as an integrator, the quantization noise is greatly reduced at the DC frequency.

  As described in Non-Patent Document 2 below, when the loop filter is a resonator instead of an integrator, a bandpass (BP) ΔΣ modulator is configured. The discrete-time resonator is composed of two delay elements or an integrator in series with loop feedback. This resonator is composed of a switched capacitor (SC) driven by a two-phase clock.

  Non-Patent Document 3 below includes an A / D converter composed of a bandpass ΔΣ modulator, a flexible, small chip area, low power consumption and excellent signal processing performance of DSP-based digital IF AM / An FM car radio receiver is described.

  Non-Patent Document 4 below describes a low-pass (LP) delta-sigma modulator that uses a loop filter as an integrator to supply an analog input signal directly to the input of the quantizer so that the integrator processes only the quantization noise. And low distortion is described.

  Non-Patent Document 5 below describes a low-pass (LP) ΔΣ modulator that uses a loop filter as an integrator to directly integrate an analog input signal to an input of a quantizer, thereby reducing the amplitude of the integrator. Suppresses the nonlinearity of the vessel.

  Non-Patent Document 6 below describes that an analog input signal is directly supplied to an input of a quantizer in a quadrature bandpass (BP) ΔΣ modulator. The quadrature bandpass (BP) ΔΣ modulator described in Non-Patent Document 6 below is a complex quadrature analog input of a real part and an imaginary part as described in Non-Patent Document 7 below. A complex quadrature digital output signal is generated from the signal.

Teemu O. Salo et al, “80-MHz Bandpass ΔΣ Modulators for Multimode Digital IF Receivers”, IEEE JOURNAL OF SOLID-STATES CIRCUITS, VOL. 38, NO. 3, MARCH 2003, PP. 464-474. Temu Salo et al, “A LOW-VOLTAGE SINGLE-OPAMP 4TH-ORDER BAND PASS ΔΣ MODULATOR”, The 2001 IEEE International Symposium 9 Circus 352-355. F. Addici et al, “A DSP-Based Digital IF AM / FM Car-Radio Receiver”, Proceedings of the 29th European Solid-State Circuits Conf. 16-18. 2003, PP. 201-2004. J. et al. Silva et al, “Wideband low-distortion delta-sigma ADC topology”, ELECTRONICS LETTERS, 7th June 2001 Vol. 37 No. 12 PP. 737-738. KiYoung Nam et al, "A 1.2-V 15-bit 2.5-MS / s Oversampling ADC with Reduced Integral Swings", IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERC. 515-518. R. Maurino at al. “MULTIBIT QUADRATURE SIGMA-DELTA MODULATOR WITH DEMS SCHEME”, Proceedings of the 2004 International Symposium on Circuits and Systems, 6-9 My PP. 1136-1139. Stephen A. Jantzi et al. “Quadrature Bandpass ΔΣ Modulation for Digital Radio”, IEEE JOURNAL OF SOLID-STATES CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997, PP. 1935-1950.

  As described in Non-Patent Document 1, in the digital IF receiver, the RF reception signal is first down-converted to the first intermediate frequency by the RF modulator. The first intermediate frequency signal is A / D converted into a digital signal by a bandpass ΔΣ modulator that performs high resolution A / D conversion of the narrowband high frequency signal. Prior to the present invention, the inventors engaged in the development of a digital IF receiver constituting an AM / FM radio.

<< Digital IF receiver constituting AM / FM radio developed prior to the present invention >>
FIG. 1 is a circuit diagram showing a digital IF receiver constituting an AM / FM radio developed by the present inventors prior to the present invention. As shown in the figure, the digital IF receiver includes an RF analog front end RF_AFE and a digital signal processing large-scale integrated circuit LSI.

  The RF reception signal received by the AM / FM radio antenna ANT is supplied to the input of the RF bandpass filter 1 of the RF analog front end RF_AFE. The output of the RF band pass filter 1 is supplied to the input of the low noise amplifier 2. The output of the low noise amplifier 2 is supplied to the input of a band pass filter 3 for image removal. The output of the bandpass filter 3 for image removal is supplied to one input of the reception mixer 5. The RF local signal from the voltage controlled oscillator 4 serving as the RF local signal oscillator is supplied to the other input of the reception mixer 5. In the reception mixer 5, the RF amplification output signal of the bandpass filter 3 and the RF local signal from the voltage controlled oscillator 4 are mixed, and a first intermediate frequency signal is generated from the output of the reception mixer 5 by first down conversion. . The first intermediate frequency signal is amplified by the intermediate frequency amplifier 6 and then supplied to the input of the intermediate frequency bandpass filter 7. The output of the intermediate frequency bandpass filter 7 is amplified by an AGC amplifier 8 and then supplied to an A / D converter 9 composed of an LSI bandpass delta sigma modulator BPΔΣMod. The A / D converter 9 configured by a bandpass ΔΣ modulator that performs high-resolution A / D conversion of a narrow-band high-frequency signal performs A / D conversion from an analog signal having a first intermediate frequency to a digital signal. The digital output signal of the A / D converter 9 is supplied to an LSI digital signal processor (DSP) 10 to generate an AM demodulated signal or an FM demodulated signal by software processing demodulation.

<< A / D converter composed of a bandpass ΔΣ modulator developed prior to the present invention >>
FIG. 2 is a diagram showing an A / D converter 9 constituted by a band-pass ΔΣ modulator of a digital IF receiver constituting the AM / FM radio of FIG. The analog input signal Vin output from the AGC amplifier 8 is supplied to one input terminal of the resonator 92, and the output signal of the D / A converter 99 is supplied to the other input terminal of the resonator 92. The resonator 92 includes an adder 921 and two delay circuits 922 and 923. The input signal Vin is supplied to one input terminal of the adder 921, and the output signal of the delay circuit 923 is supplied to the other input terminal of the adder 921 after being multiplied by −1. Further, the output signal of the D / A converter 99 is supplied to the other input terminal of the adder 921 after being multiplied by −1. The output signal of the resonator 92 from the output of the delay circuit 922 is supplied to one input terminal of the resonator 94, and the output signal of the D / A converter 96 is supplied to the other input terminal of the resonator 94. The resonator 94 includes an adder 941 and two delay circuits 942 and 943. The output signal of the resonator 92 is supplied to one input terminal of the adder 941, and the output signal of the delay circuit 943 is supplied to the other input terminal of the adder 941 after being multiplied by -1. The output signal of the D / A converter 96 is supplied to the other input terminal of the adder 941 after being doubled. The output signal of the resonator 94 from the output of the delay circuit 942 is supplied to the input of the quantizer 95, and the digital output signal Vout is generated from the output of the quantizer 95. The digital output signal Vout is a digital output signal corresponding to the level of the analog input signal Vin. The other digital output signal of the quantizer 95 is transmitted to the local D / A converter 96 and the delay circuit 98 via the delay circuit 97. The output signal of the delay circuit 98 is inversely converted into an analog feedback signal by the local D / A converter 99. Analog feedback signals from the local D / A converters 96 and 99 are fed back to the feedback inputs of the resonators 92 and 94. The two delay circuits 922 and 923 of the resonator 92, the two delay circuits 942 and 943 of the resonator 94, and the delay circuits 97 and 98 respectively receive the input signal in response to the sampling signal having the sampling frequency fs. Do a delay.

  FIG. 3 is a waveform diagram for explaining the operation of the resonator 92 of the A / D converter constituted by the bandpass ΔΣ modulator of FIG. Note that the frequency of the analog input signal Vin satisfies a resonance condition equal to ¼ of the sampling frequency fs. The analog input signal Vin supplied to one input terminal of the adder 921 at the input of the resonator 92 of FIG. 2 and the sampling signal fs supplied to the delay circuits 922 and 923 are shown at the top of FIG. ing. In the delay circuit 922 in the previous stage of the resonator 92, a signal delay of ¼ period (the signal period of the sampling frequency fs) of the analog input signal Vin occurs, and in the delay circuit 923 in the subsequent stage of the resonator 92, the analog input signal Vin is further increased. Signal delay of 1/4 period. The output signal of the delay circuit 923 is supplied to the other input terminal of the adder 921 after being multiplied by −1. The adder 921 adds the analog input signal Vin and the output signal of the delay circuit 923. Therefore, the resonator 92 resonates at the resonance frequency of the frequency of the analog input signal Vin (a quarter of the sampling frequency fs). The resonator 92 includes two delay circuits 922 and 923 to generate a second-order delay. A delay operation substantially similar to the operation of the preceding-stage resonator 92 is also performed in the subsequent-stage resonator 94. An A / A configured by a bandpass ΔΣ modulator including a front-stage resonator 92, a rear-stage resonator 94, a quantizer 95, local D / A converters 96 and 99, and delay circuits 97 and 98. The D converter generates a fourth-order delay as a whole.

  FIG. 4 is a diagram illustrating frequency characteristics of an A / D converter configured by the bandpass ΔΣ modulator of FIG. Resonators 92 and 94 of the A / D converter configured by the bandpass ΔΣ modulator of FIG. 2 resonate at a resonance frequency f0 (a quarter of the sampling frequency fs), respectively. The analog input signal Vin is transmitted to the input of the quantizer 95 via the resonators 92 and 94. The digital output of the quantizer 95 is converted into an analog output signal by the local D / A converters 96 and 99 via the delay circuits 97 and 98 and input to the resonators 92 and 94. The quantization error due to subtraction in the adder 921 is fed back to the resonator 92 via the resonators 92 and 94, the quantizer 95, and the local D / A converter 99. That is, the resonance frequency component of the quantization error causes a large feedback. As a result, as shown in FIG. 4, the quantization noise is reduced in the vicinity of the resonance frequency f0, and the quantization noise between the low frequency and the high frequency is increased.

  However, in the development of the digital IF receiver that constitutes the AM / FM radio prior to the present invention, the present inventors have developed an A / D converter composed of a bandpass ΔΣ modulator of the digital IF receiver shown in FIG. It was found that the input conversion noise is high and a good S / N ratio cannot be obtained.

  As described above, the analog input signal Vin is transmitted to the input of the quantizer 95 via the resonators 92 and 94 as described above. By configuring the quantizer 95 with a multi-bit quantizer, the problem of the input dynamic range of the quantizer 95 can be improved. However, when the internal signal of the resonator 92 exceeds the internal dynamic range of the resonator 92, the A / D conversion accuracy of the A / D converter configured by the bandpass ΔΣ modulator deteriorates. Therefore, the gain of the resonator 92 needs to be set low so that the internal signal of the resonator 92 does not exceed the internal dynamic range of the resonator 92. However, when the resonator 92 has a low gain, the input conversion noise of the resonator 92 increases, so that a good S / N ratio cannot be obtained.

  Accordingly, an object of the present invention is to improve the S / N ratio of an A / D converter composed of a bandpass ΔΣ modulator.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a typical semiconductor integrated circuit according to the present invention is composed of a non-quadrature type bandpass ΔΣ modulator (BPΔΣMod), and converts an analog input signal (Vin) into a digital output signal (Vout). including. The bandpass ΔΣ modulator is a resonator (92, 94) that exhibits bandpass characteristics at a predetermined frequency (f0) in response to the analog input signal and exhibits attenuation characteristics at other frequencies; and A quantizer (95) to which an output signal is supplied and a local D / A converter (96) to which an output signal of the quantizer is supplied. The bandpass ΔΣ modulator generates a difference signal between the analog input signal and the local analog signal output from the local D / A converter, and supplies the difference signal to the resonator. The bandpass ΔΣ modulator further includes an adder (Add) for supplying the analog input signal to an input of the quantizer.

  Therefore, the adder (Add) forms a feed forward path (Ffd) for supplying the analog input signal (Vin) to the input of the quantizer (95). Substantially only the quantization error of the difference between the digital output of the quantizer (95) of the analog input signal (Vin) and the analog input signal (Vin) is supplied into the resonator (92, 94). The signal level of only the quantization error supplied to the inside of the resonator is significantly reduced from the signal level in the case of the bandpass ΔΣ modulator shown in FIG. Therefore, the resonator can have a high gain, and the noise equivalent to the input of the resonator is reduced, so that a good S / N ratio can be obtained.

  The present inventors have provided a feedforward path for supplying an analog input signal to the input of a quantizer in an A / D converter composed of a non-quadrature bandpass ΔΣ modulator, and the quantization error is input to the resonator. To the basic technical idea of the present invention that greatly reduces the input signal level of the resonator. The non-quadrature type bandpass ΔΣ modulator of the present invention is not affected by the overhead due to the quadrature mixer and the variation between the two systems, which are problems in the quadrature type bandpass ΔΣ modulator.

  In Non-Patent Document 4 and Non-Patent Document 5, it is described that an analog input signal is directly supplied to an input of a quantizer in a low-pass (LP) ΔΣ modulator using a loop filter as an integrator. The first half of the basic technical idea of the present invention, which is a non-quadrature type bandpass (BP) ΔΣ modulator, is missing.

  Non-Patent Document 6 describes that an analog input signal is directly supplied to an input of a quantizer in a quadrature bandpass (BP) ΔΣ modulator. However, the first half of the basic technical idea of the present invention called a non-quadrature type bandpass (BP) ΔΣ modulator is missing. Moreover, since the input signal level of the resonator is greatly reduced, the resonator can have a high gain, and the input conversion noise of the resonator is reduced, the description that a good S / N ratio can be obtained, Missing.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to improve the S / N ratio of the A / D converter configured by the bandpass ΔΣ modulator.

FIG. 1 is a circuit diagram showing a digital IF receiver constituting an AM / FM radio developed by the present inventors prior to the present invention, and shows an AM / FM radio according to an embodiment of the present invention. It is also a circuit diagram which shows the digital IF receiver which comprises. FIG. 2 is a diagram showing an A / D converter constituted by a band-pass ΔΣ modulator of a digital IF receiver constituting the AM / FM radio of FIG. FIG. 3 is a waveform diagram for explaining the operation of the double delay resonator 92 of the A / D converter configured by the bandpass ΔΣ modulator of FIG. FIG. 4 is a diagram illustrating frequency characteristics of an A / D converter configured by the bandpass ΔΣ modulator of FIG. FIG. 5 is a diagram showing an A / D converter 9 constituted by a band-pass ΔΣ modulator of a digital IF receiver constituting an AM / FM radio according to one embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing a configuration of a previous stage resonator inside the bandpass ΔΣ modulator shown in FIG. FIG. 7 is a diagram illustrating frequency characteristics of an A / D converter configured by the bandpass ΔΣ modulator of FIG. FIG. 8 is a diagram showing an A / D converter 9 configured by a bandpass ΔΣ modulator according to another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. It is. FIG. 9 shows an A / D converter 9 constituted by a bandpass ΔΣ modulator according to still another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. FIG. FIG. 10 is a circuit diagram showing the configuration of the quantizer of the A / D converter configured by the bandpass ΔΣ modulator of FIGS. 5, 8, and 9. FIG. 11 is a diagram showing an A / D converter constituted by a bandpass ΔΣ modulator according to still another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. It is.

<Typical embodiment>
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical semiconductor integrated circuit (LSI) of the present invention according to a typical embodiment of the present invention includes a non-quadrature type bandpass ΔΣ modulator (BPΔΣMod), and an analog input signal (Vin). Is converted into a digital output signal (Vout). The bandpass ΔΣ modulator is a resonator (92, 94) that exhibits bandpass characteristics at a predetermined frequency (f0) in response to the analog input signal and exhibits attenuation characteristics at other frequencies different from the predetermined frequency. including. The bandpass ΔΣ modulator includes a quantizer (95) to which an output signal of the resonator is supplied, and a local D / A converter (96) to which an output signal of the quantizer is supplied. The bandpass ΔΣ modulator generates a difference signal between the analog input signal and a local analog signal output from the local D / A converter (96), and supplies the signal to the resonator. The bandpass ΔΣ modulator further includes an adder (Add) for supplying the analog input signal to the input of the quantizer (see FIG. 5).

  According to the embodiment, the feed forward path (Ffd) for supplying the analog input signal to the input of the quantizer is formed by the adder (Add). The quantization error of the difference between the digital output of the quantizer of the analog input signal and the analog input signal is generated at the input of the resonator (92, 94). The signal level of only the quantization error supplied to the inside of the resonator is significantly reduced compared to the signal level in the case of the bandpass ΔΣ modulator shown in FIG. Therefore, the resonator can have a high gain, and the noise equivalent to the input of the resonator is reduced, so that a good S / N ratio can be obtained.

  As a preferred embodiment, the resonator, the quantizer, and the local D / A converter operate in response to a sampling signal (Φs) having a predetermined frequency (fs). The predetermined frequency of the sampling signal is set so as to have an error from four times the maximum frequency fin (max) of the analog input signal.

  Therefore, according to the preferred embodiment, it is possible to reduce the influence of odd harmonics of the sampling signal.

  As a more preferred embodiment, the resonator (92) includes a plurality of integrating circuits (926, 927) connected in series between the input and output of the resonator, and the output of the resonator. And a feedback circuit (925) connected between the inputs (see FIG. 6).

  Therefore, according to the more preferred embodiment, the predetermined frequency can set the error from four times the maximum frequency of the analog input signal by the coefficient (-2-b) of the feedback circuit. .

  As a specific embodiment, at least one integration circuit (927) of the plurality of integration circuits of the resonator (92) is configured by a double sampling architecture. That is, the integration circuit (927) is controlled by two sampling capacitors (CaA, CaB) and two sampling control signals (ΦA, ΦB) having an antiphase half the predetermined frequency of the sampling signal. Switch (see FIG. 6).

  As a specific embodiment, the non-quadrature type bandpass ΔΣ modulator (BPΔΣMod) converts a single analog input signal (Vin) into a single digital output signal (Vout) (see FIG. 5). .

  [2] An A / D converter configured by a bandpass ΔΣ modulator (BPΔΣMod) according to another embodiment of the present invention and converting an analog input signal (Vin) into a digital output signal (Vout) is included. The bandpass ΔΣ modulator is a resonator (92, 94) that exhibits bandpass characteristics at a predetermined frequency (f0) in response to the analog input signal and exhibits attenuation characteristics at other frequencies different from the predetermined frequency. including. The bandpass ΔΣ modulator includes a quantizer (95) to which an output signal of the resonator is supplied, and a local D / A converter (96) to which an output signal of the quantizer is supplied. The bandpass ΔΣ modulator generates a difference signal between the analog input signal and a local analog signal output from the local D / A converter (96), and supplies the signal to the resonator. The bandpass ΔΣ modulator further includes an adder (Add) for supplying the analog input signal to the input of the quantizer (see FIG. 5). A signal transmission circuit (103, 104, 101) that reduces the influence of the quantizer spike noise on the input of the resonator while supplying the analog input signal to the input of the adder. Between the input of the resonator and the input of the resonator (see FIGS. 5, 8, 9, and 11).

  As a result, the influence of the quantizer spike noise on the resonator input can be reduced.

  As a preferred embodiment, the signal transmission circuit includes any of a low-pass filter (103, 104), a voltage follower (101), and a signal delay circuit (103, 104).

  [3] A semiconductor integrated circuit (LSI) according to another embodiment of the present invention includes an RF analog front end (RF_AFE), an A / D converter (9), and a digital signal processing unit (DSP). Included inside the chip. The RF analog front end includes a low noise amplifier (2), an RF local signal oscillator (4), and a reception mixer (5). The A / D converter includes a bandpass ΔΣ modulator (BPΔΣMod) that converts an analog input signal (Vin) into a digital output signal (Vout).

  The low noise amplifier amplifies an RF reception signal received by an antenna (ANT). The RF amplified signal of the low noise amplifier is supplied to one input of the reception mixer, and the RF local signal from the RF local signal oscillator is supplied to the other input of the reception mixer. In the receiving mixer, the RF amplified output signal and the RF local signal are mixed, and a first intermediate frequency signal is generated from the output of the receiving mixer by first down conversion.

  By supplying the first intermediate frequency signal to the A / D converter configured by the bandpass ΔΣ modulator, the A / D converter converts the analog signal of the first intermediate frequency into a digital signal. A / D conversion is executed. The non-quadrature bandpass ΔΣ modulator specifically includes an adder (Add) for supplying the analog input signal to the input of a quantizer (see FIG. 5). Alternatively, a signal transmission circuit (103, 104, 101) that reduces the influence of the quantizer spike noise on the input of the resonator is provided between the input of the adder and the input of the resonator. (See FIGS. 5, 8, 9, and 11).

  As a preferred embodiment, a plurality of RF amplification signals having a plurality of frequency bands are frequency-converted to the first intermediate frequency signal having a common frequency by the first down conversion in the reception mixer.

  In a more preferred embodiment, the plurality of RF amplification signals are an FM radio RF reception signal and an AM radio RF reception signal.

  As another more preferred embodiment, the plurality of RF amplification signals are at least two RF reception signals of GSM850, GSM900, DCS1800, PCS1900, and WCDMA RF reception signals.

<< Description of Embodiment >>
Next, the embodiment will be described in more detail. The best mode for carrying out the present invention will be described below in detail with reference to the drawings. Note that members having the same function are denoted by the same reference symbols throughout the drawings for describing the best mode for carrying out the invention, and the repetitive description thereof will be omitted.

<< Digital IF receiver constituting AM / FM radio according to one embodiment of the present invention >>
FIG. 1 is a circuit diagram showing a digital IF receiver constituting an AM / FM radio according to an embodiment of the present invention. As shown in the figure, the digital IF receiver includes an RF analog front end RF_AFE and a digital signal processing large-scale integrated circuit LSI.

  The RF reception signal received by the AM / FM radio antenna ANT is supplied to the input of the RF bandpass filter 1 of the RF analog front end RF_AFE. The output of the RF band pass filter 1 is supplied to the input of the low noise amplifier 2. The output of the low noise amplifier 2 is supplied to the input of a band pass filter 3 for image removal. The output of the bandpass filter 3 for image removal is supplied to one input of the reception mixer 5. The RF local signal from the voltage controlled oscillator 4 serving as the RF local signal oscillator is supplied to the other input of the reception mixer 5. In the reception mixer 5, the RF amplification output signal of the bandpass filter 3 and the RF local signal from the voltage controlled oscillator 4 are mixed, and a first intermediate frequency signal is generated from the output of the reception mixer 5 by first down conversion. . The RF reception signal of FM radio is 65 MHz to 108 MHz, and the RF reception signal of AM radio is 145 kHz to 10 MHz. The RF analog front end RF_AFE converts the RF reception signal of the FM radio and the RF reception signal of the AM radio into a first intermediate frequency signal (for example, 10.7 MHz) having a common frequency. As a result, when configuring an AM / FM radio, the voltage controlled oscillator 4, the receiving mixer 5, the intermediate frequency amplifier 6, the intermediate frequency bandpass filter 7, the AGC amplifier 8, and the A / D converter 9 can be commonly used. It becomes possible. The first intermediate frequency signal is amplified by the intermediate frequency amplifier 6 and then supplied to the input of the intermediate frequency bandpass filter 7. The output of the intermediate frequency bandpass filter 7 is amplified by an AGC amplifier 8 and then supplied to an A / D converter 9 composed of an LSI bandpass delta sigma modulator BPΔΣMod. The A / D converter 9 configured by a bandpass ΔΣ modulator that performs high-resolution A / D conversion of a narrow-band high-frequency signal performs A / D conversion from an analog signal having a first intermediate frequency to a digital signal. . The digital output signal of the A / D converter 9 is supplied to an LSI digital signal processor (DSP) 10 to generate an AM demodulated signal or an FM demodulated signal by software processing demodulation.

<< Digital IF receiver constituting mobile phone according to another embodiment of the present invention >>
As another embodiment of the present invention, a digital IF receiver constitutes a multimode / multiband mobile phone. In this case, RF reception signals of different frequencies of GSM850, GSM900, DCS1800, PCS1900, WCDMA multimode and multiband are the same as the first intermediate frequency signal of the RF analog front end RF_AFE in FIG. The frequency is converted to a first down conversion (for example, 60 MHz). In order to enable this, the voltage controlled oscillator 4 as the RF local signal oscillator generates RF local signals in a plurality of frequency bands. The RF reception frequency of GSM850 is 869 to 894 MHz, and the RF reception frequency of GSM900 is 925 to 960 MHz. The RF reception frequency of DCS1800 is 1805 to 1880 MHz, the RF reception frequency of PCS1900 is 1930 to 1990 MHz, and the RF reception frequency of WCDMA is 2110 to 2170 MHz. GSM is an abbreviation for Global System for Mobile Communication, and DCS is an abbreviation for Digital Cellular System. PCS is an abbreviation for Personal Communication System, and WCCAM is an abbreviation for Wideband Code Division Multiple Access. The voltage controlled oscillator 4 as the RF local signal oscillator includes a voltage controlled oscillation circuit and a frequency dividing circuit. In any case, when the voltage controlled oscillation circuit oscillates in the high frequency band and receives the low RF reception frequency signals of GSM850 and GSM900, the frequency dividing circuit divides the oscillation output signal of the voltage controlled oscillation circuit. The divided local signal is supplied to the other input of the receiving mixer 5. In this manner, RF reception signals having different frequencies of GSM850, GSM900, DCS1800, PCS1900, and WCDMA can be frequency-converted by first down conversion to a first intermediate frequency signal having a common frequency of 60 MHz. This first intermediate frequency signal can be A / D converted into a digital signal by an A / D converter 9 constituted by a bandpass ΔΣ modulator. A digital output signal of the A / D converter 9 is supplied to an LSI digital signal processor (DSP) 10 to generate a baseband demodulated signal by software processing demodulation.

<< Basic A / D Converter Consisting of Bandpass ΔΣ Modulator According to One Embodiment of the Present Invention >>
FIG. 5 is a diagram showing an A / D converter 9 constituted by a band-pass ΔΣ modulator of a digital IF receiver constituting an AM / FM radio according to one embodiment of the present invention shown in FIG. The A / D converter 9 in FIG. 5 is a non-quadrature type bandpass ΔΣ modulator different from the quadrature bandpass (BP) ΔΣ modulator described in Non-Patent Document 6 and Non-Patent Document 7. (BPΔΣMod), which converts a single analog input signal (Vin) into a single digital output signal (Vout). The single analog input signal and the single digital output signal are a complex quadrature analog input signal and a complex quadrature digital output signal of the real part and the imaginary part independent of each other as described in Non-Patent Document 7. It is something to exclude. However, a single analog input signal and a single digital output signal are a non-inverted single input signal and an inverted single input signal or a non-inverted single output signal and an inverted single output signal that are different from each other. It is included, not excluded.

  The A / D converter 9 according to one embodiment of the present invention shown in FIG. 5 is fundamentally different from the A / D converter 9 developed by the inventors prior to the present invention shown in FIG. The A / D converter 9 of FIG. 5 further includes an adder Add for supplying the analog input signal Vin to the input of the quantizer 95. The low-pass filters 103 and 104 and the signal delay circuits 103 and 104 added to the A / D converter 9 in FIG. 5 are secondary differences and will be described in detail later. The quantizer 95 may be called an ADC (analog / digital converter).

  Therefore, in the A / D converter 9 of FIG. 5, a direct feedforward path Ffd for directly supplying the analog input signal Vin to the input of the quantizer 95 is formed by the adder Add which is a fundamental difference. Since the time delay in the low-pass filter 103 is set to be negligibly smaller than the time delay in the resonators 92 and 94, the analog input signal Vin can be directly fed forward path Ffd and adder Add without substantial time delay. To the input of the quantizer 95. In a relatively short time, the digital output of the quantizer 95 is converted back to an analog feedback signal by the local D / A converter 96. The analog feedback signal from the local D / A converter 96 is fed back to the input of the resonator 92. A quantization error of the difference between the analog feedback signal obtained by inverse conversion of the digital output of the quantizer 95 and the analog input signal Vin via the low-pass filter 104 is generated at the input 921 of the resonator 92. The signal level of only the quantization error supplied to the resonators 92 and 94 in the A / D converter 9 of FIG. 5 is higher than the signal level in the case of the bandpass ΔΣ modulator shown in FIG. It is greatly reduced. Therefore, the resonators 92 and 94 can have a high gain, and the input conversion noise of the resonators 92 and 94 is reduced, so that a good S / N ratio can be obtained. The high gain of the resonator 92 is realized by increasing the gain coefficients k1 and k2 of the two integrating circuits 926 and 927 of the resonator 92. Similarly, the high gain of the resonator 94 can be realized by setting the gain coefficients k3 and k4 of the two integrating circuits 946 and 947 of the resonator 94 to large values.

  The analog input signal Vin of the output of the AGC amplifier 8, which is a common first intermediate frequency signal of 10.7 MHz of FM / AM of the digital IF receiver constituting the AM / FM radio of FIG. The signal is supplied to the input of the quantizer 95 through the forward path Ffd. The analog input signal Vin output from the AGC amplifier 8 is supplied to one input terminal of the resonator 92 through the low-pass filter 104 set to a large delay time as described above. The other input terminal of the resonator 92 is supplied with an analog feedback signal for inverse conversion of the digital output from the local D / A converter 96. The resonator 92 includes an adder 921, two delay circuits 924 and 929, and two integration circuits 926 and 927. The input signal Vin via the delay circuit 929 is supplied to one input terminal of the adder 921. The output signal of the D / A converter 96 via the delay circuit 924 is − to the other input terminal of the adder 921. It is supplied after being doubled. The output signal of the integrating circuit 927 via the feedback circuit 925 is supplied to the other input terminal of the adder 921. When the output signal of the resonator 92 is supplied to the input of the resonator 94, it is supplied to the adder Add via the amplifier 991. The resonator 94 includes an adder 941, two integrating circuits 946 and 947, and a delay circuit 944. The output signal of the resonator 92 via the delay circuit 944 is supplied to one input terminal of the adder 941, and the output signal of the integration circuit 947 is supplied to the other input terminal of the adder 941 via the feedback circuit 945. Is done. One input terminal of the adder Add is supplied with the analog input signal Vin via the low-pass filter 103 and the direct feed forward path Ffd, and the other input terminal is supplied with the output signal of the resonator 94. The output signal of the resonator 92 is supplied to the other terminal of the adder Add after being amplified Gv times by the amplifier 991. An added value of the three input signals of the adder Add is supplied to the input of the quantizer 95, and a digital output signal Vout is generated from the output of the quantizer 95. The digital output signal Vout is a digital output signal corresponding to the level of the analog input signal Vin. The other digital output signal of the quantizer 95 is converted back to an analog feedback signal by the local D / A converter 96. The analog feedback signal from the local D / A converter 96 is fed back to the input of the resonator 92. The two integrating circuits 926 and 927 of the resonator 92, the two integrating circuits 946 and 947 of the resonator 94, and the delay circuits 921, 924 and 944 are respectively the highest frequency fin (Max) of the analog input signal Vin. The input signal is delayed in response to a sampling signal having a sampling frequency fs that is four times the frequency of. The quantizer 95 and the local D / A converter 96 are also supplied with a sampling signal having a sampling frequency fs that is four times the highest frequency fin (Max) of the analog input signal Vin. Since the center frequency of the common first intermediate frequency signal of FM / AM of the digital IF receiver constituting the AM / FM radio of FIG. 1 is 10.7 MHz, the maximum frequency fin (Max) of the analog input signal Vin is substantially omitted. 11 MHz. Accordingly, the sampling frequency fs of the sampling signal is approximately 44 MHz.

≪Reduction of spike noise during sampling≫
On the other hand, high-level spike noise generated in the quantizer 95 during sampling by the sampling signal Φs having the sampling frequency fs may be input to the resonator 92 via the adder Add and the direct feedforward path Ffd. FIG. 10 is a circuit diagram showing a configuration of the quantizer 95 of the A / D converter 9 configured by the bandpass ΔΣ modulator of FIGS. 5, 8, and 9. As shown in the figure, the quantizer 95 includes an input switch In_SW1 that supplies an input signal V, a reference switch In_SW2 that supplies a reference voltage Vref, a sampling capacitor Cin, an operational amplifier opamp, and a feedback switch FD_SW. Includes voltage comparator. The spike noise signal component of the sampling signal Φs that drives the input switch In_SW1 is input to the resonator 92 from the input of the quantizer 95 via the input switch In_SW1 and the adder Add and the direct feedforward path Ffd. . Then, it became clear by examination of the present inventors that the S / N ratio of the A / D converter composed of the bandpass ΔΣ modulator is deteriorated.

  The low-pass filters 103 and 104 added to the A / D converter 9 in FIG. 5 reduce the level at which spike noise components from the quantizer 95 due to the sampling signal Φs having the sampling frequency fs are input to the resonator 92. It is. The low-pass filters 103 and 104 include a resistor R2 and a capacitor C2. The low-pass filters 103 and 104 transmit the analog input signal Vin having a center frequency of 10.7 MHz without being substantially attenuated, but spike noise components having a frequency of approximately 44 MHz are sufficiently attenuated. The low-pass filter 103 also has a function of reducing the level of the EMI interference signal transmitted from the large scale integrated circuit LSI to the RF analog front end RF_AFE in the digital IF receiver of FIG. That is, a spike noise component having a frequency of about 44 MHz from the input of the LSI A / D converter 9 is attenuated by the low-pass filter 103 and transmitted to the input terminal of the analog input signal Vin.

≪Reduction of influence by harmonic distortion≫
In the above embodiment, the sampling frequency fs of the sampling signal Φs is set to a frequency that is four times the highest frequency fin (Max) of the analog input signal Vin. However, in this case, the S / N ratio deteriorates due to folding of odd harmonics due to the influence of harmonic distortion of the sampling signal Φs caused by distortion of the internal circuit of the A / D converter 9 of FIG. In order to avoid this problem, the sampling frequency fs of the sampling signal Φs has an error from four times the maximum frequency fin (Max) of the analog input signal Vin. For example, when the center frequency of the analog input signal Vin is 10.7 MHz, the sampling frequency fs of the sampling signal Φs is set to 37 MHz.

  FIG. 6 is a diagram showing the configuration of the resonator 92 in the previous stage inside the bandpass ΔΣ modulator shown in FIG. 5 that enables the above. The subsequent-stage resonator 94 can be configured in substantially the same manner as the two previous-stage resonators 92. The front-stage resonator 92 includes integrator circuits 926 and 927, delay circuits 924 and 929, and a feedback circuit 925 having a coefficient (−2−b). In particular, an error of an arbitrary value can be realized by the coefficient of the feedback circuit 925. FIG. 7 is a diagram illustrating frequency characteristics of an A / D converter configured by the bandpass ΔΣ modulator of FIG.

≪Double sampling architecture≫
Compared with a low-pass (LP) ΔΣ modulator that uses a loop filter as an integrator, a band-pass (BP) ΔΣ modulator that uses a loop filter as a resonator instead of an integrator, the frequency of the analog input signal and the sampling signal of the resonator The sampling frequency becomes higher. Normally, the power consumption of an A / D converter composed of a bandpass (BP) ΔΣ modulator increases as the frequency increases.

  The double-sampling architecture is adopted in the sampling circuit unit of the delay circuit 924, the sampling circuit unit of the delay circuit 929, the sampling circuit unit of the feedback circuit 925, and the sampling circuit unit of the integration circuit 927 in the configuration of the resonator 92 in the previous stage of FIG. As a result, low power consumption is realized. The parallel sampling capacitors CinA and CinB of these sampling circuit sections are connected to two systems of switches driven by sampling switch signals ΦA and ΦB having opposite phases. The frequencies of the sampling switch signals ΦA and ΦB having opposite phases are set to a frequency fs / 2 that is half the sampling frequency fs of the sampling signal Φs, and the power consumption is also reduced to half. An integrator is realized by the operational amplifiers opamp1 and opamp2, the integration capacitors Cd and Cb, and the sampling capacitors CinA, CinB, CcA, CcB, CaA, and CaB. The timing of the sampling switch and the capacitance ratio between the sampling capacitor and the integration capacitor realize the delay effect of the delay circuits 924 and 929 and the integration circuit 927 and the signal amplification effect of the feedback circuit 925, respectively.

≪Pipeline operation between quantizer and local D / A converter≫
FIG. 8 is a diagram showing an A / D converter 9 configured by a bandpass ΔΣ modulator according to another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. It is.

  In FIG. 8, the delay circuit 100 for absorbing the difference between the timing of the digital output signal of the quantizer 95 and the timing of the inverse conversion to the analog feedback signal by the local D / A converter 96 is It is inserted between the output and the input of the local D / A converter 96. By performing a pipeline operation between the quantizer and the local D / A converter, an operation timing margin between the quantizer and the local D / A converter is expanded. Accordingly, the timing of signal supply from the analog input signal Vin via the low-pass filter 104 to the adder 921 is delayed. In other words, when another delay circuit 930 is connected to the delay circuit 929 at the input of the resonator 92, the operation timing is matched.

≪Non-pipeline operation between quantizer and local D / A converter≫
The overhead due to the addition of the delay circuit 930 in FIG. 8 may be a serious problem. When the delay circuit is configured using an operational amplifier, power consumption is remarkably increased. Even when a configuration without using an operational amplifier is used, a sampling capacity with a large occupied area is required for another system, and the increase in area becomes a problem.

  FIG. 9 shows an A / D converter 9 constituted by a bandpass ΔΣ modulator according to still another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. FIG. In the A / D converter 9 configured by the bandpass ΔΣ modulator shown in FIG. 9, the delay circuit 100 and the additional delay circuit 930 of the A / D converter 9 of FIG. 8 are omitted.

  FIG. 10 is a circuit diagram showing a configuration of the quantizer 95 of the A / D converter 9 configured by the bandpass ΔΣ modulator of FIG. As shown in the figure, the quantizer 95 includes an input switch In_SW1 that supplies an input signal V, a reference switch In_SW2 that supplies a reference voltage Vref, a sampling capacitor Cin, an operational amplifier opamp, and a feedback switch FD_SW. Includes voltage comparator. The input switch In_SW1 is driven by the positive phase sampling signal Φs, and the reference switch In_SW2 and the feedback switch FD_SW are driven by the negative phase sampling signal / Φs. Two-stage latch circuits FL, RL1, and RL2 are connected to the output of the voltage comparator via a switch Cp_SWC. The output signal of the voltage comparator is latched in the preceding latch FL of the two-stage latch circuit in response to the anti-phase sampling signal / Φs. The outputs of the two-stage latches RL1 and RL2 are connected in parallel to the output of the preceding-stage latch FL of the two-stage latch circuit. In response to the double-cycle positive-phase sampling signal Φs2 and the double-cycle negative-phase sampling signal / Φs2, one latch RL1 and the other latch RL2 of the two rear-stage latches RL1 and RL2 are interleaved and the front-stage latch FL Are alternately latched. Further, the output signals of one latch RL1 and the other latch RL2 of the two subsequent latches of the quantizer 95 are alternately supplied to the input of the local D / A converter 96 in response to the sampling signals Φs and / Φs. Is done. By this interleaving operation, the operation timing margin between the quantizer 95 and the local D / A converter 96 is expanded.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  FIG. 11 shows an A / D converter 9 constituted by a bandpass ΔΣ modulator according to still another embodiment of the present invention for the digital IF receiver constituting the AM / FM radio of FIG. FIG. In the figure, a voltage follower 101 constituted by an operational amplifier opamp is arranged in the direct feed forward path Ffd. The analog input signal Vin is supplied to the non-inverting input terminal + of the operational amplifier opamp of the voltage follower 101. The output terminal of the operational amplifier opamp of the voltage follower 101 is connected to the inverting input terminal − and to the input of the adder Add. The operational amplifier opamp of the voltage follower 101 drives the input of the adder Add with high driving capability in response to the analog input signal Vin. Further, the input parasitic capacitance Cin_p between the non-inverting input terminal + and the inverting input terminal − of the operational amplifier opamp of the voltage follower 101 is set to be small. Since the output impedance of the operational amplifier opamp of the voltage follower 101 is low, the operational amplifier opamp of the voltage follower 101 can reduce the level at which the spike noise component from the quantizer 95 is input to the resonator 92.

  Further, even if the voltage follower 101 used in FIG. 11 is replaced by the signal delay units 103 and 104, the influence of spike noise can be reduced. However, a signal delay circuit is also provided between the input of the adder Add and the input of the resonator 92 by placing a delay circuit in the clock signal that determines the sampling timing at the signal input of the adder Add and the input of the resonator 92. A signal delay effect equivalent to that of the constituent can be obtained.

  The two resonators 92 and 94 are not limited to being connected in series, and three resonators 92 and 94 can be connected in series. In this case, an A / D converter using a sixth-order bandpass ΔΣ modulator instead of the fourth-order is configured as a whole, and a larger quantization noise reduction effect is obtained. Furthermore, the number of double delay resonators can be one. In this case, an A / D converter using a second-order bandpass ΔΣ modulator instead of the fourth-order is configured as a whole.

  Further, for example, the present invention is applied to a digital IF receiver constituting a wireless LAN, Bluetooth, ultra-wideband impulse radio (UWB-IR), etc. in addition to a digital IF receiver constituting an AM / FM radio or a cellular phone. It can be widely applied to in-vehicle devices, home appliances, and other devices and devices using wireless communication.

  Further, for example, in FIG. 1, the circuit portion of the RF analog front end RF_AFE can be integrated inside the chip of the digital signal processing large-scale integrated circuit LSI by improving the integration density. This integrated chip will be effective in reducing the product cost of digital IF receivers constituting AM / FM radio, multimode / multiband mobile phones, wireless LAN, Bluetooth, and UWB-IR.

ANT antenna 1 RF band pass filter 2 low noise amplifier 3 band pass filter 4 voltage controlled oscillator as RF local signal oscillator 5 reception mixer 6 intermediate frequency amplifier 7 intermediate frequency band pass filter 8 AGC amplifier 9 A / D converter 10 DSP
92 resonator 921 adder 922 delay circuit 923 delay circuit 924 delay circuit 925 feedback circuit 926 integration circuit 927 integration circuit 928 delay circuit 929 delay circuit 930 delay circuit 94 resonator 941 adder 942 delay circuit 943 delay circuit 944 delay circuit 945 delay circuit 945 Circuit 946 Integration circuit 947 Integration circuit 95 Quantizer 96 Local D / A converter 97 Delay circuit 98 Delay circuit 99 Local D / A converter 991 Amplifier circuit 100 Delay circuit 103 Low-pass filter 104 Low-pass filter 101 Voltage follower Add adder Ffd Direct feed forward path

Claims (15)

An A / D converter configured by a bandpass ΔΣ modulator and converting an analog input signal into a digital output signal;
The bandpass ΔΣ modulator is
A signal transmission circuit to which the analog input signal is supplied;
A resonator that receives the analog input signal and the feedback signal , exhibits a bandpass characteristic at a predetermined frequency in response to the analog input signal, and exhibits an attenuation characteristic at another frequency different from the predetermined frequency;
An adder to which the output signal of the resonator and the output signal of the signal transmission circuit are supplied;
A quantizer supplied with the output signal of the adder ;
A local D / A converter to which the output signal of the quantizer is supplied,
The band-pass ΔΣ modulator receives the local analog signal output of the previous SL local D / A converter to said resonator as the feedback signal,
The resonator is a semiconductor integrated circuit that generates a difference signal based on the analog input signal and the local analog signal , outputs the difference signal with the bandpass characteristic and the attenuation characteristic, and outputs the difference signal .   The semiconductor integrated circuit according to claim 1, wherein the signal transmission circuit includes any one of a low-pass filter, a voltage follower, and a signal delay circuit. Clock signal for determining the sampling timing at the input of the resonator and the input of the adder, a semiconductor integrated circuit according to claim 1, wherein supplied via the delay circuit.   The resonator, the quantizer, and the local D / A converter operate in response to a sampling signal having a predetermined frequency, and the predetermined frequency of the sampling signal is the highest frequency of the analog input signal. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is set so as to have an error from four times as much. The resonator is
A differential signal generated based on the analog input signal, the feedback signal, and the internal feedback signal is supplied and output to an output terminal of the resonator, and a plurality of delay circuits or integrating circuits connected in series ;
The semiconductor integrated circuit of claim 1 signal at the output terminal of the previous SL resonator and a feedback circuit for outputting the internal feedback signal is supplied.   The plurality of delay circuits of the resonator or at least one delay circuit or one integration circuit of the plurality of integration circuits includes two sampling capacitors and a sampling switch signal having a phase opposite to half of the predetermined frequency of the sampling signal. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured by a double sampling architecture including two systems of switches controlled by the control. An RF analog front end, an A / D converter, and a digital signal processing unit are included in the semiconductor chip,
The RF analog front end includes a low noise amplifier, an RF local signal oscillator, and a reception mixer,
The A / D converter includes a bandpass ΔΣ modulator that converts an analog input signal into a digital output signal,
The low noise amplifier amplifies the RF reception signal received by the antenna, the RF amplification signal of the low noise amplifier is supplied to one input of the reception mixer, and the RF local signal from the RF local signal oscillator is the reception mixer. The RF mixer output is mixed with the RF amplified output signal and the RF local signal, and a first intermediate frequency signal is generated by first down conversion from the output of the receiver mixer,
By supplying the first intermediate frequency signal to the A / D converter configured by the bandpass ΔΣ modulator, the A / D converter converts the analog signal of the first intermediate frequency into a digital signal. A / D conversion is performed,
The bandpass ΔΣ modulator is
A signal transmission circuit to which the analog input signal is supplied;
A resonator that receives the analog input signal and the feedback signal , exhibits a bandpass characteristic at a predetermined frequency in response to the analog input signal, and exhibits an attenuation characteristic at another frequency different from the predetermined frequency;
An adder to which the output signal of the resonator and the output signal of the signal transmission circuit are supplied;
A quantizer supplied with the output signal of the adder ;
A local D / A converter to which the output signal of the quantizer is supplied,
The band-pass ΔΣ modulator receives the local analog signal output of the previous SL local D / A converter to said resonator as the feedback signal,
The resonator is a semiconductor integrated circuit that generates a difference signal based on the analog input signal and the local analog signal , outputs the difference signal with the bandpass characteristic and the attenuation characteristic, and outputs the difference signal .   The semiconductor integrated circuit according to claim 7, wherein a plurality of RF amplification signals having a plurality of frequency bands are frequency-converted to the first intermediate frequency signal having a common frequency by the first down conversion in the reception mixer.   9. The semiconductor integrated circuit according to claim 8, wherein the plurality of RF amplification signals are an RF reception signal of FM radio and an RF reception signal of AM radio.   9. The semiconductor integrated circuit according to claim 8, wherein the plurality of RF amplification signals are at least two RF reception signals of GSM850, GSM900, DCS1800, PCS1900, and WCDMA RF reception signals.   The semiconductor integrated circuit according to claim 7, wherein the signal transmission circuit includes any one of a low-pass filter, a voltage follower, and a signal delay circuit. Clock signal for determining the sampling timing at the input of the resonator and the input of the adder, a semiconductor integrated circuit according to claim 7, wherein the supplied via the delay circuit.   The resonator, the quantizer, and the local D / A converter operate in response to a sampling signal having a predetermined frequency, and the predetermined frequency of the sampling signal is the highest frequency of the analog input signal. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is set so as to have an error from four times as much. The resonator,
A plurality of delay circuits or integrating circuits connected in series, which are supplied with the difference signal generated based on the analog input signal, the feedback signal, and the internal feedback signal and output to the output terminal of the resonator ; ,
The semiconductor integrated circuit according to claim 13, further comprising: a feedback circuit that is supplied with a signal at the output terminal of the resonator and outputs the internal feedback signal .   At least one delay circuit of the plurality of delay circuits of the resonator includes two sampling capacitors and two systems of switches controlled by a sampling switch signal having an antiphase half of the predetermined frequency of the sampling signal. The semiconductor integrated circuit according to claim 7, which is configured by a double sampling architecture.

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