JP4901388B2 - Image forming apparatus - Google Patents

Description

  The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus that stably provides a high-quality image by stabilizing drive control of a drive motor.

  In an image forming apparatus using an electrophotographic system, a high voltage is discharged in order to form a uniform charge on an image carrier such as a photosensitive drum. The writing unit tends to be weak in electrical connection with the main body, and among them, if the grounding is weak, it is strongly affected by external noise. The writing unit is disposed close to the image carrier due to the structure of the image forming apparatus, and the image carrier is also disposed close to a charging device using corona discharge, proximity charging, and the like. For this reason, the writing unit is likely to receive external noise from a high-voltage power source for generating an electrostatic charge, and erroneous detection may occur in which the external noise is detected as an abnormality of the drive motor.

Up to now, as a drive control technique of a drive motor, for example, a technique disclosed in Japanese Patent Laid-Open No. 4-281380 (Patent Document 1) can be cited. In Patent Document 1, in order to shorten the braking time of the rotary polygon mirror driven at high speed, a rotation braking means for forcibly braking the rotation of the drive motor is provided, and a braking signal is output when the drive motor is stopped. Thereafter, the output phase of the PLL (phase-locked loop) driver is controlled so that the rotation instruction signal is turned off after a predetermined time set in advance.
JP-A-4-281380

  The image forming apparatus described in Patent Document 1 makes it possible to shorten the time for braking the rotary polygon mirror. On the other hand, since the writing unit must hold a rotating polygon mirror that rotates at high speed, the grounding property tends to be low, and the durability against external noise is relatively weak. Sometimes stopped.

  That is, in an image forming apparatus that forms an image by rotating the rotary polygon mirror at a high speed, even in an operating environment with a lot of external noise, the external abnormality of the drive motor is not erroneously detected as an abnormality of the drive motor. Therefore, there is a need for an image forming apparatus that can appropriately cope with high accuracy and high speed.

  The present invention has been made to solve the above-mentioned problems, and in units of the clock cycle of the operation clock of the drive motor with respect to the output signal detected by detecting that the rotation of the drive motor has reached the set value. A signal obtained by delaying the output signal is generated, and a logical product of the output signal and the delayed output signal is used as a processing output signal. As a result, glitches due to charging noise or the like superimposed on the output signal are removed, and erroneous detection can be prevented. In the present invention, external noise includes asynchronous noise that is not synchronized with the operation clock of the drive motor, such as chattering, in addition to charging noise.

  Also, in the present invention, when the output signal transitions to a level indicating that the set rotational speed has been reached and then transitions again to a level indicating that the rotational speed deviates from the set rotational speed, the state is reset from the outside. By providing an abnormality notification circuit that holds the image until the image forming apparatus is interrupted, the image forming apparatus can respond at high speed in response to the detection of the abnormality. Further, according to the present invention, there is provided a selection circuit that selects a plurality of signals and supplies them as output signals in response to individual states of the image forming apparatus.

  According to the present invention, there is provided an image forming apparatus capable of effectively preventing erroneous detection due to external noise, minimizing a delay in malfunction detection processing, and enabling noise removal and malfunction detection with excellent real-time characteristics. be able to.

That is, according to the present invention, an image forming apparatus that forms an electrostatic latent image by imagewise exposing a laser beam to an image carrier that carries an electrostatic charge,
A rotary polygon mirror that is rotatably disposed in a drive motor whose rotation speed is controlled by an operation clock and that scans and exposes the laser beam;
A lock detection circuit that detects that the rotational speed of the rotary polygon mirror has reached a set value and transitions an output signal; and
A signal processing circuit that delays the output signal in units of clock cycles of the operation clock in order to eliminate the influence of external noise on the output signal ;
An image forming apparatus is provided that includes a gate logic circuit that performs a logical product of the output signal and the output of the signal processing circuit to generate a processed output signal .

  The signal processing circuit of the present invention can be synchronized with the operation clock. The signal processing circuit of the present invention can remove asynchronous noise superimposed on the output signal.

  In the present invention, the clock cycle unit for processing the output signal can be set by the number of flip-flop circuits connected. The output signal of the present invention can notify an abnormal state of the rotation operation of the rotary polygon mirror.

  In the present invention, there can be provided a selection circuit for selecting and outputting the output signal from a synchronous output signal synchronized with the operation clock or a processed output signal processed by the signal processing circuit.

In the present invention, an abnormality notification circuit that outputs an abnormal signal in response to the transition of the processing output signal again after the transition of the processing output signal in a state where the operation clock is supplied, and interrupting the abnormal signal A processing device that accepts the signal as a signal, and the image forming device can interrupt the image forming sequence in response to the detection of the abnormal signal.

  FIG. 1 is a diagram illustrating a configuration of a typical image forming apparatus 10. An image forming apparatus 10 shown in FIG. 1 is configured as a full-color image forming apparatus using an electrophotographic system, and feeds a document and contacts a document with a document table, and an optical holding unit. And a scanner 14 for reading an image from a document in contact with the section. The image forming apparatus 10 further includes a writing unit 16 including a laser light source such as a laser diode and a rotating polygon mirror for imagewise exposing an image acquired by the scanner 14 onto an image carrier.

  The writing unit 16 performs imagewise exposure on the charged image carrier 18 with a laser beam from a semiconductor laser, thereby forming an electrostatic latent image on the image carrier. In the present invention, the image carrier 18 is provided in a number corresponding to four colors of cyan (C), magenta (M), yellow (Y), and black (BK), and rotated at high speed with respect to each. Imagewise exposure is performed from a polygon mirror.

  In addition, a transfer processing unit 20 is disposed at a subsequent stage of the series of image carriers 18. The transfer processing unit 20 includes a primary transfer member 22 that is generally formed as a conductive roller, and an intermediate transfer member 24. Further, the image forming apparatus 10 includes a primary transfer member 22 and a primary transfer voltage generation unit (not shown) that applies a transfer bias potential to the primary transfer member 22. In the embodiment shown in FIG. 1, the intermediate transfer member 24 is an endless belt provided between the driven rollers 26 a and 26 b and the driving roller 30.

  In many cases, the intermediate transfer member 24 has a predetermined resistance value by dispersing conductive carbon or conductive metal oxide in a thermoplastic or thermosetting polymer compound in consideration of moldability and the like. Designed. A transfer bias is applied to the intermediate transfer member 24 through the primary transfer member 22. The toner image developed by the developing device 28 and attached on the image carrier 18 is transferred to the intermediate transfer member 24 by the transfer bias. Is done.

  The toner image transferred to the intermediate transfer member 24 comes into contact with the transfer material 32 as the intermediate transfer member 24 is conveyed in the direction of the arrow A, and is a secondary transfer member disposed in the vicinity of the driven roller 26b. The image is transferred onto the transfer material 32 by the transfer electric field from 34. The transfer material 32 carrying the toner image is then heated and pressurized by the fixing device 36 to provide a printed matter on which the toner is fixed.

  FIG. 2 is a diagram showing the internal configuration of the writing unit 16 of the image forming apparatus according to the present invention, with the casing 40 of the writing unit 16 cut away. As shown in FIG. 2, the writing unit 16 includes a rotary polygon mirror 42, an fθ lens 44, a first mirror 46, a WTL lens 48, a second mirror 50, and a third mirror 52. . A laser diode (not shown) is mounted on a laser unit (not shown), and a laser beam emitted from the laser diode is incident on a cylindrical lens (not shown).

  The cylindrical lens has a refractive index determined in the sub-scanning direction, collects the parallel beam emitted from the laser unit in the sub-scanning direction, and makes it incident on the mirror surface of the rotary polygon mirror 42. The rotary polygon mirror 42 is rotatably mounted on a drive motor 54, rotates at an angular speed of about several thousand rpm, and scans an incident laser beam in the main scanning direction. The laser beam passes through the fθ lens 44, the first mirror 46, and the WTL lens 48 and enters the second mirror 50. The WTL lens 48 corrects the surface tilt of the rotary polygon mirror. The laser beam reflected by the second mirror 50 is further reflected by the third mirror 52 and emitted from the writing unit 16 to image-modulate the electrostatic charge on the image carrier 18 to give an electrostatic latent image. Yes.

  FIG. 3 is a plan view of the writing unit 16 used in the present invention. In the writing unit 16, the rotary polygon mirror 42 is rotated in the direction of the arrow B. The laser beam from the laser unit 56 is converted into a parallel beam by the condensing lens system 58 and irradiated onto the rotary polygon mirror 42. The laser beam passes through the fθ lens 44 and is condensed in the sub-scanning direction, and is reflected by the first mirror 46 to the second mirror 48.

  The writing unit 16 is provided with a synchronization detection system 60 for detecting a writing reference position in the main scanning direction. The synchronization detection system 60 includes a synchronization detection reflection mirror 62, a synchronization detection lens 64, and a synchronization detection plate 66. In the synchronization detection system 60, the laser beam reflected at a specific position in the main scanning direction of the second mirror 50 is reflected by the synchronization detection reflection mirror 62 and condensed on the synchronization detection plate 66 by the synchronization detection lens 64. The synchronization detection plate 66 is equipped with an optical sensor composed of a PIN photodiode, and outputs a detection signal synchronized with the laser beam scanning timing.

FIG. 4 shows a block diagram of a control circuit for controlling the rotation of the drive motor 54 used in the present invention. The control circuit 70 is implemented as an engine board. The control circuit 70 includes a controller 72, which generates a PMON signal that is an operation command signal for driving the drive motor 54 and an operation clock typically having a frequency of several kHz. Yes. The generated PMON signal and the operation clock are current-amplified by the control transistors Tr ₁ and Tr ₂ , respectively, and passed to the driver unit 74 through a low-pass filter configured by capacitors C ₁ and C ₂ and resistors R ₁ and R ₂ , respectively. And operating clock is output.

  The driver unit 74 includes a drive motor 54 and a driver 76 that drives the drive motor 54. The control circuit 70 and the driver unit 74 are connected by a signal line. The PMON signal output from the controller 72 starts the rotation of the drive motor 54, and the PMCLK signal has a specified oscillation frequency. This is a rotational speed command signal for commanding the rotational speed.

  The driver 76 includes a PLL control circuit 80 including a PLL and a signal processing circuit 100 used in the present invention. When the drive motor 54 reaches the set rotational speed, the driver 76 generates an SCRDY_N signal that is a lock instruction signal that transitions from the H level to the L level, and passes the generated SCRDY_N signal to the signal processing unit 100. The signal processing unit 100 processes the SCRDY_N signal, generates a SCERR0 signal (synchronous output signal) or a SCERR1 signal (processed output signal), and outputs one of the generated signals to the controller 72. In a specific embodiment of the present invention, the lock instruction signal instructs the lock state when it is “L” level, and is not locked when it is “H” level, or indicates an abnormal state of the drive motor 54. Instruct.

  FIG. 5 is a block diagram of the PLL control circuit 80 used in the present invention. As shown in FIG. 5A, the PLL control circuit 80 used in the present invention includes a phase comparator 84 to which PMCLK is input and a low-pass filter 86. The phase comparator 84 may be configured as a circuit that includes EXOR (exclusive OR) in certain embodiments of the invention. The PLL control circuit 80 includes a power amplifier 88, an amplification / pulse shaping circuit 90, and a frequency generator (FG) 92 configured using an AC tacho generator, a shaft encoder, and the like.

The output of the power amplifier 88 is output to the drive motor 54 to drive the drive motor 54. The PLL control circuit 80 operates so as to match the phase (f _s ) of PMCLK that is an operation clock with the phase (f _T ) of the rotational frequency of the drive motor 54 that is a target frequency to be compared. Synchronize the frequency. The phase difference is sent to the low-pass filter 86 as a voltage output corresponding to the detected phase difference, and unnecessary AC components are removed to obtain a control voltage Vout for driving the drive motor 54.

  By using the PLL control circuit 80, the drive motor 54 is driven by PMCLK commanded from the controller 72. The controller 72 uses a reference clock (REFCLK) having a sufficiently high frequency, divides REFCLK, and outputs it as a PMCLK signal. Therefore, in the present invention, it is possible to set the drive motor 54 to various rotational speeds by generating PMCLK by changing the frequency division ratio of REFCLK.

  On the other hand, FIG. 5A shows a lock detection circuit 98 used in the present invention. The lock detection circuit 98 generates a lock instruction signal, and in the embodiment of the present invention, passes the lock instruction signal to the signal processing circuit 100 described later. The lock detection circuit 98 includes a comparator 94 and an OR gate 96. The comparator 94 determines that the output speed Vout of the low-pass filter 86 is within a predetermined range, and determines the set rotational speed, and a lock instruction signal. (L level) is generated. The comparator 94 receives Vref + and Vref− that are higher than the Vset that gives the set rotational speed by an allowable potential, and generates a lock instruction signal from Vout using inversion and non-inversion operations. .

  FIG. 5B shows the operation of the lock detection circuit 98 shown in FIG. Vset is a standard output voltage for giving a set rotational speed, and Vref + and Vref− are potentials giving an upper limit value and a lower limit value of the output voltage, respectively. When the output voltage Vout of the low-pass filter 86 deviates from Vref + or Vref−, it corresponds to the rotation speed being too high or too low, the output of the comparator 94 becomes H level, and the OR gate 96 outputs the lock instruction signal SCRDY_N signal. Is shifted to the H level.

  FIG. 6 shows an embodiment of the signal processing circuit 100 of the present invention. The signal processing circuit 100 shown in FIG. 7 is configured using D_FFs (D flip-flops) 102 to 110, AND gates 112 and 114, and JK_FF 116. The D-FFs 102 to 108 are SCRDY_N signals. A processing period for performing the noise removal process is given. SCRDY_N and reference clock REFCLK are input to D_FF 102, and the timing of the SCRDY_N signal is synchronized with D_FF 104.

  In D_FF 108 and D_FF 110, PMCLK, which is an operation clock of the drive motor 54, is input to CLK and synchronized with PMCLK. The Q output of the D_FF 110 is input to the AND gate 112. Further, the Q output of the D_FF 104 synchronized with REFCLK is connected to the other input terminal of the AND gate 112, and the output of the AND gate 112 is the SCERR1 signal (processing output signal). ). On the other hand, the Q output of the D_FF 104 is directly used as the SCERR0 signal (synchronous output signal). The SCERR1 output has a signal waveform delayed by two clock cycles of the operation clock from the SCRDY_N signal input to the D_FF102. Thus, the output of AND gate 112 provides a SCERR1 signal, which is a processed output signal that removes the glitch superimposed on SCRDY_N within a period of two clock cycles.

  Further, the SCERR1 signal and PMCLK are input to the D_FF 106, the inverted Q bar and SCERR1 signal are input to the AND gate 114, and the output of the AND gate 114 is input to the JK_FF 116. On the other hand, PMCLK is input as CKL of JK_FF 116, and a RESET pulse is input to the K input.

  The output of JK_FF 116 holds the state until SCERR1 once becomes L level and then becomes H level again, and functions as an abnormality notification circuit for drive motor 54.

FIG. 7 shows the control timing of the control processing of the present invention using the SCRDY_N signal generated by the lock detection circuit 98 of the present invention. In Figure 7, L-level SCRDY_N signal is a locked state reaches the set rotational speed, a timing _{T 2} of the in Fig. ).

In Figure 7, described as the processing of the signal processing circuit 100 at the timing T ₁ is the start. At timing _{T 1,} the drive motor 54 is increased rotational speed, so does not reach the set rotational speed SCRDY_N is H level. When the rotational speed of the drive motor 54 at the timing T ₂ is equal to the set value, the lock detector circuit 98 transitions the SCRDY_N signal to L level, a transition called, in a state where lock indication signal is asserted. The output Q of the D_FF 108 causes the output Q of the D_FF 108 to transition to L at the next rise of PMCLK, and the output of the D_FF 110 causes the Q output of the D_FF 110 to transition to L level at the rise of the next cycle of PMCLK. As a result, the Q output of the D_FF 110 gives the SCERR1 signal having a signal waveform delayed by two clock cycles with the operation clock PMCLK.

  The AND gate 112 performs a logical product of the D_FF 110 and the SCERR0 signal (synchronous output signal). As a result, the SCERR1 is a signal obtained by removing the glitch 118 corresponding to two clock cycles of PMCLK from the SCERR0. In addition, when SCERR1 transits to the H level again after SCERR1 transits to the L level once, SCERR2 transits to the H level corresponding to this and holds that state until the RESET pulse is input. Therefore, the SCERR2 signal can be used as a flag indicating that an abnormal state of the drive motor 54 has occurred. The SCERR2 signal is held until a RESET pulse (K = H level) is input to JK_FF116.

  When the drive motor 54 rotates normally and the image forming operation is in progress, the image carrier is charged immediately below the writing unit 16 in which the drive motor 54 is disposed, resulting in charging noise. The glitch tends to be superimposed on the SCRDY_N signal. If this glitch is erroneously detected as a rotation abnormality of the drive motor 54, the sequence of the image forming operation is stopped. Such a glitch can be detected only once. In some cases, the controller 72 may determine a malfunction.

  On the other hand, the above-mentioned glitch due to charging noise has a characteristic that the applied pulse width is very short, and the SCRDY_N signal continues for a longer period if it is an inherent malfunction. For this reason, the signal processing circuit 100 according to the present invention performs noise removal in units of clock cycles of PMCLK (which is several kHz when viewed from the number of rotations) in accordance with the characteristics of charging noise, thereby achieving high speed and high speed. It becomes possible to prevent erroneous detection with high accuracy. The particular embodiment of the present invention shown in FIG. 7 can accommodate two PMCLK pulse cycles.

  Furthermore, the signal processing circuit 100 of the present invention can set an appropriate noise removal period by increasing or decreasing the number of D_FFs to be mounted, and can easily cope with differences in the printing speed and charging time of the image forming apparatus 10. Can do. Furthermore, in another embodiment of the present invention, a plurality of signal processing circuits having different noise removal periods are mounted, and a plurality of signal processing circuits are specified according to the frequency of erroneous detection of the image forming apparatus 10 or the like. A signal processing circuit can be selected and noise removal for a desired time width can be performed. Also, the present invention. The chattering of the SCRDY_N signal occurs from when the rotation of the drive motor 54 is started until the rotational speed is stabilized (locked), but the signal processing circuit according to the present invention is also effective in eliminating chattering.

  In the present invention, when the drive motor 54 is stopped, the PMON signal of the controller 72 is set to “H” and the XPMON signal is turned OFF. Thereafter, in order to confirm whether or not the rotation has actually stopped, it is not necessary to consider the removal of glitches, and the level of the SCERR0 signal may be inspected. By inputting the SCERR2 signal to the interrupt port of the processing device that controls the operation of the image forming apparatus 10 when an operation abnormality of the drive motor 54 occurs, the image forming apparatus 10 can be transmitted with a minimum time lag. The braking of the drive motor 54 and the stop command for the image forming sequence can be performed at high speed.

  FIG. 8 shows a second embodiment of the signal processing circuit. In the signal processing circuit 120 of the second embodiment, the SCERR0 signal and the SCERR1 signal are input to a 2-in-1 multiplexer 138 that functions as a selection circuit. The embodiment shown in FIG. 8 makes it possible to switch the output signal according to the abnormality detection frequency of the drive motor 54 due to charging noise or the like or the frequency of erroneous detection for each model. The SCRDY_N signal can be selected from either SCERR0 or SCERR1 by setting the select signal in the main unit setting, and the drive motor 54 corresponding to the grounding state of the light collecting unit 16 can be controlled more easily and efficiently. Make it possible.

  As described above, according to the present invention, according to the type of abnormality of the drive motor and the characteristics of the noise to be removed, the abnormality detection of the drive motor is made highly accurate and speeded up, so that the quality is more stable. It is possible to provide an image forming apparatus that provides the output of

1 is a diagram showing an embodiment of an image forming apparatus of the present invention. The figure which showed the internal structure of the condensing unit of this invention. The top view of a writing unit. The block diagram of the control circuit of the drive motor used by this invention. The block diagram of the PLL control circuit used by this invention. The figure which showed embodiment of the signal processing circuit of this invention. The figure which showed the processing timing of the signal processing circuit of this invention. The figure which showed 2nd Embodiment of the signal processing circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Image forming apparatus, 12 ... Document processing part, 14 ... Scanner, 16 ... Writing unit, 18 ... Image carrier, 20 ... Transfer processing part, 22 ... Primary transfer member, 24 ... Intermediate transfer body, 26 ... Follow-up Roller, 28 ... developer, 30 ... drive roller, 32 ... transfer material, 34 ... secondary transfer member, 36 ... fixing device, 40 ... housing (writing unit), 42 ... rotating polygon mirror, 44 ... f [theta] lens 46 ... 1st mirror, 48 ... WTL lens, 50 ... 2nd mirror, 52 ... 3rd mirror, 54 ... Drive motor, 56 ... Laser unit, 58 ... Condensing lens system, 60 ... Synchronous detection system, 62 ... Sync detection reflection mirror, 64 ... Sync detection lens, 66 ... Sync detection plate, 70 ... Control circuit, 72 ... Controller, 74 ... Driver unit, 76 ... Driver, 80 ... PLL control circuit, 84 ... Phase comparator, 86 ... Low 88 ... Power amplifier, 90 ... Amplification and pulse shaping circuit, 92 ... Frequency generator, 94 ... Comparator, 96 ... OR gate, 98 ... Lock detection circuit, 100 signal processing circuit, 102-110 ... D_FF, 112, 114 ... AND gate 116 ... JK_FF, 118 ... glitch, 120 ... signal processing circuit of the second embodiment

Claims (7)

An image forming apparatus for forming an electrostatic latent image by imagewise exposing a laser beam to an image carrier carrying an electrostatic charge,
A rotary polygon mirror that is rotatably disposed in a drive motor whose rotation speed is controlled by an operation clock and that scans and exposes the laser beam;
A lock detection circuit that detects that the rotational speed of the rotary polygon mirror has reached a set value and transitions an output signal; and
A signal processing circuit that delays the output signal in units of clock cycles of the operation clock in order to eliminate the influence of external noise on the output signal ;
An image forming apparatus comprising: a gate logic circuit that ANDs the output signal and the output of the signal processing circuit to generate a processed output signal .   The image forming apparatus according to claim 1, wherein the signal processing circuit is synchronized with the operation clock.   The image forming apparatus according to claim 1, wherein the signal processing circuit removes asynchronous noise superimposed on the output signal.   The image forming apparatus according to claim 1, wherein the clock cycle unit for processing the output signal is set by the number of connected flip-flop circuits.   The image forming apparatus according to claim 1, wherein the output signal notifies an abnormal state of a rotating operation of the rotary polygon mirror.   The image forming apparatus according to claim 5, further comprising a selection circuit that selects and outputs the output signal from a synchronization output signal synchronized with the operation clock or a processing output signal processed by the signal processing circuit. An abnormality notification circuit that outputs an abnormality signal in response to the transition of the processing output signal again after the transition of the processing output signal in a state where the operation clock is supplied;
The image forming apparatus according to claim 5, further comprising: a processing device that receives the abnormal signal as an interrupt signal, wherein the image forming apparatus interrupts an image forming sequence in response to detection of the abnormal signal.

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