JP4894171B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof.

  In recent years, for the purpose of improving the performance of a field effect transistor, a field effect transistor called FinFET has been proposed in which a gate electrode is provided on both sides of a protruding semiconductor region and a channel is formed on both sides of the semiconductor region. Yes.

  A typical structure of a FinFET is shown in FIG. 8A is a cross-sectional view taken along the line AA ′ in the plan view shown in FIG. 8C, and FIG. 8B is a cross-sectional view taken along the line BB ′. A buried insulating film 2 is provided on the support substrate 1, and a protruding semiconductor layer 3 (fin layer) is provided thereon. Gate electrodes 5 are provided on both side surfaces of the fin layer 3 via a gate insulating film 4. A portion of the fin layer 3 that is not covered with the gate electrode 5 is doped with a high-concentration first-conductivity-type impurity to form a source / drain region 10. A portion of the fin layer 3 covered with the gate electrode 5 forms a channel forming region 8, and by applying an appropriate voltage to the gate electrode, carriers of the first conductivity type are induced on the surface to form a channel. . When the gate electrode 5 is formed of polysilicon, a high-concentration second conductivity type impurity is generally introduced into the channel formation region, and the gate electrode 5 is formed of nickel silicide, titanium nitride, or the like so-called metal gate. In such a case, generally, a low-concentration second conductivity type impurity is or is not introduced into the channel formation region.

  Since the FinFET is a kind of MISFET, a leak current generated in the MISFET, called gate induced drain leakage (hereinafter abbreviated as GIDL), is generated. As described in Non-Patent Document 1, GIDL is a leakage current due to electrons and holes generated by band-to-band tunneling in a depletion layer located in the overlap region of the gate and drain of the MISFET. Since the tunneling probability increases as the electric field increases, the leakage current increases as the drain junction becomes steeper.

In order to reduce GIDL, it is considered effective to form a drain junction gently. As a technique for optimally designing a drain junction in a FinFET, for example, there is one reported in Non-Patent Document 2. The standard deviation when the spread in the channel length direction of the first conductivity type impurity of the source / drain is approximated by a Gaussian distribution is σ, and the impurity distribution begins to decrease in the channel length direction (region where the gate electrodes do not overlap) ) To the gate end is δ. Increasing σ while δ remains small increases the drain voltage dependency of the threshold voltage and increases off-current, but increasing δ along with σ suppresses the increase in off-current. Conversely can be reduced. When σ is large, the drain junction becomes gentle, so that GIDL can also be reduced. The problem with using such a gentle drain junction is that the on-current is degraded.
T.A. Y. Chan et al. 1987 IEDM Technical Digest, pp. 1987. 718-720 V. P. Trivedi and J.M. G. Fossum, 2004 IEEE International SOI Conference (pp. IEEE International SOI Conference), pp. 192-194

  An object of the present invention is to provide a FinFET capable of reducing GIDL while suppressing deterioration of on-current and a method for manufacturing the same.

The field effect transistor according to the present invention includes a semiconductor layer protruding upward from a substrate plane, gate electrodes provided on both side surfaces of the semiconductor layer, and gate insulation interposed between the gate electrode and the side surface of the semiconductor layer. A film, a source / drain region in which a first conductivity type impurity is introduced into the semiconductor layer, and a channel formation region in a portion sandwiched between the source / drain regions of the semiconductor layer,
A region in which a first conductivity type impurity having a concentration gradient in the channel length direction which is gentler than a concentration gradient in the channel length direction of the first conductivity type impurity in a lower portion thereof is introduced above the semiconductor layer in the source / drain region. Have.

  In the field effect transistor of the present invention, the second conductivity type impurity is introduced into the channel formation region, and the junction position between the source region and the channel formation region and the junction position between the drain region and the channel formation region are The distance can be such that the lower region is narrower than the upper region of the semiconductor layer.

  In the field effect transistor of the present invention, the first conductivity type impurity heavier than the first conductivity type impurity introduced into the lower portion is introduced into the region having a gentle concentration gradient above the semiconductor layer. Can take form.

  Further, in the field effect transistor of the present invention, the gate electrode extends on opposite side surfaces from the upper part so as to straddle the protruding semiconductor layer, and the gate insulating film is formed on the protruding semiconductor layer. It can take the form of being provided under the gate electrode over both side surfaces facing from the top.

  Further, the field effect transistor of the present invention can take a form in which a supporting substrate is provided under the protruding semiconductor layer, and the semiconductor layer is integrally connected to the supporting substrate.

  The field effect transistor of the present invention can take a form in which a support substrate is provided under the protruding semiconductor layer, and the semiconductor layer is provided on the support substrate via a buried insulating film. .

In addition, the method for producing the field effect transistor of the present invention includes:
Patterning the semiconductor layer to form a semiconductor layer protruding from the substrate plane;
Forming a gate electrode through an insulating film so as to straddle the protruding semiconductor layer;
Using this gate electrode as a mask, from both sides of the gate electrode, each of the first conductivity type impurities is parallel to the plane perpendicular to the substrate plane and parallel to the channel length direction and oblique to the substrate plane. Performing ion implantation to form an upper region of the source / drain region above the semiconductor layer;
Using the gate electrode as a mask, ion-implanting a first conductivity type impurity from a direction perpendicular to the substrate plane to form a lower region of the source / drain region below the upper region.

  The field effect transistor manufacturing method of the present invention preferably includes a step of etching the gate electrode to shorten the gate length after the step of forming the upper region and before the step of forming the lower region.

  In the field effect transistor manufacturing method of the present invention, it is preferable that a first conductivity type impurity lighter than the first conductivity type impurity in the upper region is implanted into the lower region.

  The first effect of the present invention is caused by the tunnel phenomenon by relaxing the electric field by providing a region having a gentle impurity concentration gradient in the channel length direction above the source / drain region of the protruding semiconductor layer (fin layer). The GIDL current can be reduced.

  The second effect of the present invention is that the degradation of the on-current can be suppressed by limiting the region where the impurity concentration gradient is gentle to a part of the source / drain region.

  In a normal FinFET structure, high electric field regions are formed at the upper and lower ends of the fin layer, and the upper end has a higher electric field. As a result, it was found that the tunnel phenomenon is most likely to occur in the drain depletion layer near the upper end of the fin layer, and the generation rate of electrons and holes by the tunnel is high. The FinFET of the present invention has a region in which the concentration gradient in the channel length direction of the first conductivity type impurity is gentle in the upper part of the fin layer in the source / drain region. The hole generation rate can be reduced, and as a result, the GIDL current can be reduced. On the other hand, since the drain region having a gentle concentration gradient is a part of the drain region, the deterioration of the on-current is small.

[Description of structure]
An embodiment of the present invention will be described with reference to FIG. 1A is a cross-sectional view taken along the line AA ′ in the plan view shown in FIG. 1C, and FIG. 1B is a cross-sectional view taken along the line BB ′. .

  In the present embodiment, a semiconductor layer (hereinafter referred to as “fin layer”) 3 protruding upward from the substrate is provided, and a gate electrode 5 is provided on both opposing side surfaces and upper surface of the fin layer via a gate insulating film 4. . The gate electrode 5 is patterned to a predetermined size, and source / drain regions 6 and 7 into which a first conductivity type impurity is introduced at a high concentration are formed in the fin layer 3 at a position not covered by the gate electrode 5. The

  Here, the concentration gradient in the channel length direction of the first conductivity type impurity in the upper region 7 of the source / drain region is smaller than the concentration gradient in the lower region 6 below the first conductivity type impurity. Thereby, the electric field in the depletion layer formed in the vicinity of the interface between the source / drain region 7 and the channel formation region 8 is relaxed, and the carrier generation rate due to the band-to-band tunneling phenomenon can be reduced.

  In the source / drain regions, the impurity concentration is generally constant in the channel length direction at a position sufficiently away from the gate electrode. If the constant concentration value and the position where the concentration starts to decrease from the constant concentration value are substantially the same in the lower region 6 where the concentration gradient is small and the lower region 6 where the concentration gradient is large, the upper region 7 has the first conductivity type impurity. The skirt of the distribution lengthens and the effective channel length becomes shorter in this portion. For this reason, the short channel effect becomes strong, the threshold voltage is lowered, and the off-current is increased. In order to avoid this, in the upper region 7, a position where the concentration starts to decrease may be provided at a position away from the end of the gate electrode. However, although the short channel effect resistance is improved in this way, the impurity concentration of the upper region 7 in the vicinity of the end of the gate electrode is lowered, so that the resistance value increases and the on-current is deteriorated. Therefore, if the thickness of the lower region 6 of the source / drain region is made sufficiently larger than the thickness of the upper region 7, the deterioration rate can be suppressed. Here, the thickness means a size perpendicular to the plane of the substrate.

  The thickness of the source / drain region 7 is preferably at least about half the width Wfin of the fin layer shown in FIG. 1A in order to cover a region where a high electric field is applied. On the other hand, from the viewpoint of suppressing the deterioration of the on-current, it is preferable that the height be at most about half the height Hfin of the fin layer shown in FIG. That is, the thickness of the region 7 provided on the upper portion of the fin layer is preferably set in a range of 1/2 or more of the fin layer width Wfin and 1/2 or less of the fin layer height Hfin. Here, the fin layer width Wfin means a size in a direction perpendicular to the gate length direction (channel length direction) and parallel to the substrate plane. The height Hfin of the fin layer refers to a size in a direction perpendicular to the substrate plane at a portion protruding upward from the substrate plane.

FIG. 8 shows the results obtained by simulating the amount of current obtained in the FinFET having the conventional source / drain structure as shown in FIG. 8 and the FinFET having the two-layer source / drain structure of the present invention as shown in FIG. The results are summarized in Table 1. The gate length is 80 nm, the gate insulating film thickness is 2.7 nm, the fin layer width Wfin is 15 nm, the fin layer height Hfin is 50 nm, the gate electrode material is polysilicon, and the channel formation region has a second conductivity type impurity. ^Was calculated for a structure in which was introduced at a concentration of 6 × 10 ¹⁸ cm ⁻³ .

The concentration distribution of the first conductivity type impurity in the source / drain region was set as follows. It is constant at a location farther from the gate electrode than a position separated by δ in the horizontal distance from the gate electrode end to the outside of the gate electrode, and has a concentration of 1 × 10 ²⁰ cm ⁻³ . The concentration is lowered with a Gaussian distribution given by the standard deviation σ along the gate length direction from the position separated by δ toward the gate end. In Table 1, in the conditions 1 and 2 of the source / drain structure, the concentration distribution is defined by the same δ and σ from the top to the bottom of the fin layer. In condition 2, since the value of σ is set larger than in condition 1, the concentration gradient in the channel length direction (gate length direction) is gentle. In condition 3, the region from the upper end of the fin layer to 10 nm has a distribution defined by δ and σ as in condition 2, and the region below 15 nm from the upper end of the fin layer is defined by δ and σ as in condition 1. The region from 10 nm to 15 nm from the upper end of the fin layer is a distribution in which the concentration is lowered with a Gaussian distribution given with a standard deviation of 5 nm upward based on the concentration at the position of 15 nm from the upper end of the fin layer. Using.

表１はｎ型ＭＯＳＦＥＴについて計算した結果で、表に示したソースに流れる正孔電流は、ドレイン端の空乏層領域におけるトンネル現象で発生するキャリアの生成率にほぼ等しく、ＧＩＤＬ電流を表すものと考えて良い。条件２は条件１よりも濃度勾配が緩やかで電界が小さくなることを反映してＧＩＤＬ電流が大幅に小さくなっている。しかし、ゲート電極端の抵抗率の増加の影響でオン電流が１０％程度低下している。本発明のトランジスタ構造に対応する条件３では、条件１の６０％程度のＧＩＤＬ電流に抑えられている上に、オン電流は殆んど劣化していない。なお、表に示した電流値は、実効的なチャネル幅、すなわち、（フィン層の高さＨｆｉｎ）×２＋（フィン層の幅Ｗｆｉｎ）で規格化した値である。

Table 1 shows the calculation results for the n-type MOSFET. The hole current flowing through the source shown in the table is almost equal to the generation rate of carriers generated by the tunnel phenomenon in the depletion layer region at the drain end, and represents the GIDL current. You can think about it. Condition 2 has a much smaller GIDL current than the condition 1 reflecting the fact that the concentration gradient is gentler and the electric field is smaller. However, the on-current is reduced by about 10% due to the increase in resistivity at the gate electrode end. In the condition 3 corresponding to the transistor structure of the present invention, the GIDL current is suppressed to about 60% of the condition 1, and the on-current is hardly deteriorated. The current values shown in the table are values normalized by an effective channel width, that is, (fin layer height Hfin) × 2 + (fin layer width Wfin).

  FIG. 2 is a cross-sectional view corresponding to the fin layer 3 in the B-B ′ cross-sectional view of FIG. A broken line 12 in FIG. 2 is a pn junction line in the source / drain structure of Condition 3, and the distance between the pn junction lines is larger on the fin layer. As described above, in the structure in which the second conductivity type impurity is introduced into the channel formation region, when the junction distance between the upper region and the lower region of the fin layer is larger, the decrease in the on current is suppressed while suppressing the off current and the GIDL current. Can do.

[Description of manufacturing method]
Next, with reference to FIGS. 3-7, the manufacturing method of one Embodiment of the field effect transistor by this invention is demonstrated. 4, 5, and 6, (a) is a cross-sectional view taken along the line AA ′ of the plan view shown in (c), and (b) is along the line BB ′. FIG.

First, as shown in FIG. 3, the support substrate 1 made of silicon, a buried insulating layer 2 made of an insulating material such as SiO ₂ thereon, further SOI (Silicon semiconductor layer 9 made of single crystal silicon are laminated thereon on insulator) substrate.

  Next, the semiconductor layer 9 of the SOI substrate is patterned into a predetermined shape by a lithography technique and an etching technique to form a fin layer 3 protruding from the substrate as shown in FIG.

  Next, an insulating film for the gate insulating film 4 is formed on the side surface and the upper surface of the fin layer 3, and then the gate electrode material is deposited and then patterned to be provided on the fin layer via the gate insulating film 4 A gate electrode 5 is obtained (FIG. 5). When forming the channel formation region into which the second conductivity type impurity is introduced, the impurity is introduced at an appropriate time before depositing the gate electrode material, for example, before and after the step of forming the fin layer 3 by patterning.

  After the gate electrode 5 is formed, as shown in FIG. 5, the gate electrode 5 is parallel to a plane perpendicular to the substrate surface and parallel to the channel length direction (corresponding to the line BB ′ in FIG. 5C). In addition, ion implantation of the first conductivity type impurity is performed in an oblique direction with respect to the substrate plane, and a part of the source / drain region (upper region 7) is formed above the fin layer 3. This oblique ion implantation is performed from both sides of the gate electrode, that is, from both directions in the channel length direction. 5B and 5C, ion implantation is performed along the solid arrow direction and the dotted arrow direction.

  Subsequently, after the width of the gate electrode (gate length) is shortened by isotropic etching, as shown in FIG. 6, ion implantation of the first conductivity type impurity is performed from the direction perpendicular to the substrate surface, and the fin layer 3 A part of the source / drain region (lower region 6) is formed at a position away from the upper part of the gate electrode. Generally, the spread of the concentration distribution in the incident direction of ion implantation is larger than the spread in the lateral direction perpendicular to the incident direction. For this reason, as shown in FIG. 7, the concentration gradient in the channel length direction of the first conductivity type impurity in the upper region 7 is gentler than the concentration gradient in the lower region 6 below.

  The ion implantation for forming the lower region 6 is performed to such a depth that does not affect the concentration distribution of the upper region 7. For this reason, there is a concern that the implantation energy increases, and thereby the lateral spread also increases. In order to reduce this influence, a light (small atomic weight) impurity species (for example, phosphorus if n-type) is used in the ion implantation process of the lower region 6 and a heavy (large atomic weight) in the ion implantation process of the upper region 7. ) Impurity species (for example, arsenic for n-type) are used.

  The reason for performing the etching process to reduce the width of the gate electrode before the ion implantation process of the lower region 6 is that the position where the concentration of the first conductivity type impurity in the upper region 7 starts to attenuate in the lateral direction (channel length direction) is gated. This is because it is separated from the electrode end. Thus, as described above, the upper region 7 having an impurity profile corresponding to a distribution in which both δ and σ are large can be formed, and electric field relaxation can be achieved while suppressing the short channel effect.

[Other Embodiments]
The field effect transistor of the embodiment shown in FIG. 1 has a structure in which the support substrate 1 and the fin layer 3 are separated from each other. However, as shown in FIG. 7 and 8) and the support substrate 1 are connected to the structure having the semiconductor layer 11 into which the second conductivity type impurity is introduced, and the GIDL current is reduced while suppressing the deterioration of the on-current. be able to. Here, FIG. 9A and FIG. 9B are cross-sectional views taken along lines AA ′ and BB ′, respectively, in the plan view shown in FIG. 9C.

  In the normal FinFET structure, as shown in FIG. 1, the fin layer 3 is separated from the support substrate 1 by the buried insulating film layer 2, and carriers do not flow from the fin layer 3 to the support substrate 1. In such a so-called SOI structure, for example, in nMOSFET, the potential of the channel formation region is modulated by holes generated by the tunnel phenomenon, and the potential barrier between the source and the drain is lowered to amplify the electron injection from the source. Will occur. For this reason, the leakage current increases more than the leakage current amount due to the GIDL current. In the structure as shown in FIG. 9, since holes escape to the substrate and the parasitic bipolar effect does not occur, an increase in leakage current can be prevented. However, even with such a structure, a GIDL current due to carriers generated by the tunnel phenomenon remains, and the structure of the present invention is effective in reducing it.

  In the structure shown in FIG. 9, for example, a semiconductor substrate is processed to form a protrusion, an insulating material is provided on the semiconductor substrate so that the upper portion of the protrusion is exposed, and the exposed protrusion is used as a fin layer. be able to.

  The “base plane” in the FinFET structure means an arbitrary plane parallel to the substrate and corresponds to the upper surface of the insulating layer 2 in FIGS.

  The FinFET shown in FIG. 1 and FIG. 9 extends on both side surfaces facing from the upper surface so that the gate electrode straddles the fin layer, and both side surfaces facing the gate insulating film from the upper surface of the fin layer below the gate electrode. And a so-called trigate structure in which channels are formed on the upper surface and both side surfaces of the fin layer, and the present invention is most effective for such a trigate structure. Further, the present invention can be applied to a FinFET having a so-called double gate structure in which a thick insulating film is provided on the upper surface of the fin layer, and a channel is not formed on the upper surface of the fin layer but a channel is formed only on both side surfaces. The effect of reducing the GIDL current while suppressing the deterioration of the on-current can be expected.

  The field effect transistor of the present invention is suitable for a low-power semiconductor device used for a mobile phone, a mobile terminal, or the like.

It is sectional drawing and the top view explaining embodiment of the field effect transistor of this invention. It is sectional drawing which shows the typical pn junction position in the field effect transistor of this invention. It is sectional drawing explaining embodiment of the manufacturing method of the field effect transistor by this invention. It is sectional drawing and top view explaining embodiment of the manufacturing method of the field effect transistor by this invention. 5A and 5B are a cross-sectional view and a plan view illustrating an ion implantation process for forming a source / drain region having a gentle concentration gradient in an embodiment of a method for manufacturing a field effect transistor according to the present invention. 5A and 5B are a cross-sectional view and a plan view illustrating an ion implantation process for forming a source / drain region having a steep concentration gradient in an embodiment of a method for manufacturing a field effect transistor according to the present invention. It is the figure which showed typically the concentration distribution of the horizontal direction of a source / drain area | region. It is sectional drawing and a top view explaining the conventional field effect transistor. It is sectional drawing and top view explaining other embodiment of the field effect transistor of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating layer 3 Semiconductor layer (fin layer)
4 Gate insulating film 5 Gate electrode 6 Source / drain region having a steep concentration gradient in the channel length direction 7 Source / drain region having a gradual concentration gradient in the channel length direction 8 Channel forming region 9 Semiconductor layer 10 Source / drain region 11 On the substrate Semiconductor layer to be connected 12 pn junction line

Claims (9)

A semiconductor layer projecting upward from the substrate plane; gate electrodes provided on both sides of the semiconductor layer; a gate insulating film interposed between the gate electrode and a side surface of the semiconductor layer; A source / drain region into which one conductivity type impurity is introduced, and a channel formation region in a portion sandwiched between the source / drain regions of the semiconductor layer;
A region in which a first conductivity type impurity having a concentration gradient in the channel length direction which is gentler than a concentration gradient in the channel length direction of the first conductivity type impurity in a lower portion thereof is introduced above the semiconductor layer in the source / drain region. Field effect transistor having. A second conductivity type impurity is introduced into the channel formation region;
The distance between the junction position between the source region and the channel formation region and the junction position between the drain region and the channel formation region is longer in the upper region of the semiconductor layer than in the lower region. Field effect transistor.   3. The field effect according to claim 1, wherein a first conductivity type impurity heavier than a first conductivity type impurity introduced into a lower portion of the region having a gentle concentration gradient above the semiconductor layer is introduced. Transistor.   The gate electrode extends on opposite side surfaces from the upper part so as to straddle the protruding semiconductor layer, and the gate insulating film extends over the opposite side surfaces from the upper part of the protruding semiconductor layer. The field effect transistor according to claim 1, 2 or 3 provided below.   5. The field effect transistor according to claim 1, wherein a support substrate is provided under the protruding semiconductor layer, and the semiconductor layer is integrally connected to the support substrate.   5. The field effect transistor according to claim 1, further comprising a support substrate under the protruding semiconductor layer, the semiconductor layer being provided on the support substrate via a buried insulating film. It is a manufacturing method of the field effect type transistor according to claim 1,
Patterning the semiconductor layer to form a semiconductor layer protruding from the substrate plane;
Forming a gate electrode through an insulating film so as to straddle the protruding semiconductor layer;
Using this gate electrode as a mask, from both sides of the gate electrode, each of the first conductivity type impurities is parallel to the plane perpendicular to the substrate plane and parallel to the channel length direction and oblique to the substrate plane. Performing ion implantation to form an upper region of the source / drain region above the semiconductor layer;
Using the gate electrode as a mask, and performing ion implantation of a first conductivity type impurity from a direction perpendicular to the substrate plane to form a lower region of the source / drain region below the upper region. Manufacturing method.   8. The method of manufacturing a field effect transistor according to claim 7, further comprising a step of etching the gate electrode to shorten the gate length after the step of forming the upper region and before the step of forming the lower region.   9. The method of manufacturing a field effect transistor according to claim 7, wherein a first conductivity type impurity lighter than the first conductivity type impurity in the upper region is implanted into the lower region.

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