JP4892720B2 - Minimum Euclidean distance search associative memory device - Google Patents

Description

  The present invention relates to an associative memory device that is used in information processing devices such as color and gray scale image compression and image recognition, and has a minimum Euclidean distance search function based on full parallel processing.

  In recent years, an associative memory having a minimum distance search function has attracted attention in the field of information processing technology, particularly image compression and image recognition. The associative memory is very effective for pattern matching for object recognition required for intelligent information processing and data compression using a data group called a code book. The associative memory is one of the typical functional memories having a function of retrieving the most similar (closest distance) data from a plurality of reference data in the associative memory with respect to the input data string (search data). The excellent search function is expected to dramatically improve the performance of the application having the above-described pattern matching function such as image compression and image recognition.

  Finding data that is most similar to input data from reference data of k bits × W unit widths R is a basic process in pattern matching (Non-patent Document 1). Therefore, it can be said that the minimum distance search associative memory (Patent Document 1) is a core part for information processing such as image compression and image recognition. As existing all parallel minimum distance search associative memories, those having a simple distance search function for Manhattan and Hamming distance have been proposed. These distances are defined by the following formula 1 (Non-patent Document 2).

Here, SW = {SW ₁ , SW ₂ ,..., SW _w } represents input data, and REF = {REF ₁ , REF ₂ ,..., REF _w } represents reference data. When SW _i and REF _i are 1-bit binary numbers, D is a Hamming distance. Further, when SW _i and REF _i are binary numbers of k bits (k> 1), D is a Manhattan distance. So far, a fully parallel minimum Hamming distance search architecture (Non-patent document 2) and a fully parallel minimum Manhattan distance search architecture (Non-patent documents 3 and 2) have been proposed.

  However, in an algorithm used in some applications, it is desired to apply Euclidean distance as a distance index. The Euclidean distance is expressed by Equation 2, and is more accurate than the Manhattan distance as a measure for measuring the distance between two points in the vector space.

JP 2002-288985 A JP 2005-209317 A JP 2004-5825 A D. R. Tveter, "The Pattern Recognition Basis of Artificial Intelligence," Los Alamitos, CA: IEEE computer society, 1998. HJMattausch, T.Gyohten, Y. Soda, and T. Koide, "Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance," IEEE Journal of Solid-State Circuits, Vol. 37, pp. 218 -227, 2002. HJ Mattausch, N. Omori, S. Fukae, T. Koide and T. Gyohten, "Fully-Parrallel Pattern-Matching Engine with Dynamic Adaptibility to Hamming or Manhattan Distance," 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 252 -255, 2002. P. Heim, F. Krummenacher and E. A. Vittoz, "CMOS Full-wave Operational Transconductance Rectifier with Improved DC Transfer Characteristic," Electron. Lett., Vol. 28, pp. 333-334, 1992. Y. Tulay and J. S. Marsland, "A Conic Section Function Network Synapse and Neuron Implementation in VLSI Hardware," IEEE Conf. Neural Networks, pp. 974-979, 1996. S. Churcher, A. F. Murray and H. M. Reekie, "Programmable Analogue VLSI for Radial Basis Function Networks," Electron. Lett., Vol. 29, pp. 1603-1605, 1993. O. Landolt, E. Vittoz and P. Heim, "CMOS Selfbiased Euclidean Distance Computing Circuit with Highdynamic Range," Electron. Lett., Vol. 28, pp. 352-354, 1992. S. Collins, G. F. Marshall and D. R. Brown, "An Analogue Radial Basis Function Circuit Using a Compact Euclidean Distance Calculator," IEEE Int. Symp. Circuits Systems, pp. 233-236, 1994. P. Hasler, BA Minch, J. Dugger, and C. Dorio, "Adaptive Circuits and Synapses using Floating Gate Devices," in Learning on Silicon: Adaptive VLSI Neural Systems, G. Cauwenberghs and MA Bayoumi, Eds. Boston, MA: Kluwer, pp. 33-65, 1999. M. Freeman, M. Weeks and J. Austin, "Hardware Implementation of Similarity Functions," IADIS International Conference on Applied Computing, Algarve, Portugal, vol. 2, pp. 329-332, 2005. Y. Yano, T. Koide and HJ Mattausch, "Fully Parallel Nearest Manhattan-distance Search Memory with Large Reference-pattern Number," Extend. Abst. Of the Int. Conf. On Solid State Devices and Materials (SSDM'2002), pp. 254-255, 2002.

  So far, many circuits for calculating the Euclidean distance have been proposed (Non-Patent Documents 4 to 7). However, in most of them, there are disadvantages such as limitation of the distance that can be calculated and large circuit scale.

  In order to solve these problems, several circuits using floating gates have been developed (Non-Patent Documents 8 and 9). However, since this circuit is difficult to perform circuit simulation, it is difficult to design it by predicting the circuit operation before manufacturing the chip.

  On the other hand, a circuit that sequentially calculates the Euclidean distance and a description using the hardware description language VHDL have been reported (Non-Patent Document 10). This circuit is a digital circuit using a multiplier, an adder, a register, and a square root calculation circuit. However, since the number of mounted transistors is very large, it is not suitable for an associative memory in which each reference data and input data are processed in parallel. .

  In order to calculate the Euclidean distance, a complex calculation of square and square root is required. In particular, the square root is a heavy calculation even with the latest processor. This is because the square root is calculated by repeating the approximation, that is, by repeatedly calculating until the value is within the error margin. Even if it does not have a square root calculation function as hardware, even calculation of a square root of a small value is impossible.

  As described above, an effective architecture that realizes a fully parallel minimum Euclidean distance search memory in hardware has not been proposed so far.

  In order to retrieve pattern data having the nearest Euclidean distance, calculation of the square root is not necessary, and it is sufficient to compare only the squared distances. This is because pattern matching requires only a comparison of the relative magnitudes of distances, and the square root does not change this relative magnitude. The associative memory device according to the present invention is based on such a viewpoint and is configured as follows.

A distance calculation circuit for calculating the square of the Euclidean distance based on the absolute value calculation of the difference in parallel with a plurality of reference data, and a search circuit for searching for the reference data of the minimum distance from the calculation result of the square of the Euclidean distance Is an associative memory device formed on a memory,
When the search data and the reference data are unitized in units of k bits (k> 1),
The distance calculation circuit includes:
A W column R row unit storage circuit (US) for storing the reference data in units;
A unit comparison circuit (UC) of W columns and R rows that calculates the absolute value of the difference between the reference data and the search data for each unit;
An R row word weight comparison circuit (WC) that generates a current or voltage signal corresponding to the sum of the squares of the absolute values of the differences calculated by the W column unit comparison circuit for each row. To do.

  In the associative memory device according to the present invention, the distance calculation circuit calculates the square of the Euclidean distance, and the reference data for the minimum distance is searched for in the search circuit from the calculation result of the square of the Euclidean distance. Since this is not performed, the circuit scale can be reduced and the calculation process can be speeded up. As a result, when applied to an associative memory device, the minimum Euclidean distance search can be realized with a chip configuration with low power consumption and a small area.

  As described above, the present invention has developed a Euclidean distance calculation circuit necessary for color / grayscale image compression / recognition in a fully parallel associative memory-based system, and has a low-power and small-area minimum Euclidean distance search association. A memory device is realized. In particular, this circuit configuration enables high-efficiency fully parallel associative memory device chips using conventional CMOS technology for pattern matching applications (eg, network routers, codebook-based data compression, and object recognition). To do.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings.
[Fully parallel associative memory architecture]
FIG. 1 is a block diagram showing the architecture of a fully parallel associative memory device according to the present invention. The memory core portion is composed of a memory area 100, a winner lineup amplifier circuit (hereinafter referred to as a WLA circuit (Winner Line-Up Amplifier)) 200, and an entire winner acquisition circuit (hereinafter referred to as a WTA circuit (Winner Take All Circuit)) 300. In addition, as a peripheral circuit, a column decoder and R / W circuit (Column Decoder and Read / Write (k × W Columns)) 110, a row decoder (Row Decoder (R Rows)) 120, a search data storage circuit (Search Data ( k × W Bits)) 130. This associative memory device is realized as an integrated circuit on one chip, and the memory core portion and the peripheral circuit are formed on this one chip.

  The memory area 100 includes W × R unit storage circuits (Unit Storage: US) formed of SRAM cells for storing reference data in units (k bits), and the difference between reference data and search data for each unit. W × R unit comparison circuits (Unit Comparison: UC) that calculate the absolute value of R, and R word weight comparison circuits (Word) that convert the calculated absolute difference into an analog voltage (or current) and square the conversion result Comparison: WC).

  A signal C (Comparison Signal) generated by the word weight comparison circuit WC enters the WLA circuit 200, and the WLA circuit 200 controls the signal C according to the balance of the circuit itself, and at the first stage, the voltage difference of each row is maximized. Amplify. The WLA circuit 200 and the WTA circuit 300 are characterized in that the rate of area increase with respect to the number of rows R is O (R) that is linear with respect to the number of rows R.

The WTA circuit 300 has a function of further amplifying the difference between the voltage outputs LA of the respective rows amplified by the WLA circuit 200. The output WTA of the WTA circuit 300 is a digital signal in which the winner row is “1” and the other loser rows are “0”. When returning the feedback signal to the word weight comparison circuit WC, the WLA circuit 200 uses a voltage follower circuit built in the WLA circuit 200 to speed up the feedback.
[Euclidean distance calculation circuit]
In order to retrieve pattern data having the nearest Euclidean distance, calculation of the square root is not necessary, and it is sufficient to compare only the squared distances. This is because pattern matching requires only a comparison of the relative magnitudes of distances, and the square root does not change this relative magnitude. The Euclidean distance calculation circuit used in the associative memory device of this embodiment is configured based on such a viewpoint.

As shown in FIG. 1, the Euclidean distance calculation circuit according to the present embodiment is configured by arranging W units corresponding to k bits (k> 1) in which handled data is encoded. Reference data stored in the input to become the search data and the associative memory apparatus of the associative memory device (i line) and SW respectively, when placing the REF _i, number squared Euclidean distance between SW and REF _i 3 It is expressed as

The Euclidean distance is mainly used for image data processing that requires comparison of k-bit and W data such as a color image and a grayscale image. In order to realize the calculation of the Euclidean distance, a circuit that compares the weighted search data (SW) and the reference data (REF _i ), that is, the absolute value of the difference between the two k-bit data of each of the W units ( | SW _j −REF _ij |) and a circuit for calculating the square of the absolute difference are required.

FIG. 2 is a block diagram (for W units) showing the configuration of the Euclidean distance calculation circuit for row i constructed in the associative memory device. In FIG. 2, US _{i1 to} US _iW are obtained by fetching search data units based on k-bit binary code data of the non-inverted signal SW and the inverted signals ~ SW (where ~ means inversion, the same applies hereinafter) and stored in advance. Unit storage circuits UC _{i1 to} UC _iW that store data in units of bits together with data units are each provided with a k-bit subtractor and an absolute value calculation circuit, and receive search data SW and reference data REF _i from unit storage circuits US _{i1 to} US _iW . The unit comparison circuit calculates the absolute value of the difference between the two. The data of the absolute value of the difference between the search data SW and the reference data REF _i calculated by each of the unit comparison circuits UC _{i1 to} UC _iW is used as a digital value of the output OUT = {0, 1} of each bit. sent to WC _i, in the word weight comparison circuit WC _i, to calculate the sum of the squares of the Euclidean distances of all the bits (square of the absolute differences).

In the word weight comparison circuit WC _i , a current conversion circuit 10 and an analog square circuit 20 are provided for each of the unit comparison circuits UC _{i1 to} UC _iW .

Digital signals OUT _{1 to} OUT _k output from the unit comparison circuits UC _{i1 to} UC _iW are converted into analog currents by the corresponding current conversion circuits 10. Each current conversion circuit 10 converts _k digital signals OUT _{1 to} OUT _k (digital distances) output from the corresponding unit comparison circuits into analog currents, and receives k digital PMOS signals (k) (received at the gate). Current conversion transistor) is used. Here, the output values OUT ₁ , OUT ₂ ,..., OUT _k of each bit are adjusted and weighted so as to be 2 ^k-1 times the current value of the output OUT ₁ of the least significant bit according to the position of each bit. Has been done. As an adjustment method, the gate width W _k of the transistor connected to the output OUT _{k of} each bit is multiplied by an integer (2 ^k−1 × W ₀ ) (W ₀ indicates a reference transistor width), and the square of the analog Each bit is weighted by controlling the value of the current flowing through the transistor connected to the circuit 20.

The output current I _i from each current conversion circuit 10 is squared by the corresponding analog squaring circuit 20. A circuit configuration example of the analog squaring circuit 20 is shown in FIG. The current (current corresponding to the square of the absolute difference) I _o output from each analog squaring circuit 20 flows to the match line, whereby the square of the Euclidean distance between the search data SW _i and the reference data REF _ij of each group. A current value I corresponding to the square of the Euclidean distance D _{Euclid, i} between the entire search data SW and the reference data REF _i is obtained. The current value I is converted into a voltage value and sent to the WLA circuit 200 and the WTA circuit 300. The signal of the row with the shortest Euclidean distance is amplified, and “1” is output from the row with the shortest distance.

The unit storage circuit (US) and the unit comparison circuit (UC) shown in FIG. 2 can be realized by using a known circuit, for example, by using the one disclosed in Patent Document 2. it can.
[Performance evaluation of minimum Euclidean distance search associative memory]
The performance of the minimum Euclidean distance search associative memory based on this embodiment was confirmed by simulation with HSPICE. The technology used was 0.35 μm CMOS and 16 5-bit binaries (W = 16, k = 5 in FIG. 2) and 128 reference data (R = 128 in FIG. 1). The simulation results for the Basic Squarer section of the analog squaring circuit 20 shown in FIG. 3 are shown in FIG. 4, the time for searching the reference data of the minimum Euclidean distance (Winner search time) is shown in FIG. The results are shown in FIG. Thus, the minimum Euclidean distance search associative memory according to the present embodiment can find a winner in a wide range of reference data and a winner distance.
[Modification of this embodiment]
Note that the Euclidean distance calculation circuit shown in FIG. 7 can be used instead of the Euclidean distance calculation circuit shown in FIG. In the word weight comparison circuit WC _i of the Euclidean distance calculation circuit shown in FIG. 7, a digital squaring circuit 30 and a current conversion circuit 40 are provided for each of the unit comparison circuits UC _{i1 to} UC _iW . Digital signal output from each unit comparator circuits UC _i1 ~UC _iW (k bits) OUT ₁ to OUT _k is squared by the corresponding digital squaring circuit. The output from the digital squaring circuit 30 (2k _{bits, k> 1) OUT 1 ~OUT} 2k is converted into an analog current by the corresponding current conversion circuit 40. Each current conversion circuit 40 includes 2k PMOS (current conversion transistors) that receive respective digital signals at their gates in order to convert the digital signals OUT _{1 to} OUT _2k output from the corresponding digital squaring circuit 30 into analog currents. ) Is used. Here, the output values OUT ₁ , OUT ₂ ,..., OUT _2k of each bit are adjusted and weighted so as to be 2 ^2k - ¹ times the current value of the output OUT ₁ of the least significant bit according to the position of each bit. Has been done. As an adjustment method, the gate width W _2k of the transistor connected to the output OUT _2k (k> 1) of each bit is multiplied by an integer (2 ^2k −1 × W ₀ ) (W ₀ indicates a reference transistor width). Thus, each bit is weighted by controlling the current value flowing through the transistor in the current conversion circuit 40. The current output from each current conversion circuit 40 (current corresponding to the square of the absolute difference) flows to the match line, thereby corresponding to the square of the Euclidean distance between the search data SW _i and the reference data REF _ij of each group. A current flows, and a current value I corresponding to the square of the Euclidean distance D _{Euclid, i} of the entire search data SW and reference data REF _i is obtained.

  The logic of the circuits (FIGS. 2, 3, and 7) shown in this embodiment is an example, and the logic circuit can be inverted to positive or negative logic. For example, even if the N-MOS in the memory area is changed to P-MOS and the P-MOS in the current conversion circuits 10 and 40 is changed to N-MOS, the operational effect remains unchanged.

  The associative memory device according to the present invention is used for artificial intelligence systems, data bank systems, Internet routers, mobile terminals (for example, mobile videophones), codebook-based data compression, compression such as object recognition, and general recognition processing techniques. can do.

1 is a block diagram showing an architecture of a fully parallel associative memory device using an Euclidean distance calculation circuit as an embodiment according to the present invention. The block diagram which shows the structure for 1 line of the Euclidean distance calculation circuit in the memory shown in FIG. FIG. 3 is a circuit diagram showing an internal configuration of the analog square circuit shown in FIG. 2. The figure which shows the simulation result about the Basic Squarer part of the analog squaring circuit 20 shown in FIG. The figure which shows the simulation result of Winner search time. The figure which shows the simulation result of average power consumption. The block diagram which shows the modification of the structure for 1 line of the Euclidean distance calculation circuit in the memory shown in FIG.

Explanation of symbols

100 memory area 200 winner line-up amplifier (WLA)
300 Winner Take All Circuit (WTA)
110 Row Decoder and Read / Write (kx W Column)
120 Row Decoder (R Rows)
130 Search Data Storage Circuit (Search Data (k bit x W))
US Unit Storage Circuit (Unit Storage)
UC Unit Comparison Circuit (Unit Comparison)
WC Word Weight Comparison Circuit (Word Comparison)
DESCRIPTION OF SYMBOLS 10 Current conversion circuit 20 Analog square circuit 30 Digital square circuit 40 Current conversion circuit

Claims (4)

A distance calculation circuit for calculating the square of the Euclidean distance based on the absolute value calculation of the difference in parallel with a plurality of reference data, and a search circuit for searching for the reference data of the minimum distance from the calculation result of the square of the Euclidean distance Is an associative memory device formed on a memory,
When the search data and the reference data are unitized in units of k bits (k> 1),
The distance calculation circuit includes:
A unit storage circuit of W columns and R rows for storing the reference data in units;
A unit comparison circuit of W columns and R rows that calculates the absolute value of the difference between the reference data and the search data for each unit;
A word weight comparison circuit for R rows that generates a current or voltage signal corresponding to the sum of the squares of the absolute values of the differences calculated by the unit comparison circuit for the W columns for each row.
A minimum Euclidean distance search associative memory device. In claim 1,
Each of the R row word weight comparison circuits comprises:
A current conversion circuit and an analog square circuit are provided corresponding to each of the unit comparison circuits in the corresponding row,
Each of the current conversion circuits includes:
The digital signal output from the corresponding unit comparison circuit is converted into an analog current.
Each of the analog square circuits is
The output current from the corresponding current conversion circuit is squared and output to the match line of the corresponding row.
A minimum Euclidean distance search associative memory. In claim 1,
Each of the R row word weight comparison circuits comprises:
A digital squaring circuit and a current conversion circuit are provided corresponding to each of the unit comparison circuits in the corresponding row,
Each of the digital squaring circuits
The digital signal output from the corresponding unit comparison circuit is squared,
Each of the current conversion circuits includes:
A digital signal output from a corresponding digital squaring circuit is converted into an analog current and output to a match line of the corresponding row;
A minimum Euclidean distance search associative memory. In claim 1,
The distance calculation circuit and the search circuit are formed on the same chip of a semiconductor integrated circuit,
A minimum Euclidean distance search associative memory.