JP4883001B2 - Receiving machine - Google Patents

Description

  The present invention relates to a receiver including a high frequency tuning circuit.

  Heterodyne receivers are widely used as compact and high-performance receivers. A superterodyne receiver has a characteristic of receiving an image frequency (image frequency) in addition to a target frequency and easily causing a reception failure.

A heterodyne receiver that employs a varicap tuning circuit as a high-frequency tuning circuit is known for further enhancement of performance (Patent Document 1, FIG. 1).
JP 05-48392 A

  However, receivers that use varicaps as receiver circuits must adjust the capacity of the varicaps at the production and shipment stages, and then make adjustments that focus on the attenuation of the signal in the image frequency range. It is not efficient to do. For this reason, it is common to adjust the capacity of the varicap so that the gain maximum point of the reception target frequency becomes a desired value.

A receiver using a varicap as a receiver circuit. In order to suppress a decrease in receiver sensitivity due to a decrease in gain of the device used due to temperature characteristics, etc., the receiver high-frequency tuning circuit including the amplification stage has a certain amount of surplus. Give gain.
For this reason, in the adjustment based only on the reception sensitivity best point, the image disturbance ratio is not always the best point.

Further, in the adjustment while looking at both the reception sensitivity and the image interference ratio, the adjustment target becomes enormous and adjustment is difficult.
If the focus is on the image jamming ratio, the reception sensitivity will not be the best.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a receiver that can be easily adjusted while using a varicap in a receiving circuit, and that has a good reception sensitivity and image interference ratio.

In order to achieve this object, a receiver according to the first aspect of the present invention provides:
A tuning circuit that tunes and receives a high-frequency signal;
A conversion circuit for converting the output signal of the tuning circuit into an intermediate frequency signal;
Demodulation means for demodulating the received signal from the intermediate frequency signal output from the conversion circuit;
A receiver comprising:
The tuning circuit is
A variable-capacitance diode whose capacity changes according to the first control voltage is provided, the frequency-gain characteristic is changed according to the capacity of the variable-capacitance diode, and the first gain for a signal of the target frequency A first bandpass filter having:
A variable capacitance diode connected in cascade with the first bandpass filter and having a capacitance that changes according to the second control voltage is provided, and the frequency-gain characteristic changes according to the capacitance of the variable capacitance diode. A second band-pass filter having a second gain for a signal of a target frequency;
Control means for applying the first and second control voltages to the variable capacitance diode of the first bandpass filter and the variable capacitance diode of the second bandpass filter;
The first and second bandpass filters are:
The capacitances of the variable capacitance diodes of the first and second bandpass filters are the same , the second gain is less than or equal to the first gain, and the frequency-gain characteristics of the second bandpass filter Has a configuration that is gentler than the frequency-gain characteristic of the first bandpass filter,
The control means includes
Applying the first control voltage to a variable capacitance diode of the first bandpass filter within a range from a first voltage to a second voltage;
Applying the second control voltage to a variable capacitance diode of the second band-pass filter within a range narrower than a range from the first voltage to the second voltage;
It is characterized by that.

The frequency of the tuning circuit - gain characteristic, for example, the second band-pass filter is the same frequency as the first band-pass filter - the tuned circuit obtained when it is assumed to have a gain characteristic Rather than frequency-gain characteristics,
The gain at the target frequency is small, and the difference between the gain at the target frequency and the gain for a predetermined noise is large.

  The tuning circuit may further include an amplifier that amplifies the signal of the first bandpass filter and supplies the amplified signal to the second bandpass filter.

  According to the present invention, the tuning circuit can be easily adjusted and a suitable image disturbance characteristic can be obtained.

  Hereinafter, a superheterodyne receiver (hereinafter simply referred to as a receiver) 100 according to an embodiment of the present invention will be described.

  As shown in FIG. 1, the receiver 100 of this embodiment includes an antenna 1, an antenna (ANT) tuning circuit 2, a radio frequency (RF) amplifier circuit 3, a radio frequency (RF) tuning circuit 4, a mixing circuit 5, and a local part. An oscillation circuit 6, an intermediate frequency (IF) amplification circuit 7, a demodulation circuit 8, a low frequency amplification circuit 9, a speaker 10, a system controller 11, a digital / analog conversion circuit (hereinafter abbreviated as "D / A") circuit 12, 13, an RSSI detection circuit 14, an operation unit 15, and an EEPROM 16.

The ANT tuning circuit 2 is composed of a band pass filter including a varicap (variable capacitance diode), and tunes to a target frequency f0 by a control voltage applied via the D / A 12. Details thereof will be described later.
The RF amplifier circuit 3 amplifies the received signal after being tuned by the ANT tuning circuit 2.

The RF tuning circuit 4 attenuates an unnecessary frequency band of the signal received by the ANT tuning circuit 2 and amplified by the RF amplifier circuit 3 and outputs the attenuated frequency band.
The RF tuning circuit 4 is composed of a band-pass filter including a varicap (variable capacitance diode), and the gain of the target frequency f0 is changed by a control voltage applied via the D / A 13. Details thereof will be described later.

  The mixing circuit 5 mixes the reception high-frequency signal output from the RF tuning circuit 4 and the local oscillation signal supplied from the local oscillation circuit 6, down-converts the high-frequency reception signal into an intermediate frequency (IF) signal, and outputs the signal. .

  The IF amplifier circuit 7 amplifies and outputs the intermediate frequency signal output from the mixing circuit 5.

The demodulation circuit 8 demodulates and outputs a baseband signal (here, an audio signal) from the intermediate frequency signal.
The low frequency amplifier circuit 9 amplifies the sound signal and outputs sound from the speaker 10.
Also,

  The system controller 11 includes a CPU (central processing unit), a memory, and the like, and controls the operation of the entire receiver 100 according to an operation program stored in the memory. In particular, the system controller 11 supplies a control voltage indicating a tuning frequency (target frequency) to the ANT tuning circuit 2 via the D / A 12.

  Further, the system controller 11 corresponds to the voltage signal for setting the frequency-gain characteristic in the RF tuning circuit 4 via the D / A 13 (corresponding to setting data stored in advance in the EEPROM 16 according to the target frequency). Voltage).

The RSSI detection circuit 14 measures the intensity of the signal received from the antenna 1 and outputs the measurement result to the system controller 11 as an RSSI detect signal.
The operation unit 15 includes operation keys and the like, and is operated by a user to supply a user instruction such as a target frequency to the system controller 11.

The EEPROM 16 is a non-volatile memory that stores fixed data for controlling the receiver 100, and stores a table indicating the relationship between the target frequency and the voltage supplied to the ANT tuning circuit 2.
Further, the EEPROM 16 stores setting data for controlling the frequency-gain characteristic of the RF tuning circuit 4 based on the adjustment made when the receiver 100 is manufactured and shipped. This setting data will be described later.

Next, the ANT tuning circuit 2 to the RF tuning circuit 4 will be described in detail.
As shown in FIG. 2, each of the ANT tuning circuit 2 and the RF tuning circuit 4 has a configuration in which two band pass filters (BPF) 21, 22, 41, and 42 are connected in cascade.
The first-stage, second-stage, and fourth-stage BPFs 21, 22, and 42 have a relatively narrow passband width and a relatively high Q (resonance sharpness) at the target frequency f0 as shown in FIG. As shown in FIG. 3B, the third-stage bandpass filter 41 has a characteristic that the passband width is relatively wide and the Q at the target frequency f0 is relatively low.

As an example, the BPFs 21, 22, and 42 of the first stage, the second stage, and the fourth stage have the configuration shown in FIG. 4A, and the band-pass filter 41 of the third stage is shown in FIG. It has the structure shown.
As shown in the figure, the BPFs 21, 22, and 42 of the first stage, the second stage, and the fourth stage include a coil (inductor) 111, a capacitor 112, and a series circuit of a varicap 113 and a capacitor 114 connected in parallel. The capacitor 115 and 116 connected in the front and rear are provided, and a control signal for capacitance control is applied from the control terminal 118 to the cathode of the varicap 113 via the resistor 117.

  The third-stage bandpass filter 41 has a configuration in which a resistor (damping resistor) 119 is connected to the above-described configuration.

  Further, the system controller 11 reads the setting data stored in advance in the EEPROM 16 and supplies it to the D / A 12-1, 12-2, 13-1, and 13-2 from the ports P1 to P4 at the time of starting up. A control voltage corresponding to the control terminal 118 of the BPF 21, 22, 41, 42 is applied.

  This setting data is a value within a predetermined range (for example, a value corresponding to a voltage of 0 V to 5 V) for the first, second, and fourth ports P1, P2, and P4, and for the third port P3. Is a value within a part of the predetermined range (a value corresponding to a voltage of 0 V to 2 V).

  Accordingly, a voltage within a predetermined range (voltage range of 0 V to 5 V) is applied to the control terminals 118 of the BPFs 21, 22, and 42 of the first stage, the second stage, and the fourth stage, and the BPF 41 of the third stage is applied. Is applied with a voltage within a part of the predetermined range (voltage range of 0V to 2V).

Due to the difference in configuration, the BPFs 21, 22, and 42 of the first stage, the second stage, and the fourth stage control the capacitance of the varicap 113 at the control terminal 118 so that the resonance frequency becomes the target frequency f0. When the control voltage to be applied is applied, the frequency-gain characteristic schematically shown in FIG.
In addition, when a control voltage for controlling the capacity of the varicap 113 is applied to the control terminal 118 so that the resonance frequency becomes the target frequency f0, the third bandpass filter 41 is schematically shown in FIG. The frequency-gain characteristic shown is shown.

  Thus, the BPFs 21 to 42 are connected in cascade, and the range of values that can be taken by the control voltage applied to the control terminal 118 of the BPF 41 is within the range of values that the control voltage applied to the control terminals of the BPFs 21, 22, and 42 can take. When the RSSI detect signal is maximized as a result of a part of the range, the entire high-frequency circuit (ANT tuning circuit 2, RF amplifier circuit 3, RF tuning circuit 4) has the frequency-gain shown in FIG. Show properties.

  If the control voltage range applied to the control terminal 118 of the third stage BPF 41 is the same control voltage range as the first stage, second stage, and fourth stage BPFs 21, 22, and 42, the characteristic is A relatively flat characteristic as shown in FIG. On the other hand, the range of the control voltage applied to the control terminal of the third stage BPF 41 having a relatively low frequency-gain peak and a relatively gentle frequency-gain curve is limited to the target frequency. Adjustment is performed so that the RSSI detect signal for f0 is maximized.

  For this reason, as shown in FIG. 5A, the peak gain is slightly lower than the characteristics of FIG. 5B by DC, but the frequency corresponding to the peak gain and the IF / 2 image signal is high. The gain difference at (f0 + IF / 2) increases from DB to DA. By appropriately adjusting, DA >> DB >> DC is established.

  For this reason, when the target frequency f0 and the IF / 2 image signal having the frequency relationship as shown in FIG. 6 are studied, the IF / The intensity ratio between the target signal and the IF / 2 image signal (that is, the image disturbance ratio) is controlled while controlling the gain so that the two image signals can be sufficiently attenuated and the gain at the target frequency f0 is substantially maximized. Can be large enough. Other image signals and noise, such as 2IF image signals, can be similarly attenuated.

Next, the operation of the receiver 100 having the above configuration will be described.
When the power is turned on, the system controller 11 reads the setting data 1 to setting data 4 corresponding to the target frequency f0 from the EEPROM 16, and the first from the ports P1 to P4 via the D / A 12-1 to 13-2. The voltage is applied to the control terminal 118 of the BPF 21 to 42 in the fourth to fourth stages. Thereby, the BPF 21 to 42 in the first stage to the fourth stage are set to desired characteristics as shown in FIG. 3A or 3B, respectively. Set to the characteristics shown.

  As a result, the ANT tuning circuit 2 tunes to the target frequency f0, receives a signal in a fixed band centered on the target frequency f0, and supplies the signal to the RF amplifier circuit 3.

The RF amplifier circuit 3 amplifies the signal received by the ANT tuning circuit 2 and supplies the amplified signal to the RF tuning circuit 4.
Here, as is well known, the received signal includes a target signal, an image signal, and further a half image signal. The half image signal is also called an IF / 2 image signal, and is a signal generated at a position separated from the RF signal (target frequency f0) by IF / 2.

  The RF tuning circuit 4 filters the input signal with a filtering characteristic corresponding to the control voltage supplied from the D / A 13-1 and 13-2.

  As described above, in the entire high frequency circuit (2 to 4), the gain near the frequency f0 of the target signal is slightly lower (DC in FIG. 5) than the maximum value obtained from the structure, but the gain at the target frequency is Since the gain difference DA at the IF / 2 image point is sufficiently large, the IF / 2 image signal is sufficiently attenuated while amplifying the target signal without inferiority, and a new signal having a high image disturbance ratio is generated and mixed Output to the circuit 5.

The local oscillation circuit 6 oscillates at a frequency designated by the system controller 11, and the mixing circuit 5 mixes the high frequency signal output from the RF tuning circuit 4 and the local oscillation signal from the local oscillation circuit 6, An intermediate frequency signal having a predetermined frequency is output.
The intermediate frequency amplifier circuit 7 extracts and amplifies the frequency of the target signal from the intermediate frequency signal, attenuates an unnecessary signal including noise, and outputs the attenuated signal.

The demodulation circuit 8 demodulates and outputs the audio signal.
The low frequency amplifier circuit 9 amplifies the audio signal and supplies it to the speaker 10. The speaker 10 converts sound signals into air vibrations and emits sound.

  In this way, the receiver 100 sufficiently amplifies the target signal while sufficiently attenuating the IF / 2 image signal, the 2IF image signal, and the noise to generate a signal with a high image disturbance ratio, and the mixing circuit 5. Output to.

Next, a method for adjusting the receiver 100 will be specifically described.
A default value is recorded in the EEPROM 16 at the time of manufacture, and then this default value is finely adjusted at the time of shipment or the like.
First, the person in charge of adjustment activates the transmitter that transmits the target frequency f0 and causes the receiver 100 to receive it.

  Subsequently, for example, the operation unit 15 instructs the system controller 11 to start the adjustment operation. In response to this instruction, the system controller 11 starts the high-frequency tuning circuit adjustment operation shown in FIG.

  First, the system controller 11 sets an initial value 0 or a negative value as the maximum value of RSSI (step S10).

  Next, the system controller 11 sets setting data indicating a common minimum value (0 in this example) to the D / A 12-1 to 13-2 that apply control voltages to the four BPFs 21 to 42 from the ports P1 to P4. Is supplied as an initial value (step S11). The D / A 12-1 to 13-2 convert the supplied setting data into a common control voltage and apply it to the control terminal 118 of the corresponding BPF 21 to 42.

  The system controller 11 takes in the output of the RSSI detection circuit 14, determines whether or not it is larger than the maximum value of the RSSI value stored in advance, and if so, the setting data supplied to the D / A 12-1 to 13-2 And the measured value of the RSSI detection circuit 14 are associated with each other and overwritten and stored (step S12).

  Next, the system controller 11 determines whether or not the setting data is a final value (maximum value) (step S13). In this example, it is determined whether or not the setting data is a value corresponding to 5V.

  When the system controller 11 determines that the setting data is not the final value (step S13; No), the system controller 11 adds a preset pitch (small value) Dp to the setting data, and each D / A 12-1 to 13-13. -2 from the ports P1 to P4 (step S14). However, since the setting data output from the port P3 to the D / A 13-1 has an upper limit value (for example, 2V), the data (value) is maintained after reaching the upper limit value.

  Thereafter, the control proceeds to step S12, and the same processing is repeated.

  When the above processing is repeated, the setting data reaches a value corresponding to the upper limit value (for example, 5V) (however, the setting data from the port P3 is a limited upper limit value (for example, setting data corresponding to 2V)). In step S13, “Yes” is determined.

  The system controller 11 outputs the setting data corresponding to the maximum value of RSSI recorded in the internal memory from the ports P1 to P4, and outputs the control voltage corresponding to the D / A 12-1 to 13-2, so that the BPF 21 To 42 are supplied to the control terminal 118 (step S15).

  Next, the system controller 11 sets an initial value 1 to a pointer I that specifies one of the four BPFs 21 to 42 (step S16).

  Next, the system controller 11 sets an initial value 0 or a negative value as the maximum RSSI value for the I-stage BPF (step S17).

  Subsequently, the system controller 11 outputs setting data indicating the minimum value from the I-th port PI (initially the first port P1). Note that the previous setting data is continuously output from the other ports. Initially, since I = 1, setting data corresponding to the control voltage of 0 V is output from the first port P1 to the D / A 12-1 (step S18).

  The system controller 11 takes in the RSSI detect signal from the RSSI detection circuit 14 and compares it with the maximum RSSI value for the first I stored in the internal memory. If the current RSSI value is larger, the current port PI Is stored in association with the RSSI value measured by the RSSI detection circuit 14 (step S19).

  Next, the system controller 11 determines whether or not the setting data is a final value (maximum value) (step S20). That is, when I = 1, 2, 4, it is determined whether or not the setting data is a data value indicating a maximum value (for example, 5V), and when I = 3, the setting data is within a limited range. It is determined whether or not the data indicates a value corresponding to the maximum value (for example, 2V).

  When the system controller 11 determines that the setting data is not the final value (step S20; No), the system controller 11 adds a preset pitch (minor value) Δ to the setting data and outputs it from the I-th port PI. (Step S21).

Thereafter, the control proceeds to step S19, and the same processing is repeated.
When the above processing is repeated and the setting data reaches a value corresponding to the upper limit value (for example, 5V or 2V), Yes is determined in step S20.

  The system controller 11 outputs the setting data when the maximum RSSI value is obtained for the I-stage BPF from the I-th port PI and outputs the setting data for the I-stage BPF, that is, from the port PI. The data is stored in the EEPROM 16 as data.

  Next, the system controller 11 determines whether or not the pointer I is the final value (4 in this example) (step S23). If I is not 4 (step S23; No), I is incremented by one. (Step S24), the process proceeds to Step S17, and the same processing is repeated.

  In this way, when processing for all I, that is, all BPFs, is completed, the EEPROM 16 stores setting data for the BPFs at each stage.

  Thus, the process for adjusting the receiver 100 is completed.

  When there are a plurality of target frequencies, the receiver 100 is adjusted for each target frequency, setting data for each target frequency is stored in the EEPROM 16, and setting data corresponding to the set target frequency is stored. The characteristics of the BPFs 21 to 42 may be set by reading from the EEPROM 16 and outputting from the ports P1 to P4.

As described above, according to the system of this embodiment, an output signal with a high image disturbance ratio can be obtained while adjusting the RF tuning circuit 4 based on the maximum gain point.
In addition, by limiting the range of the control voltage with the system controller 11, the range limit can be arbitrarily switched (ON / OFF), and the voltage range can also be arbitrarily and easily changed.

The present invention is not limited to the above embodiment, and various modifications and applications are possible.
For example, in the above embodiment, the BPF constituting the RF tuning circuit 4 has a four-stage configuration, but may have two, three, or five or more stages.

Further, although the BPF 41 immediately after the RF amplifier circuit 3 has a broad characteristic, the characteristic of another BPF may be broad, and a plurality of BPFs may be used. However, the range of the control voltage applied to the broad BPF is limited compared to other control voltages.
Also, the configuration of the BPF shown in FIGS. 4A and 4B is an example, and any known configuration can be used.
The receiver adjustment method described above is also an example, and can be appropriately changed if appropriate setting data can be obtained based on RSSI.

It is a block diagram which shows the structure of the receiver which concerns on embodiment of this invention. It is a figure which shows the structural example of RF tuning circuit shown in FIG. (A) And (b) is a figure which shows the characteristic of BPF shown in FIG. (A) And (b) is a figure which shows the example of a structure of BPF shown in FIG. It is a figure which shows the example of the characteristic of RF tuning circuit shown in FIG. 1, (a) is the characteristic in this embodiment, (b) is the characteristic in a conventional structure. It is a figure which shows frequency distribution of a received signal. It is a flowchart which shows the procedure which adjusts a receiving circuit.

Explanation of symbols

1 Antenna
DESCRIPTION OF SYMBOLS 2 Antenna (ANT) tuning circuit 3 High frequency (RF) amplification circuit 4 High frequency (RF) tuning circuit 5 Mixing circuit 6 Local oscillation circuit 7 Intermediate frequency amplification circuit 8 Demodulation circuit 9 Low frequency amplification circuit 11 System controller 12 D / A conversion circuit 13 D / A conversion circuit 14 RSSI detection circuit 15 Operation unit 16 EEPROM
100 receiver

Claims (3)

A tuning circuit that tunes and receives a high-frequency signal;
A conversion circuit for converting the output signal of the tuning circuit into an intermediate frequency signal;
Demodulation means for demodulating the received signal from the intermediate frequency signal output from the conversion circuit;
A receiver comprising:
The tuning circuit is
A variable-capacitance diode whose capacity changes according to the first control voltage is provided, the frequency-gain characteristic is changed according to the capacity of the variable-capacitance diode, and the first gain for a signal of the target frequency A first bandpass filter having:
A variable capacitance diode connected in cascade with the first bandpass filter and having a capacitance that changes according to the second control voltage is provided, and the frequency-gain characteristic changes according to the capacitance of the variable capacitance diode. A second band-pass filter having a second gain for a signal of a target frequency;
Control means for applying the first and second control voltages to the variable capacitance diode of the first bandpass filter and the variable capacitance diode of the second bandpass filter;
The first and second bandpass filters are:
The capacitances of the variable capacitance diodes of the first and second bandpass filters are the same , the second gain is less than or equal to the first gain, and the frequency-gain characteristics of the second bandpass filter Has a configuration that is gentler than the frequency-gain characteristic of the first bandpass filter,
The control means includes
Applying the first control voltage to a variable capacitance diode of the first bandpass filter within a range from a first voltage to a second voltage;
Applying the second control voltage to a variable capacitance diode of the second band-pass filter within a range narrower than a range from the first voltage to the second voltage;
A receiver characterized by that. The frequency-gain characteristic of the tuning circuit is
It said second band-pass filter is the first band-pass filter of the same frequency - the frequency of the tuning circuit obtained when it is assumed to have a gain characteristics - than the gain characteristic,
The gain at the target frequency is small,
The difference between the gain at the target frequency and the gain for a given noise is large.
The receiver according to claim 1. The tuning circuit is
An amplifier that amplifies the signal of the first bandpass filter and supplies the amplified signal to the second bandpass filter;
The receiver according to claim 1 or 2.

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