JP4877564B2 - Full-wave rectifier circuit - Google Patents

Full-wave rectifier circuit Download PDF

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JP4877564B2
JP4877564B2 JP2009247050A JP2009247050A JP4877564B2 JP 4877564 B2 JP4877564 B2 JP 4877564B2 JP 2009247050 A JP2009247050 A JP 2009247050A JP 2009247050 A JP2009247050 A JP 2009247050A JP 4877564 B2 JP4877564 B2 JP 4877564B2
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正和 加次
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Description

本発明は、集積回路を用いた全波整流回路に関し、特に、CMOS−LSI化に適した回路構成を有する全波整流回路に関する。   The present invention relates to a full-wave rectifier circuit using an integrated circuit, and more particularly to a full-wave rectifier circuit having a circuit configuration suitable for CMOS-LSI implementation.

集積回路を用いた全波整流回路は、バイポーラプロセスを用いれば容易に構成することができる。しかし、近年の高集積化,低消費電力化に伴いMOSプロセスが主流となり、MOSプロセスにより回路を構成することが重要である。   A full-wave rectifier circuit using an integrated circuit can be easily configured by using a bipolar process. However, with the recent high integration and low power consumption, the MOS process has become mainstream, and it is important to configure the circuit by the MOS process.

図3は、従来のMOSプロセスを用いた全波整流回路の一例を示すブロック図である。細線で囲んだ差動入力回路201は交流信号Vinを入力し、電流減算回路202は差動入力回路201の一対の出力電流から一定電流を差し引き、電流加算回路203は電流減算回路202の一対の出力電流を加え合わせる。   FIG. 3 is a block diagram showing an example of a full-wave rectifier circuit using a conventional MOS process. A differential input circuit 201 surrounded by a thin line inputs an AC signal Vin, a current subtraction circuit 202 subtracts a constant current from a pair of output currents of the differential input circuit 201, and a current addition circuit 203 is a pair of current subtraction circuits 202. Add the output current.

図4は、図3に示した各トランジスタの電流と交流信号Vinとの関係を示す波形である。先ず、交流信号Vin(図4(A)参照)を差動入力回路201に入力すると、トランジスタTr21,Tr22には、それぞれi,(I1−i)の電流が流れる(図4(B),(C)参照)。   FIG. 4 is a waveform showing the relationship between the current of each transistor shown in FIG. 3 and the AC signal Vin. First, when an AC signal Vin (see FIG. 4A) is input to the differential input circuit 201, currents i and (I1-i) flow in the transistors Tr21 and Tr22, respectively (FIGS. 4B and 4B). C)).

これらの電流をトランジスタTr23,Tr24によって、電流減算回路202のトランジスタTr25,Tr26にそれぞれ電流ミラーすることによって、トランジスタTr27,Tr28にはI2/2だけ減算された電流が流れる。即ち、トランジスタTr27に流れる電流をI(Tr27)とし、トランジスタTr28に流れる電流をI(Tr28)とすると、
I(Tr27)=i−I1/2
I(Tr28)=I1−i−I1/2=−(i−I2/2)
となる。
These currents are mirrored to the transistors Tr25 and Tr26 of the current subtraction circuit 202 by the transistors Tr23 and Tr24, respectively, so that a current subtracted by I2 / 2 flows through the transistors Tr27 and Tr28. That is, if the current flowing through the transistor Tr27 is I (Tr27) and the current flowing through the transistor Tr28 is I (Tr28),
I (Tr27) = i-I1 / 2
I (Tr28) = I1−i−I1 / 2 = − (i−I2 / 2)
It becomes.

ところが実際には、i<I1/2のときI(Tr27)<0となり、また、i>I1/2ときI(Tr28)<0となるので、このときには、トランジスタTr27,Tr28に電流は流れない(図4(D),(E)参照)。   Actually, however, I (Tr27) <0 when i <I1 / 2, and I (Tr28) <0 when i> I1 / 2, so that no current flows through the transistors Tr27 and Tr28. (See FIGS. 4D and 4E).

最後に、これらのトランジスタTr27,Tr28に流れる電流を電流加算回路203のトランジスタTr29,Tr30にミラーしてトランジスタTr31で加算することにより、図4(F)に示すような全波整流波形を得る。トランジスタTr32は出力トランジスタである。   Finally, the currents flowing through the transistors Tr27 and Tr28 are mirrored to the transistors Tr29 and Tr30 of the current adding circuit 203 and added by the transistor Tr31, thereby obtaining a full-wave rectified waveform as shown in FIG. The transistor Tr32 is an output transistor.

しかしながら、図3に示した全波整流回路では、出力電流が差動入力回路201のトランジスタTr21およびTr22の相互コンダクタンスGmで決まってしまうため、出力電流の振幅がトランジスタのプロセス変動によって変動するという欠点がある(図4(F)点線参照)。また、抵抗を用いて出力電圧を得る場合、出力電流が一定でも抵抗値の製造バラツキや温度変動によって出力電圧振幅が変わる。   However, in the full-wave rectifier circuit shown in FIG. 3, since the output current is determined by the mutual conductance Gm of the transistors Tr21 and Tr22 of the differential input circuit 201, the amplitude of the output current varies due to process variations of the transistors. (See dotted line in Fig. 4 (F)). Further, when an output voltage is obtained using a resistor, the output voltage amplitude changes due to manufacturing variations of resistance values and temperature fluctuations even if the output current is constant.

特開平8−289554号公報JP-A-8-289554

解決しようとする問題点は、回路素子の製造バラツキや温度変動による特性劣化を防止できない点である。   The problem to be solved is that it is impossible to prevent characteristic deterioration due to manufacturing variations of circuit elements and temperature fluctuations.

本発明は、差動入力トランジスタのドレインの間に抵抗を挿入することにより、差動入力回路に流れる電流をその抵抗で定まる構成にしたことを最も主要な特徴とする。   The most important feature of the present invention is that a resistor is inserted between the drains of the differential input transistor so that the current flowing through the differential input circuit is determined by the resistance.

本発明の全波整流回路は、差動入力トランジスタのドレインの間に抵抗を挿入して、差動入力回路に流れる電流をトランジスタの増幅率によらず、その抵抗で定まる構成にしたため、全波整流回路の出力を電圧として取り出す場合の電圧-電流変換抵抗と上記抵抗とで相対精度をとることにより、これらの変動があっても、出力電圧を一定に保つことができるという利点がある。   In the full wave rectifier circuit of the present invention, a resistor is inserted between the drains of the differential input transistor, and the current flowing through the differential input circuit is determined by the resistance regardless of the amplification factor of the transistor. By taking the relative accuracy between the voltage-current conversion resistor and the resistor when the output of the rectifier circuit is taken out as a voltage, there is an advantage that the output voltage can be kept constant even if these fluctuations occur.

本発明の全波整流回路の一実施例を示す回路図である。It is a circuit diagram which shows one Example of the full wave rectifier circuit of this invention. 図1に示した全波整流回路の波形図である。It is a wave form diagram of the full wave rectifier circuit shown in FIG. 従来の全波整流回路を例示する回路図である。It is a circuit diagram which illustrates the conventional full wave rectifier circuit. 図3に示した全波整流回路の動作を示す波形図である。It is a wave form diagram which shows the operation | movement of the full wave rectifier circuit shown in FIG.

図1は本発明の全波整流回路の実施例1を示す。この全波整流回路は、差動入力回路101と電流減算回路102と電流加算回路103とで構成されている。差動入力回路101は交流信号を入力して差動電流を定電流(その値を定電流源I0と同様にI0と記す)に重畳出力する。電流減算回路102は差動入力回路101からカレントミラーされる電流から定電流を減算して差動電流を出力するが、減算結果が負となる時間領域では零値を出力する。電流加算回路103は電流減算回路102からカレントミラーされる位相が180度異なる2つの差動電流を加算することにより全波整流した出力電流を得る。いま、トランジスタTr1,Tr2を流れる電流を(I0-i),(I0+i)として説明する。   FIG. 1 shows a first embodiment of a full-wave rectifier circuit according to the present invention. This full-wave rectifier circuit includes a differential input circuit 101, a current subtraction circuit 102, and a current addition circuit 103. The differential input circuit 101 receives an alternating current signal and outputs a differential current superimposed on a constant current (its value is written as I0 like the constant current source I0). The current subtracting circuit 102 subtracts a constant current from the current mirrored from the differential input circuit 101 and outputs a differential current, but outputs a zero value in a time domain where the subtraction result is negative. The current adding circuit 103 obtains an output current that has been full-wave rectified by adding two differential currents that are 180 degrees different in phase from the current subtracting circuit 102. Now, the current flowing through the transistors Tr1 and Tr2 will be described as (I0-i) and (I0 + i).

差動入力回路101は、交流信号Vinを差動入力して差電圧を発生するトランジスタTr1,Tr2と、トランジスタTr1,Tr2のドレインの間を接続して差電圧を差動電流iに変換する抵抗R1と、トランジスタTr1,Tr2それぞれのドレインに接続された定電流源I0と、差動電流を定電流に重畳した電流(I0-i),(I0+i)を電流減算回路102のTr4,Tr7へカレントミラーするトランジスタTr3,Tr6を有している。差動電流iの向きはトランジスタTr1のドレインからトランジスタTr2のドレインへ向かう方向とする。   The differential input circuit 101 is a resistor that converts the differential voltage into a differential current i by connecting the transistors Tr1 and Tr2 that generate the differential voltage by differential input of the AC signal Vin and the drains of the transistors Tr1 and Tr2. R1, the constant current source I0 connected to the respective drains of the transistors Tr1 and Tr2, and the currents (I0-i) and (I0 + i) obtained by superimposing the differential currents on the constant currents are represented by Tr4 and Tr7 in the current subtraction circuit 102. Transistors Tr3 and Tr6 that mirror the current. The direction of the differential current i is the direction from the drain of the transistor Tr1 to the drain of the transistor Tr2.

いま、トランジスタTr1,Tr2のドレインとゲート間の電位差を等しくすると、トランジスタTr1,Tr2のドレイン間、即ち抵抗R1の両端の電位差は交流信号Vinとなるので、抵抗R1を流れる電流はi=Vin/R1となってR1で定まる。   Now, if the potential difference between the drains and gates of the transistors Tr1 and Tr2 is made equal, the potential difference between the drains of the transistors Tr1 and Tr2, that is, the both ends of the resistor R1, becomes an AC signal Vin, so the current flowing through the resistor R1 is i = Vin / R1 is determined by R1.

電流減算回路102は、差動入力回路101からカレントミラーされた電流(I0+i)と電流(I0-i)により差動電流2i,-2iを生成して出力する。差動電流2iの生成は、トランジスタTr4,Tr7,Tr9,Tr10,Tr11により行なう。一方、差動電流-2iの生成は、トランジスタTr5,Tr13,Tr14,Tr15,Tr16により行なう。差動電流の生成は、下記のように、電流経路を分岐することにより減算して行なう。   The current subtracting circuit 102 generates and outputs differential currents 2i and -2i from the current mirrored current (I0 + i) and current (I0-i) from the differential input circuit 101. The generation of the differential current 2i is performed by the transistors Tr4, Tr7, Tr9, Tr10, and Tr11. On the other hand, the differential current -2i is generated by the transistors Tr5, Tr13, Tr14, Tr15, and Tr16. The generation of the differential current is performed by subtraction by branching the current path as described below.

先ず、差動入力回路101のトランジスタTr3,Tr6からカレントミラーされた電流(I0-i),(I0+i)がトランジスタTr4,Tr7で受け取られる。トランジスタTr9は、トランジスタTr4の電流(I0-i)をトランジスタTr10へカレントミラーする。トランジスタTr11は、トランジスタTr7の電流(I0+i)からトランジスタTr10の電流(I0-i)を減算することにより差動電流2iを生成する。   First, current mirrored currents (I0-i) and (I0 + i) from the transistors Tr3 and Tr6 of the differential input circuit 101 are received by the transistors Tr4 and Tr7. The transistor Tr9 mirrors the current (I0-i) of the transistor Tr4 to the transistor Tr10. The transistor Tr11 generates a differential current 2i by subtracting the current (I0-i) of the transistor Tr10 from the current (I0 + i) of the transistor Tr7.

また、差動入力回路101のトランジスタTr3,Tr6からカレントミラーされた電流(I0-i),(I0+i)はトランジスタTr5,Tr15でも受け取られる。トランジスタTr13は、トランジスタTr5の電流(I0-i)をトランジスタTr14へカレントミラーする。トランジスタTr16は、トランジスタTr14の電流(I0-i)からトランジスタTr15の電流(I0+i)を減算することにより差動電流-2I1を生成する。   Further, the current mirrored currents (I0-i) and (I0 + i) from the transistors Tr3 and Tr6 of the differential input circuit 101 are also received by the transistors Tr5 and Tr15. The transistor Tr13 mirrors the current (I0-i) of the transistor Tr5 to the transistor Tr14. The transistor Tr16 generates a differential current -2I1 by subtracting the current (I0 + i) of the transistor Tr15 from the current (I0-i) of the transistor Tr14.

以上のように、差動電流2I1,-2I1の生成は同様な回路構成で行なわれる。しかし、差動電流2i,-2iの電流加算回路103へのカレントミラーは異なる回路構成で行なわれることとなる。即ち、差動電流-2iはトランジスタTr16から電流加算回路103のトランジスタTr17へ直接にカレントミラーされるのに対して、差動電流2iはトランジスタTr11からトランジスタTr12,トランジスタTr8を経由して電流加算回路103のトランジスタTr18へカレントミラーされる。   As described above, the differential currents 2I1 and -2I1 are generated with the same circuit configuration. However, the current mirror of the differential currents 2i and -2i to the current adding circuit 103 is performed with different circuit configurations. That is, the differential current -2i is directly mirrored from the transistor Tr16 to the transistor Tr17 of the current adding circuit 103, whereas the differential current 2i is supplied from the transistor Tr11 to the transistor Tr12 and the transistor Tr8 through the current adding circuit. The current is mirrored to 103 transistor Tr18.

これは、カレントミラーは同極性のMOS同士の間でしか行なうことができないことに由来する。前者ではトランジスタTr16とトランジスタTr17が共にNMOSであるのに対して、後者ではトランジスタTr11はPMOS、トランジスタTr18はNMOSであるため、PMOSトランジスタTr11の電流をPMOSトランジスタTr12へカレントミラーし、トランジスタTr12と直列接続されたNMOSトランジスタTr8で引き継ぎ、この電流をNMOSトランジスタTr18へカレントミラーする。   This is because the current mirror can only be performed between MOSs of the same polarity. In the former, both the transistor Tr16 and the transistor Tr17 are NMOS, whereas in the latter, the transistor Tr11 is a PMOS and the transistor Tr18 is an NMOS. Therefore, the current of the PMOS transistor Tr11 is current-mirrored to the PMOS transistor Tr12, and is serially connected to the transistor Tr12. The connected NMOS transistor Tr8 takes over, and this current is mirrored to the NMOS transistor Tr18.

電流加算回路103では、トランジスタTr18を流れる差動電流2iと、トランジスタTr17を流れる差動電流-2iを合流することにより加算してトランジスタTr19に流し、トランジスタTr19は加算された差動電流2i,-2iをトランジスタTr20にカレントミラーする。トランジスタTr20を流れる差動電流2i,-2iが出力電流である。   In the current adding circuit 103, the differential current 2i flowing through the transistor Tr18 and the differential current -2i flowing through the transistor Tr17 are added together to flow to the transistor Tr19, and the transistor Tr19 adds the differential currents 2i,- 2i is current mirrored to the transistor Tr20. Differential currents 2i and -2i flowing through the transistor Tr20 are output currents.

前述のとおり、抵抗R1を流れる電流iはR1で定まる。従って、トランジスタTr20に電流−電圧変換用抵抗(図示省略)を接続して、出力電流を乗算した出力電圧とする場合、抵抗R1と電流−電圧変換用抵抗とで相対精度をとることにより、製造バラツキや温度変動があっても、出力電圧を一定に維持することができるようになる。なお、相対精度をとるとは、複数の物の間で所定の寸法比率を一致させることをいい、同一プロセスで製造することにより容易に実現することができる。   As described above, the current i flowing through the resistor R1 is determined by R1. Therefore, when a current-voltage conversion resistor (not shown) is connected to the transistor Tr20 to obtain an output voltage obtained by multiplying the output current, it is manufactured by taking the relative accuracy between the resistor R1 and the current-voltage conversion resistor. Even if there are variations and temperature fluctuations, the output voltage can be kept constant. In addition, taking relative accuracy means making a predetermined dimensional ratio correspond among several things, and can implement | achieve easily by manufacturing in the same process.

次に、以上のように構成された本全波整流回路の動作について、図2に示す波形図を参照しながら説明する。先ず、図2(A)に示すように、交流信号Vinが差動入力回路101に入力すると、トランジスタTr1に流れる電流は図2(B)、トランジスタTr2に流れる電流は図2(C)のように、位相が180度ずれた波形となる。   Next, the operation of the full-wave rectifier circuit configured as described above will be described with reference to the waveform diagram shown in FIG. First, as shown in FIG. 2A, when the AC signal Vin is input to the differential input circuit 101, the current flowing through the transistor Tr1 is as shown in FIG. 2B, and the current flowing through the transistor Tr2 is as shown in FIG. In addition, the waveform is 180 degrees out of phase.

いま、交流信号Vin、即ちトランジスタTr1の入力電圧が上がった場合、抵抗R1に流れる差動電流をiとおくと、トランジスタTr1に流れる電流(I0-i)は減少し、トランジスタTr2に流れる電流(I0+i)は増大する。   Now, when the AC signal Vin, that is, the input voltage of the transistor Tr1, rises, if the differential current flowing through the resistor R1 is set to i, the current (I0-i) flowing through the transistor Tr1 decreases and the current flowing through the transistor Tr2 ( I0 + i) increases.

トランジスタTr1に流れる電流(I0-i)とトランジスタTr2に流れる電流(I0+i)は、電流減算回路102へカレントミラーされ減算処理が行われる。その結果、トランジスタTr11に流れる電流をi(Tr11)、トランジスタTr16に流れる電流をi(Tr16)とすると、
i(Tr11)=2i
i(Tr16)=−2i
となる。しかし、トランジスタは一方向にしか電流を流さないため、i(Tr16)=0となる。i(Tr11),i(Tr16)の波形は図2(D),図2(E)に示す。
The current (I0-i) flowing through the transistor Tr1 and the current (I0 + i) flowing through the transistor Tr2 are current mirrored to the current subtracting circuit 102 and subjected to subtraction processing. As a result, if the current flowing through the transistor Tr11 is i (Tr11) and the current flowing through the transistor Tr16 is i (Tr16),
i (Tr11) = 2i
i (Tr16) =-2i
It becomes. However, since the transistor flows current only in one direction, i (Tr16) = 0. The waveforms of i (Tr11) and i (Tr16) are shown in FIGS. 2 (D) and 2 (E).

次に、交流信号Vin、即ちトランジスタTr1の入力電圧が下がった場合、抵抗R1に流れる差動電流I1の向きは図1と逆になるので、トランジスタTr1に流れる電流(I0-i)は増大し、トランジスタTr2に流れる電流(I0+i)は減少する。この場合は、上述の説明における(I0-i)と(I0+i)、i(Tr11)とi(Tr16)を入れ替えて考えればよい。   Next, when the AC signal Vin, that is, the input voltage of the transistor Tr1 is lowered, the direction of the differential current I1 flowing through the resistor R1 is opposite to that in FIG. 1, so that the current (I0-i) flowing through the transistor Tr1 increases. The current (I0 + i) flowing through the transistor Tr2 decreases. In this case, (I0-i) and (I0 + i) and i (Tr11) and i (Tr16) in the above description may be interchanged.

最後に、i(Tr11),i(Tr16)を電流加算回路103のトランジスタTr18,Tr17にカレントミラーしてトランジスタTr19で加算することにより、全波整流された電流が得られる。このトランジスタTr19を流れる電流はトランジスタTr20へカレントミラーされ、電流―電圧変換用抵抗に流すことにより出力電圧として取り出すことができる。   Finally, i (Tr11) and i (Tr16) are current mirrored to the transistors Tr18 and Tr17 of the current adder circuit 103 and added by the transistor Tr19 to obtain a full-wave rectified current. The current flowing through the transistor Tr19 is current-mirrored to the transistor Tr20 and can be taken out as an output voltage by flowing it through a current-voltage conversion resistor.

この場合、前述のように抵抗R1と電流―電圧変換用抵抗の相対精度を一致させていれば、抵抗の製造バラツキや温度変動による絶対値のずれを抑制することができる。即ち、抵抗R1の製造バラツキや温度変動と、電流―電圧変換用抵抗の製造バラツキや温度変動は一致する。そして、これらの変動は電流と電圧に対して逆方向に作用するため、図4(F)に示したように抵抗R1によってトランジスタTr20を流れる電流が変動しても、電流―電圧変換用抵抗によって相殺されるので、図2(F)に示すように出力電圧の大きさを常に一定に保つことが可能となる。   In this case, as described above, if the relative accuracy of the resistor R1 and the current-voltage conversion resistor are matched, it is possible to suppress deviations in absolute values due to manufacturing variations of the resistors and temperature fluctuations. That is, the manufacturing variation and temperature variation of the resistor R1 coincide with the manufacturing variation and temperature variation of the current-voltage conversion resistor. Since these fluctuations act in opposite directions with respect to the current and voltage, even if the current flowing through the transistor Tr20 is fluctuated by the resistor R1, as shown in FIG. Since they are canceled out, the magnitude of the output voltage can always be kept constant as shown in FIG.

101,201 差動入力回路
102,202 電流減算回路
103,203 電流加算回路
Vin 入力信号
I0 定電流源
Tr1〜Tr32 トランジスタ
R1 抵抗
101, 201 Differential input circuit
102, 202 Current subtraction circuit
103, 203 Current addition circuit
Vin input signal
I0 constant current source
Tr1-Tr32 transistor
R1 resistance

Claims (2)

全波整流回路であって、
交流信号を入力して差動電流を定電流に重畳出力する差動入力回路と、
前記差動入力回路からカレントミラーされる電流から前記定電流を減算して差動電流を
出力する電流減算回路と、
前記電流減算回路からカレントミラーされる位相が180度異なる2つの前記差動電流
を加算することにより全波整流した出力電流を得る電流加算回路とで構成され、
前記差動入力回路における差動入力トランジスタのドレインの間に、流れる電流の値が
その値で定まるような抵抗を挿入し、
前記抵抗の値は、該全波整流回路の出力電圧を得るために前記出力電流と乗算される抵
抗の値との間で、製造プロセス上所定の寸法比率を一致させたことを特徴とする全波整流
回路。
A full wave rectifier circuit,
A differential input circuit that inputs an AC signal and outputs a differential current superimposed on a constant current; and
A current subtracting circuit for subtracting the constant current from a current mirrored from the differential input circuit to output a differential current;
A current adding circuit that obtains a full-wave rectified output current by adding two differential currents that are 180 degrees different in phase from the current subtracting circuit;
Between the drains of the differential input transistors in the differential input circuit, insert a resistor such that the value of the flowing current is determined by the value,
The value of the resistor is obtained by matching a predetermined dimensional ratio in the manufacturing process between the output current and the value of the resistor multiplied to obtain the output voltage of the full-wave rectifier circuit. Wave rectifier circuit.
前記差動入力回路において前記交流信号を入力する2つのトランジスタのドレインとゲート間電圧が等しいことを特徴とする請求項1に記載の全波整流回路。   2. The full-wave rectifier circuit according to claim 1, wherein a voltage between a drain and a gate of two transistors that input the AC signal is equal in the differential input circuit.
JP2009247050A 2009-10-27 2009-10-27 Full-wave rectifier circuit Active JP4877564B2 (en)

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Application Number Priority Date Filing Date Title
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JP4877564B2 true JP4877564B2 (en) 2012-02-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102291021B (en) * 2011-07-18 2013-12-25 西安电子科技大学 PFM (Pulse Frequency Modulation) constant-current control circuit applied in AC-DC (alternating current-to-direct current) converters
JP6450212B2 (en) 2015-02-10 2019-01-09 ルネサスエレクトロニクス株式会社 Current output circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226702A (en) * 1986-03-28 1987-10-05 Toshiba Corp Detection circuit for automatic gain control circuit
JPH08289554A (en) * 1995-04-14 1996-11-01 Asahi Kasei Micro Syst Kk Full-wave rectifying circuit
JPH09232886A (en) * 1996-02-21 1997-09-05 Sony Corp Differential amplifier
JP2002314342A (en) * 2001-04-11 2002-10-25 Seiko Instruments Inc Detector circuit

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