JP4866509B2 - Timing generator and test device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing generator that generates timing. In particular, it relates to a timing generator capable of high-speed operation.
[0002]
[Prior art]
FIG. 10 shows a configuration of a conventional timing generator 200. The timing generator 200 includes a coarse delay circuit 202, a variable delay circuit 204, a minute variable delay circuit 206, a delay control unit 220a, and a delay control unit 220b. A coarse wave signal is input to the coarse delay circuit 202, and is output to the variable delay circuit 204 with a predetermined time delay based on the timing to be generated by the timing generator 200. The variable delay circuit 204 delays the rectangular wave signal by a delay amount smaller than the delay resolution of the coarse delay circuit 202 and outputs the delayed signal to the minute variable delay circuit 206. The minute variable delay circuit 206 delays the rectangular wave signal by a delay amount smaller than the delay resolution of the variable delay circuit 204, and outputs it as a timing delayed by a desired time.
[0003]
The delay control unit 220a controls the delay amount in the variable delay circuit 204. The delay control unit 220a includes a counter 208, a register 212, a selector 214, a selector control unit 218, and a holding circuit 216. The delay control unit 220a is provided with delay setting data for the variable delay circuit 204 to delay the rectangular wave signal based on the timing that the timing generator 200 should generate. The delay setting data is stored in the registers 212a to 212d. The counter 208 counts the number of times the waveform rises or falls in the rectangular wave signal, and sequentially updates the delay setting data stored in the register 212.
[0004]
The delay setting data stored in the register 212 is input to the selector 214. The selector control unit 218 counts the number of rises of the waveform of the rectangular wave signal output from the coarse delay circuit 202 and selects the delay setting data input to the selector 214 based on the number of counts. The selected delay setting data is input to the holding circuit 216. The holding circuit 216 controls the delay amount in the variable delay circuit 204 at a timing based on the falling or rising of the waveform of the rectangular wave signal output from the coarse delay circuit 202. The delay control unit 220b has the same function and configuration as the delay control unit 220a, and controls the delay amount in the minute variable delay circuit 206.
[0005]
[Problems to be solved by the invention]
With the recent increase in the speed of electronic devices, it is desired that the timing generators in the test apparatus for testing the electronic devices also operate faster. However, in the timing generator described in FIG. 9, since the delay control unit 220a and the delay control unit 220b have a selector, a counter, and the like, it is difficult to operate at high speed due to the propagation delay time of these elements. there were. In addition, since a large number of elements are required, a large-scale circuit is required. In the conventional timing generator, one rectangular wave is delayed by an analog delay circuit with respect to one timing to be generated. For this reason, the time interval of the rectangular wave passing through the analog delay circuit varies depending on the delay setting amount. Therefore, the heat generation in the analog delay circuit varies, which causes deterioration of accuracy such as delay error. In addition, in the conventional test apparatus, in order to compensate for the accuracy deterioration, it is necessary to provide a heat generation amount compensation circuit for compensating the heat generation amount in the analog delay circuit, which causes an increase in circuit scale.
[0006]
Accordingly, an object of the present invention is to provide a timing generator and a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, in the first embodiment of the present invention, a timing generator for generating timing, which receives a rectangular wave signal and outputs a first delayed signal obtained by delaying the rectangular wave signal. Controls the delay amount in the first variable delay circuit unit, the second variable delay circuit unit that receives the first delay signal, outputs the second delay signal obtained by delaying the first delay signal, and the second variable delay circuit unit A second delay amount control unit that receives second delay amount setting data for controlling a delay amount in the second variable delay circuit unit, and is based on a change point of the rectangular wave signal. The first holding circuit that holds and outputs the second delay amount setting data until one timing, and the second delay amount setting data that is output from the first holding circuit are received, and the change point of the rectangular wave signal or the first delay signal is received. Second delay until second timing based Holding the quantity setting data and provides timing generator and having a second holding circuit for controlling the delay amount in the second variable delay circuit section.
[0008]
The first aspect of the present invention further includes a first delay amount control unit that controls a delay amount in the first variable delay circuit unit, and the first delay amount control unit controls the delay amount in the first variable delay circuit unit. The first delay amount setting data is provided, and the first delay amount setting data is held until the first timing based on the change point of the rectangular wave signal to control the delay amount in the first variable delay circuit unit. You may have a circuit. The first holding circuit, the second holding circuit, and the third holding circuit may be dynamic latches. The rectangular wave signal is a clock signal having a predetermined cycle, and further includes a half cycle delay unit that delays the rectangular wave signal by approximately half a cycle of the rectangular wave signal and inputs the delayed signal to the first variable delay circuit unit. You may be prepared.
[0009]
In addition, an input selection unit that selects either the rectangular wave signal or the rectangular wave signal delayed by the half-cycle delay unit based on the timing to be generated by the timing generator, and inputs the selection to the first variable delay circuit unit. Further, it may be provided. Further, the delay amount in the first variable delay circuit unit may correspond to approximately a half cycle of the rectangular wave signal. Further, the delay amount in the second variable delay circuit unit may correspond to the delay amount resolution in the first variable delay circuit unit. In addition, a timing output unit that selects and outputs a desired rectangular wave component from the rectangular wave components included in the second delay signal output from the second variable delay circuit unit may be further provided.
[0010]
The timing output unit receives selection data for selecting a desired rectangular wave from among the rectangular wave components included in the second delay signal output from the second variable delay circuit unit, and is based on a change point of the rectangular wave signal. The fourth holding circuit that holds and outputs the selection data until the first timing and the selection data output by the fourth holding circuit are received and selected until the second timing based on the change point of the rectangular wave signal or the first delay signal The fifth holding circuit that holds and outputs data, and the selection data output from the fifth holding circuit are received, and the selection data is held until the third timing based on the change point of the first delay signal or the second delay signal. A sixth holding circuit for outputting, and a selection unit for selecting and outputting a desired rectangular wave component out of the rectangular wave components included in the second delay signal based on the selection data output by the sixth holding circuit. Do it . The fourth holding circuit, the fifth holding circuit, and the sixth holding circuit may be dynamic latches.
[0011]
The first holding circuit, the third holding circuit, and the fourth holding circuit hold the input data until the first timing based on the change point of the rectangular wave signal, and the second holding circuit and the fifth holding circuit Holds the input data until the second timing based on the change point of the first delay signal, and the sixth holding circuit receives the input data until the third timing based on the change point of the second delay signal. You may hold. Further, it is preferable that the first holding circuit, the third holding circuit, and the fourth holding circuit hold their outputs until the timing based on the falling edge of the waveform of the rectangular wave signal. Further, it is preferable that the second holding circuit and the fifth holding circuit hold the respective outputs until the timing based on the falling edge of the waveform of the first delay signal. The sixth holding circuit preferably holds the output until the timing based on the falling edge of the waveform of the second delay signal.
[0012]
The half-cycle delay unit may include means for inverting the waveform of the rectangular wave signal. The half-cycle delay unit receives the rectangular wave signal and outputs a third delayed signal that is a rectangular wave signal obtained by delaying the rectangular wave signal, and the third variable delay circuit unit outputs the third delayed signal. A fourth variable delay circuit unit that receives the third delay signal and inputs a fourth delay signal, which is a rectangular wave signal obtained by delaying the third delay signal, to the first variable delay circuit unit; The maximum delay amount in the circuit unit and the fourth variable delay circuit unit may be substantially equal to a quarter cycle of the rectangular wave signal.
[0013]
The first holding circuit, the third holding circuit, and the fourth holding circuit hold the input data until the first timing based on the change point of the rectangular wave signal output from the third variable delay circuit, The second holding circuit and the fifth holding circuit hold the input data until the second timing based on the change point of the rectangular wave signal output from the fourth variable delay circuit, and the sixth holding circuit The input data may be held until the third timing based on the change point of the delay signal.
[0014]
The timing generator generates a plurality of timings based on rectangular wave components in a plurality of regions obtained by dividing the rectangular wave signal in a predetermined time range. That is, the timing generator cuts out a rectangular wave signal for each timing generation cycle. In the timing generator, the input selection unit sequentially selects one of the rectangular wave component of the rectangular wave signal and the rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit for each timing generation cycle. 1 When the rectangular wave component of the rectangular wave signal and the rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit are close to each other when input to the variable delay circuit unit, the rectangular wave of the adjacent rectangular wave signal A blocking means for blocking the rectangular wave component of the rectangular wave signal delayed by the component or the half-cycle delay unit and inputting the rectangular wave component to the first variable delay circuit unit may be further provided.
[0015]
In addition, fourth delay amount setting data for controlling the delay amount in the fourth variable delay circuit unit is provided, and the fourth delay until the fourth timing based on the change point of the rectangular wave signal input to the third variable delay circuit unit. A seventh holding circuit that holds the amount setting data and controls the delay amount in the fourth variable delay circuit unit; and the first delay amount setting data is given; the first delay amount setting data is held until the fourth timing; An eighth holding circuit that outputs to the third holding circuit; a ninth holding circuit that receives the second delay amount setting data, holds the second delay amount setting data until the fourth timing, and outputs the second delay amount setting data to the first holding circuit; The tenth holding circuit that holds selection data until the fourth timing is input and outputs the selection data to the fourth holding circuit may be further provided.
[0016]
The seventh holding circuit, the eighth holding circuit, the ninth holding circuit, and the tenth holding circuit may be dynamic latches. The seventh holding circuit, the eighth holding circuit, the ninth holding circuit, and the tenth holding circuit hold the respective outputs until the timing based on the rising edge of the waveform of the rectangular wave signal input to the third variable delay circuit. You can do it. Further, the first holding circuit, the third holding circuit, and the fourth holding circuit may hold their outputs until the timing based on the rising edge of the waveform of the third delay signal.
[0017]
The second holding circuit and the fifth holding circuit may hold the respective outputs until the timing based on the rising edge of the waveform of the fourth delay signal. The sixth holding circuit may hold the output until the timing based on the rising edge of the waveform of the first delay signal.
[0018]
In addition, initialization means for setting the output states of the first to tenth holding circuits to a predetermined state may be further provided. The initialization means includes a clear data input means for giving predetermined data to each of the first to tenth holding circuits, and a clear signal input means for giving a data holding switching timing in each of the first to tenth holding circuits. The clear signal input means may give the data holding switching timing to each of the first to tenth holding circuits via the first to fourth variable delay circuit sections.
[0019]
The clear signal input means generates a clearing rectangular wave for giving a data holding switching timing to the first to tenth holding circuits, and the first to fourth variable delay circuit units are used for the clearing rectangular wave. The reception and clear signal input means may include means for setting the delay amount of the clear rectangular wave to substantially zero in the first to fourth variable delay circuit sections. The clear data input means may receive the clear rectangular wave generated by the clear signal input means and give predetermined data to the first to tenth holding circuits at a timing based on the clear rectangular wave. Further, the clear signal input means has the first to tenth holding circuits at a timing based on the clearing rectangular wave delayed by a time longer than the propagation delay time of the clearing rectangular wave in the first to fourth variable delay circuit units. Predetermined data may be given to.
[0020]
According to the second aspect of the present invention, there is provided a test apparatus for testing an electronic device, a pattern generating unit for generating a test pattern for testing the electronic device, and a shaping pattern that receives the test pattern and shapes the test pattern. A waveform shaping unit that inputs a signal to an electronic device, a timing generator that generates timing, an output signal that the electronic device outputs based on a test pattern, an output signal sampling circuit that samples at a timing generated by the timing generator, A determination unit configured to determine whether the electronic device is good or bad based on a sampling result in the output signal sampling circuit. The timing generator receives a rectangular wave and outputs a first delay signal obtained by delaying the rectangular wave signal. 1 variable delay circuit section and first delay signal are input and the first delay signal is delayed A second variable delay circuit unit that outputs a two-delay signal, and a second delay amount control unit that controls a delay amount in the second variable delay circuit unit. The second delay amount control unit includes a second variable delay circuit. A first holding circuit that receives second delay amount setting data for controlling a delay amount in the unit and holds and outputs the second delay amount setting data until a first timing based on a change point of the rectangular wave signal; The second variable delay circuit unit receives the second delay amount setting data output from the holding circuit and holds the second delay amount setting data until the second timing based on the change point of the rectangular wave signal or the first delay signal. And a second holding circuit for controlling the delay amount in the test apparatus.
[0021]
It should be noted that the above outline of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.
[0023]
FIG. 1 shows an example of the configuration of a test apparatus 100 according to the present invention. The test apparatus 100 includes a pattern generation unit 20 that generates a test signal, a waveform shaping unit 22 that shapes the test signal, a signal input / output unit 24 that exchanges signals with the electronic device 10, a timing generation unit 30, and pass / fail of the electronic device 10. A determination unit 26 for determining whether or not
[0024]
The pattern generation unit 20 generates a test signal for testing the electronic device 10 and inputs the test signal to the electronic device 10 via the waveform shaping unit 22 and the signal input / output unit 24. In addition, when the test signal is input to the electronic device 10, the pattern generation unit 20 generates an expected value signal to be output by the electronic device 10. The waveform shaping unit 22 shapes the test signal generated by the pattern generation unit 20. For example, the waveform shaping unit 22 inputs the test signal generated by the pattern generation unit 20 to the signal input / output unit 24 with a desired time delay. The waveform shaping unit 22 may include a timing generator that generates timing for delaying the test signal generated by the pattern generation unit 20 for a desired time. The signal input / output unit 24 is electrically connected to the electronic device 10 and inputs the test signal received from the waveform shaping unit 22 to the electronic device 10. Further, the signal input / output unit 24 receives an output signal output from the electronic device 10 based on the test signal and supplies the output signal to the determination unit 26.
[0025]
The timing generator 30 generates a desired timing and supplies it to the determination unit 26. The timing generator 30 receives a rectangular wave signal having a predetermined period and generates a desired timing based on the rectangular wave signal. The timing generator 30 may receive a reference clock for controlling the operation of the test apparatus 100 as the rectangular wave signal and generate a desired timing. The timing generator 30 supplies the timing according to the test signal generated by the pattern generator 20 to the determination unit 26 as, for example, a rectangular wave. The determination unit 26 determines the quality of the electronic device 10 based on the output signal output from the electronic device 10. For example, the determination unit 26 compares the value of the output signal output from the electronic device 10 at the timing generated by the timing generator 30 with the expected value signal generated by the pattern generation unit 20 to determine whether the electronic device 10 is good or bad. judge. The timing generator included in the waveform shaping unit 22 may have the same or similar function and configuration as the timing generator 30 described above.
[0026]
FIG. 2 is a block diagram showing an example of the configuration of the timing generator 30 according to the present invention. The timing generator 30 includes a first variable delay circuit unit 42, a second variable delay circuit unit 44, a first delay amount control unit 50, a second delay amount control unit 60, a timing output unit 70, and a half cycle. A delay unit 40 and an input selection unit 48 are provided. The timing generator 30 is given zero delay data, half-cycle delay data, first delay amount setting data, second delay amount setting data, and selection data based on the timing to be generated. The timing generator 30 is given a rectangular wave signal having a predetermined period.
[0027]
The half-cycle delay data is data for performing control to invert the rectangular wave signal given to the timing generator 30 and input it to the first variable delay circuit unit 42. The zero delay data is data for performing control to input the rectangular wave signal given to the timing generator 30 to the first variable delay circuit unit 42 without being inverted. A signal obtained by inverting the rectangular wave signal is generated in the half-cycle delay unit 40. The half cycle delay unit 40 can generate a signal delayed by approximately a half cycle of the rectangular wave signal by inverting the rectangular wave signal. As an example, the half-cycle delay unit 40 includes a register 32b, a register 34b, and a logic element 38. The half-cycle delay data may be a digital signal represented by a combination of values of 1, 0, for example. The half cycle delay data is determined based on the timing that the timing generator 30 should generate. The half-cycle delay data is input to the logic element 38 via the register 32b and the register 34b. The logic element 38 receives a signal obtained by inverting the rectangular wave signal. The logic element 38 inputs the logical product of the input half-cycle delay data and a signal obtained by inverting the rectangular wave signal to the input selection unit 48. Similarly, the zero delay data may be a digital signal, and is determined based on the timing that the timing generator 30 should generate. The zero delay data is input to the logic element 36 through the register 32a and the register 34a. The logic element 36 supplies the logical product of the input zero delay data and the rectangular wave signal to the input selection unit 48.
[0028]
The input selection unit 48 selects either a rectangular wave signal or a rectangular wave signal delayed by a half cycle by the half cycle delay unit 40 based on the timing to be generated by the timing generator 30, and the first variable delay circuit To the unit 42. The zero delay data and the half cycle delay data are determined based on the timing that the timing generator 30 should generate. In the case where the timing generator 30 generates a desired timing, when the rectangular wave signal needs to be delayed by approximately a half cycle, 1 is set to the half cycle delay data and 0 is set to the zero delay data. In addition, when the timing generator 30 generates a desired timing and the rectangular wave signal does not need to be delayed by approximately half a cycle, 1 is set to zero delay data and 0 is set to half cycle delay data. Is done.
[0029]
Normally, zero delay data is obtained by inverting half-cycle delay data. For example, when the half-cycle delay data is 1, 0, 1, 0, 1, 0 is given to the zero delay data. In this example, the input selection unit 48 outputs the logical sum of the rectangular wave signal and the inverted rectangular wave signal to the first variable delay circuit unit 42. As described above, the maximum delay amount in the first variable delay circuit unit 42 and the second variable delay circuit unit 44 can be reduced by generating a delay corresponding to a half cycle of the rectangular wave signal by the digital circuit. It is possible to generate a delayed signal with high accuracy. Further, in this example, the logic element 36 and the logic element 38 are AND circuits and the logic element 48 is an OR circuit. However, in other examples, the logic elements 36 and 38 may be configured with other logic elements. It is clear that the same function as the timing generator 30 in this example can be realized.
[0030]
The first delay amount control unit 50 controls the delay amount in the first variable delay circuit unit 42. The first delay amount control unit 50 is provided with first delay amount setting data for controlling the delay amount in the first variable delay circuit unit 42. The first delay amount control unit 50 includes a third holding circuit 56 that holds the first delay amount setting data until a desired timing. The third holding circuit 56 receives the first delay amount setting data via the register 32c and the register 34c. The first delay amount setting data is determined based on the timing that the timing generator 30 should generate.
[0031]
The first variable delay circuit unit 42 is supplied with a rectangular wave signal and outputs a first delayed signal obtained by delaying the rectangular wave signal. The first variable delay circuit unit 42 may be an analog delay circuit, for example. In this example, the delay amount in the first variable delay circuit unit 42 is approximately half or less of the rectangular wave signal. For example, when the period of the rectangular wave signal is 4 ns (nanoseconds), the first variable delay circuit unit 42 sets the rectangular wave by a delay amount of 1.5 ns, 1.0 ns, 0.5 ns, or 0 ns. A first delayed signal obtained by delaying the signal is output.
[0032]
The second delay amount control unit 60 controls the delay amount in the second variable delay circuit unit 44. The second delay amount control unit 60 is provided with second delay amount setting data for controlling the delay amount in the second variable delay circuit unit 44. The second delay amount setting data is determined based on the timing that the timing generator 30 should generate. The second delay amount control unit 60 includes a first holding circuit 52 that holds the second delay amount setting data until a desired timing, and a second holding circuit 54 that is cascade-connected to the first holding circuit 52. The first holding circuit 52 receives the second delay amount setting data via the register 32d and the register 34d, and holds the second delay amount setting data until the timing at which the third holding circuit 56 holds the output. And supplied to the second holding circuit 54. The second holding circuit 54 holds the second delay amount setting data supplied from the first holding circuit 52 until a desired timing, and controls the delay amount in the second variable delay circuit unit 44.
[0033]
The second variable delay circuit unit 54 receives the first delay signal and outputs a second delay signal obtained by delaying the first delay signal. The second variable delay circuit unit 44 may be an analog delay circuit, for example. In this example, the delay amount in the second variable delay circuit unit 42 is less than or equal to the delay resolution in the first variable delay circuit unit 42. For example, when the first variable delay circuit unit 42 delays the rectangular wave signal by a delay amount of 1.5 ns, 1.0 ns, 0.5 ns, or 0 ns, the second variable delay circuit unit 44 is 0 A second delay signal obtained by delaying the first delay signal by a minute delay amount of .5 ns or less is output.
[0034]
The timing output unit 70 selects and outputs a desired rectangular wave component from among the rectangular wave components included in the second delay signal output from the second variable delay circuit unit 44. By selecting and outputting a desired rectangular wave component from among the rectangular wave components included in the second delay signal, a delay that is an integral multiple of the period of the rectangular wave signal can be generated with respect to a predetermined timing. . The timing output unit 70 includes a fourth holding circuit 58, a fifth holding circuit 62, a sixth holding circuit 64, and a selection unit 46.
[0035]
The fourth holding circuit 58 receives selection data for selecting a desired rectangular wave from among the rectangular wave components included in the second delay signal output from the second variable delay circuit unit via the register 32e and the register 34e. receive. The selection data is determined based on the timing that the timing generator 30 should generate. The fourth holding circuit 58 holds and outputs the received selection data until a desired timing. That is, the fourth holding circuit 58 holds the output until the timing at which the first holding circuit 52 and the third holding circuit 56 hold the output.
[0036]
The fifth holding circuit 62 receives the selection data output from the fourth holding circuit 58 and holds and outputs the selection data until a desired timing. The fifth holding circuit 62 holds the output until the same timing as the timing at which the second holding circuit 54 holds the output. The sixth holding circuit 64 receives the selection data output from the fifth holding circuit 62, holds the selection data until a desired timing, and supplies the selection data to the selection unit 46.
[0037]
The selection unit 46 selects and outputs a desired rectangular wave component among the rectangular wave components included in the second delay signal based on the selection data output from the sixth holding circuit 64. The rectangular wave component is intermittently passed through the variable delay circuit unit, and the selection unit 46 selects a desired rectangular wave component, thereby reducing variations in heat generation in the first variable delay circuit 42 and the second variable delay circuit 44. Therefore, the timing generator 30 can be operated stably. Further, by intermittently passing the rectangular wave component through the variable delay circuit unit, the data held in the holding circuit can be refreshed.
[0038]
The selection data is a digital signal represented by 1 and 0, for example, and is determined based on the timing that the timing generator 30 should generate. The selection unit 46 may be a logic circuit that outputs a logical product, for example. The selection unit 46 receives the second delay signal and the selection data, and outputs a logical product of the second delay signal and the selection data, so that a desired rectangular wave component included in the second delay signal is output. Select the wave component. The first holding circuit 52, the second holding circuit 54, the third holding circuit 56, the fourth holding circuit 58, the fifth holding circuit 62, and the sixth holding circuit 64 are preferably dynamic latches. By using a dynamic latch as the holding circuit, the timing generator 30 can be operated at high speed. In addition, the circuit scale can be reduced as compared with the conventional timing generator. Each register and each holding circuit preferably include a plurality of registers or holding circuits arranged in parallel, and transmit data to be transmitted in parallel. In this case, each register and each holding circuit preferably have a decoder that decodes a signal transmitted in parallel.
[0039]
Since the timing generator 30 in this example does not include an element such as a selector, it can operate at a higher speed than the conventional timing generator. Hereinafter, a specific operation of the timing generator 30 will be described with reference to a timing chart.
[0040]
FIG. 3 is a timing chart showing an example of the operation of the timing generator 30. In this example, the period of the rectangular wave signal is assumed to be 4 ns. In FIG. 3, the horizontal axis indicates time, and one scale indicates 1 ns. The test apparatus 100 normally performs a plurality of test cycles continuously. In this example, the test apparatus 100 performs three test cycles continuously, and sets each test cycle as TS1, TS2, and TS3. Taking the length of each test cycle as an example, a case where one timing is generated in each test cycle with TS1 = 8 ns, TS2 = 10 ns, and TS3 = 8 ns will be described. As an example, a case will be described in which the timing to be generated in each test cycle is generated at the timing of TS1: 1.5 ns, TS2: 6.1 ns, and TS3: 2.5 ns from the start of each test cycle.
[0041]
In the zero delay data, the half cycle delay data, and the selection data, digital signals whose values are switched in synchronization with the cycle of the rectangular wave signal are set. In the selection data, data based on the timing to be generated by the timing generator 30 in each test cycle is set. When a delay of 4 ns is required to generate timing in each test cycle, 0 and 1 are set in the corresponding selection data, and when a delay of 4 ns is not required, the corresponding selection data is set. 1, 0 is set. In this example, the timings to be generated in each test cycle are TS1: 1.5 ns, TS2: 6.1 ns, and TS3: 2.5 ns. Therefore, as shown in FIG. 0, 0, 1, 0, 1 are set. In this example, since the timing to be generated in TS3 is 2.5 ns after the start of TS3, 1, 0 should be set in the selection data, but the length of the previous test cycle is set to the rectangular wave signal. When the sum of the remainder divided by the period and the remainder obtained by dividing the timing to be generated in the test cycle by the period of the rectangular wave signal is larger than the period of the rectangular wave signal, the selector 46 selects a desired rectangular wave. In order to select a component, control (carry control, which will be described later with reference to FIG. 4) for shifting the output of 1 of selection data of the corresponding test cycle by one clock is required.
[0042]
Data based on the timing to be generated by the timing generator 30 is set in the zero delay data and the half cycle delay data. When a delay of 2 ns is necessary in the corresponding test cycle, 0 and 0 are set for the zero delay data, and 1 and 1 are set for the half cycle delay data. Further, when a delay of 2 ns is not necessary in the corresponding test cycle, 1, 1 is set for the zero delay data, and 0, 0 is set for the half cycle delay data. That is, the sum of the remainder obtained by dividing the length of the test cycle up to the previous test cycle by the period of the rectangular wave signal and the remainder obtained by dividing the timing to be generated in the test cycle by the period of the rectangular wave signal is 1 or 1 is set in the half-cycle delay data.
[0043]
Further, in the first delay amount setting data and the second delay amount setting data, a delay amount of 2 ns or less is set in the delay amount based on the timing to be generated in each test cycle. In other words, 1.5 ns, 0 ns, and 0.5 ns are set in the first delay amount setting data in each test cycle, and 0.0 ns, 0 ns are set in the second delay amount setting data in each test cycle. .1 ns and 0.0 ns are set.
[0044]
The set zero delay data is input to the logic element 36 via the register 32a and the register 34a. Since the register 32a is driven according to the rectangular wave signal and the register 34a is driven according to the inverted signal of the rectangular wave signal, the output of the register 34a includes 1.5 periods of the rectangular wave signal and the register 32a. And zero delay data delayed by the propagation delay time in the register 34b. Similarly, the output of the register 34b is half-cycle delay data delayed by two periods of the rectangular wave signal and the propagation delay time. The logic element 36 inputs the logical product of the output of the register 34 a and the rectangular wave signal to the input selection unit 48. The logic element 38 inputs the logical product of the output of the register 34 b and the inverted signal of the rectangular wave signal to the input selection unit 48. As shown in FIG. 3, the input selection unit 48 converts the positive logic of the rectangular wave signal when the output of the register 34a is 1 and the negative logic of the rectangular wave signal when the output of the register 34b is 1 into the positive logic. A signal obtained by synthesizing the inverted signal is output as a rectangular wave signal to the first variable delay circuit.
[0045]
The first delay amount setting data is given to the register 34c via the register 32c. Since the register 32c is driven according to the rectangular wave signal and the register 34c is driven according to the inverted signal of the rectangular wave signal, the output of the register 34c includes 1.5 periods of the rectangular wave signal and each register. The first delay amount setting data delayed by the propagation delay time is output. Similarly, as shown in FIG. 3, the register 34d and the register 34e output the second delay amount setting data and the selection data at a timing substantially synchronized with the register 34c.
[0046]
As shown in FIG. 3, the third holding circuit 56 receives the output of the register 34c, holds the data until the falling edge of the rectangular wave signal output from the input selection unit 48, and is delayed by the propagation delay time in the holding circuit. Data is output and the amount of delay in the first variable delay circuit is controlled. Similarly, the first holding circuit 52 and the fourth holding circuit 58 receive the output of the register 34d and the output of the register 34e, hold the data until the falling edge of the rectangular wave signal output from the input selection unit 48, and in the holding circuit Data is output delayed by the propagation delay time.
[0047]
The rectangular wave signal output from the input selection unit 48 is input to the first variable delay circuit unit 42. The input rectangular wave signal is output after being delayed by the delay amount by the data output from the third holding circuit 56 and the propagation delay time in the first variable delay circuit unit 42. The second holding circuit 54 receives the data output from the first holding circuit 52, holds the data until the falling edge of the first delay signal output from the first variable delay circuit unit 42, and only the propagation delay time in the holding circuit Data is output with a delay, and the delay amount in the second variable delay circuit is controlled. Similarly, the fifth holding circuit 62 delays the output of the fourth holding circuit 58 by the propagation delay time and outputs it.
[0048]
The first delay signal output from the first variable delay circuit unit 42 is input to the second variable delay circuit unit 44. The second variable delay circuit unit 44 delays the received first delay signal by the amount of delay due to the data output from the second holding circuit 54 and the propagation delay time in the second variable delay circuit unit 44, and outputs it. To do. The sixth holding circuit 64 receives the data output from the fifth holding circuit 62, holds the data until the falling edge of the second delay signal output from the second variable delay circuit unit 44, and only the propagation delay time in the holding circuit Output data with a delay. The selection unit 46 selects and outputs the rectangular wave component of the second delay signal output from the second variable delay circuit unit 44 while the sixth holding circuit 64 outputs 1.
[0049]
With the operation described above, the timing generator 30 can generate a desired timing. In addition, the timing generator 30 measures the propagation delay time of each element in advance, and sets the delay amount setting data obtained by correcting the measured propagation delay time in the first delay amount setting data and the second delay amount setting data. May further be provided. The timing generator 30 may further include a storage unit that measures the propagation delay time of each element in advance and stores the measured propagation delay time.
[0050]
FIG. 4 illustrates the carry operation described in connection with FIG. FIG. 4A shows an example of the structure of the blocking means for carrying control in relation to FIG. FIG. 4B shows an example of the timing to be generated by the test cycle and timing generator 30 described with reference to FIG. FIG. 4C shows an example of the output of the input selection unit 48 when carry control is not performed in the example of the test cycle and timing shown in FIG.
[0051]
The blocking means shown in FIG. 4A has two registers and two logical product circuits. CARRY data is set in one register, and half-cycle delay data (2 ns data) when carry control is not performed as shown in FIG. 4C is set in the other register. The outputs of the two AND circuits are used as the zero delay data and the half cycle delay data described with reference to FIGS. 2 and 3, respectively. In the CARRY data, the sum of the remainder obtained by dividing the length of the test cycle by the period of the rectangular wave signal and the remainder obtained by dividing the timing to be generated in the test cycle by the period of the rectangular wave signal is the period of the rectangular wave signal. If it is larger, 1 is set, and the sum of the remainder of dividing the length of the test cycle by the period of the rectangular wave signal and the remainder of dividing the timing to be generated in the test cycle by the period of the rectangular wave signal is rectangular. 0 is set when it is less than or equal to the period of the wave signal. A register in which CARRY data is set supplies inverted data of CARRY data to two AND circuits, and the other register supplies 2 ns data to an AND circuit whose output is used as half-cycle delay data. The inverted data is supplied to an AND circuit whose output is used as zero delay data.
[0052]
In the example of the test cycle and timing shown in FIG. 4B, the timing to be generated in each test cycle is TS1: 1.5 ns, TS2: 6.1 ns, TS3: 2.5 ns. 1, 1, 0, 0, 0, 0 should be set in the data, and 0, 0, 1, 1, 1, 1 should be set in the half-cycle delay data. If the sum of the remainder obtained by dividing the length by the period of the rectangular wave signal and the remainder obtained by dividing the timing to be generated in the test cycle by the period of the rectangular wave signal is greater than the period of the rectangular wave signal, In some cases, the rectangular wave component in the cycle and the rectangular wave component in the test cycle are close to each other, and the timing generator 30 cannot be operated correctly. Therefore, in the timing generator 30 according to the present invention, in order to block the adjacent rectangular wave components, the remainder of dividing the length of the previous test cycle by the period of the rectangular wave signal and the timing to be generated in the test cycle 0 is set to zero delay data and half cycle delay data (carry control). In this example, as shown in FIG. 3, zero delay data is set to 1,1,0,0,0,1 in order, and half-cycle delay data is set to 0,0,1,1,0,1 in order. Is set. The fifth data in the zero delay data and the half cycle delay data is data set to 0 by carry control.
[0053]
FIG. 4C shows an example of a rectangular wave signal supplied to the first variable delay circuit unit 42 when the timing generator 30 does not carry control. When the timing generator does not carry control, as shown in FIG. 4 (c), 1, 1, 0, 0, 1, 1 are sequentially set to zero delay data, and half cycle delay data are sequentially set. , 0, 0, 1, 1, 0, 0 are set. The data shown in FIG. 4C is output from the registers 34a and 34b in the same manner as described with reference to FIG. The input selection unit 48 outputs a rectangular wave signal as shown in FIG. 4C based on the output of the register 34a and the output of the register 34b. In this case, as shown in FIG. 4C, the rectangular wave component indicated by the dotted line and the rectangular wave component indicated by the solid line may be close to each other, and the timing generator 30 may not operate normally. For this reason, the timing generator 30 in this example performs carry control.
[0054]
In other words, the timing generator 30 in this example generates a plurality of timings based on the rectangular wave components in a plurality of regions obtained by dividing the rectangular wave signal in a predetermined time range, and the input selection unit 48 generates the rectangular wave signal. When the rectangular wave component and the rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit 40 are sequentially selected and input to the first variable delay circuit unit 42, the rectangular wave of the rectangular wave signal When the component and the rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit 40 are close to each other, the rectangular wave component of the adjacent rectangular wave signal or the rectangular wave signal delayed by the half-cycle delay unit 40 A blocking means for blocking the wave component and inputting it to the first variable delay circuit unit may be provided.
[0055]
FIG. 5 shows an example of the configuration of the dynamic latch and the static latch. FIG. 5A shows an example of the configuration of the dynamic latch. The timing generator 30 described with reference to FIGS. 3 to 4 may use a dynamic latch described with reference to FIG. 5 as each holding circuit. As an example, the dynamic latch includes an inverter (78, 82, 86) and a transistor switch 84 having an NMOS transistor and a PMOS transistor. The dynamic latch has a gate (G) terminal and a data (D) terminal. Further, in the timing generator 30 described with reference to FIGS. 3 to 4, a dynamic latch having an NMOS of an inverter 82, an inverter 86, and a transistor switch 84 may be used as each holding circuit. That is, in the timing generator 30 described with reference to FIGS. 3 to 4, the dynamic latch does not have the PMOS of the inverter 78 and the transistor switch 84 in the dynamic latch described with reference to FIG. Good. According to the dynamic latch, the circuit scale can be further reduced.
[0056]
In the dynamic latch, the shortest path for switching and outputting data is a path for opening the NMOS gate of the transistor switch 84 from the gate (G) terminal and outputting the data signal through the inverter 86. In this case, the propagation delay time from when the clock is supplied to the dynamic latch until the data is switched and output is represented by the sum of the propagation delay times of the NMOS and the inverter 86.
[0057]
FIG. 5B shows an example of the configuration of the static latch. The static latch includes an inverter (88, 94, 96, 98), a transistor switch 90, and a transistor switch 92. The static latch has a gate (G) terminal and a data (D) terminal. In the static latch, the shortest path for switching and outputting data is a path through which the NMOS gate of the transistor switch 92 is opened from the gate (G) terminal, and the data signal is output through the inverter 94 and the inverter 96. In this case, the propagation delay time from when the clock is supplied to the static latch until the data is switched and output is represented by the sum of the propagation delay times of the NMOS, the inverter 94, and the inverter 96. As apparent from the above description, the propagation delay time of the circuit is larger in the static latch than in the dynamic latch. In terms of circuit scale, the static latch is larger than the dynamic latch.
[0058]
In the conventional timing generator, as described above, since one rectangular wave is delayed by the analog delay circuit with respect to one timing to be generated, it is difficult to refresh the dynamic latch. It has been difficult to use the latch as a holding circuit. Since the timing generator 30 according to the present invention intermittently passes the rectangular wave component to the variable delay circuit, the rectangular wave component is intermittently input to the holding circuit, and the dynamic latch is used as the holding circuit. Even in such a case, the dynamic latch can be easily refreshed. Therefore, the propagation delay time in the timing generator 30 can be reduced, and high-speed operation is possible. In addition, the circuit scale can be reduced.
[0059]
In addition, in the currently used DRAM, the sum of the gate capacitance component and the wiring capacitance component used for data retention is about 5 to 10 fF (femtofarad). In the dynamic latch described with reference to FIG. 5, the sum of the gate capacitance component used for data retention and the wiring capacitance component is substantially the same as that of the DRAM. In general, the data holding time in the DRAM is about 15 μs (microseconds). In the timing generator 30 described with reference to FIGS. 2 to 5, the refresh clock is supplied to each holding circuit at intervals of 8 ns at maximum. Therefore, the timing generator 30 using the dynamic latch described with reference to FIG. 5 can secure a sufficient margin for data retention.
[0060]
FIG. 6 shows another example of the configuration of the timing generator 30. The timing generator 30 includes a first variable delay circuit unit 42, a second variable delay circuit unit 44, a first delay amount control unit 50, a second delay amount control unit 60, a timing output unit 70, a half cycle delay unit 40, and A blocking means 110 is provided. 6, the same reference numerals as those in FIG. 2 may have the same or similar functions and configurations as those described with reference to FIGS. The timing generator 30 receives CARRY data, first delay amount setting data, second delay amount setting data, third delay amount setting data, fourth delay amount setting data, and selection data based on the timing to be generated. Given. The timing generator 30 is given a rectangular wave signal having a predetermined period.
[0061]
The first variable delay circuit unit 42 and the second variable delay circuit unit 44 have the same functions and configurations as the first variable delay circuit unit 42 and the second variable delay circuit unit 44 described with reference to FIGS. Have. The blocking means 110 has the same configuration and function as the carry control or blocking means described with reference to FIG. The half-cycle delay unit 40 includes a third variable delay circuit unit 74, a fourth variable delay circuit unit 76, and a seventh holding circuit 66. The third delay circuit unit 74 receives the rectangular wave signal and outputs a third delayed signal that is a rectangular wave signal obtained by delaying the rectangular wave signal. The fourth variable delay circuit unit 76 receives the third delay signal that is a rectangular wave signal output from the third variable delay circuit unit 74, and receives the fourth delay signal that is a rectangular wave signal obtained by delaying the third delay signal. This is input to the first variable delay circuit unit 42. The seventh holding circuit 66 receives the fourth delay amount setting data for controlling the delay amount in the fourth variable delay circuit unit 76 via the register 32g and the register 34g, and the fourth delay amount setting data until a desired timing. Is output.
[0062]
In this example, it is preferable that the maximum delay amount in the third variable delay circuit unit 74 and the fourth variable delay circuit unit 76 is substantially equal to a quarter cycle of the rectangular wave signal. In another example, the sum of the maximum delay amounts in the third variable delay circuit unit 74 and the fourth variable delay circuit unit 76 may be substantially equal to a half cycle of the rectangular wave signal. The third variable delay circuit unit 74 and the fourth variable delay circuit unit 76 may be analog delay circuits. The third variable delay circuit unit 74 and the fourth variable delay circuit unit 76 select either the maximum delay amount or the zero delay amount, respectively, and delay the rectangular wave signal. Further, when the input rectangular wave signal is delayed by the maximum delay amount in the third variable delay circuit unit 74, the input rectangular wave signal is also the maximum in the fourth variable delay circuit unit 76. Delayed by the amount of delay. Further, in the third variable delay circuit unit 74, when the input rectangular wave signal is delayed by the zero delay, that is, the propagation delay time in the third variable delay circuit unit 74, the fourth variable delay circuit unit 76 However, the input rectangular wave signal is delayed by zero delay, that is, only the propagation delay time in the fourth variable delay circuit unit 76. That is, in the third variable delay circuit unit 74 and the fourth variable delay circuit unit 76, the sum of the delay amounts by which the rectangular wave signal is delayed is approximately a half cycle of the rectangular wave signal or the propagation delay in the variable delay circuit unit. It will be minutes. By controlling the delay amount in the third variable delay circuit unit 74 and the fourth variable delay circuit unit 76, a delay amount corresponding to a substantially half cycle of the rectangular wave signal can be generated.
[0063]
The blocking unit 110 is provided with CARRY data and third delay amount setting data. The third delay amount setting data is data for controlling the delay amount in the third variable delay circuit unit 74. The CARRY data is the same as the CARRY data described with reference to FIGS. The CARRY data is supplied to the register 102, and the third variable delay amount setting data is supplied to the register 32f. The third variable delay amount setting data is set to 0 when the delay amount in the third variable delay circuit unit 74 is zero, and is 1 when the delay amount in the third variable delay circuit unit 74 is the maximum delay amount. May be a digital signal to be set. The register 102, the register 32f, the logic element 104, and the logic element 106 have functions similar to those of the register and logic element described with reference to FIG. The outputs of the logic element 104 and the logic element 106 are input to the register 34f. The register 34f controls the delay amount in the third variable delay circuit unit 74 based on the input signal. The blocking unit 110 is a unit that blocks a desired rectangular wave component of the rectangular wave signal input to the third variable delay circuit unit 74 based on the outputs of the logic element 104 and the logic element 106 input to the register 34f. Have The blocking unit 110 may block a desired rectangular wave component of the rectangular wave signal in the third variable delay circuit unit 74.
[0064]
The first delay amount control unit 50 controls the delay amount in the first variable delay circuit unit 42. The first delay amount control unit 50 is provided with first delay amount setting data for controlling the delay amount in the first variable delay circuit unit 42. The first delay amount setting data is set based on the timing that the timing generator 30 should generate. The first delay amount control unit 50 includes an eighth holding circuit 68 that holds the first delay amount setting data until a desired timing, and a third holding circuit 56. The eighth holding circuit 68 receives the first delay amount setting data, holds the first delay amount setting data until the seventh holding circuit 66 holds the output, and supplies the first delay amount setting data to the third holding circuit 56. The third holding circuit 56 holds the first delay amount setting data until a desired timing, and controls the delay amount in the first variable delay circuit unit 42.
[0065]
The second delay amount control unit 60 controls the delay amount in the second variable delay circuit unit 44. The second delay amount control unit 60 is provided with second delay amount setting data for controlling the delay amount in the second variable delay circuit unit 44. The second delay amount setting data is given based on the timing that the timing generator 30 should generate. The second delay amount control unit 60 includes a ninth holding circuit 108 that holds the second delay amount setting data, a first holding circuit 52, and a second holding circuit 54 until a desired timing. The ninth holding circuit 108 receives the second delay amount setting data via the register 32d and the register 34d, and until the timing at which the seventh holding circuit 66 and the eighth holding circuit 56 hold the output is substantially the same. The second delay amount setting data is held and supplied to the first holding circuit 52. The first holding circuit 52 receives the second delay amount setting data, holds the output until the same timing as the timing at which the third holding circuit 56 holds the output, and supplies the output to the second holding circuit 54. The second holding circuit 54 receives the second delay amount setting data output from the first holding circuit 52, holds the second delay amount setting data until a desired timing, and sets the delay amount in the second variable delay circuit unit 44. Control.
[0066]
The timing output unit 70 includes a tenth holding circuit 72, a fourth holding circuit 58, a fifth holding circuit 62, a sixth holding circuit 64, and a selection unit 46. The timing output unit 70 selects and outputs a desired rectangular wave component from among the rectangular wave components included in the second delay signal output from the second variable delay circuit unit 44. By selecting and outputting a desired rectangular wave component from among the rectangular wave components included in the second delay signal, a delay that is an integral multiple of the period of the rectangular wave signal can be generated with respect to a predetermined timing. .
[0067]
The tenth holding circuit 72 sends selection data for selecting a desired rectangular wave among the rectangular wave components included in the second delay signal output from the second variable delay circuit unit 44 via the register 32e and the register 34e. The selection data is held until the seventh holding circuit 66, the eighth holding circuit 68, and the ninth holding circuit 108 hold the output, and supplied to the fourth holding circuit 58. The selection data is determined based on the timing that the timing generator 30 should generate.
[0068]
The fourth holding circuit 58 receives the selection data from the tenth holding circuit 72, holds the selection data until the first holding circuit 52 and the third holding circuit 56 hold the output, and supplies the selection data to the fifth holding circuit. To do. The fifth holding circuit 62 receives the selection data from the fourth holding circuit 58, holds the selection data until the timing at which the second holding circuit 54 holds the output, and supplies the selection data to the sixth holding circuit 64. To do.
[0069]
The sixth holding circuit 64 receives the selection data from the fifth holding circuit 62, holds the selection data until a desired timing, and supplies it to the selection unit 46. The selection unit 46 selects a desired rectangular wave component from the rectangular wave components included in the second delay signal output from the second variable delay circuit unit 44 based on the selection data received from the sixth holding circuit 64. Output. The selection data is a digital signal represented by 1 and 0, for example, and is determined based on the timing that the timing generator 30 should generate. The selection unit 46 may be a logic circuit that outputs a logical product, for example. The selection unit 46 receives the second delay signal and the selection data, and outputs a logical product of the second delay signal and the selection data, so that a desired rectangular wave component included in the second delay signal is output. Select the wave component. The first holding circuit 52, the second holding circuit 54, the third holding circuit 56, the fourth holding circuit 58, the fifth holding circuit 62, the sixth holding circuit 64, the seventh holding circuit 66, the eighth holding circuit 68, The ninth holding circuit 108 and the tenth holding circuit 72 are preferably dynamic latches.
[0070]
In addition, the timing generator 30 supplies a predetermined delay to each holding circuit that controls the delay amount in the first variable delay circuit 42, the second variable delay circuit 44, the third variable delay circuit 74, and the fourth variable delay circuit 76. It is preferable to provide initialization means for setting the amount. As an example, the initialization unit inputs a clear signal (CLR) to each variable delay circuit unit as shown in FIG. The initialization means will be described below.
[0071]
FIG. 7 is an explanatory diagram of the initialization means described in relation to FIG. For example, the initialization means includes a clear signal input means for inputting a clear signal to each variable delay circuit section shown in FIG. 6 and a clear data input means for inputting predetermined data to the data input of each holding circuit. Have. In this example, the clear signal input means gives the data holding switching timing to each holding circuit shown in FIG. 6 via each variable delay circuit section. As an example, the clear signal input means generates a clear rectangular wave for giving a data holding switching timing to each holding circuit, and supplies it to each variable delay circuit unit. Each variable delay circuit unit supplies the received clear rectangular wave to each holding circuit.
[0072]
FIG. 7A shows an example of the configuration of the first holding circuit 52 shown in FIG. The first holding circuit 52 receives, from the gate (G) input terminal, a clear rectangular wave for giving a data holding switching timing from the fourth variable delay circuit unit 76. The first holding circuit 52 receives predetermined data from the clear data input means from an out enable (OE) input terminal. In this example, the clear data input means inputs 0 as predetermined data to the first holding circuit 52.
[0073]
The first holding circuit 52 in this example has a NAND circuit that receives 0 as received as predetermined data from the clear data input means. When the NAND circuit receives 0 as the predetermined data, the output is constant regardless of the input from the data (D) input terminal. Each holding circuit illustrated in FIG. 6 may have the same or similar function and configuration as the first holding circuit 52 described with reference to FIG. Hereinafter, the clear signal input means will be described.
[0074]
FIG. 7B shows an example of the configuration of the fourth variable delay circuit unit 76 shown in FIG. For example, the fourth variable delay circuit unit 76 includes three stages of cascaded delay circuits. Each stage delay circuit has a plurality of NAND elements. Each stage delay circuit receives a signal to be delayed from the IN terminal and controls the delay amount in the fourth variable delay circuit unit 76 from the CNT terminal. A control signal is input. In the NAND circuit in each stage of the delay circuit, a signal to be delayed is input to one input, and 1 is normally input to the other input.
[0075]
The clear signal input means inputs 0 to the other input of the delay circuit in each stage, and sets the delay amount in the fourth variable delay circuit section 76 to zero regardless of the input of CNT. The clear signal input means inputs a rectangular wave for switching the data holding timing of the first holding circuit 52 to the input of the element shown in FIG. The fourth variable delay circuit unit 76 inputs the input rectangular wave to the gate (G) terminal of the first holding circuit 52. In this case, the rectangular wave is input to the first holding circuit 52 after being delayed by the propagation delay time in the fourth variable delay circuit unit 76. The clear data input means preferably has delay means for supplying the first holding circuit 52 with a delay amount larger than the propagation delay time and a signal for inputting predetermined data to the first holding circuit 52. For example, the delay means may be a circuit in which a plurality of inverters are connected in cascade. The clear data input means may supply the rectangular wave generated by the clear signal input means to the first holding circuit 52 as a signal for inputting the predetermined data. Each variable delay circuit unit shown in FIG. 6 may have the same or similar function and configuration as the fourth variable delay circuit unit 76 described with reference to FIG.
[0076]
FIG. 7C shows the timing of signals received by the first holding circuit 52 from the gate (G) terminal and the out enable (OE) terminal. The first holding circuit 52 receives the signal from the out enable terminal with a delay of ΔT with respect to the signal received from the gate terminal. In this example, ΔT is substantially equal to the delay amount of the delay means in the clear data input means minus the propagation delay time in the variable delay circuit section. In this example, the first holding circuit 52 holds data from the falling timing of the signal input from the gate terminal. By holding the signal delayed by ΔT from the out enable terminal, data hold in the first holding circuit 52 can be ensured. From the fall of the signal input from the out enable terminal, the data output from the first holding circuit 52 is determined regardless of the signal input from the data (D) terminal.
[0077]
According to the initialization means described above, since only clear data is input to each holding circuit, the propagation delay time in each holding circuit is reduced as compared with the case where each holding circuit has data initialization means. Can be small. In addition, since the timing generator 30 includes the initialization unit, a logic operation simulation of the timing generator 30 can be easily performed when the timing generator 30 is designed. In other words, the initial value of each holding circuit is determined by the initialization means, so that the number of logic patterns necessary for performing the logic operation simulation of the timing generator 30 is larger than when the initial value of each holding circuit is indefinite. Can be reduced. In the case of the timing generator 30 described with reference to FIG. 2, the data switching of each holding circuit is performed on the negative side pulse, so the initialization means sets the rectangular wave signal input to 0. In addition, a D-FF (delay-flip-flop) with a CLR terminal and a signal for switching data of each holding circuit should be set to zero.
[0078]
FIG. 8 is a timing chart showing an example of the operation of the timing generator 30 described in relation to FIG. In this example, the period of the rectangular wave signal is assumed to be 4 ns. In FIG. 7, the horizontal axis indicates time, and one scale indicates 1 ns. The test cycle and the timing to be generated by the timing generator 30 in this example are the same as those in the timing charts described with reference to FIGS. In this example, the third variable delay circuit 72 and the fourth variable delay circuit 74 each generate a delay amount of 1 ns at the maximum.
[0079]
The same data is set in the third delay amount setting data and the fourth delay amount setting data, and the total data is 0 ns or 2 ns. The third delay amount setting data and the fourth delay amount setting data are determined based on the timing that the timing generator 30 should generate. Since the third delay amount setting data and the fourth delay amount setting data are used to control whether or not the rectangular wave signal is delayed by a half cycle, the same data as the half cycle delay data described with reference to FIG. Is set. That is, 0 ns is set at the timing when 0 is set in the half cycle delay data in FIG. 3, and 1000 ns is set at the timing when 1 is set in the half cycle delay data.
[0080]
Similarly, in the first delay amount setting data and the second delay amount setting data, the same data as the first delay amount setting data and the second delay amount setting data described with reference to FIG. 3 is set. Similarly, the selection data is set to the same data as the selection data described with reference to FIG.
[0081]
The set third delay amount setting data is output from the register 34f via the blocking means 110. As described with reference to FIG. 3, the third delay amount setting data output from the register 34f is output with a delay of approximately 6 ns. The third delay amount setting data output from the register 34f includes a signal for blocking a predetermined rectangular wave component by the blocking unit 110. The blocking unit 110 changes a part of the third delay amount setting data to a blocking signal by the same control as the carry control described with reference to FIGS. 3 and 4. In FIG. 8, the dis signal output from the register 34f is the cutoff signal. When the register 34f outputs the cutoff signal, the rectangular wave component in the rectangular wave signal is cut off. The fourth delay amount setting data, the first delay amount setting data, the second delay amount setting data, and the selection data are also substantially the same as the timing at which the register 34f outputs the third delay amount setting data from the register 34, respectively. Output at timing. As shown in FIG. 6, the output of the third variable delay circuit unit 74 is the delay data indicated by the output of the register 34f, and a signal obtained by delaying the rectangular wave signal is output.
[0082]
The seventh holding circuit 66 receives the fourth delay setting data output from the register 34g at substantially the same timing as the register 34f outputs the third delay amount setting data. The seventh holding circuit 66 holds the fourth delay setting data output from the register 34g until the rising edge of the waveform of the rectangular wave signal, and controls the delay amount in the fourth variable delay circuit unit 76. In addition, the first delay amount setting data, the second delay amount setting data, and the selection data are transferred from the eighth holding circuit 68, the ninth holding circuit 108, and the tenth holding circuit 72, respectively, and from the seventh holding circuit to the fourth delay. It is output at substantially the same timing as the setting data is output. The fourth variable delay circuit unit 76 outputs a waveform obtained by delaying the output of the third variable delay circuit unit 74 based on the fourth delay amount setting data output from the seventh holding circuit 66.
[0083]
The third holding circuit 56 receives the first delay amount setting data output from the eighth holding circuit 68 at substantially the same timing as the seventh holding circuit 66 outputs the fourth delay amount setting data. . The third holding circuit 56 holds the first delay amount setting data input from the eighth holding circuit 68 until the rising edge of the waveform output by the third variable delay circuit unit 74, and the delay in the first variable delay circuit unit 42. Control the amount. The first variable delay circuit unit 42 outputs a first delay signal obtained by delaying the waveform output by the fourth variable delay circuit unit 76 based on the first delay amount setting data output by the third holding circuit 56.
[0084]
The second holding circuit 54 receives the second delay amount setting data output from the first holding circuit 52 at substantially the same timing as the timing at which the third holding circuit 56 outputs the first delay amount setting data. The second holding circuit 54 holds the second delay amount setting data input from the first holding circuit 52 until the rising edge of the waveform output from the fourth variable delay circuit unit 76, and the delay in the second variable delay circuit unit 44. Control the amount. The second variable delay circuit unit 44 outputs a second delay signal obtained by delaying the waveform output from the first variable delay circuit unit 74 based on the second delay amount setting data output from the second holding circuit 54.
[0085]
The sixth holding circuit 64 receives the selection data output from the fifth holding circuit 62 at substantially the same timing as the second holding circuit 54 outputs the second delay amount setting data. The sixth holding circuit 64 holds the selection data input from the fifth holding circuit 62 and outputs the data until the rising edge of the waveform output by the first variable delay circuit unit 42. The selection unit 46 selects and outputs the posi logic of the second delay signal output by the second variable delay circuit unit 44 while the sixth holding circuit 64 outputs 1.
[0086]
With the operation described above, the timing generator 30 can generate a desired timing. Further, it may have a setting unit that measures the propagation delay time of each element in advance and sets the delay amount setting data obtained by correcting the measured propagation delay time in the first delay amount setting data and the second delay amount setting data. Further, in the timing generator 30 described with reference to FIG. 6, a rectangular wave signal is used without being inverted as a write clock for each holding circuit. Therefore, an NMOS transistor can be used as the transistor switch of the dynamic latch described with reference to FIG. 5, and the propagation delay time in each holding circuit can be reduced. It is generally known that the switching time of the NMOS transistor is faster than the switching time of the PMOS transistor.
[0087]
FIG. 9 illustrates the setup and hold of the delay amount setting in the variable delay circuit unit of the timing generator 30 described with reference to FIGS. 6 to 8. FIG. 9A illustrates the setup. A rectangular wave signal input to the preceding variable delay circuit section of the variable delay circuit section whose delay amount is desired to be set is shown in the upper part of FIG. The delay amount setting data of the variable delay circuit unit whose delay amount is to be set is held in the holding circuit until the rise of the rectangular wave signal input to the preceding variable delay circuit unit. The delay amount setting data held in the holding circuit is delayed by the propagation delay time (Tdt) in the holding circuit from the rectangular wave signal input to the preceding variable delay circuit unit. The output of the holding circuit is shown in the middle part of FIG.
[0088]
Further, a rectangular wave signal input to the variable delay circuit unit for which the delay amount is desired to be set is shown in the lower part of FIG. The rectangular wave signal input to the variable delay circuit unit for which the delay amount is to be set is the sum of the delay setting amount (delay) in the preceding variable delay circuit unit and the propagation delay time (Tck) in the preceding variable delay circuit unit. Lags behind the previous input square wave signal.
[0089]
In order to set up the delay amount in the variable delay circuit unit for which the delay amount is to be set, the propagation delay time Tdt in the holding circuit is determined by the delay set amount in the preceding variable delay circuit unit and the propagation delay time in the preceding variable delay circuit unit. It must be smaller than the sum Tck + delay. Since the setup margin is the smallest when delay = 0, the propagation delay time Tdt in the holding circuit must be smaller than the propagation delay time Tck in the preceding variable delay circuit section.
[0090]
FIG. 9B illustrates the hold. As shown in FIG. 9B, in order to hold the delay amount in the variable delay circuit unit for which the delay amount is to be set, the period of the rectangular wave signal (cycle), the propagation delay time (Tdt) in the holding circuit, and Is not larger than the sum of the pulse width (pwd) of the rectangular wave signal, the delay setting amount (delay) in the preceding variable delay circuit unit, and the propagation delay time (Tck) in the preceding variable delay circuit unit. Must not. That is, if the delay setting amount (delay) in the preceding variable delay circuit unit is large, the delay amount cannot be held in the variable delay circuit unit. According to the timing generator 30 described with reference to FIGS. 6 to 8, since the half cycle delay unit 40 divides the half cycle delay into two variable delay circuits, a large margin for holding can be obtained. it can. In addition, by setting the maximum delay setting amount in each variable delay circuit unit and the propagation delay time in each holding circuit to appropriate values, timing can be generated using a rectangular wave signal having an arbitrary pulse width. it can.
[0091]
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.
[0092]
【Effect of the invention】
As is apparent from the above description, according to the present invention, a timing generator capable of operating at high speed can be provided. In addition, it is possible to generate a desired timing with high accuracy by suppressing the heat generation fluctuation in the delay circuit section.
[Brief description of the drawings]
FIG. 1 shows an example of the configuration of a test apparatus 100 according to the present invention.
FIG. 2 is a block diagram showing an example of the configuration of a timing generator 30 according to the present invention.
FIG. 3 is a timing chart showing an example of the operation of the timing generator 30;
FIG. 4 illustrates the carry operation described in relation to FIG.
FIG. 5 shows an example of the configuration of a dynamic latch and a static latch.
6 shows another example of the configuration of the timing generator 30. FIG.
FIG. 7 is an explanatory diagram of the initialization means described in relation to FIG.
8 is a timing chart showing an example of the operation of the timing generator 30 described in relation to FIG.
9 illustrates setup and hold of delay amount setting in the variable delay circuit unit of the timing generator 30 described with reference to FIGS. 6 and 7. FIG.
10 shows a configuration of a conventional timing generator 200. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Electronic device, 20 ... Pattern generation part, 22 ... Waveform shaping part, 24 ... Signal input / output part, 26 ... Determination part, 30 ... Timing generator, 32, 34 ... Registers 36, 38 ... Logic elements, 42 ... First variable delay circuit, 44 ... Second variable delay circuit, 46 ... Selection unit, 48 ... Input selection unit, 50 ... 1st delay amount control part, 52 ... 1st holding circuit, 54 ... 2nd holding circuit, 56 ... 3rd holding circuit, 58 ... 4th holding circuit, 60 ... Second delay amount control unit, 62 ... fifth holding circuit, 64 ... sixth holding circuit, 66 ... seventh holding circuit, 68 ... eighth holding circuit, 70 ... timing output unit 72 ... 10th holding circuit, 74 ... 3rd variable delay circuit, 76 ... 4th variable delay circuit, 78, 82, 86, 8, 94, 96, 98 ... inverter, 84, 92 ... transistor switch, 100 ... test device, 102 ... register, 104, 106 ... logic element, 108 ... ninth latch Circuit, 110... Interrupting means

Claims (30)

A timing generator for generating timing,
A first variable delay circuit unit that receives a rectangular wave signal and outputs a first delayed signal obtained by delaying the rectangular wave signal;
A second variable delay circuit section that receives the first delay signal and outputs a second delay signal obtained by delaying the first delay signal as the timing ;
A second delay amount control unit for controlling a delay amount in the second variable delay circuit unit,
The second delay amount control unit includes:
Second delay amount setting data for controlling a delay amount in the second variable delay circuit unit is given, and the second delay amount setting data is held and outputted until a first timing based on a change point of the rectangular wave signal. A first holding circuit;
Said first holding circuit receives the second delay amount setting data output until the second timing based on the change point before Symbol first delayed signal, while holding the second delay amount setting data, the second variable And a second holding circuit for controlling a delay amount in the delay circuit section. A first delay amount control unit for controlling a delay amount in the first variable delay circuit unit;
The first delay amount control unit includes:
First delay amount setting data for controlling a delay amount in the first variable delay circuit unit is given, and the first delay amount setting data is held until the first timing based on a change point of the rectangular wave signal, The timing generator according to claim 1, further comprising a third holding circuit that controls a delay amount in the first variable delay circuit unit.   The timing generator according to claim 2, wherein the first holding circuit, the second holding circuit, and the third holding circuit are dynamic latches. The rectangular wave signal is a clock signal having a predetermined period,
4. The timing according to claim 2, further comprising a half-cycle delay unit that delays the rectangular wave signal by approximately half a cycle of the rectangular wave signal and inputs the delayed signal to the first variable delay circuit unit. 5. Generator. 5. The timing generator according to claim 4 , wherein a delay amount in the first variable delay circuit unit corresponds to a substantially half cycle of the rectangular wave signal. An input for selecting either the rectangular wave signal or the rectangular wave signal delayed by the half-cycle delay unit based on the timing to be generated by the timing generator and inputting it to the first variable delay circuit unit the timing generator of claim 4 or 5, further comprising a selection unit.   The timing generator according to claim 6, wherein a delay amount in the second variable delay circuit unit corresponds to a delay amount resolution in the first variable delay circuit unit. The timing generator according to claim 6 or 7, further comprising the timing output section for selecting and outputting a rectangular NamiNaru component contained in the second variable delay circuit section and the second delay signal output . The timing output unit includes:
The selection data for selecting a rectangular NamiNaru fraction second variable delay circuit is included in the second delayed signal output is input to said first timing based on the change point of the rectangular wave signal, the selection A fourth holding circuit for holding and outputting data;
A fifth holding circuit that receives the selection data output from the fourth holding circuit and holds and outputs the selection data until the second timing based on a change point of the rectangular wave signal or the first delay signal;
A sixth holding circuit that receives the selection data output from the fifth holding circuit and holds and outputs the selection data until a third timing based on a change point of the first delay signal or the second delay signal;
Said sixth holding circuit based on the selection data is output, the timing of claim 8, characterized in that it comprises a selector for selecting and outputting a rectangular NamiNaru component contained in the second delayed signal Generator.   The timing generator according to claim 9, wherein the fourth holding circuit, the fifth holding circuit, and the sixth holding circuit are dynamic latches. The first holding circuit, the third holding circuit, and the fourth holding circuit hold the input data until the first timing based on the change point of the rectangular wave signal,
The second holding circuit and the fifth holding circuit hold the input data until the second timing based on the changing point of the first delay signal,
11. The timing generator according to claim 9, wherein the sixth holding circuit holds the input data until the third timing based on a change point of the second delay signal. 11.   The said 1st holding circuit, the said 3rd holding circuit, and the said 4th holding circuit hold | maintain each output until the timing based on the fall of the waveform of the said rectangular wave signal. Timing generator.   13. The timing generator according to claim 11, wherein the second holding circuit and the fifth holding circuit hold respective outputs until timing based on a falling edge of a waveform of the first delay signal. . It said sixth holding circuit until timing based on the fall of the waveform of the second delay signal, the timing generator according to any one of claims 11 13, characterized in that to hold the output. The half period delay unit, a timing generator according to any one of claims 11 to 14, characterized in that it comprises a means for inverting the waveform of the rectangular wave signal. The half-cycle delay unit is
A third variable delay circuit unit that receives the rectangular wave signal and outputs a third delayed signal that is a rectangular wave signal obtained by delaying the rectangular wave signal;
A fourth delay signal, which is a rectangular wave signal obtained by receiving the third delay signal output from the third variable delay circuit unit and delaying the third delay signal, is input to the first variable delay circuit unit. A variable delay circuit unit,
In the third variable delay circuit section and the fourth variable delay circuit, the maximum amount of delay according to claim 9 or 10, characterized in that approximately equal to a quarter period of each of said square wave signal Timing generator. The first holding circuit, the third holding circuit, and the fourth holding circuit are respectively input data until the first timing based on the change point of the rectangular wave signal output from the third variable delay circuit. Hold
The second holding circuit and the fifth holding circuit hold the input data until the second timing based on the change point of the rectangular wave signal output by the fourth variable delay circuit,
The timing generator according to claim 16, wherein the sixth holding circuit holds input data until the third timing based on a change point of the first delay signal. The timing generator generates a plurality of timings based on rectangular wave components in a plurality of regions obtained by dividing the rectangular wave signal in a predetermined time range;
The input selection unit sequentially selects one of a rectangular wave component of the rectangular wave signal and a rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit, and the first variable delay circuit unit When the rectangular wave component of the rectangular wave signal is close to the rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit. 18. The apparatus according to claim 17 , further comprising: a blocking unit that blocks a wave component or a rectangular wave component of the rectangular wave signal delayed by the half-cycle delay unit and inputs the blocked rectangular wave component to the first variable delay circuit unit. Timing generator. The fourth delay amount setting data for controlling the delay amount in the fourth variable delay circuit unit is given, and until the fourth timing based on the change point of the rectangular wave signal input to the third variable delay circuit unit, A seventh holding circuit for holding four delay amount setting data and controlling a delay amount in the fourth variable delay circuit unit;
An eighth holding circuit that is provided with the first delay amount setting data, holds the first delay amount setting data until the fourth timing, and outputs the first delay amount setting data to the third holding circuit;
A ninth holding circuit that is provided with the second delay amount setting data, holds the second delay amount setting data until the fourth timing, and outputs the second delay amount setting data to the first holding circuit;
19. The timing generator according to claim 18, further comprising a tenth holding circuit that receives the selection data, holds the selection data until the fourth timing, and outputs the selection data to the fourth holding circuit. .   The timing generator according to claim 19, wherein the seventh holding circuit, the eighth holding circuit, the ninth holding circuit, and the tenth holding circuit are dynamic latches.   The seventh holding circuit, the eighth holding circuit, the ninth holding circuit, and the tenth holding circuit are each up to the timing based on the rising edge of the waveform of the rectangular wave signal input to the third variable delay circuit. 21. The timing generator according to claim 19, wherein the output of the timing generator is held. The first holding circuit, the third holding circuit, and the fourth holding circuit hold respective outputs until a timing based on a rising edge of a waveform of the third delay signal. The timing generator according to any one of claims. Said second holding circuit, and the fifth holding circuit until timing based on the rise of the waveform of the fourth delay signal, in any one of claims 19, characterized in that for holding the respective output 22 The described timing generator. Said sixth holding circuit until timing based on the rise of the waveform of the first delay signal, the timing generator according to any one of claims 19 to 23, characterized in that to hold the output. The timing generator according to any one of claims 19 to 24 , further comprising initialization means for setting each output state in the first to tenth holding circuits to a predetermined state. The initialization means includes
Clear data input means for giving predetermined data to each of the first to tenth holding circuits;
Clear signal input means for giving data holding switching timing in each of the first to tenth holding circuits;
The clear signal input means gives the data holding switching timing to each of the first to tenth holding circuits via the first to fourth variable delay circuit sections. 26. The timing generator according to 25. The clear signal input means generates a clear rectangular wave for giving a data holding switching timing to the first to tenth holding circuits,
Fourth variable delay circuit section from said first receives a rectangular wave for the clear,
27. The timing generator according to claim 26, wherein the clear signal input means has means for setting the delay amount of the clear rectangular wave to substantially zero in the first to fourth variable delay circuit sections. .   The clear data input means receives the clear rectangular wave generated by the clear signal input means, and gives the predetermined data to the first to tenth holding circuits at a timing based on the clear rectangular wave. The timing generator of claim 27, wherein:   The clear signal input means is configured to delay the first to fourth variable delay circuit units at a timing based on the clear rectangular wave delayed by a time longer than a propagation delay time of the clear rectangular wave. 30. The timing generator according to claim 28, wherein the predetermined data is supplied to a 10 holding circuit. A test apparatus for testing an electronic device,
A pattern generator for generating a test pattern for testing the electronic device;
A waveform shaping unit that receives the test pattern and inputs a shaping pattern obtained by shaping the test pattern to the electronic device;
30. A timing generator according to any one of claims 1 to 29 for generating timing;
An output signal sampling circuit that samples an output signal output from the electronic device based on the test pattern at a timing generated by the timing generator;
Based on the sampling result at the output signal sampling circuit, the test device Ru and a judging section that judges good or bad of the electronic device.

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