JP4863279B2 - Memory system and memory access method - Google Patents

Description

  The present invention relates to a memory system and a memory access method.

  There is known an information processing apparatus that uses a software program, data, and the like stored in a semiconductor memory by detachably connecting the semiconductor memory.

  Some of these semiconductor memories are equipped with a specific security technology in order to protect confidentiality of data stored therein. For example, Patent Document 1 below discloses a technique for encrypting data using predetermined key data.

JP-A-9-106690

  However, even when data encryption is performed using key data as in the technique disclosed in Patent Document 1, the contents of communication performed between the semiconductor memory and the information processing apparatus are observed. Therefore, there is a possibility that the cipher can be decrypted by analyzing a large number of samples, and the security is not sufficient.

  The present invention has been made in view of such circumstances, and an object of the present invention is to obtain a memory system and a memory access method with improved security compared to the related art.

According to a first aspect of the present invention, there is provided a memory system including a memory device having a data storage unit and a host device accessible to the memory device, wherein the host device transmits a first data to the memory device from the host device. A first processing unit that divides the bit string into a plurality of partial bit strings, changes an arrangement order of the plurality of partial bit strings, and outputs the changed partial bit strings to the memory device. The plurality of output partial bit strings are input, the arrangement order of the plurality of partial bit strings is changed to restore the first bit string, and the data storage unit is accessed based on the first bit string. have a second processing unit, said first and second respective processing unit, a buffer memory capable of storing said plurality of partial bit strings to different addresses for each partial bit string, before An address designating circuit for designating an address of the buffer memory, and one of a process of storing the plurality of partial bit strings in the buffer memory and a process of outputting the plurality of partial bit strings from the buffer memory Is executed by sequential address designation, and the other process is executed by random address designation using a predetermined parameter, whereby the arrangement order of the plurality of partial bit strings can be changed. .

  The memory system according to a second invention is the memory system according to the first invention, in particular, the memory device divides a second bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, A third processing unit that changes the arrangement order of the plurality of partial bit strings and outputs the changed partial bit strings to the host device, and the host device inputs the plurality of partial bit strings output from the memory device. And a fourth processing unit that restores the second bit string by changing an arrangement order of the plurality of partial bit strings.

A memory system according to a third aspect of the present invention includes a memory device having a data storage unit and a host device accessible to the memory device, and the memory device transmits a bit string to be transmitted from the memory device to the host device. Dividing into a plurality of partial bit strings, changing the arrangement order of the plurality of partial bit strings, and outputting to the host device, the host device output from the memory device enter the plurality of partial bit string and restores the bit string by changing the arrangement order of the plurality of partial bit string, the second processing unit have a, the first and second processing unit, respectively, said plurality A buffer memory capable of storing the partial bit string of each partial bit string at a different address, and an address designating circuit for designating the address of the buffer memory, and the buffer memory One of the process of storing the plurality of partial bit strings in the memory and the process of outputting the plurality of partial bit strings from the buffer memory is executed by sequential address designation, and the other process is performed with a predetermined parameter. It is possible to change the arrangement order of the plurality of partial bit strings by executing by random address designation using .

The memory system according to a fourth invention is the memory system according to any one of the first to third inventions, wherein the predetermined parameter is a fixed value or a plurality of values described in advance in the data table. It is one of a value selected from among these and a value generated based on a pseudo-random number.

A memory system according to a fifth invention is the memory system according to any one of the first to fourth inventions, and in particular, the address designating circuit includes a plurality of logic circuits that perform a logic operation using the predetermined parameter. It has a circuit configuration that is cascade-connected in stages.

A memory access method according to a sixth aspect of the present invention is a memory access method for accessing a memory device having a data storage unit from a host device, wherein (A) the host device transmits the memory device to the memory device. Dividing the bit string to be divided into a plurality of partial bit strings and changing the arrangement order of the plurality of partial bit strings; and (B) in the host device, the plurality of partial bit strings after the processing in step (A), Outputting to the memory device; and (C) inputting the plurality of partial bit strings output from the host device in the memory device, and changing the arrangement order of the plurality of partial bit strings to change the bit string. A restoring step; (D) in the memory device, the bit string after processing in the step (C) Zui and, a step of accessing the data storage unit, in each of the steps (A) and the step (C) is storing processing of the plurality of partial bit strings to the buffer memory, and, from the buffer memory One of the plurality of partial bit string output processes is executed by sequential address designation, and the other process is executed by random address designation using a predetermined parameter. A change in the arrangement order of the bit strings is realized .

A memory access method according to a seventh invention is a memory access method for accessing a memory device having a data storage unit from a host device, wherein (A) the memory device transmits the memory device to the host device. Dividing a bit string to be divided into a plurality of partial bit strings, and changing an arrangement order of the plurality of partial bit strings; and (B) in the memory device, the plurality of partial bit strings after processing in the step (A), Outputting to the host device; and (C) inputting the plurality of partial bit strings output from the memory device in the host device, and changing the arrangement order of the plurality of partial bit strings to change the bit string. and a step of restoring, in each of the steps (a) and the step (C), buffer memory One of the process of storing the plurality of partial bit strings in the memory and the process of outputting the plurality of partial bit strings from the buffer memory is executed by sequential address designation, and the other process is performed with a predetermined parameter. It is possible to change the arrangement order of the plurality of partial bit strings by executing by random address designation using .

According to the memory system of the first invention, the first processing unit included in the host device divides the first bit string to be transmitted from the host device to the memory device into a plurality of partial bit strings, and the plurality of partial bit strings. Is output to the memory device. Therefore, even when the first bit string transmitted from the host device to the memory device is illegally read by a third party, the arrangement order of the plurality of partial bit strings is changed. The analysis of the first bit string by the three parties becomes difficult, and the security can be improved. According to the memory system of the first invention, one of the processing for storing the plurality of partial bit strings in the buffer memory and the processing for outputting the plurality of partial bit strings from the buffer memory is performed as a sequential address. It is possible to easily and reliably change the arrangement order of a plurality of partial bit strings by executing the designation and executing the other process by specifying a random address using a predetermined parameter.

  According to the memory system of the second invention, the third processing unit included in the memory device divides the second bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, and the plurality of partial bit strings. Change the array order of and output to the host device. Therefore, even when the second bit string transmitted from the memory device to the host device is illegally read out by a third party, the arrangement order of the plurality of partial bit strings is changed. Analysis of the second bit string by the three parties becomes difficult, and security can be improved.

According to the memory system of the third invention, the first processing unit included in the memory device divides the bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, and the arrangement order of the plurality of partial bit strings. Is output to the host device. Therefore, even when a bit string transmitted from the memory device to the host device is illegally read by a third party, the arrangement order of the plurality of partial bit strings is changed by the third party. Bit string analysis becomes difficult, and security can be improved. According to the memory system of the third invention, one of the processing for storing the plurality of partial bit strings in the buffer memory and the processing for outputting the plurality of partial bit strings from the buffer memory is performed sequentially. It is possible to easily and reliably change the arrangement order of a plurality of partial bit strings by executing the designation and executing the other process by specifying a random address using a predetermined parameter.

According to the memory system of the fourth invention, when a fixed value is used as the predetermined parameter, the circuit configuration is simplified and the cost can be reduced. In addition, when a value selected from a plurality of values described in advance in the data table or a value generated based on a pseudo-random number is used as the predetermined parameter, each time the parameter is changed Since the arrangement order of the plurality of partial bit strings is also changed, security can be improved.

According to the memory system of the fifth invention, the address designating circuit has a circuit configuration in which logic circuits that perform a logical operation using a predetermined parameter are cascaded in a plurality of stages. As described above, by using a plurality of parameters, the aspect of changing the arrangement order of the plurality of partial bit strings becomes more complicated, so that the security can be improved.

According to the memory access method of the sixth invention, the bit string to be transmitted from the host device to the memory device is divided into a plurality of partial bit strings, and the arrangement order of the plurality of partial bit strings is changed, so that the memory from the host device Output to the device. Therefore, even when a bit string transmitted from the host device to the memory device is illegally read by a third party, the arrangement order of the plurality of partial bit strings is changed by the third party. Bit string analysis becomes difficult, and security can be improved. According to the memory access method of the sixth invention, one of the processing for storing a plurality of partial bit strings in the buffer memory and the processing for outputting the plurality of partial bit strings from the buffer memory is performed sequentially. It is possible to change the arrangement order of a plurality of partial bit strings easily and reliably by executing by address designation and executing the other process by random address designation using a predetermined parameter.

According to the memory access method of the seventh invention, the bit string to be transmitted from the memory device to the host device is divided into a plurality of partial bit strings, and the arrangement order of the plurality of partial bit strings is changed, so that Output to the device. Therefore, even when a bit string transmitted from the memory device to the host device is illegally read by a third party, the arrangement order of the plurality of partial bit strings is changed by the third party. Bit string analysis becomes difficult, and security can be improved. According to the memory access method of the seventh invention, one of the processing for storing a plurality of partial bit strings in the buffer memory and the processing for outputting the plurality of partial bit strings from the buffer memory is performed sequentially. It is possible to change the arrangement order of a plurality of partial bit strings easily and reliably by executing by address designation and executing the other process by random address designation using a predetermined parameter.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

  FIG. 1 is a block diagram showing a configuration of a memory system 1 according to an embodiment of the present invention. Referring to FIG. 1, the memory system 1 includes a host device 2 and a semiconductor memory 3. The host device 2 is an arbitrary data processing device. The semiconductor memory 3 is, for example, a memory card that can be detachably connected to the host device 2.

  The host device 2 includes a CPU 4, processing units 5 and 6, and an interface unit 7. The semiconductor memory 3 includes a memory cell array unit 8, processing units 9 and 10, and an interface unit 11.

  Hereinafter, a case where a read command is issued from the host device 2, data corresponding to the read command is read from the semiconductor memory 3, and returned to the host device 2 will be described as an example. However, the present invention can be applied not only to reading data from the semiconductor memory 3 but also to other processing such as writing data to the semiconductor memory 3.

  Referring to FIG. 1, CPU 4 issues a read command. Here, as an example, it is assumed that an 8-byte read command is issued. A bit string of the command (hereinafter referred to as “command bit string C1”) is input from the CPU 4 to the processing unit 5.

  FIG. 2 is a schematic diagram showing the processing contents in the processing units 5 and 9 shown in FIG. FIG. 2A shows a command bit string C1 having a length of 8 bytes.

Referring to FIG. 1, processing unit 5 divides command bit string C1 input from CPU 4 into a plurality of bit strings (hereinafter referred to as “partial bit strings”). For example, as shown in FIG. 2B, the 8-bit command bit string C1 is divided into a total of eight partial bit strings PC1 _{0 to} PC1 ₇ each having a 1-byte length in order from the top. As a result, in the command bit string C1 shown in FIG. 2B, partial bit strings are arranged in the order of PC1 ₀ → PC1 ₁ → PC1 ₂ → PC1 ₃ → PC1 ₄ → PC1 ₅ → PC1 ₆ → PC1 _{7 from} the top. Has been.

Next, as illustrated in (C) of FIG. 2, the processing unit 5 randomly changes the arrangement order of the plurality of partial bit strings PC1 _{0 to} PC1 ₇ from the state illustrated in (B) of FIG. A new command bit string C2 is obtained. Specifically, in the command bit string C2, partial bit strings are arranged in the order of PC1 ₂ → PC1 ₃ → PC1 ₀ → PC1 ₁ → PC1 ₆ → PC1 ₇ → PC1 ₄ → PC1 _{5 from} the top. The method for changing the arrangement order in the processing unit 5 will be described in detail later.

The command bit string C2 created by the processing unit 5 is collectively transmitted from the host device 2 to the semiconductor memory 3 via the interface unit 7. That is, a plurality of partial bit strings are continuously transmitted from the host device 2 to the semiconductor memory 3 in the order of PC1 ₂ → PC1 ₃ → PC1 ₀ → PC1 ₁ → PC1 ₆ → PC1 ₇ → PC1 ₄ → PC1 ₅ .

As described above, according to the memory system 1 according to the present embodiment, the processing unit 5 included in the host device 2 transmits the command bit string C1 to be transmitted from the host device 2 to the semiconductor memory 3 as a plurality of partial bit strings PC1 _{0 to} PC1. _The command bit string C2 is generated by dividing the plurality of partial bit strings PC1 _{0 to} PC1 _{7 into} an array order. Then, the generated command bit string C <b> 2 is output toward the semiconductor memory 3. Therefore, even when the command bit string C2 transmitted from the host device 2 to the semiconductor memory 3 is illegally read by a third party, the arrangement order of the plurality of partial bit strings PC1 _{0 to} PC1 ₇ is changed. Therefore, it becomes difficult to analyze the command bit string by a third party, and the security can be improved.

Next, the processing unit 9 of the semiconductor memory 3 receives the command bit string C2 transmitted from the host device 2 via the interface unit 11. Then, as illustrated in FIG. 2D, the processing unit 9 changes the arrangement order of the partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C2 so that the original command bit string C1 is restored. As a result, in the command bit string C1 shown in FIG. 2D, as in the case of the command bit string C1 shown in FIG. 2B, PC1 ₀ → PC1 ₁ → PC1 ₂ → PC1 ₃ → PC1 ₄ from the top. Partial bit strings are arranged in the order of PC1 ₅ → PC1 ₆ → PC1 ₇ . A method of restoring the arrangement order in the processing unit 9 will be described in detail later.

  Next, the processing unit 9 accesses the memory cell array unit 8 using the restored command bit string C1. In this example, since the command bit string C1 is a read command, data corresponding to the address described in the command bit string C1 is read from the memory cell array unit 8. Here, it is assumed that 8-byte data is read from the memory cell array unit 8. The bit string of the data (hereinafter referred to as “data bit string D1”) is input from the memory cell array unit 8 to the processing unit 10.

  FIG. 3 is a schematic diagram showing processing contents in the processing units 6 and 10 shown in FIG. FIG. 3A shows a data bit string D1 having a length of 8 bytes.

Referring to FIG. 1, processing unit 10 divides data bit string D1 input from memory cell array unit 8 into a plurality of partial bit strings. For example, as shown in FIG. 3B, an 8-byte data bit string D1 is divided into a total of 8 partial bit strings PD1 _{0 to} PD1 ₇ each having a 1-byte length in order from the top. In the data bit string D1 shown in FIG. 3B, partial bit strings are arranged in the order of PD1 ₀ → PD1 ₁ → PD1 ₂ → PD1 ₃ → PD1 ₄ → PD1 ₅ → PD1 ₆ → PD1 _{7 from} the top. .

Next, as illustrated in (C) of FIG. 3, the processing unit 10 randomly changes the arrangement order of the plurality of partial bit strings PD1 _{0 to} PD1 ₇ from the state illustrated in (B) of FIG. A new data bit string D2 is obtained. In the data bit string D2, partial bit strings are arranged in the order of PD1 ₅ → PD1 ₄ → PD1 ₇ → PD1 ₆ → PD1 ₁ → PD1 ₀ → PD1 ₃ → PD1 _{2 from} the top. The method for changing the arrangement order in the processing unit 10 will be described in detail later.

The data bit string D2 created by the processing unit 10 is collectively transmitted from the semiconductor memory 3 to the host device 2 via the interface unit 11. That is, a plurality of partial bit strings are continuously transmitted from the semiconductor memory 3 to the host device 2 in the order of PD1 ₅ → PD1 ₄ → PD1 ₇ → PD1 ₆ → PD1 ₁ → PD1 ₀ → PD1 ₃ → PD1 ₂ .

Thus, according to the memory system 1 according to the present embodiment, the processing unit 10 included in the semiconductor memory 3 converts the data bit string D1 to be transmitted from the semiconductor memory 3 to the host device 2 into a plurality of partial bit strings PD1 _{0 to} PD1. _The data bit string D2 is generated by dividing the plurality of partial bit strings PD1 _{0 to} PD1 _{7 into} an arrangement order. Then, the generated data bit string D2 is output toward the host device 2. Therefore, even when the data bit string D2 transmitted from the semiconductor memory 3 to the host device 2 is illegally read by a third party, the arrangement order of the plurality of partial bit strings PD1 _{0 to} PD1 ₇ is changed. Therefore, it becomes difficult for a third party to analyze the data bit string, and security can be improved.

Next, the processing unit 6 of the host device 2 receives the data bit string D2 transmitted from the semiconductor memory 3 via the interface unit 7. Then, as illustrated in FIG. 3D, the processing unit 6 changes the arrangement order of the partial bit strings PD1 _{0 to} PD1 ₇ constituting the data bit string D2 so that the original data bit string D1 is restored. As a result, in the data bit string D1 shown in FIG. 3D, similarly to the data bit string D1 shown in FIG. 3B, PD1 ₀ → PD1 ₁ → PD1 ₂ → PD1 ₃ → PD1 ₄ from the top. Partial bit strings are arranged in the order of PD1 ₅ → PD1 ₆ → PD1 ₇ . A method of restoring the arrangement order in the processing unit 6 will be described in detail later.

  The data bit string D1 restored by the processing unit 6 is input to the CPU 4. Thereby, the CPU 4 receives the data bit string D1 corresponding to the issued command bit string C1.

<Processing for changing arrangement order in processing unit 5>
FIG. 4 is a block diagram showing a configuration of the processing unit 5 shown in FIG. The processing unit 5 includes a buffer memory 21 and an address designation circuit 20. In this example, since the total number of partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C1 is 8, the buffer memory 21 has a total of 8 (or more) storage areas indicated by addresses I0 to I7. is doing. Further, since each of the partial bit strings PC1 _{0 to} PC1 ₇ is 1 byte long, the storage capacity of each storage area of the buffer memory 21 is also 1 byte (or more).

The address designating circuit 20 includes logic circuits (hereinafter referred to as “EX-OR circuits”) 22 _{0 to} 22 ₂ that perform an exclusive OR logic operation. In this example, since the total number of partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C1 is 8 (= 2 ³ ), a total of three EX-OR circuits 22 _{0 to} 22 ₂ are provided. . The value of the parameter P1 is input to one input terminal of each of the EX-OR circuits 22 _{0 to} 22 ₂ , and the value of the transfer counter T 1 is input to the other input terminal. For example, to one input terminal of the EX-OR circuit 22 ₀ is input the value of bit0 of the parameter P1, the other input terminal the value of bit0 of the transfer counter T1 is inputted. The method for determining the parameter P1 will be described in detail later. In FIG. 4, bit 0 indicates the least significant bit and bit 2 indicates the most significant bit. The addresses I0 to I7 of the buffer memory 21 are designated by a 3-bit signal S1 defined by the output values from the EX-OR circuits 22 _{0 to} 22 ₂ .

  5-7 is a figure for demonstrating the change process of the arrangement | sequence order in the process part 5. FIG. Referring to FIG. 5, in this example, the value of parameter P1 is set to “010”. The value of the transfer counter T1 is “000” → “001” → “010” → “011” → “100” → “101” → “110” → “111” in synchronization with the clock CLK shown in FIG. And increase. As a result, the value of the signal S1 defined as the exclusive OR of the value of the parameter P1 and the value of the transfer counter T1 is “010” → “011” → “000” → “001” → “110” → “ "111" → "100" → "101" Since “000” of the signal S1 corresponds to the address I0 of the buffer memory 21 and “111” corresponds to the address I7, as shown in FIG. 5, I2 → I3 → I0 → I1 → I6 → I7 → I4 → I5 In this order, the addresses of the buffer memory 21 are designated.

Referring to FIG. 6, when the command bit string C1 is stored in the buffer memory 21, the partial bit strings PC1 _{0 to} PC1 ₇ are sequentially arranged in the order of addresses I0 → I1 → I2 → I3 → I4 → I5 → I6 → I7. Are stored in each storage area of the buffer memory 21. On the other hand, when the partial bit strings PC1 _{0 to} PC1 ₇ are output from the buffer memory 21, each of the addresses I2, I3, I0, I1, I6, I7, I4, and I5 is performed in the order of random processing using the signal S1. The partial bit strings PC1 _{0 to} PC1 ₇ are output from each storage area of the buffer memory 21. As a result, partial bit strings PC1 _{0 to} PC1 ₇ are read from the buffer memory 21 in the order of PC1 ₂ → PC1 ₃ → PC1 ₀ → PC1 ₁ → PC1 ₆ → PC1 ₇ → PC1 ₄ → PC1 ₅ , thereby A command bit string C2 whose order has been changed is generated.

In addition, you may perform the reverse process to FIG. That is, referring to FIG. 7, when the partial bit strings PC1 _{0 to} PC1 ₇ are stored in the buffer memory 21, random processing using the signal S1 is performed, while the partial bit strings PC1 _{0 to} PC1 ₇ are stored in the buffer memory 21. May be processed sequentially from addresses I0 to I7. In this case, as shown in FIG. 7, for example, partial bit string PC1 ₀ is stored in the address I2, partial bit string PC1 ₁ is stored in the address I3, partial bit string PC1 ₂ are stored in addresses I0. Also in the case of FIG. 7, the command bit string C2 in which the arrangement order is changed can be obtained as in FIG.

As described above, one of the storage processing of the plurality of partial bit strings PC1 _{0 to} PC1 _{7 in} the buffer memory 21 and the output processing of the plurality of partial bit strings PC1 _{0 to} PC1 ₇ from the buffer memory 21 is sequentially performed. It is possible to change the arrangement order of the plurality of partial bit strings PC1 _{0 to} PC1 ₇ easily and reliably by executing the other process by specifying a random address using the parameter P1. is there. The same applies to processing units 6, 9, and 10 described later.

  In the above description, the example in which the processing unit 5 is configured by hardware has been described. However, a processor may be mounted and the functions of the processing unit 5 described above may be realized by software. The same applies to processing units 6, 9, and 10 described later.

<Process for Restoring Arrangement Order in Processing Unit 9>
FIG. 8 is a block diagram showing a configuration of the processing unit 9 shown in FIG. The processing unit 9 includes a buffer memory 31 and an address designation circuit 30. In this example, since the total number of partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C2 is 8, the buffer memory 31 has a total of 8 (or more) storage areas indicated by addresses I0 to I7. is doing. Further, since the partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C2 are each 1 byte in length, the storage capacity of each storage area of the buffer memory 31 is also 1 byte (or more).

The address designation circuit 30 includes EX-OR circuits 32 _{0 to} 32 ₂ . In this example, since the total number of partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C2 is 8 (= 2 ³ ), a total of three EX-OR circuits 32 _{0 to} 32 ₂ are provided. . The EX-OR circuit 32 _0-32 each one input terminal of ₂ is inputted value of the parameter P2, the respective other input terminal the value of the transfer counter T2 is input. The value of the transfer counter T2 is “000” → “001” → “010” → “011” → “100” → “101” → “110” → “111” in synchronization with the clock CLK shown in FIG. And increase. Addresses I0 to I7 of the buffer memory 31 are specified by a 3-bit signal S2 defined by output values from the EX-OR circuits 32 _{0 to} 32 ₂ .

Here, in order to accurately restore the original command bit string C1 from the command bit string C2, it is necessary to set the same value as the parameter P1 shown in FIG. 4 as the value of the parameter P2. Therefore, for example, by describing the value of the parameter P1 in a part of the plurality of partial bit strings (for example, the partial bit string PC1 ₇ ) constituting the command bit string, the value of the parameter P1 is notified from the processing unit 5 to the processing unit 9. Can do. Specifically, the value of the parameter P2 to be used for the current command is already notified to the processing unit 9 by being described in the partial bit string transmitted from the processing unit 5 to the processing unit 9 regarding the previous command. Yes. Then, the processing unit 9 uses the value of the parameter P2 (equal to the value of the parameter P1 used for the current command) to perform a restoration process for the current command.

The processing unit 9 changes the arrangement order of the partial bit strings PC1 _{0 to} PC1 ₇ constituting the command bit string C2 by the same method as the processing unit 5 described above. That is, the process of storing the command bit string C2 in the buffer memory 31 is executed by sequential address designation, and the output process of the partial bit strings PC1 _{0 to} PC1 ₇ from the buffer memory 31 is performed by random address designation using the parameter P2. Execute. Alternatively, the process of storing the command bit string C2 in the buffer memory 31 is executed by random address designation using the parameter P2, and the output process of the partial bit strings PC1 _{0 to} PC1 ₇ from the buffer memory 31 is performed by sequential address designation. Execute. Then, by setting the value of the parameter P2 equal to the value of the parameter P1, the original command bit string C1 can be restored from the command bit string C2 and output from the buffer memory 31.

<Process for Changing Arrangement Order in Processing Unit 10>
FIG. 9 is a block diagram illustrating a configuration of the processing unit 10 illustrated in FIG. 1. The processing unit 10 includes a buffer memory 41 and an address designation circuit 40. In this example, since the total number of partial bit sequences PD1 _{0 to} PD1 ₇ constituting the data bit sequence D1 is 8, the buffer memory 41 has a total of 8 (or more) storage areas indicated by addresses I0 to I7. is doing. Further, since the partial bit strings PD1 _{0 to} PD1 ₇ are each 1 byte in length, the storage capacity of each storage area of the buffer memory 41 is also 1 byte (or more).

Further, the address designating circuit 40 has an EX-OR circuit ₄₂ 0-42 _2. In this example, since the total number of partial bit sequences PD1 _{0 to} PD1 ₇ constituting the data bit sequence D1 is 8 (= 2 ³ ), a total of 3 EX-OR circuits 42 _{0 to} 42 ₂ are provided. . Each one of the input terminals of the EX-OR circuit 42 _{0-42 2} is input the value of the parameter P3, and each the other input terminal the value of the transfer counter T3 is input. Then, the EX-OR circuit ₄₂ 0-42 3-bit signal S3 which is defined by the output values from _2, address I0~I7 of the buffer memory 41 are specified.

  10 to 12 are diagrams for explaining the arrangement order changing process in the processing unit 10. Referring to FIG. 10, in this example, the value of parameter P3 is set to “101”. The value of the transfer counter T3 is “000” → “001” → “010” → “011” → “100” → “101” → “110” → “111” in synchronization with the clock CLK shown in FIG. And increase. As a result, the value of the signal S3 defined as the exclusive OR of the value of the parameter P3 and the value of the transfer counter T3 is “101” → “100” → “111” → “110” → “001” → “ 000 "→" 011 "→" 010 ". Since “000” of the signal S3 corresponds to the address I0 of the buffer memory 41 and “111” corresponds to the address I7, as shown in FIG. 10, I5 → I4 → I7 → I6 → I1 → I0 → I3 → I2 In this order, the addresses of the buffer memory 41 are designated.

Referring to FIG. 11, when data bit string D1 is stored in buffer memory 41, partial bit strings PD1 _{0 to} PD1 ₇ are sequentially arranged in the order of addresses I0 → I1 → I2 → I3 → I4 → I5 → I6 → I7. Are stored in each storage area of the buffer memory 41. On the other hand, when the partial bit strings PD1 _{0 to} PD1 ₇ are output from the buffer memory 41, each of the addresses I5 → I4 → I7 → I6 → I1 → I0 → I3 → I2 is performed in order of random processing using the signal S3. The partial bit strings PD1 _{0 to} PD1 ₇ are output from each storage area of the buffer memory 41. As a result, partial bit strings PD1 _{0 to} PD1 ₇ are read from the buffer memory 41 in the order of PD1 ₅ → PD1 ₄ → PD1 ₇ → PD1 ₆ → PD1 ₁ → PD1 ₀ → PD1 ₃ → PD1 _2. A data bit string D2 whose order has been changed is generated.

Note that the reverse process of FIG. 11 may be performed. That is, referring to FIG. 12, when the partial bit strings PD1 _{0 to} PD1 ₇ are stored in the buffer memory 41, random processing using the signal S3 is performed, while the partial bit strings PD1 _{0 to} PD1 ₇ are stored in the buffer memory 41. May be processed sequentially from addresses I0 to I7. In this case, as shown in FIG. 12, for example, partial bit string PD1 ₀ is stored in the address I5, partial bit string PD1 ₁ is stored in the address I4, partial bit string PD1 ₂ is stored in the address I7. Also in the case of FIG. 12, the data bit string D2 in which the arrangement order is changed can be obtained as in FIG.

<Process for Restoring Arrangement Order in Processing Unit 6>
FIG. 13 is a block diagram showing a configuration of the processing unit 6 shown in FIG. The processing unit 6 includes a buffer memory 51 and an address designation circuit 50. In this example, since the total number of partial bit sequences PD1 _{0 to} PD1 ₇ constituting the data bit sequence D2 is 8, the buffer memory 51 has a total of 8 (or more) storage areas indicated by addresses I0 to I7. is doing. Further, since the partial bit strings PD1 _{0 to} PD1 ₇ constituting the data bit string D2 are each 1 byte in length, the storage capacity of each storage area of the buffer memory 51 is also 1 byte (or more).

Further, the address designating circuit 50 has an EX-OR circuit ₅₂ 0-52 _2. In this example, since the total number of partial bit sequences PD1 _{0 to} PD1 ₇ constituting the data bit sequence D2 is 8 (= 2 ³ ), a total of three EX-OR circuits 52 _{0 to} 52 ₂ are provided. . Each one of the input terminals of the EX-OR circuit 52 _{0-52 2} is input the value of the parameter P4, the respective other input terminal the value of the transfer counter T4 is inputted. The value of the transfer counter T4 is “000” → “001” → “010” → “011” → “100” → “101” → “110” → “111” in synchronization with the clock CLK shown in FIG. And increase. The EX-OR circuit ₅₂ 0-52 3-bit signal S4, which is defined by the output values from _2, address I0~I7 the buffer memory 51 are specified.

Here, in order to accurately restore the original data bit string D1 from the data bit string D2, it is necessary to set the same value as the parameter P3 shown in FIG. 9 as the value of the parameter P4. Thus, for example, by describing the value of the parameter P3 in partial bit string PD1 _7, it is possible to notify the value of the parameter P4 from the processing unit 10 to the processing unit 6. Specifically, the value of the parameter P4 to be used for the current data is already notified to the processing unit 6 by being described in the partial bit string transmitted from the processing unit 10 to the processing unit 6 regarding the previous data. Yes. Then, the processing unit 6 uses the value of the parameter P4 (equal to the value of the parameter P3 used for the current data) to perform a restoration process for the current data. Alternatively, the CPU 4 of the host device 2 may set the values of the parameters P3 and P4 and notify the processing units 6 and 10 of the values.

The processing unit 6 changes the arrangement order of the partial bit strings PD1 _{0 to} PD1 ₇ constituting the data bit string D2 by the same method as the processing unit 10 described above. That is, the storage process of the data bit string D2 in the buffer memory 51 is executed by sequential address designation, and the output process of the partial bit strings PD1 _{0 to} PD1 ₇ from the buffer memory 51 is performed by random address designation using the parameter P4. Execute. Alternatively, the storage processing of the data bit string D2 in the buffer memory 51 is executed by random address designation using the parameter P4, and the output processing of the partial bit strings PD1 _{0 to} PD1 ₇ from the buffer memory 51 is performed by sequential address designation. Execute. Then, by setting the value of the parameter P4 equal to the value of the parameter P3, the original data bit string D1 can be restored from the data bit string D2 and output from the buffer memory 51.

<Method for determining parameter P1>
Hereinafter, a method for determining the parameter P1 will be described, but the other parameters P2 to P4 can be determined by the same method.

  FIG. 14 is a block diagram showing a first configuration example of the address designation circuit 20 shown in FIG. The parameter determination unit 60 is, for example, a 3-bit register. In the above example, a fixed value “010” is set in the register in advance as the parameter P1. The set value of the register may be updated at every predetermined timing such as when the power is turned on. The EX-OR circuit 22 generates a signal S1 based on the parameter P1 and the transfer counter T1. Thus, by using a fixed value as the parameter P1, the circuit configuration is simplified and the cost can be reduced.

FIG. 15 is a block diagram showing a second configuration example of the address designating circuit 20 shown in FIG. The PN generation unit 61 generates a pseudo random number (hereinafter referred to as “PN”) by an arbitrary algorithm. The parameter determination unit 60 determines the parameter P1 based on the PN input from the PN generation unit 61. For example, the lower 3 bits of the PN generated by the PN generation unit 61 are set as the parameter P1. Each time a command is issued, the parameter determination unit 60 may retrieve the PN from the PN generation unit 61 and update the value of the parameter P1 based on the captured PN. The EX-OR circuit 22 generates a signal S1 based on the parameter P1 and the transfer counter T1. As described above, when a value generated based on PN is used as the parameter P1, the arrangement order of the partial bit strings PC1 _{0 to} PC1 ₇ is changed every time the parameter P1 is changed. Can be increased.

FIG. 16 is a block diagram showing a third configuration example of the address designation circuit 20 shown in FIG. A data table 62 in which a plurality of parameter values are described is created in advance, and the data table 62 is stored in a storage unit that can be referred to by the parameter determination unit 60. The parameter determination unit 60 randomly selects the index values A0 to An, and the parameter value corresponding to the selected index value is set as the parameter P1. The parameter determination unit 60 may change the value of the parameter P1 by updating the index values A0 to An each time a command is issued. The EX-OR circuit 22 generates a signal S1 based on the parameter P1 and the transfer counter T1. In this way, when a value selected from a plurality of values described in advance in the data table 62 is used as the parameter P1, the partial bit strings PC1 _{0 to} PC1 ₇ are changed every time the parameter P1 is changed. Since the arrangement order is also changed, security can be improved.

FIG. 17 is a block diagram showing a fourth configuration example of the address designation circuit 20 shown in FIG. The parameter determination units 60a and 60b are any of the parameter determination units 60 shown in FIGS. That is, the parameters P1a and P1b output from the parameter determination units 60a and 60b are described in advance in a fixed value (FIG. 14), a value generated based on the PN (FIG. 15), and the data table 62, respectively. One of values selected from a plurality of values (FIG. 16). The EX-OR circuit 22a outputs the signal S1a by taking the exclusive OR of the value of the parameter P1a and the value of the transfer counter T1. The EX-OR circuit 22b outputs the signal S1 by taking the exclusive OR of the value of the parameter P1b and the value of the signal S1a. As described above, the address designation circuit 20 shown in FIG. 17 has a circuit configuration in which the logic circuits 22a and 22b that perform the logical operation using the parameters P1a and P1b are cascaded in a plurality of stages. By using a plurality of parameters P1a and P1b, the mode of changing the arrangement order of the partial bit strings PC1 _{0 to} PC1 ₇ becomes more complicated, so that the security can be improved.

<Modification>
For example, with reference to FIG. 1, in the above description, an example in which the processing unit 5 and the processing unit 6 are separately configured in the host device 2 has been described, but these processing units 5 and 6 are integrated as a unit. You may comprise. In this case, the address designation circuit 20 shown in FIG. 4 and the address designation circuit 50 shown in FIG. 13 can be shared, and the buffer memory 21 shown in FIG. 4 and the buffer memory 51 shown in FIG. 13 can be shared.

  Similarly, in the above description, an example in which the processing unit 9 and the processing unit 10 are separately configured in the semiconductor memory 3 has been described. However, the processing units 9 and 10 may be configured as a single unit. good. In this case, the address designation circuit 30 shown in FIG. 8 and the address designation circuit 40 shown in FIG. 9 can be shared, and the buffer memory 31 shown in FIG. 8 and the buffer memory 41 shown in FIG. 9 can be shared.

  In the above description, in the batch transfer of bit strings having a length of a plurality of bytes, an example in which the bit string is divided into a plurality of partial bit strings in units of bytes and the arrangement order is changed in units of bytes has been described. In batch transfer of page-length bit strings, the bit string may be divided into a plurality of partial bit strings in units of pages, and the arrangement order may be changed in units of pages. In this case, in each page, the bit sequence may be further divided into a plurality of partial bit sequences in units of bytes, and the arrangement order may be changed in units of bytes.

1 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention. It is a schematic diagram which shows the processing content in the process part shown in FIG. It is a schematic diagram which shows the processing content in the process part shown in FIG. It is a block diagram which shows the structure of the process part shown in FIG. It is a figure for demonstrating the change process of arrangement | sequence order. It is a figure for demonstrating the change process of arrangement | sequence order. It is a figure for demonstrating the change process of arrangement | sequence order. It is a block diagram which shows the structure of the process part shown in FIG. It is a block diagram which shows the structure of the process part shown in FIG. It is a figure for demonstrating the change process of an arrangement | sequence order. It is a figure for demonstrating the change process of arrangement | sequence order. It is a figure for demonstrating the change process of arrangement | sequence order. It is a block diagram which shows the structure of the process part shown in FIG. FIG. 5 is a block diagram illustrating a first configuration example of an address designation circuit illustrated in FIG. 4. FIG. 5 is a block diagram illustrating a first configuration example of an address designation circuit illustrated in FIG. 4. FIG. 5 is a block diagram illustrating a first configuration example of an address designation circuit illustrated in FIG. 4. FIG. 5 is a block diagram illustrating a first configuration example of an address designation circuit illustrated in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory system 2 Host apparatus 3 Semiconductor memory 5, 6, 9, 10 Processing part 8 Memory cell array part 20, 30, 40, 50 Address designation circuit 21, 31, 41, 51 Buffer memory 22, 22a, 22b EX-OR circuit 60, 60a, 60b Parameter determination unit 61 PN generation unit 62 Data table

Claims (7)

A memory device having a data storage unit;
A host device accessible to the memory device,
The host device is
A first processing unit that divides a first bit string to be transmitted from the host device to the memory device into a plurality of partial bit strings, changes an arrangement order of the plurality of partial bit strings, and outputs the partial bit strings to the memory device. Have
The memory device includes:
The plurality of partial bit strings output from the host device are input, the arrangement order of the plurality of partial bit strings is changed to restore the first bit string, and the data storage unit is based on the first bit string access, have a second processing unit,
Each of the first and second processing units is
A buffer memory capable of storing the plurality of partial bit strings at different addresses for each partial bit string;
An address designating circuit for designating an address of the buffer memory;
Have
One of the storage processing of the plurality of partial bit strings in the buffer memory and the output processing of the plurality of partial bit strings from the buffer memory is executed by sequential address designation, and the other processing is performed. A memory system in which a change in the arrangement order of the plurality of partial bit strings is realized by executing by random address designation using a predetermined parameter. The memory device includes:
A third processing unit that divides a second bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, changes an arrangement order of the plurality of partial bit strings, and outputs the partial bit string to the host device. Further comprising
The host device is
The apparatus according to claim 1, further comprising: a fourth processing unit that inputs the plurality of partial bit strings output from the memory device and restores the second bit string by changing an arrangement order of the plurality of partial bit strings. The described memory system. A memory device having a data storage unit;
A host device accessible to the memory device,
The memory device includes:
A first processing unit that divides a bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, changes an arrangement order of the plurality of partial bit strings, and outputs the partial bit string to the host device; ,
The host device is
Enter the plurality of partial bit string output from the memory device, to change the order of arrangement of the plurality of partial bit strings to restore the bit sequence, we have a second processing unit,
Each of the first and second processing units is
A buffer memory capable of storing the plurality of partial bit strings at different addresses for each partial bit string;
An address designating circuit for designating an address of the buffer memory;
Have
One of the storage processing of the plurality of partial bit strings in the buffer memory and the output processing of the plurality of partial bit strings from the buffer memory is executed by sequential address designation, and the other processing is performed. A memory system in which a change in the arrangement order of the plurality of partial bit strings is realized by executing by random address designation using a predetermined parameter.   The predetermined parameter is any one of a fixed value, a value selected from a plurality of values described in advance in the data table, and a value generated based on a pseudo-random number. Item 4. The memory system according to any one of Items 1 to 3.   5. The memory system according to claim 1, wherein the address designation circuit has a circuit configuration in which logic circuits that perform a logical operation using the predetermined parameter are cascade-connected in a plurality of stages.   A memory access method for accessing a memory device having a data storage unit from a host device,
  (A) in the host device, dividing a bit string to be transmitted from the host device to the memory device into a plurality of partial bit strings, and changing an arrangement order of the plurality of partial bit strings;
  (B) in the host device, outputting the plurality of partial bit strings after processing in the step (A) to the memory device;
  (C) In the memory device, inputting the plurality of partial bit strings output from the host device, changing the arrangement order of the plurality of partial bit strings, and restoring the bit string;
  (D) in the memory device, accessing the data storage unit based on the bit string after processing in the step (C);
With
  In each of the step (A) and the step (C), one of a process of storing the plurality of partial bit strings in the buffer memory and a process of outputting the plurality of partial bit strings from the buffer memory Is executed by sequential address designation, and the other processing is executed by random address designation using a predetermined parameter, whereby the arrangement order of the plurality of partial bit strings is realized.   A memory access method for accessing a memory device having a data storage unit from a host device,
  (A) in the memory device, dividing a bit string to be transmitted from the memory device to the host device into a plurality of partial bit strings, and changing an arrangement order of the plurality of partial bit strings;
  (B) In the memory device, outputting the plurality of partial bit strings after processing in the step (A) to the host device;
  (C) In the host device, inputting the plurality of partial bit strings output from the memory device, changing the arrangement order of the plurality of partial bit strings, and restoring the bit string;
With
  In each of the step (A) and the step (C), one of a process of storing the plurality of partial bit strings in the buffer memory and a process of outputting the plurality of partial bit strings from the buffer memory Is executed by sequential address designation, and the other processing is executed by random address designation using a predetermined parameter, whereby the arrangement order of the plurality of partial bit strings is realized.