JP4856512B2 - Manufacturing method and manufacturing program for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a method for creating a layout pattern of a semiconductor integrated circuit.

  Conventionally, in the design of a semiconductor integrated circuit (LSI: Large Scale Integration, large-scale integrated circuit), in order to reduce the chip area, the minimum processing dimension is frequently used to reduce the wiring interval as much as possible and to reduce the wiring width. I was doing. However, in recent years, with the progress of miniaturization, for example, pattern defects such as wiring short-circuits and disconnections due to particles (Particles), and pattern defects due to dent defects generated in a CMP (Chemical Mechanical Polishing) process. In addition, there is a problem of pattern defects caused by deformation of the transfer pattern on the wafer due to light diffraction in the lithography process (exposure process). Such a problem becomes apparent particularly in a semiconductor integrated circuit having a technology node of 90 nm or 65 nm or less, and causes a reduction in the manufacturing yield of the semiconductor integrated circuit.

  More specifically, when a conventional semiconductor integrated circuit having a technology node larger than 90 nm is manufactured, the mask pattern wiring width and wiring interval are sufficiently larger than the particle size, so that a small amount of particles are generated. It was not the main factor causing pattern defects. Moreover, it was possible to cope with the occurrence of pattern defects by reducing the number of particles by performing a cleaning process or the like. However, as the processing dimensions become finer and the wiring width of the mask pattern becomes narrower and the wiring interval becomes narrower, especially in the case of a semiconductor integrated circuit having a technology node of 65 nm or less, the wiring of the mask pattern with respect to the particle size. It becomes difficult to ensure sufficient spacing and wiring width, and the incidence of pattern defects due to a small amount of particles tends to increase. Further, when a conventional semiconductor integrated circuit having a technology node larger than 90 nm is manufactured, a light diffraction phenomenon occurs when a design layout pattern created by CAD (Computer Aided Design) is transferred onto a wafer in a lithography process. Even if the shape of the transfer pattern on the wafer breaks due to the wire pattern, the wiring interval and width have sufficient margins for the degree of shape loss of the transfer pattern, causing pattern defects such as wiring short-circuiting and disconnection. It was not the cause. However, as miniaturization progresses, problems due to the deformation of the transferred pattern on the wafer due to the light diffraction phenomenon become apparent, and the pattern defects tend to increase.

  Conventionally, such a problem has been dealt with in the manufacturing department. However, due to further miniaturization in recent years, in particular, in a semiconductor integrated circuit having a technology node of 65 nm or less, the mass production can be achieved only by dealing with the manufacturing department. It has become difficult to ensure a high manufacturing yield from the initial stage.

  For this reason, the design department is also required to perform a design corresponding to the above problem, and recently, as a mechanism for solving various problems in the manufacturing stage of the semiconductor integrated circuit at the design stage, DFM (Design for Manufacturability) ) Has been proposed.

  As a technique related to such DFM, for example, a mask pattern is created using a compaction tool, a RET (Resolution Enhancement Technique) processing tool, and an OPC (Optical Proximity Correction) processing tool, and the mask process is performed on the created mask pattern. Perform a finished plane shape calculation simulation on the wafer considering the process and etching process, identify the dangerous pattern in the mask pattern using the dangerous pattern analysis tool that analyzes the simulation result, and manage the dimensions for the identified dangerous pattern There is a manufacturing method of a semiconductor integrated circuit that corrects a mask pattern by strictness (see, for example, Patent Document 1).

JP 2005-181524 A

  However, in the method of manufacturing a semiconductor integrated circuit described in Patent Document 1, the mask pattern correction by the compaction tool, the finished plane shape calculation simulation, and the analysis of the dangerous pattern are repeatedly executed until a desired mask pattern is obtained. For this reason, there is a problem that the number of steps until a desired mask pattern is obtained increases and TAT (Turn Around Time) may be increased. Further, in the method of manufacturing a semiconductor integrated circuit described in Patent Document 1, since the dangerous pattern is specified by analyzing the result of the finished plane shape calculation simulation, the correction accuracy of the mask pattern has a compaction tool, a RET processing tool, It depends on the accuracy of various tools such as an OPC processing tool and a danger pattern analysis tool. Therefore, in order to improve the mask pattern correction accuracy and improve the yield, in order to ensure sufficient accuracy of various tools, the process parameters for manufacturing the semiconductor integrated circuit between the various tools are precisely matched. There is a problem that it takes a lot of time and labor.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit capable of easily and effectively reducing pattern defects due to miniaturization with a relatively small number of steps. There is in point to do. A semiconductor integrated circuit manufacturing program capable of easily and effectively reducing pattern defects due to miniaturization with a relatively small number of steps.

  In order to achieve the above object, a method of manufacturing a semiconductor integrated circuit according to the present invention performs a temporary layout according to a dimensional constraint set based on a minimum processing dimension in manufacturing a semiconductor integrated circuit, and is obtained by the temporary layout. A correctable condition setting step for setting a correctable condition including a restriction on the chip size obtained from the design layout pattern after changing the temporary layout pattern obtained by the temporary layout based on the chip size, and the type of the dimension constraint Separately, a correction information acquisition step of acquiring a plurality of correction information consisting of relaxed size constraints that gradually relaxed the size constraints, a priority order setting step of setting a priority order for each of the correction information, The correction information used in the correction process for the temporary layout pattern is sequentially selected based on the priority order. The correction target pattern is extracted from the temporary layout pattern based on the type of the dimension constraint of the selected correction information, and the correction processing result for the correction target pattern is obtained from the selected correction information for each correction target pattern. It is determined whether or not the relaxed dimension constraint and the modifiable condition of the correction information with the higher priority are satisfied, and the relaxation processing result is the relaxation of the correction information with the higher priority than the selected correction information. The correction processing step of reflecting the correction processing result in the temporary layout pattern when a dimensional constraint and the correction possible condition are satisfied, and repeatedly executing the correction processing step for each of the correction information. One feature.

  The method for manufacturing a semiconductor integrated circuit according to the present invention having the above characteristics is characterized in that the correction information includes the correction information in which the type of the dimension constraint is a wiring interval.

  The semiconductor integrated circuit manufacturing method according to the present invention having any one of the above characteristics is characterized in that it includes the correction information in which the type of the dimension constraint is a wiring width.

  In the method of manufacturing a semiconductor integrated circuit according to the present invention having any one of the above characteristics, the correction condition includes: an area of a chip size obtained from the design layout pattern; a length of a long side of a rectangular region that accommodates the entire design layout pattern And a restriction on at least one of the lengths of the short sides of the rectangular region.

  In the method of manufacturing a semiconductor integrated circuit according to the fourth aspect of the present invention, the correctable condition is that the correction target pattern vertices after correction with respect to the number of vertices of the correction target pattern before correction extracted from the temporary layout pattern A fifth feature is that a restriction on the number changeable range is included.

  The semiconductor integrated circuit manufacturing method according to the present invention having any one of the above characteristics is characterized in that the priority order setting step includes a priority order correction step of correcting the priority order according to an external input. .

  In order to achieve the above object, a semiconductor integrated circuit manufacturing program according to the present invention includes a program step for executing, on a computer, each step in the semiconductor integrated circuit manufacturing method having any one of the above characteristics.

  According to the present invention, by using a plurality of pieces of correction information composed of relaxed dimension constraints in which the dimension constraints are relaxed step by step for each type of dimension constraints, the temporary layout is applied to the correction processing in order from the correction information having the highest priority. Since the pattern is corrected, a design layout pattern corresponding to a problem occurring in the manufacturing stage can be easily obtained in a relatively short time. In particular, by correcting the temporary layout pattern by setting the priority order of the correction information in descending order of the defect occurrence rate corresponding to the relaxed dimension constraint, the area having a relatively narrow wiring interval in the temporary layout pattern or the relatively thin pattern is corrected. It becomes possible to preferentially perform correction processing from a correction target pattern having a high defect occurrence rate, such as a region having a wiring width. As a result, it is possible to reduce the response to pattern defects in the manufacturing stage without significantly increasing the labor for layout design in the design department. Furthermore, according to the present invention, pattern defects in the lithography process can be reduced by correcting the temporary layout pattern, and a high yield can be secured from the initial stage of mass production.

  Embodiments of a method for manufacturing a semiconductor integrated circuit according to the present invention (hereinafter simply referred to as “method of the present invention” where appropriate) will be described below with reference to the drawings.

<First Embodiment>
1st Embodiment of the method of this invention is described based on FIGS.

  First, the configuration of a semiconductor integrated circuit manufacturing apparatus for executing the method of the present invention will be described with reference to FIG. As shown in FIG. 1, the manufacturing apparatus 1 includes a control unit 10 that executes the method of the present invention, a storage unit 20 that stores various data used in the method of the present invention, and an input / output that is a communication interface that communicates with the outside. Means 30 are provided, and each means is connected via a bus.

  The control means 10 is a layout means 11 that implements a temporary layout in accordance with a dimensional constraint set based on a minimum processing dimension in the manufacture of a semiconductor integrated circuit, and a temporary layout obtained by the temporary layout based on a chip size obtained by the temporary layout. Correctable condition setting means 12 for setting a correctable condition including a restriction on the chip size obtained from the design layout pattern after changing the layout pattern, relaxed dimension constraint in which the dimension constraint is relaxed step by step for each type of dimension constraint Correction information acquisition means 13 for acquiring a plurality of correction information comprising: correction priority acquisition means 14 for setting priority for each of the correction information; and correction information used in correction processing for the temporary layout pattern based on the priority order. Are selected sequentially, and temporary Whether or not the correction target pattern is extracted from the out pattern, and whether or not the correction processing result for the correction target pattern satisfies the relaxed dimension constraint and correction possible condition of the correction information having a higher priority than the selected correction information for each correction target pattern. A correction processing unit 15 configured to reflect the correction processing result in the temporary layout pattern when the correction processing result satisfies the relaxed dimension constraint and the correctable condition of the correction information having a higher priority than the selected correction information. Is done.

  In this embodiment, the layout unit 11 for executing the temporary layout is provided in the manufacturing apparatus 1. However, the temporary layout result created by the external device may be received via the input / output unit 30. . Moreover, in this embodiment, each means in the control means 10 is comprised by software with the manufacturing program which performs each process in this invention method on a computer.

  Next, each processing step of the method of the present invention will be described with reference to FIG.

  First, the manufacturing apparatus 1 acquires a design rule (dimension restriction) used in the temporary layout through the input / output unit 30 by the layout unit 11, and executes the temporary layout according to the acquired design rule (step # 101). Further, the layout unit 11 stores a temporary layout result such as a temporary layout pattern and a chip size of each layer of the semiconductor integrated circuit obtained by the temporary layout in the storage unit 20. The design rule here includes a minimum processing dimension that defines a minimum wiring width and a minimum wiring interval in the layout pattern according to the manufacturing process.

  Subsequently, the manufacturing apparatus 1 can perform correction including restrictions on the chip size obtained from the design layout pattern after changing the temporary layout pattern based on the chip size obtained by the temporary layout by the correctable condition setting unit 12. Conditions are set (step # 102, correctable condition setting step). The correctable condition in the present embodiment is the area of the chip size. More specifically, as a condition that can be corrected, for example, the area of the chip size obtained from the design layout pattern is defined as 110% or less of the area of the chip size obtained by the temporary layout performed based on the minimum processing dimension.

  Subsequently, the manufacturing apparatus 1 uses the correction information acquisition unit 13 to acquire a plurality of pieces of correction information composed of relaxed dimensional constraints obtained by gradually relaxing the dimensional constraints for each type of dimensional constraints (step # 103, correction information acquiring step). ). Furthermore, the manufacturing apparatus 1 sets the priority order for each of the acquired correction information by the priority order setting unit 14 (step # 104, priority order setting step). Here, FIG. 3 is a table showing an example of a relationship between relaxed dimension constraints and priorities when the type of dimension constraint is wiring spacing, and FIG. 4 shows each dimension constraint, that is, wiring spacing and defect occurrence rate. It is a graph which shows the relationship. As shown in FIG. 3, the relaxed dimension constraints of the present embodiment are the wiring intervals S1 to S5. As shown in FIG. 4, the minimum processing size of the wiring interval Smin <wiring interval S1 <wiring interval S2 <wiring interval S3. <Wiring interval S4 <Wiring interval S5 is set. Here, as can be seen from FIG. 4, the defect occurrence rate increases as the wiring interval becomes narrower. Therefore, the priority order setting unit 14 increases the priority as the relaxed dimension constraint in which the wiring interval is narrower. Set.

  Subsequently, the manufacturing apparatus 1 uses the correction processing unit 15 to perform correction processing on the temporary layout pattern using the correction information (step # 105, correction processing step). Hereinafter, details of the correction processing step by the correction processing means 15 will be described with reference to FIGS. 5 and 6. Here, FIG. 5A shows a partial region P1 of the temporary layout pattern including the correction target pattern as an example of the correction target pattern before the correction processing, and FIG. A region P1 ′ after the partial region P1 shown in FIG. Similarly, FIG. 6A shows a partial area P2 of the temporary layout pattern including the correction target pattern as an example of the correction target pattern before the correction processing, and FIG. A region P2 ′ after the partial region P2 shown in FIG.

  Specifically, as shown in FIG. 2, the correction processing means 15 first sequentially selects correction information used in the correction processing for the temporary layout pattern based on the priority order (step # 106). In the present embodiment, the correction information with the highest priority is selected from the correction information that is not used in the correction process. Hereinafter, a description will be given assuming that the wiring interval S1 having the first priority shown in FIG. 3 is selected from the correction information.

  Subsequently, the correction processing means 15 extracts a correction target pattern from the temporary layout pattern based on the size constraint type of the selected correction information (step # 107). Specifically, when the wiring interval S1 is selected as the type of dimension constraint of the correction information, the correction processing unit 15 in FIG. 5A, the wiring interval between the wiring pattern m1 and the wiring pattern x1, and Since the wiring interval between the wiring pattern x1 and the wiring pattern c1 does not satisfy the wiring interval S1, the wiring patterns m1 and c1 are extracted as correction target patterns. Similarly, in the correction processing unit 15, in FIG. 6A, the wiring interval between the wiring pattern m2 and the wiring pattern x22 and the wiring interval between the wiring pattern x22 and the wiring pattern c2 do not satisfy the wiring interval S1. Therefore, the wiring patterns m2 and c2 are extracted as correction target patterns.

  Subsequently, as shown in FIG. 2, the correction processing means 15 performs a correction process on the correction target pattern for each correction target pattern (step # 108). Specifically, in FIG. 5A, the correction processing unit 15 has a sufficient space on the opposite side of the adjacent pattern x1 with respect to the wiring pattern m1, so that the interval between the adjacent pattern x1 is the wiring interval S1. The process of moving to the side opposite to the adjacent pattern x1 is performed so that Further, the correction processing means 15 performs a process of narrowing the wiring width so that the distance between the adjacent pattern x1 becomes the wiring distance S1 with respect to the wiring pattern c1 shown in FIG. Further, in FIG. 6A, the correction processing unit 15 performs a process of moving the wiring pattern m2 to the side opposite to the adjacent pattern x22 so that the distance between the adjacent pattern x22 becomes the wiring distance S1. . Further, the correction processing means 15 performs a process of narrowing the wiring width so that the distance between the adjacent pattern x22 and the wiring pattern c2 shown in FIG.

  Subsequently, as shown in FIG. 2, the correction processing means 15 determines whether or not the correction processing result satisfies the relaxed dimension constraint and the correctable condition of the correction information having a higher priority than the selected correction information (Step #). 109) When the correction process result satisfies the relaxed dimension constraint and the correctable condition of the correction information having higher priority than the selected correction information (OK branch at step # 109), the correction process result is reflected in the temporary layout pattern. (Step # 110). In this embodiment, FIG. 3 shows only the correction information used in the correction process in step # 108. However, in the determination process in step # 109, the wiring interval Smin and the wiring width Wmin with the minimum processing dimension are set to the maximum. Treated as a high priority relaxed dimension constraint.

  Specifically, the correction processing unit 15 determines that the wiring interval m and the wiring width of the correction processing result for the wiring pattern m1 and the wiring pattern c1 shown in FIG. 5A are minimum processing as shown in FIG. 5B. Since it is more than the wiring interval Smin and the wiring width Wmin of the dimensions, it is determined that the relaxed dimension constraint of the correction information having higher priority than the selected correction information is satisfied. Further, the chip size is obtained from the temporary layout pattern reflecting the correction result, and when the chip size area satisfies the correctable condition (OK branch at step # 109), the correction processing result is reflected in the temporary layout pattern ( Step # 110). Further, as shown in FIG. 6B, the correction processing means 15 determines the wiring interval between the wiring pattern m2 ′ and the adjacent pattern x21 for the correction processing results for the wiring pattern m2 and the wiring pattern c2 shown in FIG. Since the wiring interval cmin is narrower than the minimum processing dimension wiring interval Smin and the wiring width of the wiring pattern c2 ′ is smaller than the minimum processing dimension wiring width Wmin, it is determined that the relaxed dimension constraint of the correction information having higher priority than the selected correction information is not satisfied. (NG branch at step # 109). In this case, the correction process is canceled and the correction process result is discarded without being reflected in the temporary layout pattern.

  The correction processing means 15 carries out a correction processing step for sequentially correcting the temporary layout pattern for all the correction information shown in FIG. 3 (step # 112). In this way, the processing for increasing the wiring interval is performed in order so as to satisfy the specification of the wiring interval of the correction information having higher priority sequentially.

  The manufacturing apparatus 1 is obtained by correcting the temporary layout pattern at the final stage of the correction processing step by the control means 10 after the correction processing step of Step # 105 by the correction processing means 15 ends (No branch at Step # 112). The designed layout pattern is stored in the storage means 20. Further, the manufacturing apparatus 1 outputs the design layout pattern by the input unit 30 in a desired data format such as a GDS2 stream format in accordance with an external input.

  FIG. 7 shows a temporary layout pattern 70 before applying the method of the present invention and a design layout pattern 72 after applying the method of the present invention. A hatched portion in FIG. 7 indicates a region having a wiring interval 71 of the minimum processing dimension. As shown in FIG. 7, the temporary layout pattern 70 before applying the method of the present invention is designed based on the minimum processing dimension. On the other hand, in the design layout pattern 72 after applying the method of the present invention of this embodiment, some of the regions having the wiring interval 71 of the minimum processing dimension in the temporary layout pattern 70 are the wiring intervals S1 to S1 shown in FIG. The region that is modified to take S5 and has the wiring interval 71 of the minimum processing dimension is smaller than the temporary layout pattern 70 before applying the method of the present invention. That is, as can be seen from FIG. 4, since the defect occurrence rate decreases as the wiring interval becomes wider, the region having the wiring interval Smin of the minimum processing dimension with the highest defect occurrence rate is reduced, so that the method of the present invention is applied. It can be said that the design layout pattern 72 after this has a lower defect generation rate than the temporary layout pattern 70.

Second Embodiment
A second embodiment of the method of the present invention will be described with reference to FIGS. In the first embodiment, the case where the wiring interval is assumed as the type of dimension constraint of the correction information has been described. However, in this embodiment, the case where the wiring width is assumed in addition to the wiring interval as the type of dimension constraint of the correction information. explain. The configuration of the semiconductor integrated circuit manufacturing apparatus that executes the method of the present invention of this embodiment is the same as that of the manufacturing apparatus 1 of the first embodiment shown in FIG.

  The method of the present invention according to this embodiment will be described with reference to FIGS.

  As shown in FIG. 2, the manufacturing apparatus 1 first acquires the design rule used in the temporary layout through the input / output unit 30 by the layout unit 11, and performs the temporary layout according to the acquired design rule (step # 101). ). Furthermore, the layout unit 11 stores the temporary layout result in the storage unit 20 after executing the temporary layout. Subsequently, the manufacturing apparatus 1 uses the correctable condition setting unit 12 to change the temporary layout pattern obtained by the temporary layout based on the chip size obtained by the temporary layout with respect to the chip size obtained from the design layout pattern. A correctable condition including constraints is set (step # 102, correctable condition setting step). The correctable condition of the present embodiment is the area of the design layout pattern, as in the first embodiment.

  Subsequently, the manufacturing apparatus 1 uses the correction information acquisition unit 13 to acquire a plurality of pieces of correction information composed of relaxed dimensional constraints obtained by gradually relaxing the dimensional constraints for each type of dimensional constraints (step # 103, correction information acquiring step). ). Furthermore, the manufacturing apparatus 1 sets the priority order for each of the acquired correction information by the priority order setting unit 14 (step # 104, priority order setting step). Here, FIG. 8 is a table showing an example of the relationship between the relaxed dimension constraint and the priority order. The relaxed dimension restrictions of this embodiment are the wiring intervals S1 to S5 and the wiring widths W1 to W5. Similarly to the first embodiment, the wiring intervals S1 to S5 are set such that the minimum processing size of the wiring interval Smin <wiring interval S1 <wiring interval S2 <wiring interval S3 <wiring interval S4 <wiring interval S5. Yes. The wiring widths W1 to W5 are set so that the minimum processing dimension of the wiring width Wmin <wiring width W1 <wiring width W2 <wiring width W3 <wiring width W4 <wiring width W5. Also, the priority order of the wiring intervals S1 to S5 and the wiring widths W1 to W5 is as follows: wiring interval S1 <wiring width W1 <wiring interval S2 <wiring width W2 <wiring interval S3 <wiring width W3 <wiring interval S4 <wiring width W4 < The wiring interval S5 <the wiring width W5 is set. That is, the priority is set so that the priority becomes higher as the relaxed dimension constraint in which the wiring interval is defined narrower, and the priority becomes higher in the relaxed dimension constraint in which the wiring width is narrower.

  Subsequently, the manufacturing apparatus 1 uses the correction processing unit 15 to perform correction processing on the temporary layout pattern using the correction information (step # 105, correction processing step). Hereinafter, the details of the correction processing step by the correction processing means 15 will be described with reference to FIGS. Here, FIG. 9A shows a partial region P3 of the temporary layout pattern including the correction target pattern as an example of the correction target pattern before the correction processing, and FIG. A region P3 ′ after the partial region P3 shown in FIG. Similarly, FIG. 10A shows a partial area P4 of the temporary layout pattern including the correction target pattern as an example of the correction target pattern before the correction processing, and FIG. The area P4 ′ after the partial area P4 shown in FIG.

  Specifically, as shown in FIG. 2, the correction processing means 15 first sequentially selects correction information used in the correction processing for the temporary layout pattern based on the priority order (step # 106). In the present embodiment, as in the first embodiment, correction information is selected in order from the highest priority. Hereinafter, a description will be given assuming that the wiring width W1 having the second priority shown in FIG. 8 is selected from the correction information.

  Subsequently, the correction processing means 15 extracts a correction target pattern from the temporary layout pattern based on the size constraint type of the selected correction information (step # 107). Specifically, when the wiring width W1 is selected as the type of dimension constraint in the correction information, the correction processing unit 15 extracts a wiring pattern c3 that does not satisfy the wiring width W1 as a correction target pattern in FIG. In FIG. 10A, the wiring pattern c4 that does not satisfy the wiring width W1 is extracted as a correction target pattern.

  Subsequently, as shown in FIG. 2, the correction processing means 15 performs a correction process on the correction target pattern for each correction target pattern (step # 108). Specifically, in FIG. 9A, the correction processing unit 15 of the present embodiment performs a process of increasing the wiring width on the adjacent pattern x31 side so as to satisfy the wiring width W1 with respect to the wiring pattern c3. In addition, in FIG. 10A, the correction processing unit 15 of the present embodiment performs a process of increasing the wiring width on the side of the adjacent pattern x42 so as to satisfy the wiring width W1 with respect to the wiring pattern c4.

  Subsequently, as shown in FIG. 2, the correction processing means 15 determines whether or not the correction processing result satisfies the relaxed dimension constraint and the correctable condition of the correction information having a higher priority than the selected correction information (Step #). 109) When the correction process result satisfies the relaxed dimension constraint and the correctable condition of the correction information having higher priority than the selected correction information (OK branch at step # 109), the correction process result is reflected in the temporary layout pattern. (Step # 110). In this embodiment as well, as in the first embodiment, FIG. 8 shows only the correction information used for the correction process in step # 108. However, in the determination process in step # 109, the minimum processing dimension is shown. The wiring interval Smin and the wiring width Wmin are treated as relaxed dimension constraints having the highest priority.

  Specifically, as shown in FIG. 9B, the correction processing means 15 of the present embodiment has a higher priority for the correction processing result for the wiring pattern c3 shown in FIG. 9A, as shown in FIG. 9B. Since the wiring interval is not less than S1 and each wiring width is not less than the wiring width Wmin of the minimum processing dimension, it is determined that the relaxed dimension constraint of the correction information having higher priority than the selected correction information is satisfied. Further, the chip size is obtained from the temporary layout pattern reflecting the correction result, and when the chip size area satisfies the correctable condition (OK branch at step # 109), the correction processing result is reflected in the temporary layout pattern ( Step # 110). Further, the correction processing means 15 of the present embodiment has a wiring processing interval between the wiring pattern c4 ′ and the adjacent pattern x42, as shown in FIG. 10B, for the correction processing result for the wiring pattern c4 shown in FIG. Therefore, since it is equal to or less than the wiring interval S1 having a higher priority, it is determined that the relaxed dimension constraint of the correction information having a higher priority than the selected correction information is not satisfied (NG branch in step # 109). In this case, the correction process is canceled and the correction process result is discarded without being reflected in the temporary layout pattern.

  The correction processing means 15 performs a correction processing step for sequentially correcting the temporary layout pattern for all the correction information shown in FIG. 8 (step # 112). In this way, the process of increasing the wiring interval and the wiring width is performed in order so as to satisfy the relaxed dimension constraint of the correction information having higher priority sequentially.

  The manufacturing apparatus 1 is obtained by correcting the temporary layout pattern at the final stage of the correction processing step by the control means 10 after the correction processing step of Step # 105 by the correction processing means 15 ends (No branch at Step # 112). The design layout pattern thus stored is stored in the storage means 20, and the design layout pattern is output in a desired data format according to the input from the outside by the input means 30.

  FIG. 11 shows a temporary layout pattern 110 before applying the method of the present invention of this embodiment and a design layout pattern 112 after applying the method of the present invention. A hatched portion in FIG. 11 indicates a region having a wiring interval 111 of the minimum processing dimension. As shown in FIG. 11, the temporary layout pattern 110 before applying the method of the present invention of this embodiment is designed based on the minimum processing dimension. On the other hand, as shown in FIG. 11, the design layout pattern 112 after applying the method of the present invention of the present embodiment has some of the regions having the wiring width 111 of the minimum processing dimension in the temporary layout pattern 110. The area that takes the wiring width 111 of the minimum processing dimension is reduced as compared with the temporary layout pattern 110 before applying the method of the present invention. Although the wiring width is not particularly shown, the design after applying the method of the present invention is reduced because the area having the minimum processing dimension with the highest defect occurrence rate is reduced as in the case of the wiring interval. It can be said that the layout pattern 112 has a lower defect generation rate than the temporary layout pattern 110.

<Another embodiment>
<1> In the first embodiment, the wiring intervals S1 to S5 are defined as relaxation dimension constraints. In the second embodiment, the wiring intervals S1 to S5 and the wiring widths W1 to W5 are defined as relaxation dimension constraints. It is not limited. As the relaxed dimension constraint, any parameter that can improve the manufacturing yield of the semiconductor integrated circuit, such as a reduction in the defect occurrence rate and a reduction in variation in the shape of the mask pattern transferred onto the wafer, can be set.

  In addition, the relaxed dimension constraint, for example, defines only the relaxed dimension constraint to be used first for each type of dimension constraint, and the relaxed dimension constraint used in the immediately preceding modification processing step is constant every time the modification processing step is performed. A new relaxation dimension constraint may be obtained by increasing the amount or a certain percentage, and the next correction processing step may be executed using this. In this case, for example, if the wiring interval and the wiring width are defined as the relaxed dimension constraints, the wiring interval in the temporary layout pattern is maximized and the wiring width is maximized within the range of the correctable condition. can do.

  <2> In each of the above embodiments, the restriction on the area of the chip size is defined as a condition that can be corrected. However, the present invention is not limited to this. For example, it may be a restriction on the length of the long side of the rectangular area that accommodates the entire design layout pattern and the length of the short side of the rectangular area, or may be defined by combining these restrictions.

  Furthermore, the correctable condition may include a restriction on the changeable range of the number of vertices of the correction target pattern after correction with respect to the number of vertices of the correction target pattern before correction extracted from the temporary layout pattern. This restriction can prevent the shape of the correction target pattern from becoming more complicated than necessary.

  <3> In each of the above embodiments, the priority order setting step (step # 104) may include a priority order correction step of correcting the priority order according to an external input. In this case, the priority order setting unit 14 receives the priority order via the input / output unit 30.

  The method of the present invention can be applied to a manufacturing apparatus for designing a standard cell type semiconductor integrated circuit, a manufacturing apparatus for designing a master slice type semiconductor integrated circuit, and the like.

1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit manufacturing apparatus that realizes a semiconductor integrated circuit manufacturing method according to the present invention; The flowchart which shows each process of the manufacturing method of the semiconductor integrated circuit concerning this invention The table | surface which shows the example of 1 relationship between the relaxation dimension restrictions used in 1st Embodiment of the manufacturing method of the semiconductor integrated circuit based on this invention, and a priority. Graph showing the relationship between wiring spacing and defect rate Schematic block diagram showing an example of a correction target pattern in the method for manufacturing a semiconductor integrated circuit according to the present invention Schematic block diagram showing an example of a correction target pattern in the method for manufacturing a semiconductor integrated circuit according to the present invention 1 is a schematic configuration diagram showing layout patterns before and after applying a first embodiment of a semiconductor integrated circuit manufacturing method according to the present invention; A table showing an example of a relationship between relaxed dimension constraints and priorities used in the second embodiment of the method of manufacturing a semiconductor integrated circuit according to the present invention. Schematic block diagram showing an example of a correction target pattern in the method for manufacturing a semiconductor integrated circuit according to the present invention Schematic block diagram showing an example of a correction target pattern in the method for manufacturing a semiconductor integrated circuit according to the present invention The schematic block diagram which shows the layout pattern before and behind applying 2nd Embodiment of the manufacturing method of the semiconductor integrated circuit which concerns on this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Manufacturing apparatus 10 Control means 11 Layout means 12 Correction possible condition setting means 13 Correction information acquisition means 14 Priority order setting means 15 Correction processing means 20 Storage means 30 Input / output means 70 Temporary layout pattern 71 Wiring interval 72 Design layout pattern P Correction target Pattern S Wiring interval W Wiring width m, c Wiring pattern x Adjacent pattern

Claims (7)

After performing a temporary layout according to the dimension constraints set based on the minimum processing dimension in the manufacture of a semiconductor integrated circuit, and changing the temporary layout pattern obtained by the temporary layout based on the chip size obtained by the temporary layout A correctable condition setting step for setting correctable conditions including restrictions on the chip size obtained from the design layout pattern of
Correction information acquisition step of acquiring a plurality of correction information consisting of relaxed dimension constraints that gradually relaxed the dimension constraints for each type of the dimension constraints;
A priority setting step for setting a priority for each of the correction information;
Sequentially selecting the correction information used in the correction process for the temporary layout pattern based on the priority order;
Extracting a correction target pattern from the temporary layout pattern based on the type of the dimension constraint of the selected correction information;
For each of the correction target patterns, it is determined whether the correction processing result for the correction target pattern satisfies the relaxed dimension constraint and the correctable condition of the correction information having a higher priority than the selected correction information,
The correction process for reflecting the correction process result in the temporary layout pattern when the correction process result satisfies the relaxed dimension constraint and the correctable condition of the correction information having a higher priority than the selected correction information. A process,
The method of manufacturing a semiconductor integrated circuit, wherein the correction processing step is repeatedly executed for each of the correction information.   The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the correction information includes the correction information in which a type of the dimension constraint is a wiring interval.   3. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the correction information includes the modification information in which a type of the dimension constraint is a wiring width.   The amendable condition is at least one of an area of a chip size obtained from the design layout pattern, a length of a long side of a rectangular region that accommodates the entire design layout pattern, and a length of a short side of the rectangular region. 4. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising a restriction on the two.   The said correction possible condition includes the restriction | limiting with respect to the changeable range of the vertex number of the correction target pattern after correction with respect to the vertex number of the correction target pattern before correction extracted from the said temporary layout pattern. The manufacturing method of the semiconductor integrated circuit of description.   6. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the priority order setting step includes a priority order correction step of correcting the priority order according to an external input.   7. A program for manufacturing a semiconductor integrated circuit, comprising a program step for executing each step in the method for manufacturing a semiconductor integrated circuit according to claim 1 on a computer.

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