JP4852263B2 - Semiconductor device manufacturing method and semiconductor device chip pattern correction program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which appropriate correction or transformation can be performed for a divided chip pattern. <P>SOLUTION: The method includes steps of: determining a plurality of computation areas A11, A12 adjacent to each other in a region where chip patterns P29, P30 of a semiconductor device are present on a design plane; forming a computation margin area 59 for each computation area A11 outside and adjacent to the computation area so as to expand the computation area A11 to the computation margin area 59; selecting chip patterns P29, P30 disposed even in a portion in the computation area A11 by each computation area A11, A12; correcting the chip patterns P29, P30 selected in the respective computation areas A11, A12; and fabricating a real pattern on a wafer based on the corrected chip patterns P29b, P30b. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a chip pattern correction program for a semiconductor device.

  The layout in the chip of the semiconductor device is created as a chip pattern, for example, in the GDSII data format. Even when a semiconductor device is manufactured based on this chip pattern, the actual pattern of the semiconductor device may be different from the chip pattern. Therefore, a chip pattern corrected for the manufacture of the semiconductor device is used so that the actual pattern matches the chip pattern. In manufacturing a semiconductor device, a chip pattern converted into a data format suitable for manufacturing is used. Thus, the chip pattern is corrected and the data format is converted prior to the manufacture of the semiconductor device.

  Conventionally, the correction of the chip pattern and the conversion of the data format of the chip pattern have been performed by the computer for each chip and each mask (see, for example, Patent Document 1).

In recent years, the amount of chip pattern data has increased due to miniaturization and integration of semiconductor devices. When chip pattern correction or chip pattern data format conversion is performed on a single chip by a computer, the memory capacity required for chip pattern correction exceeds the actual memory capacity, and swap memory is often used. became. Since the access speed of the swap memory is slower than that of the real memory, the required execution time is very large compared to the required CPU time under such circumstances, and the original performance of the software cannot be exhibited. Further, the CPU time required for correction and conversion is often proportional to the power of the number N of chip patterns to be corrected and converted. For this reason, the more figures there are, the more time it takes to process the chip. In order to reduce the required CPU time and the required execution time, it is conceivable to divide a range to be corrected or converted into a smaller range such as a chip, and process again for each divided range and then combine them again. However, since the chip pattern is divided depending on the divided range, there is a case where a figure including a minute step or an unevenness is generated when the divided chip pattern is subjected to processing such as correction to be combined. . Small steps and irregularities lowered the accuracy of the manufactured semiconductor device. That is, there is a case where appropriate correction and conversion processing cannot be performed by dividing.
JP 2003-43661 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method capable of performing appropriate correction and conversion on a divided chip pattern.

  Another object of the present invention is to provide a chip pattern correction program for a semiconductor device, which is executed by a computer capable of performing appropriate correction and conversion on the divided chip patterns.

A first feature of the present invention for solving the above problems is that a plurality of calculation areas are set in a region where a chip pattern of a semiconductor device exists on a design plane, and a plurality of calculations are performed for each of the plurality of calculation areas. A calculation margin area is provided so as to be adjacent to the outside of each area , and each of the plurality of calculation areas is expanded to the calculation margin area, and the expanded calculation area is selected from the chip patterns for each expanded calculation area . selecting a chip pattern that is disposed in a portion, respectively, and to correct the chip pattern which has been selected by each of the extended calculated area for each extended calculation area, the chip pattern of the corrected total calculated regions and it is arranged to overlap; and removing the overlapping portion of the arranged chip pattern overlapping the real pattern on the wafer based on the chip patterns removing the overlapping portion In a method of manufacturing a semiconductor device having forming a.

A second feature of the present invention is a design plane area in which a chip pattern of a semiconductor device is described which is described by one or a plurality of hierarchized files and is constituted by a plurality of cells corresponding to each file. One or a plurality of calculation areas, selecting a cell arranged at least in the calculation area for each calculation area, and a calculation area among the chip patterns described by the cells extracted for each calculation area Correct the chip pattern included even in part, arrange the corrected chip pattern of all calculation areas in an overlapping manner, remove the overlapping part of the overlapping chip pattern, and remove the overlapping part And forming a real pattern on a wafer based on the chip pattern.

A third aspect of the present invention includes the steps of setting a plurality of calculation area to the area in the presence of the chip pattern of the semiconductor device design plane, adjacent to each of the outer multiple calculation region for each of a plurality of calculation regions In this way, a calculation margin area is provided so that each of the plurality of calculation areas is expanded to the calculation margin area, and a chip arranged at least partially in each of the expanded calculation areas from the chip pattern for each extended calculation area a step of selecting a pattern, a step of correcting the chip pattern which has been selected by each of the extended calculation area extended calculated area for each, and the procedures of synthesizing the entire computational domain corrected, by post-synthesis computational domain boundaries the resulting semiconductor device chip pattern of a semiconductor device of the correction program for executing the steps of placing overlapping the chip patterns on a computer that degrade the accuracy of the A.

According to a fourth aspect of the present invention, there is provided a procedure for setting a plurality of calculation areas in a design plane area in which a chip pattern of a semiconductor device composed of a plurality of cells described in one or more files and arranged in a hierarchy is present. , A procedure for selecting at least a part of cells arranged in the calculation area for each calculation area, and a procedure for correcting a chip pattern partially included in the calculation area among the chip patterns described by the cells extracted for each calculation area And a chip pattern correction program for a semiconductor device for causing a computer to execute a procedure for superposing and arranging the corrected chip patterns of all calculation areas and a procedure for removing an overlapping portion of the chip patterns arranged in an overlapping manner. .

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can perform correction | amendment and conversion suitable for the divided | segmented chip | tip pattern can be provided.

  In addition, according to the present invention, it is possible to provide a chip pattern correction program for a semiconductor device, which can be executed by a computer and can perform appropriate correction and conversion on the divided chip patterns.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

(First embodiment)
As shown in FIG. 1, in the manufacturing method of the semiconductor device according to the first embodiment, first, in step S1, the semiconductor device is designed and chip data serving as a chip pattern is created. The chip data storage unit 1 stores the chip data.

  In step S2, a mask is designed based on the chip data, and a mask pattern serving as a chip pattern is created. The mask pattern storage unit 2 stores the mask pattern.

  In step S3, a mask is produced based on the mask pattern. In step S4, a semiconductor device is manufactured using a mask. Steps S2 and S3 can be omitted. In this case, in step S4, a semiconductor device is manufactured based on the chip data.

  As shown in FIG. 2, the design apparatus 3 according to the first embodiment includes a semiconductor device design unit 4, a mask design unit 5, a chip data storage unit 1, and a mask pattern storage unit 2. Yes. The semiconductor device design unit 4 and the mask design unit 5 include placement units 11 and 17, a local correction unit 12, a global correction unit 13, a format unit 14, a division unit 15, and a synthesis unit 16. The chip data storage unit 1 and the mask pattern storage unit 2 store uncorrected data, local correction data, global correction data, and drawing data. In the semiconductor device manufacturing apparatus, the semiconductor device design unit 4 only needs to include the placement unit 11, and the local correction unit 12, the global correction unit 13, the format unit 14, the division unit 15, and the synthesis unit 16 are not necessarily included. There is no. Further, the chip data storage unit only needs to store drawing data, and it is not always necessary to store local correction data and global correction data. On the other hand, in the semiconductor device manufacturing method, when the mask is not designed, for example, when the chip pattern of the semiconductor device is directly drawn on the semiconductor substrate, the mask design unit 5 and the mask pattern storage unit 2 are not necessarily required.

  The placement unit 11 generates a chip pattern of a chip of a semiconductor device in which cell and wiring patterns are placed. The generated chip pattern is stored as uncorrected chip data. On the other hand, the placement unit 17 generates a chip chip pattern in which a chip pattern is placed. The generated chip pattern is stored as an uncorrected mask pattern. Hereinafter, the local correction unit 12, the global correction unit 13, the format unit 14, the division unit 15, and the synthesis unit 16 can be executed in the same manner regardless of whether they are chip data or mask patterns. Therefore, in the following description, the arrangement site 17, the local correction unit 12, the global correction unit 13, the format unit 14, the division unit 15, and the synthesis unit 16 in the mask design unit 5 will be described. A description of the correction unit 12, the global correction unit 13, the formatting unit 14, the dividing unit 15, and the combining unit 16 is omitted.

  The design apparatus 3 may be a computer, and the design apparatus 3 may be realized by causing a computer to execute a procedure written in a program.

  As shown in FIG. 3, in the mask design method in step S2 according to the first embodiment, first, in step S11, the placement unit 17 places the chip pattern of the chip on the mask design plane. A correction mask pattern is generated. The uncorrected mask pattern is stored in the uncorrected data storage unit 2a in the mask pattern storage unit 2.

  Next, in step S12, the local correction unit 12 performs local correction of the chip pattern of the uncorrected mask pattern. Specifically, optical proximity effect correction (OPC) is performed. After correction, a local correction mask pattern, which is a chip pattern, is generated. The mask pattern for local correction is stored in the local correction data storage unit 2b in the mask pattern storage unit 2.

  In step S13, the mask pattern is globally corrected with mask pattern division and synthesis. Step S13 has steps S14 to S16.

  In step S14, the dividing unit 15 divides the chip pattern of the mask pattern for local correction. A divided mask pattern which is a chip pattern after division is generated. The divided mask pattern is stored in the divided data storage unit 2e in the mask pattern storage unit 2.

  In steps S15a to S15c, the global correction unit 13 performs global correction of the chip pattern of the divided mask pattern. The plurality of divided mask patterns can be executed in parallel at a plurality of steps S15a to S15c, specifically, independently at an arbitrary time. If a plurality of steps S15a to S15c are performed simultaneously, the time required for the implementation can be shortened. Then, a global correction mask pattern, which is a corrected chip pattern, is generated. The global correction mask pattern is stored in the divided global correction data storage unit 2 f in the mask pattern storage unit 2.

  In step S16, the synthesizing unit 16 synthesizes the chip pattern of the mask pattern which is divided and globally corrected. A so-called global correction mask pattern, which is a synthesized and globally corrected chip pattern, is generated. The global correction mask pattern is stored in the global correction data storage unit 2 c in the mask pattern storage unit 2.

  In step S17, the format unit 14 performs format conversion of the chip pattern of the mask pattern which has been globally corrected, and drawing data is generated. The drawing data is stored in the drawing data storage unit 2d in the mask pattern storage unit 2.

  The mask design method can be expressed by a mask design program executable by a computer as a procedure. A mask design method can be implemented by causing a computer to execute the mask design program.

  As shown in FIG. 4, the mask design method in step S2 according to the first modification of the first embodiment is compared with the mask design method in step S2 in FIG. The format of S17 is different in that it involves the division of the mask pattern in steps S22 and S25 and the synthesis of the mask pattern in steps S23 and S26. The division sizes of the mask patterns for the division in steps S22, S14, and S25 do not have to be the same, and can be determined as appropriate according to the respective corrections of the divided mask patterns and the processing time of the format.

  In step S21, local correction of the mask pattern is performed with the division and synthesis of the mask pattern. Step S21 has steps S22, S12, and S23.

  In step S22, the dividing unit 15 divides the chip pattern of the uncorrected mask pattern. A divided mask pattern which is a chip pattern after division is generated. The divided mask pattern is stored in the divided data storage unit 2e in the mask pattern storage unit 2.

  In step S12, the local correction unit 12 performs local correction of the chip pattern of the divided mask pattern. A locally corrected mask pattern, which is a corrected chip pattern, is generated. The mask pattern for local correction is stored in the divided local correction data storage unit 2g in the mask pattern storage unit 2.

  In step S23, the synthesizing unit 16 synthesizes the chip pattern of the mask pattern that has been divided and locally corrected. A so-called local correction mask pattern which is a synthesized and locally corrected chip pattern is generated. The mask pattern for local correction is stored in the local correction data storage unit 2b in the mask pattern storage unit 2.

  In step S24, the mask pattern is formatted with mask pattern division and synthesis. Step S24 has steps S25, S17, and S27.

  In step S25, the dividing unit 15 divides the chip pattern of the mask pattern for global correction. A divided mask pattern which is a chip pattern after division is generated. The divided mask pattern is stored in the divided data storage unit 2e in the mask pattern storage unit 2.

  In step S17, the formatting unit 14 formats the chip pattern of the divided mask pattern. Drawing data which is a chip pattern after formatting is generated. The drawing data is stored in the divided drawing data storage unit 2h in the mask pattern storage unit 2.

  In step S26, the synthesizing unit 16 synthesizes the chip pattern of the mask pattern divided and formatted. Drawing data that is a synthesized and formatted chip pattern is generated. The drawing data is stored in the drawing data storage unit 2d in the mask pattern storage unit 2.

  As shown in FIG. 5, the mask design method in step S2 according to the second modification of the first embodiment is different from the mask design method in step S2 in FIG. The difference is that it is performed before the local correction in step S12, and the composition of the mask pattern in step S26 is performed after the format of the mask pattern in step S17. According to this, it is possible to enjoy the effect of the division in the local correction in step S12, the global correction in step S15, and the format in step S17 by one division and synthesis.

(Second Embodiment)
As shown in FIG. 6, the mask pattern dividing / combining apparatus 18 according to the second embodiment includes a mask pattern dividing unit 15 and a mask pattern combining unit 16. The mask pattern dividing unit 15 can be used as the dividing unit 15 of FIG. The mask pattern combining unit 16 can also be used as the combining unit 16 of FIG. The mask pattern dividing unit 15 includes a calculation region setting unit 21, a calculation margin region setting unit 22, and a mask pattern selection unit 23. The mask pattern combining unit 16 includes a correction pattern arranging unit 24 and an overlap removing unit 25.

  The mask pattern dividing / synthesizing apparatus 18 may be a computer, and the mask pattern dividing / synthesizing apparatus 18 may be realized by causing a computer to execute a procedure written in a program.

  As shown in FIG. 7, in the mask pattern dividing method according to the second embodiment, first, in step S31, the calculation area setting unit 21 is a semiconductor device on a design plane on which a mask pattern chip pattern is arranged. A plurality of calculation areas are set in the area where the chip pattern exists.

  In step S32, the calculation margin area setting unit 22 sets a calculation margin area so as to be adjacent to the outside of the calculation area for each calculation area, and extends the calculation area to the calculation margin area.

  In step S <b> 33, the mask pattern selection unit 23 selects a chip pattern arranged at least in the calculation area for each calculation area. A plurality of selected chip patterns for each calculation area are collectively stored as a chip pattern division file for each calculation area. As a result, processing such as global correction of divided files can be performed for each calculation area. The CPU time required for processing such as global correction is often proportional to the power of the figure pattern number (N) to be processed, and the total CPU time can be shortened as compared with the case of no division. That is, processing such as global correction can be performed at high speed. In addition, it is possible to reduce the amount of real memory used by making the processing file smaller by dividing.

  The mask pattern dividing method can be expressed by a mask pattern dividing program executable by a computer as a procedure. By causing the computer to execute this mask pattern dividing program, the mask pattern dividing method can be implemented.

  As shown in FIG. 8, in the mask pattern synthesis method according to the second embodiment, first, in step S41, the correction pattern placement unit 24 places the mask patterns of a plurality of calculation regions on the design plane. To do.

  In step S42, the overlap removing unit 25 removes the overlapped portion of the chip patterns arranged in an overlapping manner.

  The mask pattern synthesis method can be expressed by a mask pattern synthesis program executable by a computer as a procedure. By causing the computer to execute the mask pattern synthesis program, the mask pattern synthesis method can be implemented.

  As shown in FIG. 9, the pattern file division / synthesis apparatus 31 according to the third embodiment is different from the mask pattern division / synthesis apparatus 18 of the second embodiment shown in FIG. Furthermore, the point which has the cell selection part 34, the file extraction part 35, and the division | segmentation pattern production | generation part 36 differs. The pattern file is data in which mask patterns are hierarchized. The mask pattern is composed of large-scale cells, and the large-scale cell is composed of small-scale cells. Similarly, the mask pattern can be described using a large-scale cell. Therefore, it is convenient if division and composition can be performed while maintaining the cell structure.

(Third embodiment)
A pattern file dividing / combining apparatus 31 according to the third embodiment includes a pattern file dividing unit 15 and a pattern file combining unit 16. The pattern file dividing unit 15 can be used as the dividing unit 15 in FIG. The pattern file composition unit 16 can also be used as the composition unit 16 in FIG.

  The pattern file division / synthesis apparatus 31 may be a computer, and the pattern file division / synthesis apparatus 18 may be realized by causing a computer to execute a procedure written in a program.

  As shown in FIG. 10, the pattern file dividing method according to the third embodiment is the same as step S31 and step S32 in comparison with the mask pattern dividing method according to the second embodiment. The chip pattern of the semiconductor device is described by a plurality of hierarchical files. The chip pattern of the semiconductor device is composed of a plurality of hierarchical cells. Each of the plurality of cells corresponds to a file. A large file is described by multiple small files. A chip pattern of a semiconductor device is described by a plurality of large-scale files. A large-scale cell is composed of a plurality of small-scale cells. A chip pattern of the semiconductor device is constituted by a plurality of large-scale cells. Each of the plurality of large cells corresponds to a large file. Each of the small cells corresponds to a small file.

  Next, in step S34, the cell selection unit 34 selects, for each calculation area, a large-scale cell and a small-scale cell that are at least partially arranged in the calculation area.

  In step S35, the file extraction unit 35 extracts, for each calculation area, a large file that can lay out the selected large cell and a small file that can lay out the selected small cell. Note that the plurality of files extracted for each calculation area are collectively stored as chip pattern division files for each calculation area. As a result, processing such as global correction of divided files can be performed for each calculation area. The extraction is performed while maintaining the file hierarchy. On the contrary, for each calculation area, unselected cells may be deleted from the hierarchical file while maintaining the hierarchy.

  In step S36, the division pattern generation unit 36 performs layout based on the extracted large-scale file and small-scale file, and generates a divided mask pattern.

  In step S33, the mask pattern selection unit 23 selects a mask pattern arranged at least in the calculation area for each calculation area.

  As shown in FIG. 11, the pattern file synthesizing method according to the third embodiment can be performed in the same manner as the pattern file synthesizing method of the second embodiment shown in FIG.

(Fourth embodiment)
As illustrated in FIG. 12, the global correction unit 13 according to the fourth embodiment includes a correction region dividing unit 41, a global correction amount setting unit 42, and a correction region correction unit 43. The global correction unit 13 can be used as the global correction unit 13 of FIG. The global correction amount setting unit 42 includes a pattern density calculation unit 44, a pattern density / roughness / correction amount relationship storage unit 45, a coarse / dense correction amount calculation unit 46, an etching rate ratio storage unit 47, and an etching rate ratio and position correction amount relationship storage. Part 48, position correction amount calculating part 49 and summing part 50.

  As shown in FIG. 13, in the global correction according to the fourth embodiment, first, in step S51, the correction area dividing unit 41 sets a plurality of correction areas in the area where the mask pattern exists based on the mask pattern. Set to touch each other. The area where the mask pattern exists is divided by a plurality of correction areas.

  In step S52, the global correction amount setting unit 42 sets the global correction amount of the mask pattern for each of a plurality of correction areas. Step S52 has steps S54 to S60. In step S54, the pattern density calculation unit 44 calculates the distribution of the pattern density of the mask pattern. In step S55, the relationship storage unit 45 between the pattern density and the density correction amount stores the relationship between the pattern density and the density correction amount. In step S56, the density correction amount calculation unit 46 sets the density correction amount for each of the plurality of correction areas. In step S57, the etching rate ratio storage unit 47 acquires and stores the distribution of the etching rate ratio in the mask surface. In step S58, the relationship storage unit 48 between the etching speed ratio and the position correction amount stores the relationship between the etching speed ratio and the position correction amount. In step S59, the position correction amount calculation unit 49 sets a position correction amount for each of a plurality of correction regions. In step S60, the summation unit 50 obtains the sum of the fine correction amount and the position correction amount as a global correction amount for each of a plurality of correction regions.

  In step S53, the correction area correction unit 43 corrects the mask pattern arranged in the correction area for each correction area by the global correction amount set in the correction area.

  In the first embodiment, correction of global dimensional variation will be specifically described.

  The global dimensional variation is that the final pattern of the semiconductor device changes gently in relation to the position where the semiconductor device is placed, and position dependency occurs in the error from the chip pattern. Examples of this cause include overexposure due to reflected electrons during mask drawing (fogging effect), and due to variations in the progress rate of the etching process (loading effect). Some of the global dimensional variations are caused by the shape of the chip pattern itself, such as the density distribution of the chip pattern, and others are not dependent on the shape of the chip pattern, such as placement points on the mask where the pattern is placed. . Correcting this variation and removing the position dependence of the pattern of the semiconductor device is called global dimensional variation correction or simply global correction. As a method for correcting the global dimensional variation, for example, there are a method for adjusting the electron beam irradiation amount at the time of mask drawing, a method for correcting the chip pattern in advance before drawing, and a method for adjusting parameters of the process apparatus. . In this example, a method for correcting the chip pattern in advance is shown.

  As shown in FIG. 14, chip patterns A to C of the chips of the semiconductor device are arranged on the design plane. These chips form a mask pattern 51.

  As shown in FIG. 15, one or a plurality of correction areas are set on the mask pattern 51. The correction area may be set on the entire mask surface, or may be set only on a portion requiring correction. The shape of the correction area can be arbitrarily selected, and may be arranged so as to be in contact with each other or may be arranged with a gap therebetween. The size of the correction area depends on the event to be corrected. FIG. 15 shows an example in which a plurality of correction regions a11 to a66 are arranged so as to contact each other so as to cover the entire mask pattern 51. The correction areas a11 to a66 have a rectangular shape and are arranged for each grid of the columns l1 to l6 and the rows r1 to r6.

  Next, a density distribution of the chip pattern is created, and a correction amount of the global variation amount depending on the density distribution is obtained. As shown in FIG. 16, the area density calculation regions b11 to b66 are set to contact each other so as to cover the entire mask pattern 51. The area density calculation region group needs to cover the mask pattern 51 so that there is no gap or overlap. In addition, as shown in FIG. 17, when the correction area is arranged so that the entire mask pattern does not have a gap or overlap, the correction area can be used as an area density calculation area. For each area density calculation region, the ratio (area density) occupied by the chip pattern in the area density calculation region is calculated.

  Further, the density correction amount for each correction region is obtained from the area density distribution. The relationship between the area density distribution and the density correction amount is acquired in advance by performing a test using TEG or the like. In general, the relationship between the area density and the density correction amount is not unique, and is a function that also considers the surrounding area density distribution. As an example, FIG. 18 shows a correspondence table when the relationship between the pattern density and the density correction amount is uniquely determined. Using the correspondence table of FIG. 18, as shown in FIG. 19, the correction amount for each of the correction areas a11 to a66 is obtained.

  Next, a position-dependent correction amount on the mask 51 is obtained and added to the density correction amount. The position-dependent correction amount is due to, for example, the reaction rate fluctuating due to unevenness of the reaction solution during etching and the like, and does not depend on the mask chip pattern but on the pattern arrangement point on the mask. As shown in FIG. 20, the etching rate ratio of chromium depending on the position on the mask is obtained by performing actual etching in advance and measuring. Note that the etching rate ratio is the ratio of the etching rate at the place of interest to the maximum value of the etching rate in the plane of the mask 51.

  As shown in FIG. 21, the relationship between the etching rate ratio and the position correction amount is stored. The relationship between the etching rate ratio and the position correction amount is obtained in advance by performing a test using TEG or the like. Further, the relationship between the direct position and the correction amount may be obtained without using the etching rate ratio.

  As shown in FIG. 22, using the etching rate ratio in the correction regions a11 to a66 in FIG. 20 and the relationship between the etching rate ratio and the position correction amount in FIG. Set.

  As shown in FIG. 23, the sum of the precise correction amount of FIG. 19 and the position correction amount of FIG. 22 is obtained as a global correction amount for each of the plurality of correction regions a11 to a66.

  Finally, for each of the correction areas a11 to a66, the mask patterns A to C arranged in the correction areas a11 to a66 are corrected by the global correction amount set in the correction areas a11 to a66.

  For example, the loading effect can be corrected by the above method. The loading effect is one of the major factors of the global pattern size deterioration on the mask 51 in recent years.

When correcting the loading effect, the mask 51 is divided into correction areas, and resize processing is performed in advance on figures belonging to the respective correction areas. The correction area is divided into meshes of about 1 mm ² according to the area of the variable range. The correction amount at each point can be obtained as the sum of the position-dependent correction amount and the density correction amount.

  In the second embodiment, a description will be given of a case where the global dimensional variation correction shown in the first embodiment is developed and the correction area is doubled in the primary and secondary directions.

  As shown in FIG. 24, the chip pattern D of the semiconductor device is arranged on the design plane. As shown in FIG. 25, as in the first embodiment, a plurality of correction areas am11 to am33 are set in contact with each other in an area where a chip pattern exists. This is called a positive correction area. The positive correction areas am11 to am33 are arranged for each grid of columns LM1 to LM3 and rows RM1 to RM3. Further, as shown in FIG. 26, the sub correction areas as11 to as44 are shifted from the main correction area and set so as to contact each other in the area where the chip pattern exists. The sub correction areas as11 to as44 are provided for each grid of the columns LS1 to LS4 and the rows RS1 to RS4. The sub correction areas may be arranged so as to overlap with the main correction area when the half-grid is moved obliquely as shown in FIG. 26, or overlap when moved in the vertical direction as shown in FIG. As shown in FIG. 28, they may be arranged so as to overlap when moved in the left-right direction, or these may be combined.

  As shown in FIG. 29, the large local correction amounts DM11 to DM33 for each of the positive correction areas am11 to am33 are set by the method shown in the first embodiment. Further, as shown in FIG. 30, the sub global correction amounts DS11 to DS44 for the sub correction areas as11 to as44 are set by the same method.

  Next, a pattern to be corrected in each correction area is selected. First, for each positive correction area, a pattern that is completely included in the positive correction area is selected. For example, as shown in FIG. 31, it is assumed that some patterns P1 to P3 of the mask pattern are arranged in the positive correction areas am22 to am33. As shown in FIG. 32, the pattern P2 is completely included in the main correction area am32, is selected as a pattern included in this correction area, and is corrected with the correction amount in the main correction area am32. Further, as shown in FIG. 33, the patterns P1 and P3 are arranged on the grid of the main correction region, and therefore do not satisfy the above condition and remain unselected.

  Next, as shown in FIG. 34, for each sub correction area, a pattern that is completely included in the sub correction area is selected. As shown in FIG. 35, the pattern P3 is included in the sub correction area as33 and is selected and corrected as a pattern belonging to this correction area. On the other hand, as shown in FIG. 36, the pattern P1 is arranged on the grid of the sub correction area, does not satisfy the above condition, and remains unselected.

  The remaining pattern P1 is corrected with the correction amount of the main or sub correction area. For example, as shown in FIG. 37, the pattern P1 is divided on the boundary between the positive correction regions as22 and as32 and arranged as patterns P11 and P12. As shown in FIG. 38, the patterns P11 and P12 are selected as figures belonging to the main correction areas am22 and am32, respectively, and are corrected with the respective correction amounts. As a result of the correction, a level difference is generated in the pattern P1 in a grid pattern of the main correction region. In some of such steps, a fine shot may be required during mask drawing. In general, minute shots are severely degraded in accuracy, and are desirably removed. For this reason, as shown in FIG. 39, a process of removing a step generated between the corrected patterns P11 and P12 is performed. Specifically, the pattern P13 is generated so as to be adjacent to the pattern P12, or the peripheral pattern P14 is removed from the pattern P11, thereby eliminating the step between the pattern P11 and the pattern P12.

  In the third embodiment, a case where a correction margin area is provided in each correction area will be described as a modification of the global dimensional variation correction of the second embodiment. That is, in each area, a correction margin area is provided in the positive correction area so as to extend outside the positive correction area, and a pattern completely included in this area is selected. The third embodiment is the same as the second embodiment until the pattern completely included in the positive correction area and the sub correction area is extracted and correction is performed. Next, each of the positive correction areas am11 to am33 is expanded outward, a correction margin area is provided, and a pattern that is completely included in the expansion area including the correction margin area is selected. Specifically, in the example of the second embodiment, as shown in FIG. 40, a correction margin area is added to the positive correction area am32 and an extended area 53 is provided. Next, as shown in FIG. 41, a pattern that is completely included in the extended region 53, that is, a pattern P4 is selected and corrected with the correction amount DM32 in the positive correction region am32. Similar processing is performed for all the correction areas am11 to am33. Since the extended areas overlap each other, some patterns may be selected as a plurality of areas, but may belong to only one area or may belong to all areas.

  Thereafter, the process proceeds to FIG. 37 of the second embodiment, and the following is performed in the same manner as the second embodiment. In the third embodiment, the extended area 53 is provided only in the positive correction area of the second embodiment. However, the extended area 53 may be provided in both the positive correction area and the sub correction area. Further, the process using the sub correction area may be omitted.

  In the fourth embodiment, a method for dividing a mask pattern into a plurality of calculation areas will be described in detail. Similarly to the first embodiment, in the fourth embodiment, as shown in FIG. 14, the mask 51 is arranged on the design plane, and the chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. To do. With regard to the division processing, attention is particularly paid to the chip pattern A. Similar processing is performed for the chip patterns B and C.

  One or more calculation areas are set in the area where the chip pattern A exists. The calculation area only needs to be set to an area necessary for processing, and the size, shape, number, and the like can be arbitrarily set. In FIG. 43, a plurality of calculation areas A11 to A22 are set in contact with each other in the area where the chip pattern A exists. The calculation areas A11 to A22 are arranged for each grid of columns L1 to L2 and rows R1 to R2. The calculation areas A11 to A22 are set to a size including a plurality of correction areas. Note that the boundary between the calculation areas may or may not coincide with the boundary between the correction areas. The widths dr1 and dr2 in the rows R1 to R2 of the calculation areas A11 to A22 may be equal to or smaller than the width drc in the chip pattern A from the rows R1 to R2. That is, the widths dr1 and dr2 may be equal or not equal, and the width drc may be divided into three or more by the widths dr1 and dr2, or may not be divided. Further, the widths dl1 and dl2 of the calculation areas A11 to A22 in the rows L1 to L2 may be less than or equal to the width dlc of the chip pattern A in the rows L1 to L2. The widths dl1 and dl2 may be equal or may not be equal, and the width dlc may be divided into three or more by the widths dl1 and dl2, or may not be divided.

  Next, for each calculation area, a pattern included in the calculation area is selected. For example, as shown in FIG. 44, it is assumed that a plurality of patterns P21 to P25 are arranged in the vicinity of the boundary 54 between the calculation areas A11 and A12. That is, as patterns that are completely included in the calculation area A11, patterns P21 and P23 are patterns that are completely included in the calculation area A12, patterns P24 and P25 are patterns that extend across the boundary between the calculation areas A11 and A12, and pattern P22. Has been placed. Of these patterns, patterns P21 and P23 are selected as patterns belonging to the calculation area A11, and patterns P24 and P25 are selected as patterns belonging to the calculation area A12. In addition, as shown in FIGS. 45 and 46, the pattern P22 extending over a plurality of calculation areas is assigned to all the areas included in any one of the calculation areas A11 and A12, as shown in FIGS. As shown in FIG. 49, the division is performed on the region boundary, the division pattern P22a of the pattern P22 is arranged in the calculation region A11, and the division pattern P22b is arranged in the calculation region A12. As shown in FIG. 49 and FIG. Or the method of arrange | positioning to either one of A12 can be considered. Any of these methods may be used as long as there is no problem in the subsequent processing. The plurality of selected chip patterns P21, P22, and P23 in the calculation area A11 are collectively stored as chip pattern division files corresponding to the calculation area A11. The plurality of selected chip patterns P22, P24, and P25 in the calculation area A12 are collectively stored as chip pattern division files corresponding to the calculation area A12. As a result, processing such as global correction of the divided files for the calculation areas A11 and A12 can be performed completely independently.

  If the divided calculation areas A11 to A22 and their divided files are appropriately made small by using the above dividing process, the memory usage can be reduced, and the execution time at the time of processing may be remarkably improved. This is especially noticeable when the data file before division is large, the real memory is insufficient, and the swap memory is used. In addition, the algorithm efficiency can be improved by reducing the number of patterns to be processed at one time. Further, since each of the divided areas A11 to A22 can be processed completely independently, it is effective even when parallel processing is used. For example, in the case of correcting the loading effect, if the correction is performed without using the division processing, the processing that took the CPU time of 200000 sec and the execution time of 500000 sec can be reduced to the CPU time of 120,000 sec and the execution time of 120,000 sec by using the division. Furthermore, when parallel processing was performed by two CPUs, the execution time could be reduced to 65000 seconds.

  In this method, the data size input to a general CAD tool is reduced to solve the above-described problem of a decrease in processing speed caused by a memory shortage, and the correction itself or the correction can be speeded up. Furthermore, high-precision LSI manufacturing is enabled by recombining with corrected data of other calculation areas, which will be described later. This method of dividing into calculation regions is particularly effective when the correction amount depends on the position on the mask.

  In the fifth embodiment, a problem that occurs during the synthesis of a mask pattern and a solution to the problem will be described. In the fifth embodiment, as in the first and fourth embodiments, as shown in FIG. 14, a mask 51 is arranged on the design plane, and chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. Suppose that Also in the fifth embodiment, similarly to FIG. 43 of the fourth embodiment, a plurality of calculation areas A11 to A22 are set in the area where the chip pattern A exists.

  Consider a case where the pattern P26 is divided into the patterns P26d and P26e on the boundary of the calculation area as shown in FIGS. 51 (b) and 51 (c) by the dividing method of the fourth embodiment. Thereafter, as shown in FIGS. 51 (d) and 51 (e), when global correction is performed and synthesis is performed, a step may occur at the boundary of the calculation area as shown in FIG. 51 (f). . This level difference is not eliminated by overlapping removal.

The level difference increases the number of shots at the time of mask drawing, and may deteriorate the accuracy of the pattern drawn on the mask. Improving the accuracy of LSI is the most important issue, and deterioration in drawing accuracy at the time of mask creation is not recognized even if the processing speed is increased. In particular, when drawing with very high accuracy is required, such as a gate pattern of a memory product, a problem of a connection error between shots that occurs when a figure that can be drawn with one shot is drawn with a plurality of shots cannot be ignored. Furthermore, it may occur that a minute shot as described above is required, which may be a major factor in deterioration of accuracy.

  Assume that the pattern P26 is arranged on the boundary between the calculation areas A11 and A12 as shown in FIG. For each of the calculation areas A11 and A12, a pattern arranged at least partially in each area is selected. That is, the pattern P26 is selected in both the calculation areas A11 and A12 as shown in FIGS. 52 (b) and 52 (c).

  Further, as shown in FIGS. 52 (d) and 52 (e), the patterns included in each of the calculation areas A11 and A12 are processed. Processing may be any of global correction, local correction, and format conversion to drawing data. Specifically, consider the case of the global correction described above. It is assumed that the pattern P26 belonging to the calculation area A11 is further selected as a figure belonging to the positive correction area am13, and the pattern P26 belonging to the calculation area A12 is further selected as a figure belonging to the positive correction area am14. The correction areas am13 and am14 may be the same or different. Pattern P26 is corrected in correction area A13, pattern P26a is corrected in correction area A14, and pattern P26b is generated.

  Next, the data processed for each of these calculation areas is synthesized. As shown in FIG. 52 (f), the patterns P26a and P26b processed in the calculation areas A11 and A12 are arranged so as to overlap each other in the design plane.

  Finally, as shown in FIG. 52 (g), the overlapping portion is removed from the patterns P26a and P26b arranged in an overlapping manner.

  By this process, the problem of minute steps in the division and synthesis processes can be solved, an increase in the number of shots can be suppressed, and a highly accurate mask can be manufactured.

  In the sixth embodiment, following the fourth embodiment, a mask pattern dividing method will be specifically described, particularly for a huge pattern that extends over a plurality of calculation areas.

  In the sixth embodiment, similarly to the first embodiment, as shown in FIG. 14, the mask 51 is arranged on the design plane, and the chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. To do. In addition, a plurality of calculation areas A11 to A33 are set in the chip pattern A. Further, as shown in FIG. 53, the chip pattern A is assumed to include a huge pattern P27 and a pattern P28 that extend over a plurality of calculation areas A11, A21, and A31.

  For these calculation patterns A11, A21, and A31, a pattern that is partially arranged in each area is selected. Specifically, as patterns included in A31, patterns P27 and P28 as shown in FIG. 54 (a), and as patterns included in A21, pattern P27 as shown in FIG. As shown in FIG. 54 (c), the pattern P27 is selected as the pattern included in. The pattern P27 arranged in the three calculation areas A11, A21, and A31 is selected for each of the calculation areas A11, A21, and A31, thereby avoiding the step problem at the boundary when the calculation areas are combined. be able to.

  In the seventh embodiment, a mask pattern dividing / synthesizing method will be described specifically with respect to problems and solutions for an example including a case where a single figure is composed of a plurality of patterns.

  In the seventh embodiment, as in the first and fourth embodiments, as shown in FIG. 14, a mask 51 is arranged on the design plane, and chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. Suppose that Also in the seventh embodiment, as in FIG. 43 of the fourth embodiment, a plurality of calculation areas A11 to A22 are set in the area where the mask pattern A exists.

  As shown in FIG. 55 (a), it is assumed that patterns P31 and P32 are arranged in the vicinity of the boundary between calculation regions A11 and A12. Patterns P31 and P32 are in contact with each other and form one figure. The divisional synthesis method of the fifth and sixth embodiments is applied to this pattern. First, as shown in FIG. 55 (b), a pattern P31 is selected as a pattern that is partly included in the calculation region A11. Similarly, as shown in FIG. 55 (c), patterns P31 and P32 are selected as patterns arranged at least in the calculation area A12.

  As shown in FIGS. 55 (d) and 55 (e), correction processing is performed on these selected patterns. That is, the pattern P31 belonging to the calculation area A11 is corrected, and the pattern P31a is arranged. Similarly, pattern P31 arranged in calculation area A12 is corrected to pattern P31b, and pattern P32 is corrected to P32a.

  If all the calculation areas are combined after correction, there may be a step in the vicinity of the boundary between the patterns P31a and P32a and P31b as shown in FIG. 55 (f). This step does not disappear even if the pattern P32b is generated by removing overlap as shown in FIG. 55 (g), which may lead to deterioration of drawing accuracy.

    In many data formats, one figure is generally composed of a plurality of patterns as in the above example. The above problem arises when a graphic composed of a plurality of patterns is arranged on a calculation region boundary so as to extend over a plurality of regions. As a solution, all the patterns constituting the figure may be arranged in a plurality of areas. However, generally, the pattern information does not describe the proximity conditions (contact, overlap, etc.) between the patterns. For this reason, it is very inefficient to select all the patterns composing a figure at high speed and place them in each calculation area, considering the processing time and other problems.

  In order to solve the above problem, a calculation margin area is set. As shown in FIG. 56, it is assumed that patterns P29 and P30 are arranged in the vicinity of the boundary between the calculation area A11 and the calculation area A12. It is assumed that the patterns P29 and P30 are in contact with each other and form one figure. As shown in FIG. 57, a calculation margin area 59 is set so as to contact the outside of the calculation area A11, and a new boundary 61 is provided. As a result, the calculation area A11 extends to the boundary 61.

  Next, a pattern arranged in part in the expanded calculation area A11 is selected. For example, as shown in FIG. 57, patterns P29 and P30 are both selected as patterns included in the expanded calculation area A11 without being separated.

  Next, the patterns P29 and P30 are processed in the calculation area A11. Processing may be any of global correction, local correction, and data conversion. For example, in the case of global correction, as shown in FIG. 58, patterns P29 and P30 are corrected to patterns P29b and P30b, respectively, as a result of processing in calculation area A11. However, no step is formed near the boundary between P29b and P30b. .

  Similarly, the expansion process for the calculation area A12 is performed. As shown in FIGS. 59 and 60, the calculation margin area 60 is also set so as to be in contact with the outside of the calculation area A12, and the calculation area A12 is extended to the boundary 61. Further, both patterns P29 and P30 are selected as patterns arranged even in part in the expanded calculation area A12.

  Next, as shown in FIG. 61, the selected patterns P29 and P30 are corrected. The patterns P29 and P30 are corrected as patterns belonging to the calculation area A12, respectively, and are converted into patterns P29d and P30d, respectively. In this case as well, no new step is generated near the boundary between the patterns P29d and P30d.

  Next, the calculation areas are synthesized. As shown in FIGS. 62 and 63, the patterns P29b and P30b corrected in the calculation area A11 and the patterns P29d and P30d corrected in the calculation area A12 are combined. As shown in FIG. 64, the respective patterns are arranged so as to overlap each other in a compound word forming plane.

  Further, as shown in FIG. 65, overlapping portions of the patterns P29b and P30b and the patterns P29d and P30d arranged in an overlapping manner are removed. There is no step in the resulting figure.

  The relationship between the calculation area A11, the expanded calculation area A11 including the calculation margin area 59, and the selected pattern will be described together in FIG. Patterns P41 to P43 are selected as figures included in the calculation area. In addition, patterns P41 to P46 are selected as graphics included in the expanded calculation area A11. On the other hand, the pattern P47 and the pattern P48 are not selected as the figure of the calculation area A11. There may be cases where only a part of the touching figures such as pattern P46 and pattern P47 are selected, but by adjusting the size of the correction area and the size of the calculation margin area appropriately, adjustment is made so as not to cause a step problem. can do. For example, in the case of loading effect correction, the size of the correction margin area described in the third embodiment may be taken. In other processes, the size of the calculation margin area can be set arbitrarily according to the process to be performed.

  In addition, the division and synthesis method of the seventh embodiment can completely perform the data processing after the division for each calculation area, similarly to the method of the fifth embodiment. This is because the pattern belonging to the calculation margin area is not selected for only one calculation area but is processed as a graphic belonging to both.

  The seventh embodiment is very effective in the case of processing with one CPU. However, thanks to this independence, parallel processing by multiple CPUs can be facilitated. Currently, many CAD software support multi-process processing, and it is possible to perform processing using multiple CPUs, but processing speed may be improved by performing this parallel processing rather than using that function. Many. If processing is attempted in the same time, the cost can be reduced by keeping the specifications of the computer to be used.

  In Example 8, the mask pattern dividing method of the second embodiment will be described in detail.

  Also in the eighth embodiment, as in the first and fourth embodiments, as shown in FIG. 14, a mask 51 is arranged on the design plane, and chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. Suppose that

  In the eighth embodiment, similarly to FIG. 43 of the fourth embodiment, a plurality of calculation areas A11 to A22 are set in the area where the mask pattern A exists in step S31 of FIG.

  As shown in FIG. 67, it is assumed that some patterns P51 to P54 of the mask pattern A are arranged in the calculation areas A11 and A12. Note that correction areas a11 to a36 are set on the design plane.

  As shown in FIG. 68, in step S32, a calculation margin area 59 is set so that the calculation area A11 is adjacent to the outside of the calculation area A11. Then, the calculation area A11 is expanded to the calculation margin area 59.

  As shown in FIG. 69, in step S33, chip patterns P51 to P53 arranged at least partially in the expanded calculation area A11 are selected for the expanded calculation area A11.

  As shown in FIG. 70, in step S32, a calculation margin area 60 is set so that the calculation area A12 is adjacent to the outside of the calculation area A12. Then, the calculation area A12 is expanded to the calculation margin area 60.

  As shown in FIG. 71, in step S33, chip patterns P52 to P54 that are at least partially arranged in the expanded calculation area A12 are selected for the expanded calculation area A12.

  The boundary between the calculation areas A11 and A12 may be along the boundary between the correction areas a11 to a36. In the correction of the calculation areas A11 and A12, the calculation areas A11 and A12 are divided so as to have all necessary data, so that the calculation areas A11 and A12 can be corrected completely independently. In addition, by adjusting the size of the calculation areas A11 and A12, it is possible to adjust so that the processing can be performed in the real memory installed in the computer, and the problem of a reduction in processing speed due to the shortage is solved. .

  Further, the data after the correction processing is synthesized and the figure is confirmed. As a result, newly generated steps, gaps, and the like are not confirmed, and a figure that causes deterioration in accuracy after conversion to final drawing data is not generated.

  As described above, in the eighth embodiment, it is possible to divide and correct data that has been impossible in the past. The time required for the entire processing can be reduced to a fraction of the conventional time using a conventional computer. In addition, by executing parallel processing with an increased number of CPUs, the execution time can be further reduced to half or less.

  In the ninth embodiment, a method for dividing a mask pattern having a hierarchy will be specifically described.

  In the ninth embodiment as well, as in the first and fourth embodiments, it is assumed that the mask 51 is arranged on the design plane as shown in FIG. Chip patterns A to C of the semiconductor device are arranged on the mask 51, and the chip pattern A is divided as in the fourth embodiment.

  As shown in FIG. 72, the chip pattern A is composed of a parent cell CellA. The parent cell CellA is composed of child cells Cell1 to Cell3 and grandchild cells Cell41 and Cell42 constituting mark tops. The child cell Cell1 has grandchild cells Cell11 and Cell12. The child cell Cell3 has grandchild cells Cell31 and Cell32.

  FIG. 73 shows a file F0 having a mask data structure based on the configuration of FIG. The parent cell CellA of the topmost cell of the chip pattern A has child cells Cell1 to Cell3 and position information in the marktop mask 51. The child cell Cell1 has arrangement information of the grandchild cells Cell11 and Cell12 in the child cell Cell1. Similarly, child cell Cell3 has position information of grandchild cells Cell31 and Cell32 in child cell Cell3. The mark top has position information of grandchild cells Cell41 and Cell42 in the parent cell CellA. Such a structure composed of a plurality of cells is called a hierarchical structure. The hierarchical structure may be combined into one file F0 or may be divided into a plurality of cells.

  Also in the ninth embodiment, as shown in FIG. 74, a plurality of calculation areas A11 to A22 are set in the area where the mask pattern A exists. The child cells at least partially arranged in the calculation areas A11 to A22 are arranged in the calculation area without changing the internal structure. However, if the cell is large, only the large cell is expanded and arranged as a small cell. The threshold value for determining whether or not to expand a cell may be specified within a range that does not cause inconvenience in subsequent processing, for example, based on the size of the cell. In the following description, a case will be described in which the cell Cell1 exceeds the threshold value, and the other cells Cell2 and Cell3 do not exceed the threshold value, that is, the cell Cell1 is expanded one layer and the cells Cell02 and Cell03 are not expanded.

  The calculation margin area described in the ninth embodiment may or may not be set if there is no inconvenience in subsequent processing. FIG. 75 shows the relationship between the calculation area A11, its calculation margin area 59, and cells arranged in the vicinity of the boundary. Assume that cells CellB to CellG are arranged in the vicinity of the boundary between the calculation areas A11 and A12. When the calculation area A11 does not have a margin area, the cells arranged in the calculation area A11 are CellB to CellD. When the calculation area A11 has the calculation margin area 59, cells located in the calculation area A11 are CellB to CellF.

  As shown in FIG. 76, with respect to the calculation area A11, the parent cell CellA, the child cell Cell1, and the mark top are expanded, and grandchild cells Cell11, Cell12, and Cell42 that are partly included in the calculation area A11 are arranged. For the calculation area A11, a file F11 having a new data structure different from that of the file F0 is generated. The parent cell CellA has position information in the mask 51 of the child cell Cell1. The child cell Cell1 has arrangement information of the grandchild cells Cell11 and Cell12 in the child cell Cell1. The mark top has position information of the grandchild cell Cell42 in the parent cell CellA.

  As shown in FIG. 77, with respect to the calculation area A12, the parent cell CellA and the mark top are expanded, and the child cells Cell1 and Cell2 and the grandchild cell Cell42 included in the calculation area A12 are arranged. For the calculation area A12, a file F12 having a new data structure different from that of the file F0 is generated. The parent cell CellA has position information in the mask 51 of the child cells Cell1 and Cell2. The child cell Cell1 has arrangement information of the grandchild cells Cell11 and Cell12 in the child cell Cell1. The mark top has position information of the grandchild cell Cell42 in the parent cell CellA.

  As illustrated in FIG. 78, with respect to the calculation area A21, the parent cell CellA, the child cell Cell1, and the mark top are expanded, and grandchild cells Cell12 and Cell41 that are partly included in the calculation area A21 are arranged. Regarding the calculation area A21, a file F21 having a new data structure different from that of the file F0 is generated. The parent cell CellA has position information in the mask 51 of the child cell Cell1. The child cell Cell1 has arrangement information of the grandchild cell Cell12 in the child cell Cell1. The mark top has position information of the grandchild cell Cell41 in the parent cell CellA.

  As shown in FIG. 79, regarding the calculation area A22, the parent cell CellA, the child cell Cell1, and the mark top are expanded, and the child cell Cell3 and the grandchild cells Cell12 and cell41 that are included in the calculation area A22 are arranged. For the calculation area A22, a file F22 having a new data structure different from that of the file F0 is generated. The parent cell CellA has position information in the mask 51 of the child cells Cell1 and Cell3. The child cell Cell1 has arrangement information of the grandchild cell Cell12 in the child cell Cell1. The child cell Cell3 has arrangement information of the grandchild cells Cell31 and Cell32 in the child cell Cell3. The mark top has position information of the grandchild cell Cell41 in the parent cell CellA.

  The cells selected for each of the calculation areas A11 to A22 are stored as independent files F11 to F22 for each of the calculation areas A11 to A22. This enables processing such as global correction of the divided file for each calculation area.

  In step S36 of FIG. 10, for each of the calculation areas A11 to A22, the extracted chip chip patterns A to C, the extracted child cells Cell1 to Cell3, the mark top, and the grandchild cells Cell11, Cell12, Cell31, Cell32, A layout is generated based on Cell 41 and Cell 42, and a divided mask pattern is generated.

  In step S33, a mask pattern arranged at least partially in the calculation areas A11 to A22 is selected for each of the calculation areas A11 to A22.

  In the ninth embodiment, in the division processing, not only the CAD processing speed but also the output calculation areas A11 to A22 can be further reduced in data size. For this reason, whether or not a pattern is attached to a certain calculation area A11 to A22 is determined based on the position and size information of the figure group such as an array or cell structure including the pattern, and the figure group is attached to the calculation area A11 to A22. Judgment is made by judging whether to do. When attached to the calculation areas A11 to A22, the figure group is extracted. By this division processing, the hierarchy of input data is divided without being fully expanded, and the output data size can be reduced. And with commercially available CAD tools, it is often faster to correct data with a clean hierarchy extracted for each figure group than to process the developed data, and the entire correction process is processed. It can be performed at higher speed.

  In the tenth embodiment, the processing for the array arrangement will be described in the pattern file dividing method of the third embodiment.

  In the tenth embodiment, as in the first and ninth embodiments, as shown in FIG. 14, a mask 51 is arranged on the design plane, and chip patterns A to C of the chip of the semiconductor device are arranged in the mask 51. Suppose that

  As shown in FIG. 80, in the chip pattern A, it is assumed that the same cells Cell41 to Cell43 are arranged in an array in one column and three rows. Calculation areas A11 and A12 are set in the area where the chip pattern A exists. The file pattern is described by one or a plurality of files having a hierarchy. The top cell of the chip pattern A has the arrangement information of the cells Cell41 to Cell43.

  As shown in FIG. 81, regarding the calculation area A11, among the one-row and three-column array of cells Cell41 to Cell43, array cells Cell41 and Cell42 of one row and two columns that are partly included in the calculation area A11 are arranged.

  Similarly, as shown in FIG. 82, regarding the calculation area A12, among the one-row and three-column arrays of Cell41 to Cell43, the array cells Cell42 and Cell43 of one row and two columns that are also included in the calculation area A12 are arranged. .

  By this processing, information necessary for independent processing for each calculation area can be obtained.

  In the eleventh embodiment, processing that further speeds up the processing described in the tenth embodiment will be described.

  In the eleventh embodiment, as in the first, ninth, and tenth embodiments, as shown in FIG. 14, a mask 51 is arranged on the design plane, and chip patterns A to C of chips of the semiconductor device are arranged in the mask 51. Suppose that

  As shown in FIG. 83, it is assumed that in the chip pattern A, the same cells Cell41 to Cell43 are arrayed in one column and three rows. Calculation areas A11 and A12 are set in the area where the chip pattern A exists. The file pattern is described by one or a plurality of files having a hierarchy. The top cell of the chip pattern A has cell 41 to cell 43 arrangement information. The outline of the 1-by-3 array of cells Cell41 to Cell43 is obtained.

  As shown in FIG. 84, when the calculation outline A11 includes even a part of the outline of the array, the cells Cell41 to Cell43 of the entire array of one row and three columns are arranged in the calculation area A11.

  Similarly, as shown in FIG. 85, regarding the calculation area A12, when the array outline Outline is arranged even in a part of the calculation area, the cells Cell41 to Cell43 of the entire array of one row and three columns are arranged in the calculation area A12.

  By this processing, division including information necessary for independent processing for each of the calculation areas A11 and A12 can be performed. Further, in the tenth embodiment, it is necessary to determine and divide the positions and sizes of various cells, whereas in the eleventh embodiment, the determination may be made only by the information of the outline of the array, and the processing can be omitted, and the speed can be increased. Is possible.

  In Example 12, the production of the mask in step S3 in FIG. 1 of the method for manufacturing the semiconductor device according to the first embodiment will be specifically described.

  As shown in FIG. 86A, a chromium film 72 is formed on the mask substrate 1. A resist film 73 is formed on the chromium film 72.

  As shown in FIG. 86B, the resist film 73 is exposed by irradiating the resist film 73 with an electron beam having the same beam width wa as the corrected pattern width wa.

  As shown in FIG. 86 (c), the resist film 73 is developed, and a pattern of the resist film 73 having a pattern width wb changed from the corrected pattern width wa by the coarse / fine correction amount is formed.

  As shown in FIG. 86 (d), the chromium film 72 is etched using the resist film 73 as a mask, and a pattern of the chromium film 72 having a pattern width wc that is further changed by the position correction amount from the pattern width wb is formed.

  As shown in FIG. 86 (e), by removing the resist film 73, it is possible to provide a mask having the pattern width wc expected by the mask design section.

  In Example 13, the fabrication of the semiconductor device in step S4 of FIG. 1 of the method for fabricating the semiconductor device of the first embodiment will be specifically described.

  As shown in FIG. 87 (a), wiring 84 is embedded in the interlayer insulating film 81. A conductor film 82 such as an aluminum (Al) film to be a wiring is formed on the interlayer insulating film 81. A resist film 83 is formed on the conductor film 82.

  As shown in FIG. 87B, the resist film 83 is exposed, and ultraviolet rays having an irradiation width we that is changed by a correction amount for the proximity effect correction from the pattern width wd of the wiring pattern on the corrected mask are exposed. Irradiate.

  As shown in FIG. 87 (c), the resist film 83 is developed, and a pattern of the resist film 83 having a pattern width wf that is changed from the pattern width we by the density correction amount due to the pattern density in the development of the resist film 83 is formed. Is done.

  As shown in FIG. 87 (d), the conductor film 82 is etched using the resist film 83 as a mask, and the conductor film 82 having a pattern width wg that is changed from the pattern width wf by a coarse / fine correction amount due to the density of the pattern in the etching. A pattern is formed.

  As shown in FIG. 87 (e), by removing the resist film 83, it is possible to provide a semiconductor device having the pattern width wg expected by the semiconductor device design unit.

  In Example 14, the fabrication of the semiconductor device in step S4 in FIG. 1 of the method for fabricating the semiconductor device of the first embodiment will be specifically described.

  As shown in FIG. 88A, a wiring 94 is embedded in an interlayer insulating film 91 that becomes a base substrate. An insulating film 92 to be an interlayer insulating film is formed on the interlayer insulating film 91. A resist film 93 is formed on the insulating film 92.

  As shown in FIG. 88B, the resist film 93 is exposed, and ultraviolet rays having an irradiation width wi that is changed from the pattern width wh of the corrected wiring pattern by the correction amount for the proximity effect correction are exposed. Irradiate.

  As shown in FIG. 88 (c), the resist film 93 is developed to form a pattern of the resist film 93 having a pattern width wj that is changed from the pattern width wi by the density correction amount due to the pattern density in the development of the resist film 93. Is done.

  As shown in FIG. 88 (d), the insulating film 92 is etched using the resist film 93 as a mask, and the insulating film 92 having a pattern width wk changed from the pattern width wj by the density correction amount due to the pattern density in the etching. A pattern is formed.

  As shown in FIG. 88 (e), the resist film 93 is removed, and as shown in FIG. 86 (f), a conductor film 95 is formed on the insulating film 92, and the conductor film 95 is formed on the pattern of the insulating film 92. Embed.

  As shown in FIG. 88 (g), by removing the conductor film 95 on the insulating film 92 by the CMP method, it is possible to provide a semiconductor device having the pattern width wl expected in the semiconductor device design section. it can.

3 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. It is a block diagram of the design apparatus which concerns on 1st Embodiment. It is a flowchart of the design method of the mask which concerns on 1st Embodiment. It is a flowchart of the design method of the mask which concerns on the modification 1 of 1st Embodiment. It is a flowchart of the design method of the mask which concerns on the modification 2 of 1st Embodiment. It is a block diagram of the division | segmentation combining apparatus of the mask pattern which concerns on 2nd Embodiment. It is a flowchart of the division method of the mask pattern concerning a 2nd embodiment. It is a flowchart of the synthetic | combination method of the mask pattern which concerns on 2nd Embodiment. It is a block diagram of the division | segmentation synthetic | combination apparatus of the pattern file which concerns on 3rd Embodiment. It is a flowchart of the division | segmentation method of the pattern file which concerns on 3rd Embodiment. It is a flowchart of the synthetic | combination method of the pattern file which concerns on 3rd Embodiment. It is a block diagram of the global correction | amendment part which concerns on 4th Embodiment. It is a flowchart of the global correction method which concerns on 4th Embodiment. It is a top view on the design plane in which the design data of the mask which concerns on Example 1 was described. FIG. 3 is a plan view on a design plane on which design data and a correction area of a mask according to Example 1 are described. It is a top view on the design plane in which the design data and area density calculation region of the mask concerning Example 1 were described. 6 is a table of pattern density for each pattern correction area, which is design data of a mask according to Example 1; It is a table | surface showing the relationship between a pattern density and a correction amount. 7 is a table of correction amounts depending on a pattern density for each pattern correction region, which is design data of a mask according to the first embodiment. 4 is a distribution diagram of a chromium etching rate ratio of the mask according to Example 1. FIG. It is a table | surface showing the relationship between etching rate ratio and correction amount. 6 is a table of correction amounts depending on an etching rate for each pattern correction region, which is mask design data according to Example 1; 6 is a table of summed correction amounts for each pattern correction area, which is mask design data according to Embodiment 1; It is a top view on the design plane in which the design data of the mask which concerns on Example 2 was described. FIG. 10 is a plan view on a design plane on which design data and a first correction area of a mask according to Example 2 are described. FIG. 10 is a plan view on a design plane on which mask design data and a second correction area having an oblique relationship with a first correction area are described according to Example 2; It is a top view on the design plane in which the 2nd correction area of the 1st correction area and the up-and-down relation was described. It is a top view on the design plane in which the 2nd correction area of the 1st correction area and the horizontal direction relation was described. 12 is a table of correction amounts for each first correction area of a pattern, which is design data for a mask according to Embodiment 2. 10 is a table of correction amounts for each second correction area of a pattern, which is design data for a mask according to Embodiment 2. FIG. 6 is a plan view (No. 1) on a design plane for explaining a global correction method according to a second embodiment. FIG. 10 is a plan view (No. 2) on the design plane for explaining the global correction method according to the second embodiment. FIG. 10 is a plan view (No. 3) on the design plane for explaining the global correction method according to the second embodiment. FIG. 10 is a plan view (No. 4) on the design plane for explaining the global correction method according to the second embodiment. FIG. 10 is a plan view (No. 5) on a design plane for explaining a global correction method according to a second embodiment; FIG. 10 is a plan view (No. 6) on a design plane for explaining a global correction method according to a second embodiment; FIG. 12 is a plan view (No. 7) on a design plane for explaining a global correction method according to a second embodiment; FIG. 10 is a plan view (No. 8) on a design plane for explaining a global correction method according to a second embodiment; FIG. 10 is a plan view (No. 9) on a design plane for explaining a global correction method according to a second embodiment; FIG. 9 is a plan view (No. 1) on a design plane for explaining a global correction method according to a third embodiment. FIG. 10B is a plan view (No. 2) on the design plane for explaining the global correction method according to the third embodiment. FIG. 10 is a plan view (No. 3) on a design plane for explaining a global correction method according to a third embodiment; FIG. 9A is a plan view (No. 1) on a design plane for explaining a mask pattern dividing method according to a fourth embodiment; FIG. 10B is a plan view (No. 2) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 10D is a plan view (No. 3) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 10D is a plan view (No. 4) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 10B is a plan view (No. 5) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 6D is a plan view (No. 6) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 14 is a plan view (No. 7) on a design plane for explaining a mask pattern dividing method according to the fourth embodiment; FIG. 10B is a plan view (No. 8) on the design plane for explaining the mask pattern dividing method according to the fourth embodiment. FIG. 10A is a plan view (No. 1) on a design plane for explaining a mask pattern dividing method and a combining method according to a fifth embodiment; FIG. 10B is a plan view (No. 2) on the design plane for explaining the mask pattern dividing method and the combining method according to the fifth embodiment. FIG. 16 is a plan view (No. 1) on a design plane for explaining a mask pattern dividing method according to a sixth embodiment; FIG. 10B is a plan view (No. 2) on the design plane for explaining the mask pattern dividing method according to the sixth embodiment. FIG. 10A is a plan view (No. 1) on a design plane for explaining a mask pattern dividing method and a combining method according to a seventh embodiment; FIG. 10B is a plan view (No. 2) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment. FIG. 10D is a plan view (No. 3) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment; FIG. 10D is a plan view (No. 4) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment. FIG. 20 is a plan view (No. 5) on a design plane for explaining a mask pattern dividing method and a combining method according to Embodiment 7; FIG. 16 is a plan view (No. 6) on a design plane for explaining a mask pattern dividing method and a combining method according to Embodiment 7; FIG. 10D is a plan view (No. 7) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment. FIG. 10D is a plan view (No. 8) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment; FIG. 19 is a plan view (No. 9) on a design plane for explaining a mask pattern dividing method and a synthesizing method according to Embodiment 7. FIG. 10D is a plan view (No. 10) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment; FIG. 11D is a plan view (No. 11) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment; FIG. 13D is a plan view (No. 12) on the design plane for explaining the mask pattern dividing method and the combining method according to the seventh embodiment; FIG. 10A is a plan view (No. 1) on a design plane for explaining a mask pattern dividing method according to an eighth embodiment; FIG. 10B is a plan view (No. 2) on the design plane for explaining the mask pattern dividing method according to the eighth embodiment. FIG. 10D is a plan view (No. 3) on the design plane for explaining the mask pattern dividing method according to the eighth embodiment; FIG. 10D is a plan view (No. 4) on the design plane for explaining the mask pattern dividing method according to the eighth embodiment; FIG. 10B is a plan view (No. 5) on the design plane for explaining the mask pattern dividing method according to the eighth embodiment; It is the top view (the 1) on the design plane for demonstrating the division | segmentation method of the pattern file which concerns on Example 9. FIG. FIG. 20 is a structure diagram (No. 1) showing a hierarchical structure of pattern files for explaining a pattern file dividing method according to Embodiment 9. It is the top view (the 2) on the design plane for demonstrating the division | segmentation method of the pattern file which concerns on Example 9. FIG. FIG. 22 is a plan view (No. 3) on the design plane for explaining a pattern file dividing method according to the ninth embodiment; FIG. 29 is a structure diagram (No. 2) illustrating a hierarchical structure of pattern files for explaining a pattern file dividing method according to the ninth embodiment; FIG. 29 is a structure diagram (part 3) illustrating a hierarchical structure of a pattern file for explaining a pattern file dividing method according to the ninth embodiment; FIG. 22 is a structure diagram (part 4) illustrating a hierarchical structure of a pattern file for explaining a pattern file dividing method according to the ninth embodiment; FIG. 20 is a structural diagram (No. 5) showing a hierarchical structure of a pattern file for explaining a pattern file dividing method according to Embodiment 9. FIG. 22A is a plan view (No. 1) on a design plane for explaining a pattern file dividing method according to the tenth embodiment; FIG. 22B is a plan view (No. 2) on the design plane for explaining the pattern file dividing method according to the tenth embodiment; FIG. 29 is a plan view (No. 3) on the design plane for explaining the pattern file dividing method according to the tenth embodiment; FIG. 22B is a plan view (No. 1) on the design plane for explaining the pattern file dividing method according to the eleventh embodiment; FIG. 28B is a plan view (No. 2) on the design plane for explaining the pattern file dividing method according to the eleventh embodiment; FIG. 29 is a plan view (No. 3) on the design plane for explaining the pattern file dividing method according to the eleventh embodiment; It is sectional drawing of the mask for demonstrating the manufacturing method of the mask based on Example 12. FIG. It is sectional drawing of the semiconductor device etc. for demonstrating the manufacturing method of the semiconductor device which concerns on Example 13. FIG. It is sectional drawing of the semiconductor device etc. for demonstrating the manufacturing method of the semiconductor device which concerns on Example 14. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Chip data memory | storage part 2 Mask pattern memory | storage part 3 Design apparatus 4 Semiconductor device design part 5 Mask design part 11 Arrangement | positioning part 12 Local correction | amendment part 13 Global correction | amendment part 14 Format part 15 Division | segmentation part 16 Synthesis | combination part 17 Arrangement | positioning part 18 Mask pattern division | segmentation Synthesizer 19 Mask pattern dividing device 20 Mask pattern synthesizing device 21 Calculation area setting unit 22 Calculation margin area setting unit 23 Mask pattern selection unit 24 Correction pattern arrangement unit 25 Overlap removal unit 31 Pattern file division and synthesis device 32 Pattern file division Dividing device 33 Pattern file synthesizing device 34 Cell selecting unit 35 File extracting unit 36 Dividing pattern generating unit 41 Correction region dividing unit 42 Global correction amount setting unit 43 Correction region correcting unit 44 Pattern density calculating unit 45 Pattern density and density correction amount Relation storage 46 Calculation of density correction 47 etching rate ratio storage unit 48 relationship storage unit between etching rate ratio and position correction amount 49 position correction amount calculation unit 50 summation unit 51 mask on design plane 52 mask position coordinates 53 margin correction region 54 boundary 55 to 58 correction amount 59, 60 Margin calculation area

Claims (5)

Setting a plurality of calculation areas in the area where the chip pattern of the semiconductor device on the design plane exists;
And said a plurality of each calculation region, each calculated margin region to be adjacent to the outside of the plurality of calculation regions is provided, to extend each of the plurality of calculation area to the calculated margin area,
And said the extended each calculation region, from among the chip pattern, selects the chip patterns arranged at a portion on each of the extended calculation area,
And said the extended each calculation region, corrects the chip pattern selected by each of the extended calculation area,
Arranging chip patterns for all corrected calculation areas,
Removing the overlapping portion of the chip patterns arranged in an overlapping manner;
Forming a real pattern on the wafer based on the chip pattern from which the overlapping portion has been removed .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the selected chip pattern is stored for each calculation area. Setting one or more calculation areas in the area of the design plane where the chip pattern of the semiconductor device composed of one or more cells in a hierarchy exists;
Selecting, for each of the calculation areas, the cells arranged even in part in the calculation area;
Of the chip patterns included in the selected cell, selecting a chip pattern that is partially included in the calculation area;
Correcting the selected chip pattern for each calculation region;
Arranging chip patterns for all corrected calculation areas,
Removing the overlapping portion of the chip patterns arranged in an overlapping manner;
Forming a real pattern on the wafer based on the chip pattern from which the overlapping portion has been removed . A procedure for setting a plurality of calculation areas in the area where the chip pattern of the semiconductor device on the design plane exists,
For each of the plurality of calculation regions, the procedure in which the plurality of the respective calculated margin region to be adjacent to the outside of the calculation area is provided, to extend each of the plurality of calculation area to the calculated margin area,
Wherein the extended each calculation region, from among the chip pattern, a step of selecting a chip pattern that is disposed in a portion on each of the extended calculation area,
A step of the to extended each calculation region, corrects the chip pattern selected by each of the extended calculation area,
Procedure to arrange the corrected chip pattern of all calculation areas in an overlapping manner ,
A chip pattern correction program for a semiconductor device for causing a computer to execute a procedure for removing an overlapping portion of the chip patterns arranged in an overlapping manner. A procedure for setting one or a plurality of calculation areas in a design plane area where a chip pattern of a semiconductor device constituted by one or a plurality of cells in a hierarchy exists;
For each of the calculation areas, a procedure for selecting the cells arranged at least in the calculation area;
A step of selecting a chip pattern included in a part of the calculation area among chip patterns included in the selected cell; a step of correcting the selected chip pattern for each calculation area;
Procedure to arrange the corrected chip pattern of all calculation areas in an overlapping manner ,
A chip pattern correction program for a semiconductor device for causing a computer to execute a procedure for removing an overlapping portion of the chip patterns arranged in an overlapping manner.

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