JP4845826B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method for variable-length encoding image data, storing the data in a memory, reading out the decoded variable-length encoded data, and decoding and outputting the data. The present invention relates to an image processing apparatus and an image processing method capable of reducing the time from the start of data encoding to the end of decoding.

  In image forming apparatuses such as multifunction printers and digital multi-function peripherals equipped with facsimile functions, printer functions, scanner functions, and copying functions, input images are required to achieve higher speed, more functions, higher image quality, etc. Data is temporarily stored in an image memory (frame memory), and printing timing adjustment, image processing / editing, and the like can be performed.

  In such an image forming apparatus, in order to increase the speed from image reading to printing and reduce the cost, it is necessary to use the image memory efficiently. In order to reduce the cost, it is conceivable to reduce the memory capacity. However, if the memory capacity is reduced, the amount of pixel data that can be accumulated at one time is reduced, and high-speed printing becomes difficult. Therefore, generally, image data is encoded and the amount of data is reduced (compressed) and then stored in a memory. For example, in the image processing apparatus described in Patent Document 1, image data input from a scanner is encoded (compressed), stored in an image memory, and encoded data stored in the image memory is decoded (expanded). Then, a processing flow for outputting to the plotter is taken.

  Here, when a general SDRAM (Synchronous DRAM), DDR (Double Data Rate) memory, or the like is assumed as an image memory, writing of encoded data to the image memory (memory write) is performed by a DMA (Direct Memory Access) controller. ) And reading of the stored encoded data from the image memory (memory read) is performed. In general, this DMA controller is provided with a buffer memory to adjust the timing of encoding of image data, writing of encoded data to the image memory, reading of the encoded data, and decoding of the read encoded data.

  By the way, in order to speed up the first copy time (the time from the start of reading the original image from the scanner to the completion of the copy image printing), the encoded data written in the memory is immediately read from the memory. It is necessary to use the decryption process.

  Here, when image data is encoded by a fixed-length compression method in which a block having a predetermined number of pixels is compressed into a fixed-length code having a fixed code length, the size of the encoded data for the predetermined image block in one page of the document Is always constant, on the writing side, when a predetermined amount of encoded data is stored in the buffer memory, it is read out and written to the image memory, and on the reading side, the encoded data stored in the image memory is read Can be read out and written to the buffer memory, read out and sent to the decoding process.

  However, with variable-length coding schemes such as the JPEG (Joint Photographic Experts Group) format, the data compression rate varies greatly depending on the input image, and when an image with little change such as a solid image is encoded, In addition, since the compression rate is high, the amount of generated code is extremely small, and there is a problem that writing (memory write) to the image memory is not easily performed. In such a situation, if the memory read on the decoding process side is executed at a constant rate, the memory read may overtake the memory write.

  For this reason, when the variable-length encoding method is adopted, encoding of the entire image of one page is completed, and all the data is written in the image memory. Then, memory read is started and decoding processing is executed. As a result, there is a problem that the first copy time 301 becomes long as shown in FIG. 4A.

JP 2001-212329 A

  The present invention has been made to solve such a problem, and its purpose is to perform variable-length encoding of image data and store it in a memory, and when reading and decoding the stored encoded data, It is to be able to shorten the time from the start of encoding image data in units of pages to the end of decoding.

According to the first aspect of the present invention, there is provided encoding means for variable-length encoding image data, write-side buffer means for temporarily storing variable-length encoded data output from the encoding means, and the writing side From the storage means for accumulating the variable length encoded data read from the buffer means, the read side buffer means for temporarily accumulating the variable length encoded data read from the storage means, and the read side buffer means An image having decoding means for decoding the read variable-length encoded data, and write control means for reading the variable-length encoded data stored in the write buffer means and transferring it to the storage means In the processing device, the write control unit may elapse a predetermined time from the start of writing when the accumulation amount of the write side buffer unit reaches a first predetermined amount or before reaching the first predetermined amount. When any earlier An image processing apparatus characterized by transferring at square timing.
According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the read control means for reading the variable length encoded data stored in the storage means and transferring it to the read side buffer means, and the write control means Has a transfer notification means for notifying the read control means that variable length encoded data has been transferred to the storage means, and the read control means performs transfer in response to a notification from the transfer notification means. Features.
According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, the writing control means causes the writing side buffer means to receive a second place less than the first predetermined amount when the predetermined time has elapsed. When the fixed amount of variable-length encoded data is not accumulated, the transfer timing is delayed until it is accumulated.
According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the second predetermined amount is an integral multiple of a bit width of a signal line connecting the write side buffer means and the storage means. It is characterized by.
According to a fifth aspect of the present invention, there is provided a first step of converting image data into variable length encoded data, a second step of storing the variable length encoded data in write side buffer means, and the write side buffer. A third step of reading out the variable length encoded data stored in the means and storing it in the storage means; a fourth step of reading out the stored variable length encoded data and storing it in the read side buffer means; A fifth step of reading out the variable-length encoded data stored in the reading-side buffer means and decoding it into image data, wherein the storage amount of the writing-side buffer means in the second step The third step is executed at the earlier timing when the first predetermined amount is reached or when a predetermined time has elapsed from the start of accumulation before reaching the first predetermined amount. This is an image processing method.
A sixth aspect of the present invention is the image processing method according to the fifth aspect, further comprising a sixth step of monitoring an execution status of the third step, and based on a monitoring result of the sixth step. The fourth step is performed.
According to a seventh aspect of the present invention, in the image processing method according to the fifth aspect, when the predetermined time elapses in the second step, the accumulation amount of the writing side buffer means is smaller than the first predetermined amount. If the predetermined amount is not reached, a step of delaying the timing of executing the third step until the second predetermined amount is reached is provided.

[Action]
According to the first aspect of the present invention, when the storage amount of the variable length encoded data stored in the write side buffer means reaches the first predetermined amount or before the first predetermined amount is reached, the writing is started. The variable length encoded data is read from the writing side buffer means and transferred to the storage means at the earlier timing when a predetermined time elapses from.
According to the invention of claim 2, the write control means notifies the read control means that the variable length encoded data has been transferred to the storage means, and the read control means is stored in the storage means in response to the notification. The variable length encoded data is read out and transferred to the reading side buffer means.
According to the invention of claim 3, when the predetermined amount of time has elapsed before the storage amount of the variable-length encoded data stored in the write-side buffer means reaches the first predetermined amount, the write-side buffer means receives the first If the second predetermined amount of variable-length encoded data smaller than the predetermined amount is not accumulated, transfer is performed when accumulated.
According to the fourth aspect of the present invention, when a predetermined time elapses before the storage amount of the variable length encoded data stored in the write side buffer means reaches the first predetermined amount, the write side buffer means is written to the write side buffer means. If variable length encoded data that is an integral multiple of the bit width of the signal line connecting the input buffer means and the storage means has not been accumulated, transfer is performed when accumulated.
According to the fifth aspect of the present invention, when the storage amount of the variable-length encoded data in the writing side buffer means reaches the first predetermined amount or before reaching the first predetermined amount, a predetermined time from the start of storage. The variable length encoded data stored in the writing side buffer means is read out and stored in the storage means at the earlier timing when the time has elapsed.
According to the sixth aspect of the present invention, the execution status of the step of reading and storing the variable length encoded data stored in the write side buffer means is monitored, and the stored variable length encoding is determined according to the monitoring result. Data is read and stored in the read side buffer means.
According to the seventh aspect of the present invention, when a predetermined time elapses before the storage amount of the variable length encoded data stored in the write side buffer means reaches the first predetermined amount, the write side buffer means receives the first If the second predetermined amount of variable-length encoded data smaller than the predetermined amount is not accumulated, when it is accumulated, the variable-length encoded data is read from the writing side buffer means and stored in the storage means.

  According to the present invention, when image data is variable-length encoded and stored in a memory, and when the stored encoded data is read and decoded, the time from the start of encoding image data in units of pages to the end of decoding Can be shortened.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. The image processing apparatus writes a scanner 101, a JPEG encoder 102 that encodes image data from the scanner 101 in JPEG format, and JPEG code data encoded by the JPEG encoder 102 into a memory 114 through a data bus 115. A write-side DMA controller (hereinafter referred to as WDMAC) 104, a read-side DMA controller (hereinafter referred to as RDMAC) 108 that reads JPEG code data written in the memory 114 through the data bus 115, and JPEG code data read by the RDMAC 108 A JPEG decoder 111 for decoding, an image processing unit 112 for performing predetermined image processing on the image data decoded by the JPEG decoder 111, and a plotter 113 for printing an image based on the image data subjected to the image processing A transfer trigger signal generated at a predetermined timing and applied to the WDMAC 104 Having.

  A scanner 101 is a device that reads an image of a document by an image sensor such as a CCD, and outputs image data for one line of one byte per pixel (8 bits) in units of 100 μsec.

  The WDMAC 104 is a DMA controller for performing a memory write to the memory 114. The WDMAC 104 has a two-stage toggle buffer 107 made up of buffers 107 a and 107 b each having 256 bytes, and one buffer stores JPEG code data input from the JPEG encoder 102 under the control of the buffer control unit 105. At this time, the stored JPEG code data is read from the other buffer and output as packet data to the memory 114) via the data bus 115.

  Here, since the size of the buffers 107a and 107b is 256 bytes, the data size of one packet is 256 bytes or less. Also, the bandwidth of the data bus 115 is set so that the 256-byte data read time accumulated in the buffers 107a and 107b is sufficiently faster than the write time from the JPEG encoder 102 to the 256-byte buffers 107a and 107b. Is very wide. Therefore, the switching control of writing and reading of the buffers 107a and 107b is performed by the buffer control unit 105 upon completion of writing of 256 bytes from the JPEG encoder 102 to the buffer.

  Furthermore, the transfer trigger generation unit 103 performs timer monitoring by counting up an internal timer counter, and the buffer control unit 105 does not generate a certain period of time for switching the buffers 107a and 107b (here, 200 μsec for two lines) outputs a trigger signal for forcibly generating the switching timing of the buffers 107a and 107b, and resets the timer counter to zero. In addition, when the buffer control unit 103 receives a signal indicating that the buffers 107a and 107b have been switched, the transfer trigger generation unit 103 counts up the internal timer counter from 0 again.

  Also, when the buffer control unit 105 receives a trigger signal from the transfer trigger generation unit 103, the write amount to the buffer from the JPEG encoder 102 is the minimum unit size of packet data (here 16 bytes). If it is not a multiple of, the function of waiting for the switching of the buffers 107a and 107b until the next multiple of 16 bytes is accumulated is also provided. Here, since the minimum unit size of packet data is 16 bytes, the data bus 115 and the memory 114 are very efficient during data transfer when the bus width (bit width) of the memory 114 is 128 bits or 256 bits. Address control is possible.

  The transfer packet monitoring unit 106 issues packet information related to the JPEG encoded data transferred by the memory 114 of the WDMAC 104 to the RDMAC 108. The packet information issued here is the data size of the packet transferred to the memory 114 (256 bytes or less as described above).

  The RDMAC 108 is a DMA controller for performing memory read from the memory 114. Like the RDMAC 104, the RDMAC 108 has a two-stage toggle buffer 110 that includes buffers 110a and 110b each having 256 bytes. The switching timing of the buffers 110a and 110b is controlled by the buffer control unit 109. At this time, packet information issued by the transfer packet monitoring unit 106 indicating that the memory write of packet data of a predetermined size by the WDMAC 104 has been completed is received, and control is performed based on the information.

  The JPEG code data read from the toggle buffer 110 is transferred to the JPEG decoder 111, JPEG decoded, and decompressed to image data. The decoded image data is subjected to a binarization process accompanied by an error diffusion process by the image processing unit 112 and is output to the plotter 113.

  Next, the image processing operation of the present embodiment will be described in the case of reading an image 201 composed of a natural image area 202 and a solid image area 203 as shown in FIG. The size of the image 201 in the main scanning direction is 1024 pixels, and the size in the sub-scanning direction is 1500 lines. The upper 800 line is the natural image area 202, and the lower 700 line is the solid image area 203. Here, for easy understanding, the compression efficiency of the JPEG encoder 102 is fixed to “8” for the natural image area 202 and fixed to “85” for the solid image area 203.

  The scanner 101 starts reading the image 201, and the image data is input to the JPEG encoder 102. When the image 201 is read from above, encoding is first performed from the natural image region 202. Since the JPEG compression efficiency is 8, a 256-byte JPEG code is generated every time 2048-byte image data is compressed. Here, since the size of the image 201 read from the scanner 101 in the main scanning direction is 1024 pixels, a code of 256 bytes is generated every time almost two lines of image data are processed. Since the scanner 101 outputs one line of data every 100 μsec, a 256-byte JPEG code is generated in units of 200 μsec. Accordingly, during encoding of the natural image area 202, the toggle buffer 107 of the WDMAC 104 is switched between accumulation and reading in the buffers 107a and 107b every 200 μsec. The WDMAC 104 writes 256 bytes of encoded data as one packet data every 200 μsec into the memory 114 via the data bus 115.

  Next, it is assumed that the scanner 101 finishes reading an image of the 800-line natural image area 202 and starts reading the solid image area 203. At this time, since the JPEG compression efficiency is 85, for example, when 2048-byte image data for two lines is compressed, a 24-byte JPEG code is generated.

  Accordingly, in order to store 256 bytes having the size of the buffers 110a and 110b of the toggle buffer 110 of the WDMAC 104, it is necessary to input 21760 bytes, that is, about 21 lines of image data. However, since there is a situation in which the buffers 110a and 110b are not switched for a period of 200 μsec, the transfer trigger generation unit 103 forcibly switches the buffers 110a and 110b and writes the memory to the buffer control unit 105. A trigger signal for performing the above is sent.

  When the buffer control unit 105 receives the trigger signal, 200 μsec, that is, two lines of data in the solid image area 203 are compressed, and the toggle buffer 110 stores only 24 bytes. Therefore, the buffer control unit 105 performs buffer switching after waiting for 32 bytes to be accumulated, which is a multiple of the next 16 bytes. As a result, the JPEG code of 32 bytes per packet is output from the WDMAC 104 to the memory 114. Thus, by providing the transfer trigger generation unit 103, periodic data writing to the memory 114 is realized regardless of the compression rate of the input image. Therefore, as shown in FIG. 4B, the first copy time 302 is significantly shortened compared to the first copy time 301 of the conventional apparatus shown in FIG. 4A.

  FIG. 3 is a flowchart showing a flow of operations of the WDMAC 104 and the RDMAC 109 described above. Here, the image input side is WDMAC 104 and the image output side is RDMAC 109.

  As shown in this figure, when the WDMAC 104 starts operating in step S1 and executes a memory write for one packet in step S2, the transfer packet monitoring unit 106 issues packet information to the RDMAC 108 in step S3. Steps S2 and S3 are repeated until it is determined in step S4 that the page has been completed.

  On the other hand, even if the RDMAC 108 starts operating in step S11, it waits (waits) for a memory read in step S12. When it is determined in step S13 that packet information has been received from the transfer packet monitoring unit 106, memory read for one packet is executed in step S14. Steps S12 to S14 are repeated until it is determined in step S15 that the page has been completed.

  In this way, the image output side can also be activated as the image input starts. The image output side automatically waits for a memory read until it receives notification of packet information from the image input side. That is, it is not necessary to control the start timing and the like on the image output side with respect to the image input side as software control.

It is a block diagram which shows the structure of the image processing apparatus of embodiment of this invention. It is a figure which shows an example of the image of embodiment of this invention. It is a flowchart which shows the flow of operation | movement of WDMAC and RDMAC of embodiment of this invention. It is a figure which shows the first copy time of a conventional apparatus and this embodiment.

Explanation of symbols

  102: JPEG encoder, 103: Transfer trigger generation unit, 104: WDMAC, 105, 109 ... Buffer control unit, 106: Transfer packet monitoring unit, 107, 110 ... Toggle buffer 108 RDMAC 111 JPEG decoder 114 Memory 115 Data bus

Claims (7)

Coding means for variable-length coding image data, write-side buffer means for temporarily storing variable-length coded data output from the coding means, and read from the write-side buffer means Storage means for storing variable-length encoded data, read-side buffer means for temporarily storing variable-length encoded data read from the storage means, and variable-length code read from the read-side buffer means An image processing apparatus comprising: decoding means for decoding the encoded data; and write control means for reading the variable-length encoded data stored in the write-side buffer means and transferring it to the storage means,
The writing control means is earlier when the accumulation amount of the writing side buffer means reaches a first predetermined amount or when a predetermined time elapses from the start of writing before reaching the first predetermined amount. The image processing apparatus is characterized in that the data is transferred at the same timing. The image processing apparatus according to claim 1.
Read control means for reading the variable length encoded data stored in the storage means and transferring it to the read side buffer means, and the reading that the write control means has transferred the variable length encoded data to the storage means An image processing apparatus comprising: transfer notification means for notifying the control means, wherein the read control means transfers in response to a notification from the transfer notification means. The image processing apparatus according to claim 1.
When the predetermined time has elapsed, the write control means stores the write-side buffer means if the second predetermined amount of variable-length encoded data smaller than the first predetermined amount has not been stored. The image processing apparatus is characterized in that the transfer timing is delayed until The image processing apparatus according to claim 3.
2. The image processing apparatus according to claim 1, wherein the second predetermined amount is an integral multiple of a bit width of a signal line connecting the write side buffer means and the storage means. A first step of converting image data into variable-length encoded data; a second step of storing the variable-length encoded data in the write-side buffer means; and a variable length stored in the write-side buffer means A third step of reading out the encoded data and storing it in the storage means, a fourth step of reading out the stored variable length encoded data and storing it in the reading side buffer means, and storing in the reading side buffer means And a fifth step of reading the variable length encoded data and decoding it into image data,
The earlier timing when the accumulation amount of the writing side buffer means reaches the first predetermined amount in the second step or when a predetermined time elapses from the start of accumulation before reaching the first predetermined amount. The image processing method is characterized in that the third step is executed. The image processing method according to claim 5.
An image processing method comprising: a sixth step for monitoring an execution status of the third step, and executing the fourth step based on a monitoring result of the sixth step. The image processing method according to claim 5.
The second predetermined amount when the accumulated amount of the write side buffer means has not reached the second predetermined amount smaller than the first predetermined amount when the predetermined time has elapsed in the second step. An image processing method comprising a step of delaying a timing of executing the third step until reaching