JP4845350B2 - Parallel processing unit - Google Patents

Description

  The present invention relates to a parallel processing technique applicable to information processing such as pattern recognition.

Conventionally, as a method of realizing a large-scale multilayer neural network using a small-scale circuit, a method of performing time division processing is known (for example, refer to Patent Documents 1 and 2). When a multilayer neural network is implemented as an analog / digital mixed circuit or a fusion circuit, it is often difficult to realize parallel processing by arranging all the components such as neurons and synapses in parallel on a two-dimensional plane. Therefore, in the prior art, time division processing is performed using a small number of neurons or synapse circuit elements. A method of dividing a large-scale network structure into small-scale network modules has been conventionally disclosed (see, for example, Patent Documents 3 and 4).
Japanese Patent No. 2679730 Japanese Patent No. 3110434 Japanese Patent No. 3035106 Japanese Patent No. 3210319

  However, among the conventional techniques, the time division processing method uses the same hardware in order to solve a large-scale problem, so the processing time depends on the complexity of the problem and the size of the scale. There is a problem that the advantage of the parallel processing inherent in the neural network cannot be fully utilized.

  In addition, the higher the loading frequency from the memory of the receptive field structure (synaptic connection load distribution) of each neuron, or the readout frequency of the intermediate result from the memory holding the intermediate processing result of each layer, the processing is caused by the memory access time. When switching the neuron output and load data using a switching element, there is a problem that the power consumption required for switching is accumulated and the overall power consumption becomes very large.

  Further, the method of dividing into small network modules has a disadvantage that the circuit scale as a whole is not reduced.

  The present invention has been made in view of the above problems, and it is an object of the present invention to greatly improve calculation efficiency when each layer of a hierarchical neural network is performed in a time division manner with a plurality of calculation elements.

  In order to achieve the object of the present invention, for example, a parallel processing apparatus of the present invention comprises the following arrangement.

That is, in a hierarchical neural network having a local receptive field structure common between neuron elements,
Division multiplexing that divides the output signal from the neuron element belonging to the previous hierarchical level as data input to the synaptic connection that defines the receptive field so that each divided signal has an overlapping part in time series with other divided signals It has the means.

  According to the configuration of the present invention, when each layer of the hierarchical neural network is performed in a time division manner with a plurality of arithmetic elements, the arithmetic efficiency can be greatly improved.

  Hereinafter, the present invention will be described in detail according to preferred embodiments with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a basic configuration of a parallel processing apparatus according to the present embodiment. As shown in the figure, the parallel processing apparatus according to the present embodiment includes a data input control circuit 1, a neuron array circuit block 2, a synapse array circuit block 3, a processing result holding memory 4, a division multiplexed signal generation circuit block 5, an acceptance The field structure control circuit block 6 and the overall control circuit block 7 are the main components.

  Here, when a multilayer neural network is implemented as an analog / digital mixed circuit or a fusion circuit, it is often difficult to realize parallel processing by arranging all the components such as neurons and synapses in parallel on a two-dimensional plane. . Therefore, also in this embodiment, time division processing is performed using a small number of neurons or synapse circuit elements. That is, processing in each layer is performed in a time division manner.

  Also, in the time division processing performed in the prior art, the loading frequency of the receptive field structure (synaptic connection load distribution) of each neuron from the memory or the reading frequency of the intermediate result from the memory holding the intermediate processing result of each hierarchy is high. The processing time becomes slower and the power consumption increases, but by using the multiplexed data expression described below, it is possible to avoid a decrease in processing speed due to memory access and an increase in power consumption due to switching energy. It becomes possible.

  In FIG. 1, a data input control circuit 1 is a control circuit for inputting image data or the like from a sensor or a database, and has a primary storage memory therein.

  In the neuron array circuit block 2, a plurality of neuron circuits belonging to a predetermined hierarchy in the hierarchical processing structure are arranged. That is, in this embodiment, what is realized by using the neuron array circuit block 2 in a certain time range is one layer of a multilayer neural network (or a neuron involved in detection of one feature class in one layer) Neurons belonging to other layers (or neurons involved in the detection of other feature classes) are realized in different time zones.

  In the synapse array circuit block 3, synapse connection circuits between neurons are arranged in a two-dimensional array. Here, a case where there is a synaptic connection between different layers will be described. The synapse array circuit block 3 realizes synapse connection to a certain hierarchical level.

  In the synapse array circuit block 3, the receptive field structure control circuit block 6 controls the coupling structure with the neuron circuit in the neuron array circuit block 2. The receptive field structure control circuit block 6 stores receptive field structure data corresponding to the feature class in its own internal memory.

  The processing result holding memory 4 is a memory that temporarily holds the output from the neuron array circuit block 2. The division multiplexing signal generation circuit block 5 supplies the output signal from the neuron array to the synapse array circuit block 3 after time division multiplexing.

  The overall control circuit 7 controls the operation of each circuit block to control signal input / output from the lower layer to the upper layer in the multilayer neural network.

  Note that the multilayer neural network realized by the parallel processing device according to the present embodiment is not limited to the feedforward coupling type, and may include a regression coupling or a feedback coupling.

  FIG. 5 is a diagram showing a configuration of a model of a multilayer neural network realized by the parallel processing device according to the present embodiment.

  The neural network shown in the figure handles information related to recognition (detection) of objects or geometric features in a local area in input data hierarchically, and its basic structure is a so-called Convolutional network. Structure (LeCun, Y. and Bengio Y., 1995, “Convolutional Networks for Images Speech, and Time Series” in Handbook of Brain Theory and Neural Networks (M. Arbib, Ed.), MIT Press, pp. 255-258) It is. The output from the final layer (uppermost layer) is a recognized target category as a recognition result and position information on the input data.

  In FIG. 5, a data input layer 101 is a layer for inputting local area data from a photoelectric conversion element such as a CMOS sensor or a CCD element. The feature detection layer 102a (1, 0) displays local low-order features (a specific direction component, a specific spatial frequency component, and other geometric features such as a color component feature in the image pattern input from the data input layer 101. Multiple feature categories at multiple scale levels or resolutions at the same location in a local region (or a local region centered on each point of a predetermined sampling point over the entire screen) centered on each position on the entire screen. As many as are detected. For this purpose, it has a receptive field structure corresponding to the type of feature (for example, when a line segment in a predetermined direction is extracted as a geometric feature) It consists of neuron elements that generate a corresponding pulse train.

  The feature integration layer 103a (2, 0) has a predetermined receptive field structure (hereinafter, the receptive field means the coupling range with the output element of the immediately preceding layer, and the receptive field structure means the distribution of the coupling load). A plurality of neuron element outputs in the same receptive field 105 from the feature detection layer 102a (1, 0) (subsampling by local averaging, maximum output detection, etc.) ). Each receptive field of neurons in the feature integration layer has a common structure among neurons in the same layer. This is called weight sharing.

  Each of the feature detection layers ((1, 1), (1, 2),..., (1, M)) subsequent to the feature detection layer 102a, and the feature integration layer ((2, 1) subsequent to the feature integration layer 103a. ), (2, 2),..., (2, M)) each have a predetermined receptive field structure and function in the same manner as the above-described layers. That is, the feature detection layer ((1, 1),...) Detects a plurality of different features in the feature detection module 104a (the same applies to 104b), and the feature integration layer ((2, 1),...) In the feature integration module 106a (same for 106b), detection results relating to a plurality of features from the preceding feature detection layer are integrated.

  However, the feature detection layer is coupled (wired) to receive the cell element output of the preceding feature integration layer belonging to the same channel. In addition, subsampling, which is processing performed in the feature integration layer 103, is performed by averaging the output from the local region (local receptive field of the feature integration layer neuron) from the feature detection cell population of the same feature category, or maximizing Value detection is performed.

  8A and 8B show the output (from the cell) of the neuron group (ni) of the feature integration (or feature detection) cells that form a receptive field for a certain feature detection (or feature integration) cell (neuron in the feature detection layer). It is a figure which shows the structure of the coupling | bonding means which participates when it sees and input. The signal transmission unit 203 forms a local common bus line, and pulse signals from a plurality of neurons are transmitted in time series on the signal transmission line.

  In so-called excitatory coupling, pulse signals are amplified in a synaptic coupling circuit, and inhibitory coupling conversely provides attenuation. When information is transmitted using a pulse signal, amplification and attenuation can be realized by any of amplitude modulation, pulse width modulation, phase modulation, and frequency modulation of the pulse signal. In this embodiment, the synapse coupling circuit is mainly used as a phase modulation element of a pulse, and signal amplification is converted into a substantial advance of the pulse arrival time as a characteristic intrinsic amount, and attenuation is converted as a substantial delay. Is done. As a circuit for performing pulse phase modulation, configurations disclosed in JP-A-10-327054, JP-A-5-37317, JP-A-6-61808 and the like are known.

  When the synapse coupling circuit performs pulse phase modulation, the arrival position (phase) on the time axis specific to each feature is given to the output destination neuron, but in addition to the phase, the level of the input signal (in phase) Phase shift corresponding to a value obtained by multiplying a given coefficient by a coefficient corresponding to a predetermined synaptic load. In this case, qualitatively, the excitatory coupling gives a phase advance of the arrival pulse with respect to a certain reference phase, and the inhibitory coupling similarly gives a delay.

  In FIG. 8A, each neuron element nj (1 ≦ j ≦ k) outputs a pulse signal (spike train), and performs so-called integral-and-fire type input / output processing. First, the neuron circuit will be described. Each neuron element is an expansion model based on so-called integrate-and-fire neurons. When the result of linear addition of the input signal (pulse train corresponding to the action potential) exceeds the threshold value, it fires and pulses This is the same as a so-called integrate-and-fire neuron in that a state signal is output.

  FIG. 8B shows an example of a basic configuration representing the operation principle of a pulse generation circuit (CMOS circuit) as a neuron element, which enables execution of weighted integration of an input pulse signal within a predetermined time window.

  Here, it is configured to receive an excitatory and inhibitory input as an input signal. Note that the operation control mechanism of the pulse firing timing of each neuron element is not the main point of the present application, and thus the description thereof is omitted.

  Next, a method for generating a division multiplexed signal in a neural network having a hierarchical structure will be described.

  The output from the lower layer in the receptive field of a certain upper layer neuron forms a subset of all the neuron outputs in the lower layer. In the so-called Convolutional Network structure, neurons that belong to the same feature class at the same hierarchical level have a common receptive field structure, but the subset of lower-layer neuron output that is input to each upper-layer neuron is partially A data set with duplicates. Therefore, a synapse array circuit corresponding to one receptive field structure is inputted by dividing and multiplexing different data sets of lower layer neuron outputs.

  The data input to the synapse circuit at a given position in a given receptive field structure depends on the position of neurons in the feature detection layer (corresponding to the position on the input image data), and the data is already It has been read. Therefore, when the signal input operation to each neuron in the feature detection layer is performed in a predetermined order, the feature integration layer neuron output to be input to each synapse circuit in the receptive field of the feature detection layer neuron is Since it is determined according to the position of the feature detection layer neuron, a signal input to each synapse circuit can be generated in advance as time series data determined by the scanning order of the feature detection layer neuron. That is, partial reproduction can be performed by performing predetermined sampling of output data from all neurons stored in advance as feature series output data given to each synapse circuit as time series data.

  In this embodiment, outputs from all neurons (total n · m) belonging to a predetermined feature class in the feature integration layer in the preceding stage of the feature detection layer are sequentially read in time series (in a raster format or the like) ( (N · m time-series data shown in FIG. 3A) and stored as read data in a predetermined processing result holding memory 4 (SDRAM, MRAM, FRAM, etc.).

  Thereafter, the division multiplexing signal generation circuit block 5 causes the feature integration layer neuron output (data read from the processing result holding memory 4) belonging to the receptive field of each neuron of the feature detection layer to have overlapping portions as shown in FIG. 3A. Then, the divided data are temporally connected as shown in FIG. 3B to form one time series data (FIG. 3B), or the divided data are output in parallel as shown in FIG. 3C. A branch is input to each synapse (synapse 1, synapse 2,...) Of the synapse array circuit. By utilizing this method, partial reproduction of an arbitrary waveform can be performed with high accuracy and at high speed. Note that predetermined signal conversion may be performed on the read data from the processing result holding memory 4. For example, when a pulse signal is handled by a neuron circuit and a synapse circuit, it may be converted into signal data having a pulse phase or pulse width corresponding to the value of read data.

  As shown in FIG. 4A, partial cutout data whose sections do not overlap each other may be stored in a plurality of memories and output in parallel. In this case, as shown in FIG. 4B, for example, the division multiplexed signal generation circuit block 5 includes a segmented sampling unit 59, a memory data transfer control unit 56, a plurality of memories 57 (M1, M2,..., Mk), a pulse signal generator. 55 (PG1, PG2,..., PGk), a D / A converter 52 (DA1, DA2,..., DAk), and a parallel output port 54.

  Data transfer between adjacent memories is possible, and each time the position of a feature detection layer neuron belonging to a certain feature class is sequentially switched, each data address in the memory is shifted to transfer non-overlapping data from the adjacent memory. Then, the partial cut-out data to be output from each memory is updated, and D / A conversion and pulse signal generation are performed on each partial data and output in parallel. As described above, the contents of the data held in each memory are section data which are overlapped before and after data transfer, and multiplexed data transfer is performed as a whole.

  The output level on the vertical axis of the data shown in FIG. 3B represents a higher output level as the phase value is smaller in the representation format of the neuron output by the pulse phase (value is in the range of 0 to 2π). The data of FIG. 3B is a continuous curve display, but is actually discrete data obtained by sampling each neuron output in the receptive field. In the pulse phase expression, as shown in FIG. 6, each section divided by a certain time width corresponds to a different neuron in the lower layer, and the pulse phase expression is performed at a position (analog amount) in the section.

  Partial segmentation of time-series data is performed by a multiplexing sampling circuit 51 in the division multiplexing signal generation circuit block 5 shown in FIG. 2A. The multiplexed sampling circuit 51 performs segmented sampling, which is a function for extracting predetermined section data from a series of data sets. As shown in FIG. 2, the division multiplexing signal generation circuit block 5 includes a function generation circuit 50, a multiplexing sampling circuit 51, a D / A converter 52, a demultiplexer 53, and a pulse signal generator 55 as main components.

  Here, the data read out from the processing result holding memory 4 is input, the multiple sampling circuit 51 samples a plurality of time series data sets input to each synapse circuit as shown in FIG. Generate digital waveforms. The D / A converter 52 and the pulse signal generator 55 generate a pulse phase modulation signal having a phase corresponding to the neuron output level of the previous hierarchical level. The phase reference of this pulse signal is given by a predetermined timing signal (clock signal).

  Partially cut-out data is a receptive field structure that has a common structure among neurons when raster scanning a two-dimensionally arranged upper layer neuron array circuit among the outputs from lower layer neurons belonging to the upper layer neuron's receptive field Data to be input to a synapse circuit at a specific position in the time series. The synapse numbers (synapse 1, synapse 2,...) On the synapse array circuit are arranged in raster scanning order.

  When the multiplexed sampling circuit 51 is configured to output the partial cutout data from a plurality of ports (for example, one column of the synapse array circuit) in parallel and in parallel, the synapse array circuit block 3 and Each input / output port of the division multiplexing signal generation circuit 5 (corresponding to the parallel output port 54 of the division multiplexing generation circuit 5 in FIG. 2B) can be connected in parallel.

  In this time-series data set, if the corresponding synapse circuit blocks are close to each other (that is, if the neurons receiving signals modulated by the synapses are in close proximity to each other), the data shown in FIG. It becomes sampled data.

  The multiplexed sampling circuit 51 sorts data in a partially overlapping section from output data (assumed to be sampled in time series) from all neurons involved in a feature class having a feature integration layer. And each piece of segment data is temporally linked to generate one time series data (see FIG. 3B), or each piece of segment data is output in parallel (see FIG. 3C).

  In this embodiment, as a representation format of a plurality of neuron outputs of a neural network, a data representation format that handles a plurality of data sets in units of partial section data in the original complete data in this way is divided. It is called multiplexed expression, and an expression form that is shifted in time like the former is called time division multiplexed expression.

  The time-series data generated from the multiplexed sampling circuit 51 and the function generation circuit 50 is D / A converted by the D / A converter 52, and the demultiplexer 53 branches and outputs each time division data to a predetermined synapse circuit. This branching is performed by switching in the switching circuit built in the demultiplexer circuit 53 every time the update timing data of a time segment synchronized with a predetermined clock signal is input.

  If the position on the time axis of the signal is set in advance within a predetermined range according to the position of the synapse connection, the position of the synapse is identified by the pulse signal position on the time axis, and the clock The signal is branched using a demultiplexer 53 that operates in synchronization with the signal, and an output signal from the feature integration layer is appropriately input to a predetermined synapse circuit.

  The processing performed in the division multiplexed signal generation circuit block 5 is a digital circuit that creates a digital waveform by the look-up table (LUT) method (by the LUT generation circuit 50 in FIG. 2A), and converts the signal in the necessary range to D / A. A method of making an analog waveform by a converter may be used.

  According to the data representation format for division multiplexing as described above, it is not necessary to repeat input / output operations relating to data writing to or reading from the memory, and only one memory access per feature class is required. Therefore, it is possible to prevent the processing time from being reduced due to the memory access time and increase the speed.

  In the present embodiment, a synapse array corresponding to one receptive field with respect to a certain feature class of a single neuron is utilized by utilizing that a receptive field has a common structure between feature detection (integration) layer neurons that detect features of the same class. The above-described division multiplexed signal is input to the synapse circuit using a circuit, and time window integration of the modulated pulse train signal is performed in each neuron circuit.

  In the present embodiment, the synapse array circuit block 3 includes a demultiplexer as an output branching means for switching the output destination neurons of the neuron array circuit block 2 and realizes neurons belonging to the next hierarchical level or the next feature class. Signal propagation from the synapse array circuit block 3 to the array block 2 is performed via a demultiplexer in which an output destination (that is, an output destination neuron) is switched in a predetermined order. That is, the modulated pulse train data output from each synapse circuit is output to a neuron circuit in which each pulse is different.

  If an array of neuron circuits that are involved in the detection of multiple different feature classes at the same hierarchical level cannot be placed in parallel on the same board, the configuration inside the neuron array circuit block for each feature class to be detected Switching to a configuration suitable for class detection (or resetting the internal state) may be performed sequentially. In order to realize the control of the receptive field structure that changes the synapse circuit configuration and the characteristic control of the neuron circuit, a circuit configuration such as FPGA (Field Programmable Gate Array) or FPAA (Field Programmable Analog Array) may be used.

  Further, the parallel processing device described above can be mounted as a pattern recognition unit on a camera or other image input unit, or on a printer, display, or other image output unit. As a result, a specific object is recognized or detected by a small circuit configuration with low power consumption, and for a predetermined operation, for example, for an image input unit, focusing, exposure correction, zooming, or color correction centering on the specific object. Etc. can be performed. The image output means can also automatically perform processing such as optimum color correction for a specific subject.

  Next, by mounting a pattern detection (recognition) device to which the parallel processing device according to this embodiment is applied to an imaging device that is one of the image input devices, focusing on a specific subject, color correction of a specific subject, exposure The case of performing the control will be described with reference to FIG. FIG. 11 is a diagram illustrating a configuration of an example in which the pattern detection (recognition) apparatus according to the present embodiment is used in an imaging apparatus.

  Here, the imaging device 1101 includes an imaging optical system 1102 including a photographing lens and a zoom photographing drive control mechanism, a CCD or CMOS image sensor 1103, an imaging parameter measurement unit 1104, a video signal processing circuit 1105, a storage unit 1106, and an imaging operation. Control signal generator 1107 for generating control signals such as control of image capturing and image pickup conditions, display display 1108 that also serves as a finder such as EVF, strobe light emitting unit 1109, recording medium 1110, etc., and the above-described time-division multiplexing A parallel processing device (which functions as a pattern recognition device) that performs the conversion processing is provided as a recognition parallel processing device 1111.

  The imaging device 1101 performs, for example, a recognition parallel processing device 1111 to detect a person registered in advance in a captured video (with detection of the existing position and size). Then, when the position and size information of the person is input from the recognition parallel processing device 1111 to the control signal generation unit 1107, the control signal generation unit 1107 is based on the output from the imaging parameter measurement unit 1104. Generates control signals for optimal focus control, exposure condition control, white balance control, etc.

  As a result of applying the above-described parallel processing device to pattern detection (recognition) and using it in the imaging device as described above, it is possible to perform human detection and optimum control of shooting based on it at high speed with a small and low power consumption circuit. It becomes like this.

  As described above, according to the present embodiment, by using a data expression that multiplexes intermediate outputs of a plurality of arithmetic elements at once in a parallel processing device in which a plurality of arithmetic elements are coupled in parallel. The calculation efficiency can be greatly improved.

  In particular, in a hierarchical neural network (for example, a convolutional network structure) in which the receptive field structure is partially shared, multiple data sets input to each neuron having the shared receptive field are processed in a time-sharing manner. In this case, each data set is expressed in a function, curve, or lookup table format in a time-division multiplexed manner, so that the memory access associated with each data set input / output can be minimized. , Processing speed can be improved.

[Second Embodiment]
In the present embodiment, in a circuit configuration that implements a multilayer neural network, a multiplexed representation of a data structure is performed by multiplexing signals from different neurons in the frequency domain.

  In addition, signals from each receptive field are separated by filtering in the frequency domain in an upper layer neuron that detects a plurality of lower layer neuron outputs (a multiplexed signal in which signals of different baseband frequencies are mixed). Hereinafter, the multiplexing process on the frequency axis of the data structure will be described.

  In this embodiment, in a hierarchical neural network in which local receptive field structures of neurons involved in detection of the same feature class as shown in FIG. Different baseband frequencies may be assigned in units of receptive fields input to (belonging to the same feature class). That is, the “waveform” signal of the time-series output data (input to different neurons) corresponding to each receptive field is modulated and placed on a carrier signal having a different baseband frequency. FIG. 12 is a diagram conceptually showing the spectrum of each component (output to different neurons) of the frequency-multiplexed signal.

  As an example of frequency multiplexing, a case where an optical signal is used as a signal propagating between layers and an optical data is used as a signal propagation carrier and the data structure of the output from each neuron is wavelength-multiplexed will be described below. . FIG. 7 shows a configuration diagram of a main part when wavelength multiplexing is performed. The wavelength multiplexing technology is described in a special article (pages 111-140) of the magazine Optronics (May 1996), a special article (page 3-31) of the optical technology contact (October 2001 issue), etc. Yes.

  In this case, each layer of the multilayer neural network is formed of a CMOS circuit 150 (IEEE Circuits and Systems Magazine, vol. 1, No. 3, 2001, pp. 22-) formed on a transparent sapphire substrate 130 in a predetermined wavelength range. Article 30: See "Silicon on Sapphire CMOS for Optoelectronic Microsystems,"), wavelength multiplexing light source 120 (multiple fixed wavelength light sources with different wavelengths, or semiconductor laser array as wavelength tunable light source, etc.), wavelength selectivity The optical filter 100 having a photoelectric conversion unit, a photoelectric conversion unit (photodetector) 110, and the like. The CMOS circuit 150 is mainly composed of a neuron array circuit and / or a synapse array circuit.

  As the interlayer coupling unit 140, an optical fiber, an optical medium network having wavelength selectivity represented by a diffraction grating array optical waveguide, a spatial light modulation element having a light deflection function such as a photoacoustic element, or the like is used. When the CMOS circuit 150 includes a neuron array circuit but does not include the synapse array circuit block 2, it is assumed that the interlayer coupling unit 140 includes a synapse array circuit including optical amplifiers having different gains depending on wavelengths. In this case, an optical amplifying device having a gain different depending on the wavelength with respect to the optical signal after passing through the wavelength tunable or fixed wavelength optical filter may be used as a device corresponding to the synaptic load.

  In this way, the synapse array circuit block 2 has each signal (either an electric signal or a light wave signal) separated from the signal multiplexed on the frequency axis (output set from a plurality of receptive fields) using a filter. Performs a predetermined product-sum operation on the synaptic load values and output signals from other neuron elements in the frequency domain to which each signal belongs, and a product obtained in a different frequency domain using a demultiplexer or other means for branch output The sum operation result (which may be either an electric signal or a light wave signal) is branched and output to an output destination neuron corresponding to the frequency domain. Note that the product-sum operation with a synaptic load value for a pulse signal (electrical signal) is described in the literature (AF Murray et al., “Pulse-Stream VLSI Neural Networks Mixing Analog and Digital Techniques,” IEEE Trans. On Neural Networks, vol.2, pp.193-204., 1991) can be used.

  The neuron element is configured as an analog / digital mixed (fusion) circuit on the CMOS circuit 150, and its output signal is an optical signal having a different wavelength according to the receptive field to which the neuron element belongs (after all, depending on the output destination neuron). And output as a wavelength multiplexed signal. For this purpose, a light source (configured by a semiconductor laser array or the like) 120 is set in combination with the output part of the neuron element.

  When the feature detection layer neurons of the hierarchical neural network of FIG. 5 are realized in the neuron array circuit block 2, each synapse circuit of the synapse array circuit block 3 coupled thereto detects a feature class having a feature detection layer. Forming a receptive field structure of a neuron that forms part or all of a connection structure with neurons belonging to one or a plurality of feature classes of the feature integration layer.

  When the synapse circuit block forms all of the connection structure that constitutes one receptive field of the feature detection layer neuron, the multiplexed signals to be input to each neuron belonging to a feature class of the feature detection layer are mutually connected. It is the same feature integration layer neuron output that belongs to overlapping receptive fields and should be input to different feature detection layer neurons.

[Third Embodiment]
In this embodiment, when the receptive fields of the neurons in the hierarchical neural network have a partially common structure, the structures of a plurality of digital data sets input to the plurality of neurons having the common receptive field structure are collectively displayed. Thus, the data representation format is multiplexed in the bit depth direction.

  As shown in FIG. 9, the division multiplexed signal generation circuit block according to the present embodiment includes a segmented sampling unit 59, a parameter approximating unit 65, a bit depth direction data converting unit 60, a segmented data synthesizing unit 61, and the like. .

  For example, the parameter approximating unit 65 fits a curve represented by a parametric approximating the “waveform” of each segment data, and sets the parameter data (assuming k pieces) as a result as one segment data and To do.

  The multiplexed representation of data is performed by the bit depth direction converting unit 60 and the segmented data synthesizing unit 61. When the data corresponding to a specific position of the receptive field structure is expressed by Q bits, if the number of output destination neurons that share the receptive field structure is k, the data representation is shown in the upper graph of FIG. And each segment data to each output destination neuron is expressed by [Q / N] = p bits (where [x] means rounding x to an integer).

  That is, the bit depth direction data conversion unit 60 assigns 0 to p bits to the first segment data and p + 1 to 2p bits to the second segment data as shown in the lower diagram of FIG. Thus, a divided representation of a plurality of segmented data is performed in the bit depth direction.

  Each segment data is further expressed in s divisions in the bit depth direction so as to represent s parameter data. Needless to say, the division in the bit depth direction needs to be set so that the result of the conversion by the synapse circuit performed later falls within the bit width p of the given divided data. Each segment data is data to be input to each of a plurality of neurons having a common receptive field structure, and is an output from other neurons belonging to each receptive field.

  The segment data combining unit 61 generates one combined data as shown in the lower diagram of FIG. 10 using the segment data converted in the bit depth direction as described above as an example. Although not shown in FIG. 9, the segmented data combining unit 61 may obtain an analog signal by performing predetermined D / A conversion or other conversion on the combined data.

  The synapse array circuit block 3 performs a predetermined operation corresponding to the synapse load value (such as integration of the synapse load value and the divided data) for each divided data of the signal multiplexed in the bit depth direction. When the product-sum operation result for the divided data having the same bit depth is obtained, each operation result multiplexed in the bit depth direction is divided and extracted by a shift register or the like, and a branch output unit such as a demultiplexer (FIG. 1). (Not shown in FIG. 2), the data is branched and output to neurons (in the neuron array circuit block 2) corresponding to each bit depth level.

  If the above-described curve fitting is not performed, the parameter approximation unit 65 is not necessary, but is represented by a finite number (k) of data sets, and the entire data set is expressed in a multiplexed manner. Shall not change.

  As described above, the processing speed can be further improved by using the frequency-multiplexed representation of the entire intermediate data set or the multiplexed representation in the bit depth direction.

  In the above embodiment, a neural network is used as a processing system that performs information processing from a lower layer to an upper layer with a hierarchical structure. However, the present invention is not limited to this.

It is a block diagram which shows the basic composition of the parallel processing apparatus which concerns on the 1st Embodiment of this invention. FIG. 6 is a diagram showing a configuration of a division multiplexed signal generation circuit block 5; FIG. 6 is a diagram showing a configuration of a division multiplexed signal generation circuit block 5; It is a figure for demonstrating the content which processes the output from all the neurons which belong to the predetermined feature class of the feature integration layer in the front | former stage of a feature detection layer. It is a figure for demonstrating the content which processes the output from all the neurons which belong to the predetermined feature class of the feature integration layer in the front | former stage of a feature detection layer. It is a figure for demonstrating the content which processes the output from all the neurons which belong to the predetermined feature class of the feature integration layer in the front | former stage of a feature detection layer. It is a figure explaining the example which stores the partial cut-out data which an area does not mutually overlap in a some memory, and outputs it in parallel. It is a figure which shows the structure of the division multiplexing signal generation circuit block 5 in the case of processing partially cut-out data as shown in FIG. 4A. It is a figure which shows the structure of the model of the multilayer neural network which the parallel processing apparatus concerning this embodiment implement | achieves. It is a figure explaining the pulse phase expression of the signal to each neuron. It is a figure which shows the principal part block diagram in the case of performing wavelength multiplexing. Participates in the output from the neuron group (ni) of feature-integrated (or feature-detected) cells that form a receptive field for certain feature-detected (or feature-integrated) cells (neurons in the feature-detecting layer) It is a figure which shows the structure of the coupling | bonding means to do. Participates in the output from the neuron group (ni) of feature-integrated (or feature-detected) cells that form a receptive field for certain feature-detected (or feature-integrated) cells (neurons in the feature-detecting layer) It is a figure which shows the structure of the coupling | bonding means to do. It is a figure which shows the structure of the division multiplexing signal generation circuit block of the 3rd Embodiment of this invention. It is a figure explaining the data expression in 3rd Embodiment. It is a figure which shows the structure of the example which used the pattern detection (recognition) apparatus which concerns on the 1st Embodiment of this invention for an imaging device. It is a figure which shows notionally the spectrum of each component (output to a different neuron) of the frequency multiplexed signal.

Claims (11)

In a hierarchical neural network having a local receptive field structure common between neuron elements,
Division multiplexing that divides the output signal from the neuron element belonging to the previous hierarchical level as data input to the synaptic connection that defines the receptive field so that each divided signal has an overlapping part in time series with other divided signals A parallel processing apparatus in which data structures are multiplexed, characterized by comprising means. The hierarchical neural network has a hierarchical structure in which a feature detection layer and a feature integration layer are alternately arranged, and the feature detection layer and the feature integration layer each detect and integrate at least one feature. 2. A parallel processing apparatus in which the data structure according to claim 1 is multiplexed. The structure of the data input to the synapse connection is such that a signal representing an integration result relating to a preset feature from the previous hierarchical level is included in a preset region where the input data of the hierarchical neural network overlap each other. 2. The parallel processing apparatus according to claim 1 , wherein the data structure is arranged as one time series data as a signal corresponding to each position. The structure of data input to the synapse connection is a signal representing an integration result relating to a preset feature from the previous hierarchical level, and a plurality of preset sampling point positions of the entire input data to the hierarchical neural network extracted in response to, in claim 3, characterized in that formed by arranging a set of data corresponding to partially overlapping interval with each other in the input data from the extracted signal as one time-series data A parallel processing device in which the described data structure is multiplexed. The structure of data input to the synapse connection is a signal representing an integration result relating to a preset feature from the previous hierarchical level, and a plurality of preset sampling point positions of the entire input data to the hierarchical neural network And a set of the signals corresponding to a plurality of partial sections of the input data that do not overlap with each other are arranged in parallel from the extracted signals, and the signals of the partial sections are adjacent to each other. 4. The parallel processing apparatus according to claim 3 , wherein a part of the data in the partial section is transferred as one time series data. The hierarchical neural network has a structure in which a plurality of synapse connection circuits and a plurality of neuron circuits are arranged in a preset method, and the structure of data input to the synapse connection circuit is determined from the previous hierarchical level. Is a time-series data in which signals representing the integration results relating to preset features are arranged in the time axis direction, each data being associated with a preset sampling position of the input data and corresponding to a different sampling position. 5. The parallel processing apparatus according to claim 4 , wherein the time-series data arranged in the time axis direction and input to the adjacent synapse coupling circuits include data overlapping each other. . The time-series data is a partial data set in advance from the entire data extracted in time series by associating a signal representing an integration result relating to a preset feature from the previous hierarchical level with different sampling positions of the input data. 7. The parallel processing apparatus according to claim 6 , wherein the data structures are arranged as one time series data. In a hierarchical neural network having a local receptive field structure common between neuron elements,
Synaptic connections that define receptive fields;
Division multiplexed signal generating means for dividing and converting an output signal from a neuron element belonging to the previous hierarchical level as data input to the synapse connection so that each divided signal has an overlapping portion with another divided signal; A parallel processing apparatus in which data structures are multiplexed. The division multiplexed signal generation means includes:
A sampling means for sampling a plurality of the output signals and extracting the output signals of a plurality of overlapping sections;
9. The parallel processing device with multiplexed data structure according to claim 8 , further comprising: a time-series data generation circuit that generates a single time-series data by integrating a plurality of segmented data. The division multiplexed signal generation means includes:
A sampling means for sampling a plurality of the output signals and extracting the output signals of a plurality of non-overlapping sections;
A plurality of memories each storing segmented data;
Memory control means for performing data transfer control between the plurality of memories so that there is overlapping partitioned data before and after data transfer;
9. The parallel processing apparatus according to claim 8 , further comprising parallel output means for outputting the segmented data in the memory in parallel each time the data transfer is performed. 11. The data structure according to claim 9 or 10 , wherein the segmented data is data obtained by time-sequentially outputting other neuron element belonging to a preset receptive field of the neuron element. Parallel processing device.

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