JP4844143B2 - Memory bus load adjustment device - Google Patents

Description

  The present invention relates to a memory bus load adjusting device for inputting / outputting a plurality of video signals to / from a memory.

2. Description of the Related Art Conventionally, a memory load adjustment device is known as an interface for displaying a plurality of video signals on a single display device (see, for example, Patent Documents 1 and 2) . A specific example of this memory load adjusting device is shown in FIG.

  FIG. 4 is a block diagram of a conventional memory bus load adjusting device. As shown in this figure, the conventional memory bus load adjusting device 200 includes input IFs (interfaces) 11 to 13 for inputting video signals (for example, NTSC signals) from the outside, input side memories 21 to 23, and memory arbitration. The circuit unit 41, the shared memory 50, the output side memories 61 to 63, and the output IFs 81 to 83 for outputting video signal data from the output side memories 61 to 63 to a display device (not shown). Yes.

  The input side memories 21 to 23 and the output side memories 61 to 63 are so-called FiFo memories for adjusting the input / output speed of the video signal. Such input-side memories 21 to 23 and output-side memories 61 to 63 have a capacity for storing data for one line of one screen (frame), for example, and output from the oldest data among the stored data. .

  The memory arbitration circuit unit 41 inputs data from the input side memories 21 to 23 and stores the data in the shared memory 50 and outputs the data stored in the shared memory 50 to the output side memories 61 to 63. It has a function of reading and writing data in accordance with the priority order of reading data from the input side memories 21 to 23 preferentially and writing to which output side memories 61 to 63. Yes. The priority order is determined by the memory arbitration circuit unit 40 based on a result confirmed in advance by a desktop calculation or a test by an actual machine.

  The shared memory 50 is a storage medium having a capacity for storing a plurality of frames of data. The shared memory 50 outputs data input from the input side memories 21 to 23 via the memory arbitration circuit unit 41 to the output side memories 61 to 63 in response to a request from the memory arbitration circuit unit 41.

  In the memory bus load adjusting device 200 having the above configuration, when the video signals input to the input IFs 11 to 13 are input to the input memories 21 to 23, the video signals are stored in the input memories 21 to 23, respectively. Each piece of data is read out by the memory arbitration circuit unit 40 in accordance with the priority order and stored in the shared memory 50. Further, each data stored in the shared memory 50 is written in each output side memory 61-63 according to the priority in the memory arbitration circuit unit 41, and is output to the display device via each output IF 81-83. .

As described above, according to the priority order determined by the memory arbitration circuit unit 41, the data is read from the input memories 21 to 23 and the data is written to the output memories 61 to 63. .
JP-A-11-53247 Japanese Patent Laid-Open No. 11-191075

  However, in the above conventional technique, if the number of video signals to be handled increases, the shared memory 50 must be shared by many video signals. Therefore, the memory arbitration circuit unit 41 reads and writes data by desktop calculation or the like. It becomes difficult to determine priorities. As a result, even if each video signal is taken into the memory bus load adjusting device 200, there is a possibility that all the data is not output to the display device. Therefore, for example, display of 60 frames per second becomes display of 30 frames, and real-time display cannot be performed, and display quality may be deteriorated.

  In view of the above points, the present invention efficiently reads out the data stored in each input side memory and stores it in the shared memory, and efficiently outputs the data stored in the shared memory to the output side memory. It is an object of the present invention to provide a memory bus load adjusting device that can efficiently share a memory card.

  In order to achieve the above object, the present invention monitors a data amount of each of a plurality of input side memories (21 to 23), and obtains a minimum value of a free capacity of each input side memory that changes with time. Monitor units (31-33) and a plurality of output side memories (61-63), respectively, and monitor the amount of data, respectively, and obtain a maximum value of the free capacity of each output side memory that changes with time, respectively. And monitor units (71 to 73). Furthermore, the read priority is set so that the minimum value of the free space of each input side memory is obtained from each input side monitor unit, and the input side memory with the smallest obtained minimum value of free space is given the highest priority to read the data. Obtain the maximum value of the free capacity of each output side memory from the command output means and each output side monitor unit, and write the data giving the highest priority to the output side memory with the largest acquired maximum value of each free capacity And a priority order determination circuit section (90) having a means for outputting a write priority command. Then, the memory arbitration circuit unit (40) reads data from the memory on the input side that should have the highest priority, and stores the read data in the shared memory (50). Also, based on the write priority command, for each output side memory to which data should be written with the highest priority, the data read from the input side memory corresponding to the output side memory to be written and stored in the shared memory is shared It is characterized by reading from the memory and writing to the output side memory that should be given the highest priority.

  In this way, data can be read preferentially from the input side memory with a small free capacity and stored in the shared memory. Therefore, even if many video signals are input from the outside, the data of each input side memory can be efficiently stored in the shared memory, and the data of the video signal input from the outside is stored in each input side memory. It is also possible to prevent data from being lost beyond the amount of data that can be generated.

  Similarly, data can be written in preference to the output side memory having a large free space. As a result, the data stored in the shared memory can be efficiently output to each output side memory, and even if many video signals are handled, the shared memory can be efficiently shared. In addition, since one line of video signal data can be written to the output-side memory without interruption, it is possible to prevent deterioration in screen display quality in the display device such as video interruption.

  In this case, when data of one line constituting one screen represented by the video signal is input to the output-side memory, the output-side monitor unit outputs data indicating screen display start time (A) in one line. The period from the output from the external memory to the end of reading (B) when it is no longer necessary to read one line of data from the shared memory is used as the monitoring period, and the maximum free capacity is acquired during this monitoring period. Can do.

  In this way, data can be output from the output side memory to the outside without interruption, and as a result, the quality of image display can be ensured.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the following, the same components as those shown in FIG.

  The memory bus load adjusting device shown in the present embodiment is used, for example, as one that takes in a plurality of video signals and outputs them together in one display device, and functions as a signal interface mounted on, for example, a car navigation device of a vehicle. Is.

  FIG. 1 is a block diagram of a memory bus load adjustment device according to an embodiment of the present invention. As shown in this figure, the memory bus load adjusting device 100 includes input IFs 11 to 13, input side memories 21 to 23, input side monitor units 31 to 33, a memory arbitration circuit unit 40, and a shared memory 50. , Output side memories 61 to 63, output side monitor units 71 to 73, output IFs 81 to 83, and a priority order determining circuit unit 90.

  The input IFs 11 to 13 are interfaces for inputting video signals from the outside. That is, the input IFs 11 to 13 input, for example, data of 60 frames (screens) per second as NTSC signals. In the present embodiment, a plurality of input IFs 11 to 13 are provided, and different video signals and the like are input to the input IFs 11 to 13, respectively. Note that the video signals include those having different screen display sizes.

  The input side memories 21 to 23 are storage media for inputting the video signals input to the input IFs 11 to 13 and are used for adjusting the input speed of the video signals. Such input side memories 21 to 23 are configured as FiFo memories, and output data input from the input IFs 11 to 13 in the order of input. In the present embodiment, the input side memories 21 to 23 have a storage capacity for storing data for one line in one frame, for example.

  The input side monitoring units 31 to 33 monitor the data amount of the input side memories 21 to 23, and are provided corresponding to the input side memories 21 to 23, respectively. In the present embodiment, the input side monitor units 31 to 33 acquire the maximum value of the data amount that changes with time, in other words, the minimum value of the free capacity (margin number) of the input side memories 21 to 23.

  These input IFs 11 to 13, input side memories 21 to 23, and input side monitor units 31 to 33 are set as one set for one video signal, and a set corresponding to the number of video signals handled by the memory bus load adjusting device 100. A number is provided.

  The memory arbitration circuit unit 40 reads data stored in the input side memories 21 to 23 and stores the data in the shared memory 50, and writes the data stored in the shared memory 50 to the output side memories 61 to 63. . The memory arbitration circuit unit 40 having such a function prioritizes one of the input side memories 21 to 23 based on a command from the priority order determination circuit unit 90, and the input side memory 21 to be prioritized. To read out data from ˜23 and store it in the shared memory 50 and read out from the input side memories 21 to 23 corresponding to the output side memories 61 to 63 with respect to the output side memories 61 to 63 to which data should be preferentially written. Means for writing the data stored in the shared memory 50 to the output side memories 61 to 63 to be prioritized.

  The shared memory 50 is a storage medium having a capacity for storing a plurality of frames of data, and is configured by a so-called DDR2 memory. The shared memory 50 outputs each data input from the input side memories 21 to 23 via the memory arbitration circuit unit 40 to the output side memories 61 to 63 in response to a request from the memory arbitration circuit unit 40. In the present embodiment, the shared memory 50 has a storage capacity of, for example, 4 frames.

  The output side memories 61 to 63 are storage media that store data input from the memory arbitration circuit unit 40. The output side memories 61 to 63 are configured as FiFo memories in the same manner as the input side memories 21 to 23.

  The output side monitor units 71 to 73 monitor the data amount of the output side memories 61 to 63, and are provided corresponding to the output side memories 61 to 63, respectively. In the present embodiment, the output side monitoring units 71 to 73 acquire the minimum value of the data amount that changes with time, in other words, the maximum value of the free capacity (margin number) of the output side memories 61 to 63.

  Further, the monitor period for the output side memories 61 to 63 in the output side monitor units 71 to 73 is such that when one line of one frame is displayed, the output side memories 61 to 63 start to display the one line on the screen on the display device. Is a period until it is not necessary to read data from the memory arbitration circuit unit 40.

  The output IFs 81 to 83 are interfaces that output data from the output side memories 61 to 63 to a display device (not shown).

  The output IFs 81 to 83, the output side memories 61 to 63, and the output side monitor units 71 to 73 are provided corresponding to the input IFs 11 to 13, the input side memories 21 to 23, and the input side monitor units 31 to 33, respectively.

  The priority order determination circuit unit 90 prioritizes which input side memories 21 to 23 give priority to data read from the memory arbitration circuit unit 40 and which output side memories 61 to 63 write data. The priority order is determined. Such a priority determining circuit unit 90 is constituted by a microcomputer including a CPU, for example.

  Specifically, the priority order determination circuit unit 90 acquires a minimum value of the free capacity from each of the input side monitor units 31 to 33 and acquires a maximum value of the free capacity from each of the output side monitor units 71 to 73, respectively. Means. Furthermore, the priority order determination circuit unit 90 sets a priority order to read data with the highest priority given to the input side memories 21 to 23 having the smallest minimum value of each free capacity acquired from the input side monitor units 31 to 33. And means for outputting a read priority command for reading data in the set priority order to the memory arbitration circuit unit 40, and an output side memory having the largest maximum value of each free capacity acquired from each of the output side monitor units 71 to 73 And a means for setting a priority order to write data with the highest priority on 61 to 63 and outputting a write priority command for writing data in the set priority order to the memory arbitration circuit unit 40.

  The above is the configuration of the memory bus load adjustment device 100 according to the present embodiment.

  Next, the operation of the memory bus load adjusting device 100 will be described with reference to the drawings. First, a description will be given of which input side memory 21 to 23 has priority for reading data from the input side memories 21 to 23 by the memory arbitration circuit unit 40.

  First, different video signals are inputted to the input IFs 11 to 13 shown in FIG. Each video signal is input with a plurality of video signals that the user wants to display, such as those having different display sizes and those that are once displayed on the screen again. Note that these video signals are input from the outside, for example, for each line of one frame.

  The video signal data input to each of the input IFs 11 to 13 is stored in the input side memories 21 to 23 corresponding to the respective input IFs 11 to 13, and the data stored in the input side memories 21 to 23 is stored in memory arbitration. The data is read by the circuit unit 40 and stored in the shared memory 50. This is shown in FIG.

  FIG. 2 is a diagram showing the data amount of one line input to the input side memories 21 to 23 with respect to time. As shown in this figure, one line is composed of screen area data and left and right blank area data of the screen area. In this embodiment, the input side memories 21 to 23 are synchronized with the phase of Vsync. Is input.

  The video signal data input to the input side memories 21 to 23 is read to the memory arbitration circuit unit 40 in the order of the input data and stored in the shared memory 50 while being input to the input side memories 21 to 23. The Therefore, as shown in FIG. 2, the amount of data stored in the input-side memories 21 to 23 fluctuates while increasing and decreasing repeatedly with the passage of time.

  As described above, while data is being written to or read from the input side memories 21 to 23, the input side monitor units 31 to 33 corresponding to the input side memories 21 to 23 have the time shown in FIG. The peak value of the fluctuating data amount is monitored, and the maximum value of the data amount in one line, that is, the minimum value of the free capacity is acquired. Such minimum values of the free capacities of the input side memories 21 to 23 are respectively acquired by the input side monitor units 31 to 33 corresponding to the input side memories 21 to 23, respectively.

  Then, the minimum value of each free capacity acquired by each of the input side monitor units 31 to 33 is acquired by the priority order determination circuit unit 90. As a result, the priority determining circuit unit 90 compares the minimum free capacity values of the input side memories 21 to 23 to determine which of the input side memories 21 to 23 has a small free capacity, that is, a limit on the amount of data that can be stored. Is determined. Therefore, in the priority order determination circuit unit 90, the memory arbitration circuit unit 40 is configured so that the data stored in the input side memories 21 to 23 having the smallest free capacity is read out with the highest priority. Priorities for reading data to the memories 21 to 23 are set. The priority order set in this way is output from the priority order determination circuit unit 90 to the memory arbitration circuit unit 40 as a read priority command.

  In the memory arbitration circuit unit 40 that has received the read priority command, data is read from the input memories 21 to 23 having a higher priority in accordance with the priority set in the read priority command, and the read data is shared. Stored in the memory 50. Thereby, the data of the video signal inputted to each of the input IFs 11 to 13 can be efficiently stored in the shared memory 50. Further, it is possible to prevent the data of the video signal input to the input IFs 11 to 13 from being lost beyond the amount of data that can be stored.

  In addition, when acquiring the minimum value of the free capacity of each input side memory 21-23 in each input side monitor part 31-33, the monitoring period is not provided in particular.

  Next, a description will be given of which of the output side memories 61 to 63 is prioritized and the memory arbitration circuit unit 40 writes the data stored in the shared memory 50.

  First, when the data stored in the shared memory 50 is written to the output side memories 61 to 63 and output to the outside via the output IFs 81 to 83, the memory arbitration circuit unit 40 reads the data stored in the shared memory 50. The data is output to the output side memories 61 to 63 corresponding to the input side memories 21 to 23 inputted from the outside. And the data written in the output side memories 61-63 are output to the display apparatus which is not illustrated via output IF81-83. This is shown in FIG.

  FIG. 3 is a diagram showing one line of data input to the output side memories 61 to 63 with respect to time. As shown in this figure, one line of data is input from the memory arbitration circuit unit 40 to the output side memories 61 to 63 in synchronization with the phase Vsync.

  The video signals input to the output side memories 61 to 63 are output to the display device via the output IFs 81 to 83 in the order of the input data while being input to the output side memories 61 to 63. Therefore, as shown in FIG. 3, the data amount of the data stored in the output side memories 61 to 63 fluctuates while increasing and decreasing over time as in FIG. 2, and finally the screen in one line. All data in the area is ejected from the output side memories 61-63. That is, when the output of the data for one line is completed in the output side memories 61 to 63, the free capacity of the output side memories 61 to 63 becomes 0, and the data of the next line is input.

  As described above, while data is being written or read in the output side memories 61 to 63, the output side monitor units 71 to 73 corresponding to the output side memories 61 to 63 have the time shown in FIG. The peak value of the fluctuating data amount is monitored, and the minimum value of the data amount in one line, that is, the maximum value of the free capacity is acquired. Such maximum values of the free capacities of the output-side memories 61 to 63 are acquired by the output-side monitor units 71 to 73 corresponding to the output-side memories 61 to 63, respectively.

  In the present embodiment, when acquiring the maximum value of the free capacity of each of the output-side memories 61 to 63 as described above, the shared memory 50 starts from the screen display start time A when reading ends (B) of the screen display of one line. The period from the end of reading until the end of reading B, which eliminates the need to read data from, is set as a monitoring period, and the maximum value of the free capacity is monitored during this monitoring period. When the output side monitor units 71 to 73 obtain the maximum value of the free capacity of one line, a new maximum value of the free capacity is acquired during the monitoring period for the next line. The maximum value of the free space acquired in this way is updated as needed with the latest value.

  This is because all the data stored in the output side memories 61 to 63 is output to the display device via the output IFs 81 to 83, the output side memories 61 to 63 become empty, and the display device cannot display the screen. This is for the purpose of efficiently inputting data to the output side memories 61 to 63 that always have the most available data capacity. Therefore, unlike the case of inputting a video signal, a monitor period is provided for obtaining the maximum value of the free capacity of the output side monitor units 71 to 73.

  Then, the maximum value of each free capacity acquired by each of the output side monitor units 71 to 73 is acquired by the priority order determination circuit unit 90. As described above, since the monitoring period is provided, the priority determination circuit unit 90 acquires the maximum value of the free capacity of each of the output side memories 61 to 63 in a short cycle.

  When the maximum value of the free space is acquired in this way, the priority determination circuit unit 90 compares the maximum value of the free space in each of the output side memories 61 to 63, and the free space is large, that is, the stored data amount is It is determined which of the remaining output side memories 61 to 63 is small. Therefore, in the priority order determination circuit unit 90, the memory arbitration circuit unit 40 causes the output side memories 61 to 63 to preferentially write data to the output side memories 61 to 63 having the largest free space maximum value. The priority of data writing to the is set. The priority order of writing set in this way is output from the priority order determining circuit unit 90 to the memory arbitration circuit unit 40 as a write priority command.

  In the memory arbitration circuit unit 40 to which the write priority command is input, data is written to the output side memories 61 to 63 having a higher priority according to the priority set in the write priority command. That is, in the memory arbitration circuit unit 40, the data read from the input side memories 21 to 23 corresponding to the output side memories 61 to 63 is read from the shared memory 50, and the corresponding output side memories 61 to 63 are read. Is written.

  As a result, data can be efficiently written in the output side memories 61 to 63 having a large free space. In addition, since one line of data can be output from the output-side memories 61 to 63 to the output IFs 81 to 83 without interruption, it is possible to prevent the quality of the screen display in the display device from being deteriorated.

  The above operation is performed for each line of one frame, and data is captured and output efficiently.

  As described above, in the present embodiment, a plurality of externally input video signals are taken into the input-side memories 21 to 23, and data is read with priority given to those with a small free space in the input-side memories 21 to 23. And is stored in the shared memory 50. Thereby, even if many video signals are input from the outside, the data of the input side memories 21 to 23 can be efficiently stored in the shared memory 50, and the video signal data input from the outside is It is possible to prevent data from being lost beyond the amount of data that can be stored in the input side memories 21 to 23.

  In addition, in each of the output side memories 61 to 63, data having a large free space is preferentially written. As a result, the data stored in the shared memory 50 can be efficiently output to the output-side memories 61 to 63, and the shared memory 50 can be efficiently shared even if many video signals are handled. Further, since one line of video signal data can be written to the output side memories 61 to 63 without interruption, it is possible to prevent deterioration of the screen display quality in the display device such as video interruption. That is, even when a large number of video signals having different display areas are handled, the video can be displayed on the screen without degrading the video quality of each video signal.

  As described above, the influence of latency can be prevented, and the quality of each video in the display device can be ensured.

(Other embodiments)
The structure shown by the said embodiment shows an example, Comprising: It is not limited above. For example, the priority order determination circuit unit 90 and the memory arbitration circuit unit 40 are separate, but an integrated unit may be used.

It is a block block diagram of the memory bus load adjustment apparatus which concerns on one Embodiment of this invention. It is the figure which showed the data amount of 1 line inputted into the input side memory with respect to time. It is the figure which showed the data amount of 1 line inputted into the output side memory with respect to time. It is a block block diagram of the conventional memory bus load adjustment apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11-13 ... Input IF, 21-23 ... Input side memory, 31-33 ... Input side monitor part, 40 ... Memory arbitration circuit part, 50 ... Shared memory, 61-63 ... Output side memory, 71-73 ... Output side Monitor unit, 81 to 83... Output IF.

Claims (2)

A plurality of input side memories (21 to 23) to which data of a plurality of video signals are respectively input;
A shared memory (50) in which data input to each input side memory is stored;
A plurality of output-side memories (61 to 63) to which data stored in the shared memory is input;
A plurality of input side monitoring units provided corresponding to each of the plurality of input side memories, respectively monitoring the amount of data in the input side memory, and acquiring a minimum value of the free capacity of the input side memory that changes with time (31-33),
A plurality of output side monitoring units provided corresponding to each of the plurality of output side memories, respectively, for monitoring the data amount of the output side memory, and acquiring the maximum value of the free capacity of the output side memory that changes with time (71-73),
Read priority that obtains the minimum value of the free space of each input side memory from each input side monitor unit, and reads the data with the highest priority given to the input side memory with the smallest minimum value of each acquired free space Get the maximum value of the free capacity of each output side memory from the means for outputting the command and each output side monitor unit, and give priority to the output side memory with the largest maximum value of each acquired free capacity A priority order determination circuit unit (90) having means for outputting a write priority command for writing
Based on the read priority command input from the priority order determination circuit unit, means for reading data from the input side memory to be given the highest priority and storing the read data in the shared memory; Based on the write priority command input from the decision circuit unit, the data to be written with the highest priority among the output side memories is read from the input side memory corresponding to the output side memory to be written, and A memory bus load adjustment device comprising: a memory arbitration circuit unit (40) having means for reading data stored in a shared memory from the shared memory and writing to the output-side memory to be given the highest priority . When the data on one line constituting one screen represented in the video signal is input to the output-side memory, the output-side monitor unit receives data indicating the screen display start time (A) on the one line. The period from the output to the outside from the output side memory until the end of reading (B) when it is no longer necessary to read the data of the one line from the shared memory is set as the monitoring period, and the maximum free capacity in this monitoring period. 2. The memory bus load adjusting device according to claim 1, wherein a value is acquired.

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