JP4843929B2 - Heat treatment method of GaAs crystal and GaAs crystal substrate - Google Patents
Heat treatment method of GaAs crystal and GaAs crystal substrate Download PDFInfo
- Publication number
- JP4843929B2 JP4843929B2 JP2004306718A JP2004306718A JP4843929B2 JP 4843929 B2 JP4843929 B2 JP 4843929B2 JP 2004306718 A JP2004306718 A JP 2004306718A JP 2004306718 A JP2004306718 A JP 2004306718A JP 4843929 B2 JP4843929 B2 JP 4843929B2
- Authority
- JP
- Japan
- Prior art keywords
- gaas crystal
- heat treatment
- gaas
- crystal
- specific resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Description
本発明は、各種電子素子の基板などに用いられるＧａＡｓ結晶の熱処理方法およびその熱処理方法により得られたＧａＡｓ結晶基板に関する。 The present invention relates to a heat treatment method for GaAs crystals used for substrates of various electronic devices and the like, and a GaAs crystal substrate obtained by the heat treatment method.
半絶縁性ＧａＡｓ結晶は、高速動作および低消費電力を必要とする電子デバイス用の基板材料として用いられている。かかるＧａＡｓ結晶の結晶面内における結晶特性のばらつきが大きいと、そのＧａＡｓ結晶を用いて作製された電子デバイスのデバイス特性のばらつきも大きくなり、電子デバイスの歩留まりが低下する。 Semi-insulating GaAs crystals are used as substrate materials for electronic devices that require high-speed operation and low power consumption. When the variation in the crystal characteristics of the GaAs crystal in the crystal plane is large, the variation in the device characteristics of the electronic device manufactured using the GaAs crystal is also large, and the yield of the electronic device is lowered.
このため、結晶特性のばらつきを低減させるために、結晶成長後のＧａＡｓ結晶インゴットまたはＧａＡｓ結晶ウエハに熱処理を行なうことが提案されている。現在までに、炭素濃度が０．５×１０15ｃｍ-3〜２．５×１０15ｃｍ-3で、１．５×１０7Ω・ｃｍ程度の比抵抗を有するＧａＡｓ結晶について、所定の条件の熱処理を行なうことにより、比抵抗の面内分布のばらつきを１０％未満とすることが提案されている（たとえば、特許文献１参照）。 For this reason, in order to reduce variation in crystal characteristics, it has been proposed to perform heat treatment on a GaAs crystal ingot or GaAs crystal wafer after crystal growth. To date, a GaAs crystal having a specific resistance of about 1.5 × 10 7 Ω · cm at a carbon concentration of 0.5 × 10 15 cm −3 to 2.5 × 10 15 cm −3 is subjected to predetermined conditions. It has been proposed that the variation in the in-plane distribution of the specific resistance is less than 10% by performing the heat treatment (for example, see Patent Document 1).
しかしながら、電子デバイスにおいてより高速動作化、低消費電力化が求められ、半絶縁性ＧａＡｓ結晶にもより高い比抵抗が求められている。ＧａＡｓ結晶の比抵抗を高くするほど、ＧａＡｓ結晶中のキャリア濃度は低くなるため、ＧａＡｓ結晶内における比抵抗のばらつき、キャリアの移動度のばらつきなどが大きくなる。 However, higher speed operation and lower power consumption are required for electronic devices, and higher specific resistance is also required for semi-insulating GaAs crystals. The higher the specific resistance of the GaAs crystal, the lower the carrier concentration in the GaAs crystal. Therefore, variations in specific resistance and carrier mobility in the GaAs crystal increase.
特に、比抵抗が従来よりも１桁以上高い１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのような半導体領域から絶縁体領域に位置する半絶縁性ＧａＡｓ結晶において、比抵抗のばらつきおよびキャリア移動度のばらつきを低減する方法については、今まで知られていなかった。
上記状況に鑑みて、本発明は、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのような高い比抵抗を有するＧａＡｓ結晶の結晶主面に平行な面内における比抵抗値および／またはキャリア移動度のばらつきを低減するために、このＧａＡｓ結晶を熱処理する方法およびこの熱処理によって得られるＧａＡｓ結晶基板を提供することを目的とする。 In view of the above circumstances, the present invention has a specific in resistivity 1 × 10 8 Ω · cm~8 × 10 8 Ω · high specific plane parallel to the principal crystal plane of GaAs crystal having a resistivity such as cm resistor An object of the present invention is to provide a method for heat-treating this GaAs crystal and a GaAs crystal substrate obtained by this heat-treatment in order to reduce variations in value and / or carrier mobility.
上記目的を達成するため、本発明は、縦型ブリッジマン法および縦型温度傾斜法のいずれかにより成長させた、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍかつ炭素濃度が５×１０15ｃｍ-3〜１×１０16ｃｍ-3のＧａＡｓ結晶を、８００℃〜１０００℃で１０時間〜５０時間熱処理することにより、結晶主面に平行な面内における比抵抗のばらつきが１０％未満となるＧａＡｓ結晶の熱処理方法である。ここで、比抵抗のばらつきとは、比抵抗の平均値に対する標準偏差の百分率（１００×標準偏差／平均値）をいう。 To achieve the above object, the present invention is vertical Bridgman method and grown by either of a vertical temperature gradient method, the resistivity is 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm and carbon By subjecting a GaAs crystal having a concentration of 5 × 10 15 cm −3 to 1 × 10 16 cm −3 to heat treatment at 800 ° C. to 1000 ° C. for 10 hours to 50 hours , a specific resistance in a plane parallel to the crystal main surface is obtained. This is a heat treatment method for GaAs crystals in which the variation of the GaAs crystal is less than 10% . Here, the variation in specific resistance means the percentage of standard deviation with respect to the average value of specific resistance (100 × standard deviation / average value).
本ＧａＡｓ結晶の熱処理方法において、熱処理の時間を２０時間〜５０時間とすることができる。また、縦型ブリッジマン法および縦型温度傾斜法のいずれかにおけるＧａＡｓ結晶の成長条件は、融液側の温度勾配を１〜２℃／ｃｍとし、結晶側の温度勾配を５〜６℃／ｃｍとすることができる。また、熱処理を不活性ガス雰囲気下または減圧雰囲気下で行なうことができる。また、ＧａＡｓ結晶は、本熱処理を行なうことにより、結晶主面に平行な面内におけるキャリア移動度のばらつきを１０％未満とすることができる。ここで、キャリア移動度のばらつきとは、キャリア移動度の平均値に対する標準偏差の百分率（１００×標準偏差／平均値）をいう。 In the heat treatment method of the present GaAs crystal, the heat treatment time can be set to 20 hours to 50 hours. The growth conditions of the GaAs crystal in either the vertical Bridgman method or the vertical temperature gradient method are as follows: the temperature gradient on the melt side is 1 to 2 ° C./cm, and the temperature gradient on the crystal side is 5 to 6 ° C./cm. cm. Further, the heat treatment can be performed in an inert gas atmosphere or a reduced pressure atmosphere . Also, GaAs crystal, by performing the heat treatment, the dispersion of carrier mobility in a plane parallel to the principal crystal plane can be less than 10%. Here, the variation in the carrier mobility, refers to the percentage (100 × standard deviation / mean) of the standard deviation to the mean value of the career mobility.
また、本発明は、上記いずれかのＧａＡｓ結晶の熱処理方法により熱処理されて得られたＧａＡｓ結晶基板である。 The present invention also provides a GaAs crystal substrate obtained by heat treatment by any one of the above GaAs crystal heat treatment methods.
上記のように、本発明によれば、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのような高い比抵抗を有するＧａＡｓ結晶であっても、結晶主面に平行な面内における比抵抗値および／またはキャリア移動度のばらつきを低減することができる。 As described above, according to the present invention, even GaAs crystal resistivity has a high resistivity, such as 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm, parallel to the principal crystal plane Variations in the in-plane specific resistance value and / or carrier mobility can be reduced.
本発明にかかるＧａＡｓ結晶の熱処理方法は、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのＧａＡｓ結晶を８００℃〜１０００℃で、１０時間〜５０時間熱処理する方法である。かかる条件の熱処理を施すことにより、比抵抗の高いＧａＡｓ結晶の結晶主面に平行な面内における比抵抗および／またはキャリア移動度のばらつきを低減することができる。 Heat treatment method of the GaAs crystal of the present invention has a specific resistance at 800 ° C. to 1000 ° C. The GaAs crystal of 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm, is a method of heat treatment 10 to 50 hours . By performing the heat treatment under such conditions, it is possible to reduce variations in specific resistance and / or carrier mobility in a plane parallel to the crystal main surface of the GaAs crystal having high specific resistance.
ここで、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのＧａＡｓ結晶は、その製造方法には特に制限はないが、以下の方法により得ることができる。たとえば、特開平１０−３６１９７号公報にも開示されているように、縦型ブリッジマン法（Vertical Bridgman method；以下、ＶＢ法という）、縦型温度傾斜法（Vertical Gradient Freeze method；以下、ＶＧＦ法という）などの結晶成長方法において、結晶成長容器内に種結晶、ＧａＡｓ原料および封止剤としての酸化ホウ素とともにドーパント原料として所定量のカーボンを収納し、炭素原子を含むＧａＡｓ融液を種結晶に接触させて形成し、このＧａＡｓ融液から種結晶上に炭素原子をドーパントとして含むＧａＡｓ結晶を成長させる。 Here, a GaAs crystal having a specific resistance of 1 × 10 8 Ω · cm to 8 × 10 8 Ω · cm is not particularly limited, but can be obtained by the following method. For example, as disclosed in Japanese Patent Laid-Open No. 10-36197, vertical Bridgman method (hereinafter referred to as VB method), vertical temperature gradient method (vertical gradient freeze method; hereinafter referred to as VGF method). In a crystal growth method, a crystal growth vessel contains a seed crystal, a GaAs raw material, and boron oxide as a sealant together with a predetermined amount of carbon as a dopant raw material, and a GaAs melt containing carbon atoms is used as a seed crystal. A GaAs crystal containing carbon atoms as a dopant is grown on the seed crystal from the GaAs melt.
ここで、炭素原子はアクセプターキャリアとして働き、ＧａＡｓ結晶内のドナーキャリア濃度（たとえば、ＥＬ２濃度）を低減するため、炭素原子をドーピングすることによりＧａＡｓ結晶の比抵抗を高めることができる。上記方法においては、ドーパント原料としてカーボンをＧａＡｓ原料に添加することによって、多量の炭素原子をＧａＡｓ結晶にドーピングすることができ、１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍの高い比抵抗を有するＧａＡｓ結晶の製造が可能となる。 Here, the carbon atoms act as acceptor carriers, and the donor carrier concentration (for example, EL2 concentration) in the GaAs crystal is reduced, so that the specific resistance of the GaAs crystal can be increased by doping carbon atoms. In the above method, high by the addition of carbon to the GaAs material as the dopant material, the it can be doped with a large amount of carbon atoms in the GaAs crystal, 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm ratio A GaAs crystal having resistance can be manufactured.
上記のようにして得られた比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのＧａＡｓ結晶を、８００℃〜１０００℃で、１０時間〜５０時間熱処理する。熱処理温度が８００℃未満であると比抵抗のばらつきの低減は小さく、処理温度が１０００℃を超えるとＥＬ２濃度などのドナーキャリア濃度が変動する。また、処理時間が１０時間未満であると比抵抗のばらつきの低減は小さく、処理時間が５０時間を超えても比抵抗のばらつきの低減は進まない。 The GaAs crystal of the above manner resistivity obtained is 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm, at 800 ° C. to 1000 ° C., a heat treatment for 10 hours to 50 hours. When the heat treatment temperature is less than 800 ° C., the reduction in specific resistance variation is small, and when the treatment temperature exceeds 1000 ° C., the donor carrier concentration such as EL2 concentration varies. Further, when the processing time is less than 10 hours, the reduction in specific resistance variation is small, and even when the processing time exceeds 50 hours, the reduction in specific resistance variation does not proceed.
本発明にかかるＧａＡｓ結晶の熱処理方法において、熱処理を行なう雰囲気には特に制限はないが、不活性ガス雰囲気下または減圧雰囲気下で行なうことが好ましい。不活性ガス雰囲気下または減圧雰囲気下で行なうことにより、ＧａＡｓ結晶の酸化劣化を低減することができる。ここで、不活性ガス雰囲気下における不活性ガスは、ＧａＡｓ結晶と反応しないガスであれば特に制限はないが、Ｎ2ガス、Ａｒガスなどが好ましく用いられる。また、減圧雰囲気下における減圧度は、特に制限はないが、１０2Ｐａ〜１０4Ｐａが好ましく用いられる。 In the GaAs crystal heat treatment method according to the present invention, the atmosphere in which the heat treatment is performed is not particularly limited, but is preferably performed in an inert gas atmosphere or a reduced pressure atmosphere. Oxidation degradation of the GaAs crystal can be reduced by carrying out in an inert gas atmosphere or a reduced pressure atmosphere. Here, the inert gas in the inert gas atmosphere is not particularly limited as long as it does not react with the GaAs crystal, but N 2 gas, Ar gas, or the like is preferably used. Further, the degree of pressure reduction in a reduced pressure atmosphere is not particularly limited, but 10 2 Pa to 10 4 Pa is preferably used.
本発明にかかるＧａＡｓ結晶の熱処理の用いられるＧａＡｓ結晶は、その炭素濃度が５×１０15ｃｍ-3〜１×１０16ｃｍ-3であることが好ましい。ＧａＡｓ結晶に炭素原子をドーピングして、ＧａＡｓ結晶の炭素濃度を５×１０15ｃｍ-3〜１×１０16ｃｍ-3とすることにより、容易にＧａＡｓ結晶の比抵抗を１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍとすることができる。また、このときＧａＡｓ結晶のＥＬ２濃度は、１．０×１０16ｃｍ-3〜１．５×１０16ｃｍ-3となる。 The GaAs crystal used for the heat treatment of the GaAs crystal according to the present invention preferably has a carbon concentration of 5 × 10 15 cm −3 to 1 × 10 16 cm −3 . By doping the GaAs crystal with carbon atoms and setting the carbon concentration of the GaAs crystal to 5 × 10 15 cm −3 to 1 × 10 16 cm −3 , the specific resistance of the GaAs crystal can be easily set to 1 × 10 8 Ω · cm to 8 × 10 8 Ω · cm. At this time, the EL2 concentration of the GaAs crystal is 1.0 × 10 16 cm −3 to 1.5 × 10 16 cm −3 .
本発明にかかる熱処理を行なうことにより、熱処理後のＧａＡｓ結晶の結晶主面に平行な面内における比抵抗のばらつきは１０％未満となる。ここで、ＧａＡｓ結晶の結晶主面とは、結晶における最大面をいい、基板または電子デバイスに用いられる際の基板の主面または電子デバイスの主面となる。 By performing the heat treatment according to the present invention, the variation in specific resistance in the plane parallel to the crystal main surface of the GaAs crystal after the heat treatment is less than 10%. Here, the crystal main surface of the GaAs crystal refers to the maximum surface of the crystal, which is the main surface of the substrate or the main surface of the electronic device when used in a substrate or an electronic device.
また、本発明にかかる熱処理を行なうことにより、熱処理後のＧａＡｓ結晶の結晶主面に平行な面内におけるキャリア移動度のばらつきは１０％未満となる。ここで、キャリア移動度μは、ＧａＡｓ結晶の主面に垂直の方向に電界Ｅをかけたときのキャリア速度Ｖとすると、μ＝Ｖ／Ｅ（単位：ｃｍ2・Ｖ-1・sec-1）で与えられる。ここで、キャリアとは電気伝導に関わる電子および正孔をいう。 Further, by performing the heat treatment according to the present invention, the carrier mobility variation in the plane parallel to the crystal main surface of the GaAs crystal after the heat treatment becomes less than 10%. Here, the carrier mobility μ is μ = V / E (unit: cm 2 · V −1 · sec −1) , assuming that the carrier velocity V is when the electric field E is applied in a direction perpendicular to the main surface of the GaAs crystal. ). Here, carriers refer to electrons and holes involved in electrical conduction.
本発明に用いられるＧａＡｓ結晶においては、比抵抗とキャリア移動度とには大きな相関関係があって、比抵抗が１×１０8Ω・ｃｍ〜８×１０8Ω・ｃｍのとき、キャリア移動度は１×１０3ｃｍ2・Ｖ-1・sec-1〜７×１０3ｃｍ2・Ｖ-1・sec-1となる。また、本発明にかかる熱処理によって、比抵抗のばらつきが低減するとともに、キャリア移動度のばらつきも低減する。 In the GaAs crystal used in the present invention, the the resistivity and carrier mobility when there is a large correlation, when specific resistance of 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm, the carrier mobility 1 × 10 3 cm 2 · V −1 · sec −1 to 7 × 10 3 cm 2 · V −1 · sec −1 . Further, the heat treatment according to the present invention reduces variations in specific resistance and also reduces variations in carrier mobility.
上記のように、本発明にかかるＧａＡｓ結晶の熱処理により、比抵抗のばらつきおよびキャリア移動度のばらつきが低減したＧａＡｓ結晶基板が得られる。さらに、このＧａＡｓ結晶基板を用いた電子デバイスのデバイス特性のばらつきが低減し、電子デバイスの歩留まりが向上する。 As described above, the heat treatment of the GaAs crystal according to the present invention provides a GaAs crystal substrate with reduced specific resistance variation and carrier mobility variation. Furthermore, variations in device characteristics of electronic devices using this GaAs crystal substrate are reduced, and the yield of electronic devices is improved.
また、上記ＧａＡｓ結晶基板を電子デバイスの基板などの用いる場合には、結晶のひずみの除去などのためにＲＴＡ（Rapid Thermal Annealing）などの熱処理を行なう場合があり、ＧａＡｓ結晶基板上に半導体層を形成させるためにＭＢＥ（Molecular Beam Epitaxy）法、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法、ＶＰＥ（Vapor Phase Epitaxy）法などを適用する場合がある。このような場合には、熱処理されたＧａＡｓ結晶が、その後のＲＴＡ、ＭＢＥなどにおいて、さらに熱処理されることになるが、本発明者は、ＲＴＡ、ＭＢＥなどにおける熱処理温度および熱処理時間が、本発明にかかる熱処理の熱処理温度および熱処理時間に比べて低温度および短時間である限り、ＧａＡｓ結晶の比抵抗およびキャリア移動度のばらつきは低く維持されることも確認した。 When the GaAs crystal substrate is used as an electronic device substrate or the like, heat treatment such as RTA (Rapid Thermal Annealing) may be performed to remove crystal distortion, and a semiconductor layer is formed on the GaAs crystal substrate. In some cases, MBE (Molecular Beam Epitaxy) method, MOCVD (Metal Organic Chemical Vapor Deposition) method, VPE (Vapor Phase Epitaxy) method and the like are applied to form the film. In such a case, the heat-treated GaAs crystal is further heat-treated in subsequent RTA, MBE, etc., but the present inventor believes that the heat treatment temperature and heat treatment time in RTA, MBE, etc. It was also confirmed that variations in the specific resistance and carrier mobility of the GaAs crystal were kept low as long as the heat treatment temperature and heat treatment time were low and short in time.
したがって、本発明にかかる熱処理を行なったＧａＡｓ結晶に対して、ＲＴＡを行なう場合は窒素雰囲気下で７００℃〜９００℃程度で１分間〜５分間程度の条件とすることが好ましく、ＭＢＥを行なう場合は減圧雰囲気下で５００℃〜７００℃程度で０．５時間〜２時間程度の条件とすることが好ましい。 Therefore, when RTA is performed on the GaAs crystal subjected to the heat treatment according to the present invention, it is preferable that the conditions are about 700 ° C. to 900 ° C. for about 1 minute to 5 minutes in a nitrogen atmosphere, and MBE is performed. Is preferably about 500 to 700 ° C. and about 0.5 to 2 hours under a reduced pressure atmosphere.
以下の実施例および比較例に基づいて、本発明をさらに具体的に説明する。 The present invention will be described more specifically based on the following examples and comparative examples.
（比較例１）
ＶＢ法により、以下のようにして比抵抗の高いＧａＡｓ結晶を作製した。すなわち、結晶成長容器として内径１０．１６ｃｍ（４インチ）×高さ２０ｃｍのｐＢＮ（pyrolytic boron nitride）製の坩堝を用いて、この坩堝に、ＧａＡｓ種結晶と、ＧａＡｓ多結晶体（ＧａＡｓ結晶原料）と、カーボン（ドーパント原料）とを収納した。次に、１２４０℃以上に加熱して、ＧａＡｓ、Ｃ（炭素原子）およびＡｓを含む融液を、ＧａＡｓ種結晶に接触するように形成した。次に、この融液と結晶（ＧａＡｓ種結晶または成長させるＧａＡｓ結晶）との界面における結晶成長温度を１２３８℃、融液側の温度勾配を１〜２℃／ｃｍ、結晶側の温度勾配を５〜６℃／ｃｍとして、ＧａＡｓ単結晶を成長させた。結晶成長時間１００時間で、直径１０．１６ｃｍ（４インチ）×高さ２０ｃｍのＧａＡｓ結晶が得られた。
(Comparative Example 1)
A GaAs crystal having a high specific resistance was produced by the VB method as follows. That is, using a crucible made of pBN (pyrolytic boron nitride) having an inner diameter of 10.16 cm (4 inches) × height of 20 cm as a crystal growth vessel, a GaAs seed crystal and a GaAs polycrystal (GaAs crystal raw material) And carbon (dopant raw material). Next, it heated to 1240 degreeC or more, and the melt containing GaAs, C (carbon atom), and As was formed so that a GaAs seed crystal might be contacted. Next, the crystal growth temperature at the interface between the melt and the crystal (GaAs seed crystal or GaAs crystal to be grown) is 1238 ° C., the temperature gradient on the melt side is 1 to 2 ° C./cm, and the temperature gradient on the crystal side is 5 A GaAs single crystal was grown at ˜6 ° C./cm. With a crystal growth time of 100 hours, a GaAs crystal having a diameter of 10.16 cm (4 inches) × height of 20 cm was obtained.
得られたＧａＡｓ結晶を厚さ６００μｍのＧａＡｓ結晶基板にスライスして、ＧａＡｓ結晶の中央部のＧａＡｓ結晶基板の炭素原子濃度を荷電粒子放射化分析法により測定したところ８．０×１０15ｃｍ-3であり、ＥＬ２濃度を赤外光吸収法により測定したところ８．９×１０15ｃｍ-3であった。 The obtained GaAs crystal was sliced into a GaAs crystal substrate having a thickness of 600 μm, and the carbon atom concentration of the GaAs crystal substrate at the center of the GaAs crystal was measured by charged particle activation analysis. 8.0 × 10 15 cm − 3 and EL2 concentration measured by an infrared absorption method was 8.9 × 10 15 cm −3 .
また、得られたＧａＡｓ結晶基板の面内において１０ｍｍピッチでそれぞれの位置における比抵抗をホール測定法により測定することにより、結晶主面に平行な面内における比抵抗のばらつきを算出した。上記比抵抗は平均値が５．５×１０8Ω・ｃｍ、標準偏差が１．２×１０8Ω・ｃｍであり、比抵抗のばらつきは２２％であった。 In addition, by measuring the specific resistance at each position at a pitch of 10 mm in the plane of the obtained GaAs crystal substrate by the Hall measurement method, the variation in specific resistance in the plane parallel to the crystal main surface was calculated. The specific resistance had an average value of 5.5 × 10 8 Ω · cm, a standard deviation of 1.2 × 10 8 Ω · cm, and variation in specific resistance was 22%.
また、得られたＧａＡｓ結晶基板の面内において１０ｍｍピッチでそれぞれの位置におけるキャリア移動度をホール測定法により測定することにより、結晶主面に平行な面内におけるキャリア移動度のばらつきを算出した。上記キャリア移動度は平均値が３．４×１０3ｃｍ2・Ｖ-1・sec-1、標準偏差が７．６×１０2ｃｍ2・Ｖ-1・sec-1であり、キャリア移動度のばらつきは２３％であった。結果を表１にまとめた。 Further, the carrier mobility at each position was measured by the Hall measurement method at a pitch of 10 mm within the surface of the obtained GaAs crystal substrate, thereby calculating the carrier mobility variation in the plane parallel to the crystal main surface. The carrier mobility has an average value of 3.4 × 10 3 cm 2 · V −1 · sec −1 and a standard deviation of 7.6 × 10 2 cm 2 · V −1 · sec −1. The variation was 23%. The results are summarized in Table 1.
（実施例１）
比較例１で得られたＧａＡｓ結晶を、９５０℃で２０時間の熱処理（本発明にかかる熱処理）を行なった。熱処理後のＧａＡｓ結晶を厚さ６００μｍのＧａＡｓ結晶基板にスライスして、ＧａＡｓ結晶の中央部のＧａＡｓ結晶基板を取り出した。
Example 1
The GaAs crystal obtained in Comparative Example 1 was heat-treated at 950 ° C. for 20 hours (heat treatment according to the present invention). The heat-treated GaAs crystal was sliced into a GaAs crystal substrate having a thickness of 600 μm, and the GaAs crystal substrate at the center of the GaAs crystal was taken out.
得られたＧａＡｓ結晶基板の炭素原子濃度は８．０×１０15ｃｍ-3であり、ＥＬ２濃度は１．２×１０16ｃｍ-3であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置における比抵抗は、平均値が３．９×１０8Ω・ｃｍ、標準偏差が２．９×１０7Ω・ｃｍであり、結晶基板主面内における比抵抗のばらつきは７％であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置におけるキャリア移動度は、平均値が４．６×１０3ｃｍ2・Ｖ-1・sec-1、標準偏差が１．７×１０2ｃｍ2・Ｖ-1・sec-1であり、結晶基板主面内におけるキャリア移動度のばらつきは４％であった。結果を表１にまとめた。 The obtained GaAs crystal substrate had a carbon atom concentration of 8.0 × 10 15 cm −3 and an EL 2 concentration of 1.2 × 10 16 cm −3 . Further, the specific resistance at the position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 3.9 × 10 8 Ω · cm and a standard deviation of 2.9 × 10 7 Ω · cm. The variation in specific resistance in the main surface was 7%. The carrier mobility at the position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 4.6 × 10 3 cm 2 · V −1 · sec −1 and a standard deviation of 1.7 × 10 2. cm 2 · V −1 · sec −1 , and the carrier mobility variation within the crystal substrate main surface was 4%. The results are summarized in Table 1.
（比較例２）
比較例１で得られたＧａＡｓ結晶基板に、さらに、窒素雰囲気下、８００℃、２分間の条件で、ＲＴＡを行なった。ＲＴＡ後のＧａＡｓ結晶基板の炭素原子濃度は８．０×１０15ｃｍ-3であり、ＥＬ２濃度は１．２×１０16ｃｍ-3であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置における比抵抗は、平均値が４．４×１０8Ω・ｃｍ、標準偏差が７．１×１０7Ω・ｃｍであり、結晶基板主面内における比抵抗のばらつきは１６％であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置におけるキャリア移動度は、平均値が２．２×１０3ｃｍ2・Ｖ-1・sec-1、標準偏差が９．４×１０2ｃｍ2・Ｖ-1・sec-1であり、結晶基板主面内におけるキャリア移動度のばらつきは４３％であった。結果を表１にまとめた。
(Comparative Example 2)
The GaAs crystal substrate obtained in Comparative Example 1 was further subjected to RTA under a nitrogen atmosphere at 800 ° C. for 2 minutes. The carbon atom concentration of the GaAs crystal substrate after RTA was 8.0 × 10 15 cm −3 and the EL 2 concentration was 1.2 × 10 16 cm −3 . Further, the specific resistance at a position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 4.4 × 10 8 Ω · cm and a standard deviation of 7.1 × 10 7 Ω · cm. The variation in specific resistance in the main surface was 16%. Further, the carrier mobility at a position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 2.2 × 10 3 cm 2 · V −1 · sec −1 and a standard deviation of 9.4 × 10 2. cm 2 · V −1 · sec −1 , and the carrier mobility variation in the main surface of the crystal substrate was 43%. The results are summarized in Table 1.
（実施例２）
実施例１で得られたＧａＡｓ結晶基板に、さらに、窒素雰囲気下、８００℃、２分間の条件で、ＲＴＡを行なった。ＲＴＡ後のＧａＡｓ結晶基板の炭素原子濃度は８．０×１０15ｃｍ-3であり、ＥＬ２濃度は１．２×１０16ｃｍ-3であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置における比抵抗は、平均値が３．５×１０8Ω・ｃｍ、標準偏差が３．０×１０7Ω・ｃｍであり、結晶基板主面内における比抵抗のばらつきは９％であった。また、このＧａＡｓ結晶基板の面内において１０ｍｍピッチ毎の位置におけるキャリア移動度は、平均値が３．６×１０3ｃｍ2・Ｖ-1・sec-1、標準偏差が１．７×１０2ｃｍ2・Ｖ-1・sec-1であり、結晶基板主面内におけるキャリア移動度のばらつきは５％であった。結果を表１にまとめた。
(Example 2)
The GaAs crystal substrate obtained in Example 1 was further subjected to RTA under a nitrogen atmosphere at 800 ° C. for 2 minutes. The carbon atom concentration of the GaAs crystal substrate after RTA was 8.0 × 10 15 cm −3 and the EL 2 concentration was 1.2 × 10 16 cm −3 . Further, the specific resistance at the position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 3.5 × 10 8 Ω · cm and a standard deviation of 3.0 × 10 7 Ω · cm. The variation in specific resistance in the main surface was 9%. The carrier mobility at the position of every 10 mm pitch in the plane of the GaAs crystal substrate has an average value of 3.6 × 10 3 cm 2 · V −1 · sec −1 and a standard deviation of 1.7 × 10 2. cm 2 · V −1 · sec −1 , and the carrier mobility variation in the crystal substrate main surface was 5%. The results are summarized in Table 1.
表１において比較例１と実施例１とを対比すると、比抵抗の平均値が５．５×１０8Ω・ｃｍのＧａＡｓ結晶に本発明にかかる熱処理を行なうことにより、ＧａＡｓ結晶の結晶主面に平行な面内における比抵抗のばらつきは２２％から７％に低減し、キャリア移動度のばらつきは２３％から４％に低減した。このような比抵抗およびキャリア移動度のばらつき低減により、かかるＧａＡｓ結晶を基板として用いた電子デバイスのデバイス特性が著しく安定する。 In Table 1, when Comparative Example 1 and Example 1 are compared, the main surface of the GaAs crystal is obtained by performing the heat treatment according to the present invention on a GaAs crystal having an average specific resistance of 5.5 × 10 8 Ω · cm. The variation in specific resistance in the plane parallel to the thickness was reduced from 22% to 7%, and the variation in carrier mobility was reduced from 23% to 4%. By reducing the variation in specific resistance and carrier mobility, device characteristics of an electronic device using such a GaAs crystal as a substrate are remarkably stabilized.
また、比較例２と実施例２とを対比すると、本発明にかかる熱処理を行なわずにＲＴＡを行なったＧａＡｓ結晶基板においては、比抵抗のばらつきが１６％、キャリア移動度のばらつきが４３％であったのに対し、本発明にかかる熱処理を行なった後にＲＴＡを行なったＧａＡｓ結晶基板においては、比抵抗のばらつきが９％、キャリア移動度のばらつきが５％と、いずれもばらつきが低減した。 Further, comparing Comparative Example 2 with Example 2, the GaAs crystal substrate subjected to RTA without performing the heat treatment according to the present invention had a specific resistance variation of 16% and a carrier mobility variation of 43%. On the other hand, in the GaAs crystal substrate subjected to RTA after the heat treatment according to the present invention, the variation in specific resistance was 9% and the variation in carrier mobility was 5%, both of which were reduced.
すなわち、実施例２に示すように、本発明をかかる熱処理を行なったＧａＡｓ結晶基板に、その熱処理温度よりも低い温度およびその熱処理時間よりも短い時間でＲＴＡを行なっても、ＧａＡｓ結晶基板の比抵抗およびキャリア移動度のばらつきは、本発明にかかる熱処理を行なわなかったＧａＡｓ結晶基板に比べて、低く維持された。同様に、本発明にかかる熱処理を行なったＧａＡｓ結晶基板に、その熱処理温度よりも低い温度およびその熱処理時間よりも短い時間でＭＢＥ成長と同一の熱履歴の熱処理を行なっても、ＧａＡｓ結晶基板の比抵抗およびキャリア移動度のばらつきは、本発明にかかる熱処理を行なわなかったＧａＡｓ結晶基板に比べて、低く維持された。 That is, as shown in Example 2, even when RTA is performed on a GaAs crystal substrate subjected to the heat treatment according to the present invention at a temperature lower than the heat treatment temperature and shorter than the heat treatment time, the ratio of the GaAs crystal substrate Variations in resistance and carrier mobility were kept low compared to GaAs crystal substrates that were not heat-treated according to the present invention. Similarly, even if the heat treatment with the same thermal history as MBE growth is performed on the GaAs crystal substrate subjected to the heat treatment according to the present invention at a temperature lower than the heat treatment temperature and shorter than the heat treatment time, Variations in specific resistance and carrier mobility were kept low compared to a GaAs crystal substrate not subjected to the heat treatment according to the present invention.
なお、今回開示された実施の形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be understood that the embodiments and examples disclosed this time are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
Claims (6)
結晶主面に平行な面内における比抵抗のばらつきが１０％未満となるＧａＡｓ結晶の熱処理方法。 Vertical Bridgman method and grown by either of a vertical temperature gradient method, the resistivity is 1 × 10 8 Ω · cm~8 × 10 8 Ω · cm and a carbon concentration of 5 × 10 15 cm -3 ~1 By heat treating a GaAs crystal of × 10 16 cm −3 at 800 ° C. to 1000 ° C. for 10 hours to 50 hours ,
A heat treatment method for a GaAs crystal in which variation in specific resistance in a plane parallel to the crystal main surface is less than 10% .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004306718A JP4843929B2 (en) | 2004-10-21 | 2004-10-21 | Heat treatment method of GaAs crystal and GaAs crystal substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004306718A JP4843929B2 (en) | 2004-10-21 | 2004-10-21 | Heat treatment method of GaAs crystal and GaAs crystal substrate |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011161765A Division JP2011219362A (en) | 2011-07-25 | 2011-07-25 | GaAs CRYSTAL SUBSTRATE |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006117464A JP2006117464A (en) | 2006-05-11 |
| JP4843929B2 true JP4843929B2 (en) | 2011-12-21 |
Family
ID=36535716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004306718A Expired - Fee Related JP4843929B2 (en) | 2004-10-21 | 2004-10-21 | Heat treatment method of GaAs crystal and GaAs crystal substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4843929B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5777479B2 (en) * | 2011-10-14 | 2015-09-09 | 株式会社タムラ製作所 | Method for manufacturing β-Ga2O3-based substrate and method for manufacturing crystal laminated structure |
| CN111032930B (en) * | 2017-09-21 | 2024-01-02 | 住友电气工业株式会社 | Semi-insulating gallium arsenide crystal substrate |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6472999A (en) * | 1987-09-14 | 1989-03-17 | Nippon Mining Co | Heat treatment of compound semiconductor single crystal |
| JPH02239181A (en) * | 1989-03-10 | 1990-09-21 | Sumitomo Metal Mining Co Ltd | Device and method for crystal growth |
| JPH0784360B2 (en) * | 1990-02-28 | 1995-09-13 | 住友金属鉱山株式会社 | Method for manufacturing semi-insulating GaAs substrate |
| JPH0597596A (en) * | 1991-10-08 | 1993-04-20 | Hitachi Cable Ltd | Gaas crystal and gaas device using the same |
| JP2967780B1 (en) * | 1998-09-28 | 1999-10-25 | 住友電気工業株式会社 | GaAs single crystal substrate and epitaxial wafer using the same |
| JP2004026584A (en) * | 2002-06-26 | 2004-01-29 | Sumitomo Electric Ind Ltd | METHOD OF MANUFACTURING GaAs SINGLE CRYSTAL AND GaAs SINGLE CRYSTAL |
-
2004
- 2004-10-21 JP JP2004306718A patent/JP4843929B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006117464A (en) | 2006-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101341471B1 (en) | One hundred millimeter high purity semi-insulating single crystal silicon carbide wafer | |
| JP6508050B2 (en) | Method of manufacturing silicon carbide ingot, method of manufacturing silicon carbide substrate, and method of manufacturing semiconductor device | |
| EP2659030B1 (en) | Method of manufacturing silicon single crystal and silicon single crystal | |
| CN101351580A (en) | Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering | |
| US10892334B2 (en) | n-Type SiC single crystal substrate, method for producing same and SiC epitaxial wafer | |
| JP2010532584A5 (en) | ||
| KR20100039291A (en) | Suppression of oxygen precipitation in heavily doped single crystal silicon substrates | |
| JP5103745B2 (en) | High frequency diode and manufacturing method thereof | |
| JP2967780B1 (en) | GaAs single crystal substrate and epitaxial wafer using the same | |
| JP2742247B2 (en) | Manufacturing method and quality control method for silicon single crystal substrate | |
| JP4843929B2 (en) | Heat treatment method of GaAs crystal and GaAs crystal substrate | |
| JP2011219362A (en) | GaAs CRYSTAL SUBSTRATE | |
| JP2017512911A (en) | Boron doped n-type silicon target | |
| US7157354B2 (en) | Method for gettering transition metal impurities in silicon crystal | |
| Teramoto et al. | Behavior of gold in cadmium telluride crystals | |
| JP2017197413A (en) | Compound semiconductor substrate and manufacturing method thereof | |
| CN114174569A (en) | Carbon-doped monocrystalline silicon wafer and method for producing same | |
| Lin et al. | Effects of heat treatment and plastic deformation on the photoelectronic properties of high‐resistivity GaAs: Cr | |
| JP6333182B2 (en) | Silicon wafer and manufacturing method thereof | |
| WO2021060369A1 (en) | Sic substrate, sic substrate production method, sic semiconductor device, and sic semiconductor device production method | |
| Ayedh et al. | Controlling the carbon vacancy concentration in 4H-SiC subjected to high temperature treatment | |
| JP7264100B2 (en) | Method for controlling donor concentration in silicon single crystal substrate | |
| JP2002289820A (en) | Method for manufacturing simox substrate, and simox substrate | |
| JP6988737B2 (en) | Manufacturing method of silicon wafer and silicon wafer | |
| JP2024004663A (en) | Determination method of upper limit of oxygen concentration in silicon single crystal substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070822 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090520 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101102 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101228 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110201 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110401 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110426 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110725 |
|
| A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20110801 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110913 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110926 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4843929 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |