JP4837549B2 - Physical random number generator and physical random number generator - Google Patents

Description

  The present invention relates to a physical random number generator suitable for various uses, and specific examples of the use include simulation (eg, stochastic model simulation, Markov chain Monte Carlo method, particle filter), security (eg, common) Key encryption key, authentication key, authentication random number, quantum encryption key), game machine (for example, amusement, arcade game, personal computer game, simulation game), computer graphics, and the like.

  In recent years, high-speed and high-quality random numbers are required in the security communication field, etc. to encrypt and authenticate large amounts of data due to advances in communication technology, handling of personal information, electronic transactions, etc. Also, in numerical simulations, it has become possible to process a larger amount of data due to CPU speedup, advances in parallel processing, pursuit of high accuracy and high efficiency, etc., requiring a large amount of random numbers at high speed and high quality. Has been.

The random number includes a pseudo random number generated by an algorithm (calculation) and a physical random number (intrinsic random number) generated using a physical phenomenon in the natural world.
Since the pseudo-random number is generated by calculation, it is easy to increase the speed. However, since the pseudo-random number is calculated by the algorithm given the initial value, there is a drawback that the random number sequence is easily predicted from the initial value and the algorithm. In addition, since pseudorandom numbers have periodicity in a random number sequence, they may not be suitable for use in fields such as security and simulation.
On the other hand, since physical random numbers are generated using random physical phenomena represented by thermal noise inside the semiconductor, initial values and algorithms such as pseudo-random numbers are unnecessary, and the random number sequence has periodicity. Therefore, it is impossible to predict random numbers.Therefore, physical random numbers are not used in security communication fields that require difficulty in prediction or statistical simulation fields that require non-reproducible true random numbers. Demand is increasing rapidly.

As for physical random numbers, a method of digitizing (binarizing) electrical noise generated by a diode, a transistor or the like as a random number source through a filter circuit, an amplifier circuit, an A / D converter, or the like (for example, Patent Document 1). Patent Document 2).
Japanese Patent Laid-Open No. 11-085472 JP 2002-41281 A

By the way, in order to generate a physical random number at a high speed, a high-speed circuit capable of generating and amplifying electrical noise as a random number source at a high speed and converting it into data reliably is necessary. Because cost and advanced circuit technology are required (usually, the random number generation speed is greatly affected by the performance of the A / D converter used), it is difficult to obtain high-speed physical random numbers easily at low cost. Met.
In addition, by increasing the speed, the random number source may become unstable or noise measurement accuracy may decrease, and the quality of the generated physical random number may decrease.

The present invention has been made in view of such problems, aims to provide highly reliable physical random number producing generator and a physical random number generation equipment at low cost to the physical high quality random numbers can be generated at high speed It is said.

That is, the physical random number generator according to claim 1 includes two sets of noise sources, and a first amplifier circuit and a second amplifier circuit that remove and amplify each DC component of noise generated from these noise sources, A comparison circuit that compares the output voltages of the first amplification circuit and the second amplification circuit and outputs 0 or 1; a flip circuit that holds the output of the comparison circuit in synchronization with a reference clock and obtains a physical random number A flop, an offset voltage circuit connected to one input of the comparison circuit to set an offset voltage of the comparison circuit, and a uniformized feedback circuit for controlling the offset voltage circuit , and A uniform feedback circuit includes a register that holds the flip-flop output, an adder that adds 1 to the output of the register to generate a comparison value, and the reference clock A first counter for measuring the first counter, a first comparator for generating the repetition period twice as large as the comparison value from the count value of the first counter and the comparison value from the adder, and the flip for each repetition period A second counter that measures the number of occurrences of 0 or 1 on the flop output, and the comparison value (count value <comparison value) or comparison output (count value) by comparing the count value of the second counter with the comparison value The offset voltage circuit is controlled such that the occurrence rate of 0 or 1 of the flip-flop output is 50% within the repetition period determined by the physical random number. In addition, the offset voltage circuit includes two sets of switch circuits that operate based on the output of the second comparator (count value <comparison value, count value> comparison value), and the switch circuit. A charging / discharging circuit comprising a CR circuit of connected resistors and capacitors, and charging / discharging the capacitor by turning on the switch circuit; and a third amplifying circuit for amplifying an output of the charging / discharging circuit to generate an offset voltage is characterized in Rukoto is composed of a.

The physical random number generator according to claim 2 includes two sets of noise sources, a differential amplifier circuit that amplifies a noise difference by removing a direct current component of each noise generated from the noise sources, and the difference A comparison circuit that compares the output voltage of the dynamic amplifier circuit with a reference voltage and outputs 0 or 1, a flip-flop that holds the output of the comparison circuit in synchronization with a reference clock and obtains a physical random number, and the comparison circuit The offset voltage circuit that is connected to the reference voltage side input and sets the offset voltage of the comparison circuit, and the uniform feedback circuit that controls the offset voltage circuit , and the uniform feedback circuit Measures the register that holds the flip-flop output, an adder that adds 1 to the output of the register to generate a comparison value, and the reference clock number 1 counter, a first comparator for generating the repetition period twice as large as the comparison value from the count value of the first counter and the comparison value from the adder, and the flip-flop output for each repetition period A second counter that measures the number of occurrences of 0 or 1 and a comparison value (count value <comparison value) or comparison output (count value> comparison value) by comparing the count value of the second counter with the comparison value And a second comparator for controlling the offset voltage circuit so that the occurrence rate of 0 or 1 of the flip-flop output is 50% within a repetition period determined by the physical random number, and The offset voltage circuit includes two sets of switch circuits that operate based on the output of the second comparator (count value <comparison value, count value> comparison value) and a resistor connected to the switch circuit. , Is constituted by including a CR circuit of the capacitor, the charging and discharging circuit that performs charging and discharging of the capacitor by the on operation of the switching circuit, and the third amplifier circuit for generating an offset voltage by amplifying the output of the charging and discharging circuit It is characterized by that.

According to a third aspect of the present invention, in the physical random number generator according to the first or second aspect , the third amplification is connected to an input of the comparison circuit different from an input to which the offset voltage circuit is connected. An amplifier circuit having the same configuration as the circuit is provided.

According to a fourth aspect of the present invention, in the physical random number generator according to the first or second aspect , the offset voltage circuit operates at an output (n <m, n> m) of the second comparator. And a D / A converter that converts the output value of the reversible counter into an analog value to generate the offset voltage.

The invention according to claim 5 is the physical random number generator according to any one of claims 2 to 4 , wherein the output of the second comparator (count value <comparison value) during the repetition period, or When detecting that any one of the outputs (count value> comparison value) has continuously appeared a predetermined number of times, an abnormality detection means for generating an abnormality signal is provided.

The invention according to claim 6 is the physical random number generator according to any one of claims 1 to 5 , wherein the noise source is connected to a series circuit of a resistor and a Zener diode or a constant current source. A Zener diode or a transistor circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series and the input and output are short-circuited is characterized.

The invention according to claim 7 is the physical random number generator according to any one of claims 1 to 6 , wherein the shift register and a part of data held in the shift register are used as input data, A selection circuit having a part of the address data; and an exclusive OR circuit that performs an exclusive OR of an output of the selection circuit and a physical random number output from the flip-flop, and the exclusive OR circuit Is provided with a uniformizing circuit using the output of the shift register as input data of the shift register.

Further, a physical random number generator according to claim 8 is provided with a plurality of physical random number generators according to any one of claims 1 to 7 disposed so as to be capable of parallel operation, and among the plurality of physical random number generators. Each of the random number outputs of one physical random number generator and the random number outputs of the remaining physical random number generators is individually provided with a plurality of exclusive OR circuits for performing exclusive OR.

According to the first to seventh aspects of the present invention, since the noise from the noise source is converted into data (binarized) by the amplifier circuit and the comparison circuit without using an expensive A / D converter, It is possible to realize a physical random number generator capable of generating high-quality physical random numbers at high speed without being affected by external noise, power supply fluctuations, environmental changes, and the like.
Further, the uniform feedback circuit is provided, and the offset voltage of the comparison circuit is adjusted based on the random number output so that the appearance rate of the random number 0 or 1 is corrected to 50%. And high-quality physical random numbers that do not have regularity, correlation, or periodicity can be generated at high speed.
Furthermore, as described in claim 7 , by providing a uniformizing circuit, a physical random number with better uniformity can be generated at high speed.

According to the invention described in claim 8 , the physical random number generators are connected in multiple stages and operated in parallel, and each random number output of these physical random number generators is excluded from the random number output of another physical random number generator. By performing a logical OR, it is possible to realize a physical random number generator capable of generating a large amount of high-quality high-speed physical random numbers.

  Embodiments of a physical random number generator according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a physical random number generator according to the present invention, and FIG. 2 shows waveforms of respective parts.
As shown in FIGS. 1 and 2, the physical random number generator 10 according to the present embodiment calculates two sets of noise sources 1a and 1b and the DC components of noise A and noise B generated from these noise sources 1a and 1b. A first amplifying circuit 2 and a second amplifying circuit 3 that remove and amplify high frequency components, and a comparison circuit that compares the output voltages of the first amplifying circuit 2 and the second amplifying circuit 3 with each other and outputs 0 or 1 4 and the comparison output of this comparison circuit 4, 0 or 1 is sequentially held in synchronization with the rising edge of the reference clock, and a D-type flip-flop 5 that generates a physical random number is offset to the + input of the comparison circuit 4 The offset voltage circuit 7 supplies the voltage vfb, and a uniform feedback circuit 6 that adjusts the offset voltage vfb of the offset voltage circuit 7.

  Here, the noise sources 1a and 1b described above include a noise source by a series circuit of a resistor R1 and a Zener diode D1 as shown in FIG. 9A, and a constant current source 25 as shown in FIG. 9B. A noise source by the connected Zener diode D1, a transistor circuit in which a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2 are connected in series (cascade connection) as shown in FIG. Various noise sources, such as a configured noise source, can be used.

  As shown in FIG. 3, the uniform feedback circuit 6 includes a register 11 (for example, a shift register), an adder 12, a first comparator 13, a first counter 14, a second counter 15, a second comparator 16, It consists of a control circuit 17 and the like.

As shown in the timing diagrams of FIGS. 3 and 4, the register 11 sequentially holds a part of the random number output from the flip-flop 5 in synchronization with the reference clock, and stores the value (c) of the held data. The cycle setting value (c) for setting the repetition cycle of the uniformized feedback circuit 6 is used.
The adder 12 adds 1 to the period setting value (c) to generate a comparison value (m = c + 1), and the comparison value (m) is input to one comparison input of the first comparator 13 as comparison data ( 2m-1). The first comparator 13 is a comparator for generating a repetition period of feedback control, and 1 is added to the period set value (c) because the output random number (0 to m− This is because the range of 1) is converted to the range of (1 to m).

The first counter 14 measures the number of reference clocks, inputs the count value to the other comparison input of the first comparator 13 and compares it with the above-mentioned comparison data (2m-1), thereby comparing its comparison output. As a result, a coincidence signal (t = 2m) having a repetition period (2 m) times the reference clock is generated.
In addition, the register 11 and the first counter are reset by the repetition period (t), and after the reset is released, the random number holding operation by the register 11 and the reference clock measuring operation by the first counter 14 are newly started. .
In this configuration, the repetition period (t) changes randomly according to the random value held in the register 11.

The second counter 15 measures the number of occurrences of 1 (or 0) of the random number output of the flip-flop 5 for each repetition period (t), and the count value (n) is one of the second comparators 16. Is input to the comparison input. Further, the comparison value (m) generated by the adder 12 is input to the other comparison input of the second comparator 16, and the measurement value (n) and the comparison value (m) are input to the second comparator 16. Are compared, and a comparison output (n <m, n> m) corresponding to the comparison result is output.
The comparison outputs (n <m, n> m) are current-amplified in the control circuit 17, and drive signals Drive_p and Drive_n for driving switch circuits Q1 and Q2 of the offset voltage circuit 7 described later are output.

  As shown in FIG. 1, the offset voltage circuit 7 includes two switch circuits (P-channel MOS transistor Q1 and N-channel MOS transistor Q2) operated by the drive signals Drive_p and Drive_n output from the control circuit 17, and a resistor R1. , R2 and a capacitor C1 CR circuit, and a buffer third amplifier circuit 8 for amplifying the output of the charge / discharge circuit 9 to generate an offset voltage vfb.

Then, as shown in FIG. 4, when the drive signal Drive_p is output from the control circuit 17 and the MOS transistor Q1 is turned on (at this time, the MOS transistor Q2 is turned off), the capacitor C1 is supplied from the power source Vcc through the MOS transistor Q1 and the resistor R1. Is charged, and the offset voltage vfb increases due to the charging voltage. When the drive signal Drive_n is output from the control circuit 17 and the MOS transistor Q2 is turned on (at this time, the MOS transistor Q1 is turned off), the charge of the capacitor C1 is discharged to the power source Vee side via the resistor R2 and the MOS transistor Q2. The offset voltage vfb drops.
When the offset voltage vfb is increased, the number of occurrences of 1 in the comparison output of the comparison circuit 4 increases and the number of occurrences of 0 decreases. Conversely, when the offset voltage vfb is lowered, the number of occurrences of 1 decreases and the number of occurrences of 0 increases.

  As described above, the offset voltage on the + input side of the comparison circuit 4 is adjusted according to the number of 1 (or 0) of the random number output generated within the repetition period (t) by the control of the uniformizing feedback circuit 6, and the comparison is performed. By automatically changing the comparison output of the circuit 4, that is, the appearance state of 0 and 1, the appearance rate of 1 or 0 of the random number output from the flip-flop 5 is automatically adjusted so as to converge to 50% probabilistically. Can do. This makes it possible to generate a uniform physical random number.

  Further, in the physical random number generator 10 of the first embodiment, as shown in FIG. 5 instead of FIG. 1, the third amplifying circuit 8 constituting the offset voltage circuit 7 on the negative input side of the comparison circuit 4 is provided. By providing the same circuit configuration as that in FIG. 1, the input form of the comparison circuit 4 can be made symmetrical, so that the external noise superimposed on each input of the comparison circuit 4 via the third amplifier circuit 8 can be reduced. Power supply noise or waveform distortion due to power supply fluctuations can be reliably canceled out in the comparison circuit 4, and a circuit configuration with excellent noise resistance can be realized. Other circuit configurations are the same as those in FIG.

  Further, the offset voltage circuit 7 is replaced with a combination circuit of the charge / discharge circuit 9 and the third amplifier circuit 8 as shown in FIGS. 1 and 5, and a reversible counter 18 (up / down counter) as shown in FIG. And a D / A converter 19 may be used.

In the offset voltage circuit 7 configured as described above, the reversible counter 18 operates in synchronization with the reference clock when a comparison output (n <m, n> m) is output from the second comparator 16. That is, when the comparison output (n <m) is output, the reversible counter 18 counts up and operates to count down at the comparison output (n <m).
The digital output value of the reversible counter 18 is converted to an analog value by the D / A converter 19 and supplied to the + input of the comparison circuit 4 as the offset voltage vfb. In other words, the offset voltage vfb increases as the reversible counter 18 counts up, and the offset voltage vfb decreases as the reversible counter 18 counts down. The reversible counter 18 is reset every repetition period (t). After the reset is released, the reversible counter 18 starts a counting operation based on the comparison output (n <m, n> m).

  Thus, also in this circuit configuration, the offset voltage on the + input side of the comparison circuit 4 is set in accordance with the number of random output 1 (or 0) generated within the repetition period (t) by the uniformizing feedback circuit 6. By adjusting and changing the comparison output of the comparison circuit 4, that is, the appearance state of 0 and 1, the random number output from the flip-flop 5 and the appearance rate of 1 or 0 are automatically adjusted to 50% probabilistically. Can do.

  Further, the physical random number generator 10 of the present embodiment includes an abnormality detection circuit (abnormality detection means) that monitors the operation of feedback control by the uniformized feedback circuit 6 described above.

  FIG. 7 shows an example, and a continuity detector 21 that detects that the comparison output (n <m) or (n> m) of the second comparator 16 is continuously output, and the comparison output (n A third counter 22 that measures the number of consecutive times <m) and (n> m) and a third comparator 23 that compares the count value of the third counter 22 with a predetermined number (comparison data) set in advance. When the count value of the third counter 22 exceeds a predetermined number for some reason, an abnormal operation confirmation signal is output from the third comparator 23.

FIG. 8 shows another example of the abnormality detection circuit, in which an overflow detection circuit 24 for detecting an overflow is provided at the output of the reversible counter 18 (up / down counter) of the offset voltage circuit 7.
When the comparison output (n <m) or comparison output (n> m) of the second comparator 16 is continuously input to the reversible counter 18 and the count is over (for example, if the reversible counter 18 has an 8-bit configuration) When the overflow is detected, the counter output becomes FFH or 00H.) When the overflow detection circuit 24 detects the count output FFH or 00H, an abnormal operation confirmation signal is output.

  By monitoring the abnormal operation confirmation signal from the abnormality detection circuit and quickly detecting an abnormality in the circuit operation in the physical random number generator 10, the quality deterioration of the physical random number generated by the physical random number generator 10 can be prevented in advance. It becomes possible.

FIG. 10 shows a second embodiment of the physical random number generator according to the present invention.
The physical random number generator 10 according to the second embodiment is the same as that of the first embodiment shown in FIG. 1 except that one differential amplifier 26 is used instead of the first amplifier 2 and the second amplifier 3. The same as the physical random number generator 10.

In the physical random number generator 10 of the second embodiment, the difference between noises obtained by removing each DC component is amplified by the differential amplifier circuit 26, and the output voltage thereof is compared with the reference voltage in the comparison circuit 4, and the comparison output 0 or 1 is output. Is output. The reference voltage of the comparison circuit 4 is the output of the offset voltage circuit 7 (offset voltage vfb), and by outputting the random number by adjusting the offset voltage vfb via the uniformizing feedback circuit 6 as in the first embodiment. The appearance rate of 1 or 0 can be automatically adjusted to converge to 50% stochastically.
In this case as well, although not shown, by providing a circuit similar to the third amplifier circuit 8 on the negative input side of the comparison circuit 4 and making the input form of the comparison circuit 4 symmetrical, as in FIG. , Noise resistance can be improved.

FIG. 11 shows a configuration of a physical random number equalizing circuit 30, which includes an exclusive OR circuit 33, a shift register 31, and a selector 32 (selection circuit). Part of the data held in the shift register 31 is input data to the selector 32, and the other part is address data.
The physical random number generated by the physical random number generator 10 (flip-flop 5) is subjected to exclusive OR with the random number output of the selector 32 in the exclusive OR circuit 33 and also to the data input of the shift register 31. Entered.

  In this way, a part of the physical random number input to the data input of the shift register 31 becomes the address data, and the own stored data is selected and output at random. Even if the random numbers are biased, they are uniformed by the uniformizing circuit 30. Therefore, physical random numbers (uniform physical random numbers) with excellent uniformity can be obtained.

  FIG. 12 shows a multi-bit output physical random number generator 40 in which a plurality (P units) of physical random number generators 10 are arranged and operated in parallel. The physical random number generator 40 includes a physical random number generator 10 for improving quality in addition to the P physical random number generators 10 described above, and a P provided for each physical random number output. The exclusive OR circuit 41 performs exclusive OR of the random number output of the (P + 1) th physical random number generator 10 for improving the quality and the random number output of each of the P physical random number generators 10. As a result, the quality of the physical random number is further improved, and a high-quality multi-bit (P-bit) physical random number (high-quality physical random number) can be obtained.

  The physical random number generator 40 uses the physical random number generator 10 provided with the random number uniformizing circuit 30 shown in FIG. 11 to provide a higher quality multi-bit physical random number having excellent uniformity. Can be obtained.

  Next, a verification method for verifying the uniformity of physical random numbers generated by the physical random number generator 40 of FIG. 12 will be described.

In the first verification method, each random number (uniform physical random number (1 to P + 1)) output from a plurality of (P + 1) physical random number generators 10 in FIG. 12 is converted into a plurality of bytes as shown in FIG. (Q bytes) Acquired simultaneously as a random number sequence (for example, stored in a memory mounted on the device), and the correlation between each byte between any two of the plurality of random number sequences (1 to P + 1 columns) In this method, the number (r) is calculated from Equation 1, and the correlation between the random number sequences is verified from the obtained correlation coefficient.
Table 1 shows an example of the correlation with respect to the correlation function (r). Based on the range value of 0 to 1 of the calculated correlation function (r), whether the correlation is good or bad is determined.

  Next, the second verification method obtains each random number (uniform physical random number (1 to P + 1)) output from a plurality of (P + 1) physical random number generators 10 in FIG. Then, for each random number sequence (1 to P + 1 sequence), the correlation coefficient (r) between arbitrary bytes is calculated from Equation 1, and the autocorrelation in each random number sequence is calculated based on Table 1 from the obtained correlation coefficient. It is a method to verify.

  In this verification method, as shown in FIG. 14, even-numbered bytes are obtained for each random number sequence, where the number of acquired random numbers output from the (P + 1) physical random number generators 10 is (2 × q) bytes. And a method of obtaining a correlation coefficient between odd-numbered bytes, or, as shown in FIG. 15, the number of acquired bytes of each random number output from a plurality (P + 1) of physical random number generators 10 is (q + s) For each random number sequence, a method of obtaining a correlation between (s) bytes and the like can be adopted.

Next, in the third verification method, as described above, each random number (uniform physical random number (1 to P + 1)) output from plural (P + 1) physical random number generators 10 in FIG. A method of acquiring and calculating the chi-square value (X ² ) of each random number sequence 1-byte frequency from Equation 2, and comparing the obtained chi-square value and the significance level value to verify the uniformity in each random number sequence It is.
That is, for example, a significance level of 1% chi-squared value as the verification criteria (X ²⁾ is 310.475, significance level of 5% of the chi-square value (X ²⁾ is set to 293.248, the verification data amount (byte amount) Verify whether the calculated chi-square value is below the significance level.

式２において、ｋは乱数を表現するビット数で８、ｎは乱数の数量でバイト数、ｐｉは乱数値ｉの出現確率（一様乱数の場合は全てのｉについてｐｉ＝１／２５６）、ｘｉは乱数値ｉの度数を示す。

In Equation 2, k is the number of bits representing a random number, 8 is the number of random numbers and the number of bytes, pi is the appearance probability of the random value i (pi = 1/256 for all i in the case of uniform random numbers), xi represents the frequency of the random value i.

  As described above, in the verification method according to the present embodiment, verification of random numbers in each random number sequence is performed in units of bytes, but of course, it is also possible to perform in units of multiple bits. Further, although the output random numbers (uniform physical random numbers (1 to P + 1)) of each physical random number generator 10 are used as the verification data, the output random numbers (high quality) of the plural (P pieces) exclusive OR circuits 41 are used. Physical random numbers (1 to P)) may be used as verification data.

  With this verification method, it is possible to efficiently and easily verify the quality of the physical random number generated by the physical random number generator 40, that is, the presence or absence of uniformity, regularity, correlation, and periodicity. It can greatly contribute to securing.

The figure which shows the structure of the physical random number generator by 1st Embodiment of this invention. The figure which shows the waveform of each part of the physical random number generator of this invention. The figure which shows the structure of a uniform feedback circuit. FIG. 4 is a timing diagram illustrating the operation of the uniformized feedback circuit of FIG. 3. The figure which shows the structure different from FIG. 1 of the physical random number generator by 1st Embodiment of this invention. The figure which shows the structure different from FIG. 1 of an offset voltage circuit. The figure which shows the structure of an abnormality detection circuit. The figure which shows the structure different from FIG. 7 of an abnormality detection circuit. The figure which shows the structural example of a noise source. The figure which shows the structure of the physical random number generator by 2nd Embodiment of this invention. The figure which shows the structure of a random number equalization circuit. 1 shows a configuration of a physical random number generator according to an embodiment of the present invention. The figure which shows the data for a test | inspection of the physical random number generator of this invention. The figure which shows the data for autocorrelation tests of the physical random number generator of this invention. The figure which shows the data for autocorrelation tests different from FIG. 14 of the physical random number generator of this invention.

Explanation of symbols

1a, 1b Noise source 2 First amplifier circuit 3 Second amplifier circuit 4 Comparison circuit 5 Flip-flop 6 Uniform feedback circuit 7 Offset voltage circuit 8 Third amplifier circuit 9 Charge / discharge circuit 10 Physical random number generator 11 Register 12 Adder 14 First counter 13 First comparator 15 Second counter 16 Second comparator 18 Reversible counter (up / down counter)
19 D / A converter 26 Differential amplifier circuit 30 Uniform circuit 31 Shift register 32 Select circuit (selector)
33, 41 Exclusive OR circuit 40 Physical random number generators Q1, Q2 Switch circuit (MOS transistor)

Claims (8)

Two sets of noise sources, a first amplifier circuit and a second amplifier circuit for amplifying by removing a DC component of each noise generated from these noise sources, and outputs of the first amplifier circuit and the second amplifier circuit A comparison circuit that compares voltages and outputs 0 or 1; a flip-flop that holds the output of the comparison circuit in synchronization with a reference clock and obtains a physical random number; and one input of the comparison circuit The offset voltage circuit for setting the offset voltage of the comparison circuit, and a uniform feedback circuit for controlling the offset voltage circuit ,
The uniform feedback circuit includes a register that holds the flip-flop output, an adder that adds 1 to the output of the register to generate a comparison value, and a first counter that measures the number of reference clocks. A first comparator that generates the repetition period twice as large as the comparison value from the count value of the first counter and the comparison value from the adder; and 0 or 1 of the flip-flop output for each repetition period A second counter that counts the number of occurrences of the second counter, and compares the count value of the second counter with the comparison value to generate a comparison output (count value <comparison value) or a comparison output (count value> comparison value). 2 comparators so that the occurrence rate of 0 or 1 of the flip-flop output is 50% within a repetition period determined by the physical random number. It controls the circuit,
The offset voltage circuit includes two sets of switch circuits that operate based on the output of the second comparator (count value <comparison value, count value> comparison value), and a resistor and capacitor CR circuit connected to the switch circuit. the provided a charging and discharging circuit that performs charging and discharging of the capacitor by the on operation of the switching circuit, and wherein Rukoto and a third amplifier circuit for generating an offset voltage by amplifying the output of the charging and discharging circuit A physical random number generator. Two sets of noise sources, a differential amplifier circuit that amplifies the difference in noise by removing the DC component of each noise generated from these noise sources, the output voltage of the differential amplifier circuit and the reference voltage are compared, and 0 Or a comparator circuit that outputs 1, a flip-flop that holds the output of the comparator circuit in synchronization with a reference clock and obtains a physical random number, and an input on the reference voltage side of the comparator circuit, An offset voltage circuit for setting an offset voltage, and a uniform feedback circuit for controlling the offset voltage circuit ,
The uniform feedback circuit includes a register that holds the flip-flop output, an adder that adds 1 to the output of the register to generate a comparison value, and a first counter that measures the number of reference clocks. A first comparator that generates the repetition period twice as large as the comparison value from the count value of the first counter and the comparison value from the adder; and 0 or 1 of the flip-flop output for each repetition period A second counter that counts the number of occurrences of the second counter, and compares the count value of the second counter with the comparison value to generate a comparison output (count value <comparison value) or a comparison output (count value> comparison value). 2 comparators so that the occurrence rate of 0 or 1 of the flip-flop output is 50% within a repetition period determined by the physical random number. It controls the circuit,
The offset voltage circuit includes two sets of switch circuits that operate based on the output of the second comparator (count value <comparison value, count value> comparison value), and a resistor and capacitor CR circuit connected to the switch circuit. the provided a charging and discharging circuit that performs charging and discharging of the capacitor by the on operation of the switching circuit, and wherein Rukoto and a third amplifier circuit for generating an offset voltage by amplifying the output of the charging and discharging circuit A physical random number generator. The amplifier circuit having the same configuration as that of the third amplifier circuit is provided at an input different from the input to which the offset voltage circuit is connected of the comparison circuit. Physical random number generator. The offset voltage circuit includes a reversible counter that operates at an output (n <m, n> m) of the second comparator, and a D / D that generates an offset voltage by converting an output value of the reversible counter into an analog value. physical random number generator according to claim 1 or 2, characterized in that composed of the a converter. When it is detected that either one of the output of the second comparator (count value <comparison value) or the output (count value> comparison value) has continuously appeared in advance during the repetition period, The physical random number generator according to any one of claims 1 to 4 , further comprising abnormality detection means for generating an abnormality signal . The noise source is a series circuit of a resistor and a Zener diode, a Zener diode connected to a constant current source, or a transistor circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series and the input and output are short-circuited. The physical random number generator according to claim 1 , wherein the physical random number generator is configured as follows. A shift register, a selection circuit using a part of the data held in the shift register as input data and the other part as address data, an output of the selection circuit, and a physical random number output from the flip-flop of performing an exclusive OR and an exclusive OR circuit, the exclusive OR circuit outputs the claims 1 to 6, characterized in that it comprises the equalizing circuit that receives data of the shift registers A physical random number generator according to any one of the above. A plurality of physical random number generators according to any one of claims 1 to 7, which are arranged so as to be capable of parallel operation, and random number output and remaining of one physical random number generator among the plurality of physical random number generators physical random number generator characterized by comprising each a plurality of exclusive OR circuits individually performing an exclusive OR of the physical random number generator a random number output.

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