JP4836199B2 - Current prediction method, simulation program, recording medium storing simulation program, and current prediction apparatus - Google Patents

Description

  The present invention relates to prediction of a current generated when a plurality of buffers are simultaneously switched in a circuit.

  In a semiconductor integrated circuit such as an LSI (Large Scale Integrated cuicuit), the power supply voltage is lowered due to miniaturization of the semiconductor processing process, and the number of internal gates is further increased. When many buffers are switched at the same time under such circumstances, the fluctuation of the potential of the power supply / ground generated when the through current flows on the power supply / ground becomes large. That is, the power supply current generated by the simultaneous switching not only becomes noise that degrades the signal quality of other parts of the circuit, but also the circuit may not operate normally due to fluctuations in the power supply / ground potential.

  Therefore, it is required to predict simultaneous switching at the design stage and avoid the risk of problems. Japanese Patent Application Laid-Open No. 2004-228561 proposes a method of modeling power supply wiring of a semiconductor device and evaluating simultaneous switching noise.

On the other hand, as a countermeasure against simultaneous switching noise, a method of reducing a peak of an instantaneously generated current by intentionally shifting the switch timing of each buffer as in Patent Document 2 has been proposed. By making use of the fact that a phase difference occurs between the currents generated from each buffer by shifting the switch timing, and adjusting the shift timing of the switch timing, the currents generated from the buffers interfere with each other, and the timing time difference The effect of reducing the amplitude of the frequency component according to is obtained.
JP 2004-54522 A JP 2005-338421 A

  The effect of reducing the noise current amount due to the switch timing time difference as described above can be analyzed using a technique such as that shown in Patent Document 1, but if there are multiple timing time differences, It takes an enormous amount of time to perform circuit simulation on the pattern.

  The present invention has been made to solve the above-described problems, and the problem is that the current that flows in the circuit when each buffer is operated at different switch timings can be predicted simply and in a short time. It is to provide a current prediction method.

  The present invention according to one aspect is a method for predicting the magnitude of current in a circuit in which a plurality of buffers each outputting the same current operates, and the circuit simulation is performed and the circuit is operated when the plurality of buffers operate simultaneously. A simulation step to obtain the frequency component of the current flowing through the circuit, and a delay that includes the number of buffers included in each group and a delay when a plurality of buffers are divided into a plurality of groups and a delay is given to the operation timing between the groups. Assuming that the frequency component of the current obtained in the acquisition step and the frequency component of the current obtained in the simulation step divided by the total number of buffers is the frequency component of the current output by each buffer, and depending on the delay information acquired in the acquisition step Multiple buffers of the frequency component of the current flowing through the circuit when A first amplitude reduction amount calculating step for calculating an amplitude reduction amount that is a ratio to a frequency component of a current flowing through the circuit when the fa operates simultaneously; a frequency component of the current obtained in the simulation step and a first amplitude reduction amount; A frequency component of the current that flows in the circuit when a plurality of buffers operate according to the delay information acquired in the acquisition step by multiplying the amplitude reduction amount calculated in the calculation step for each frequency. Current calculation step.

  Preferably, the frequency component of the current obtained in the simulation step divided by the total number of buffers is assumed to be the frequency component of the current output by each buffer, and multiple buffers operate according to different delay information different from the delay information A second amplitude reduction amount calculating step for calculating an amplitude reduction amount that is a ratio of the frequency component of the current flowing through the circuit to the frequency component of the current flowing through the circuit when a plurality of buffers are simultaneously operated; and a simulation step By multiplying the frequency component of the current obtained in step 1 and the amplitude reduction amount calculated in the second amplitude reduction amount calculation step for each frequency, a plurality of buffers operate according to different delay information. A second current calculation step of calculating a frequency component of the flowing current.

  More preferably, the frequency component of the current calculated in the first current calculation step and the second current calculation step is compared with a predetermined allowable value, and the calculated frequency component of the current is less than the allowable value. In this case, the method further includes a step of recording delay information when the first current calculation step and the second current calculation step calculate the frequency component of the current.

  Preferably, the acquisition step acquires delay information in which the number of buffers included in each group is equal.

  Preferably, the acquisition step acquires delay information having the same delay given between the groups.

  The present invention according to another aspect is a method for predicting the magnitude of current in a circuit in which a plurality of buffers each outputting the same current operates, and the circuit is simulated and the circuit is operated when the plurality of buffers operate simultaneously. Delay information including the step of obtaining the time response of the current flowing through the plurality of buffers, the number of buffers included in each group when the plurality of buffers are divided into a plurality of groups, and delay is given to the operation timing between the groups, and the delay Is obtained in the step of obtaining delay information, assuming that the current time response obtained by dividing the current time response obtained in the step of obtaining the current time response by the total number of buffers is the time response of the current output by each buffer. Calculating a time response of a current flowing in the circuit when a plurality of buffers operate according to the delay information, Provided.

  The present invention according to another aspect is a program for causing a computer having an arithmetic unit to predict the magnitude of current in a circuit in which a plurality of buffers that output equal currents operates, and the arithmetic unit performs circuit simulation. The simulation step to obtain the frequency component of the current flowing in the circuit when multiple buffers operate simultaneously, and when the calculation unit divides the multiple buffers into multiple groups and delays the operation timing between the groups Each buffer outputs a result obtained by dividing the frequency component of the current obtained in the simulation step by the total number of buffers in the obtaining step for obtaining delay information including the number of buffers included in each group and delay information. Assuming the frequency component of the current, depending on the delay information acquired in the acquisition step An amplitude reduction amount calculating step for calculating an amplitude reduction amount that is a ratio of a frequency component of a current flowing through the circuit when a plurality of buffers are operated to a frequency component of a current flowing through the circuit when the plurality of buffers are simultaneously operated; The arithmetic unit multiplies the frequency component of the current obtained in the simulation step by the amplitude reduction amount calculated in the amplitude reduction amount calculation step for each frequency, and thereby a plurality of buffers according to the delay information acquired in the acquisition step. A current calculation step of calculating a frequency component of a current flowing through the circuit when the circuit operates.

  The present invention according to another aspect provides a computer-readable recording medium storing the above program.

  The present invention according to another aspect is an apparatus for predicting the magnitude of current in a circuit in which a plurality of buffers each outputting an equal current operates, and performs circuit simulation, and the circuit is operated when the plurality of buffers operate simultaneously. The simulation means for obtaining the frequency component of the current flowing through the memory, the storage means for storing the frequency component obtained by the simulation means, and the plurality of buffers are divided into a plurality of set groups, and the operation timing between the groups is set. The number of buffers included in each group when giving a delay, the acquisition means for acquiring delay information including the delay, and the current output by each buffer that is obtained by dividing the frequency component stored in the storage means by the total number of buffers Multiple buffers depending on the delay information acquired in the acquisition step. An amplitude reduction amount calculating means for calculating an amplitude reduction amount that is a ratio of a frequency component of a current flowing in the circuit to a frequency component of a current flowing in the circuit when a plurality of buffers are simultaneously operated; Current flowing in the circuit when a plurality of buffers operate according to the delay information acquired in the acquisition step by multiplying the frequency reduction component calculated by the amplitude reduction amount calculated in the amplitude reduction amount calculation step for each frequency. Current calculating means for calculating the frequency component of

  According to the present invention, it is possible to easily and quickly predict the current flowing in the circuit when each buffer is operated by shifting the switch timing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

(1. System configuration of the present invention)
FIG. 1 is a block diagram showing the configuration of a simulation apparatus 100 according to the present invention. The configuration of the simulation apparatus 100 will be described with reference to FIG.

  The simulation apparatus 100 includes a computer main body 102, an FD drive 106 for reading and writing information on a flexible disk (hereinafter referred to as “FD”) 116 connected to the computer main body 102 via a bus 105, a CD An optical disc drive 108 for reading information on an optical disc such as a ROM (Compact Disc Read-Only Memory) 118, a communication interface 128 for exchanging data with the outside, a monitor 104 as a display device, and an input device As a keyboard 110 and a mouse 112.

  The computer main body 102 includes a CPU (Central Processing Unit) 120 connected to the bus 105, a memory 122 including a ROM (Read Only Memory) and a RAM (Random Access Memory), and a direct access memory device, for example, a hard disk 124.

  The hard disk 124 includes a program 160 for executing circuit analysis, a program 161 for executing current prediction, circuit information 240 of the integrated circuit to be designed, delay information 250 indicating the switching timing of the buffer group, and delay information. Change information 260 indicating how to give the change, an allowable current value 270, an analysis result 280 for storing the result of the circuit analysis, and an evaluation result 290 that predicts the current value corresponding to the delay information.

  Here, the circuit information 240 may be supplied from an external database via the communication interface 128. Note that information obtained by a known technique such as information on the net list inside the semiconductor and the parasitic capacitance of the substrate can be used as the circuit information 240. The delay information 250 may be supplied from an external database via the communication interface 128, or may be generated by the CPU 120 in accordance with the operation of the keyboard 110 or the mouse 112 by the user.

  The program for performing the simulation according to the present invention may be supplied by a storage medium such as the FD 116 or the CD-ROM 118, or may be supplied by another computer via a communication line. The circuit analysis may be executed by an external computer via the communication interface 128 and the result may be stored in the hard disk 124.

  The CPU 120 functioning as an arithmetic processing unit executes processing corresponding to each program described above using the memory 122 as a working memory.

  The CD-ROM 118 may be another medium, such as a DVD (Digital Versatile Disc) -ROM or a memory card, as long as it can record information such as a program installed in the computer main body. In this case, the computer main body 102 is provided with a drive device that can read these media. The bus 105 may be connected to a magnetic tape device that is detachably loaded with a cassette type magnetic tape.

  The program for performing the simulation according to the invention is software executed by the CPU 120 as described above. Generally, such software is stored and distributed in a storage medium such as the CD-ROM 118 and the FD 116, read from the storage medium by the optical disk drive 108 or the FD drive 106, and temporarily stored in the hard disk 124. Alternatively, when the simulation apparatus 100 is connected to the network, it is temporarily copied from the server on the network to the hard disk 124. Then, the data is further read from the hard disk 124 to the RAM in the memory 122 and executed by the CPU 120. In the case of network connection, the program may be directly loaded into the RAM and executed without being stored in the hard disk 124.

  The computer hardware itself shown in FIG. 1 and its operating principle are general. Therefore, an essential part for realizing the functions of the present invention is software stored in a storage medium such as the FD 116, the CD-ROM 118, and the hard disk 124.

  A functional configuration of the CPU 120 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a functional configuration of the CPU 120.

  The circuit simulation unit 210 receives the circuit information 240 as an input, and calculates a current flowing through the circuit when a plurality of buffers operate simultaneously by a circuit simulator such as SPICE. The circuit simulation unit 210 records the analysis result 280 on the hard disk 124.

  The delay information update unit 220 reads the delay information 250 from the hard disk 124 and changes the read delay information 250 based on the change information 260. Then, the changed delay information 250 is stored in the hard disk 124.

  The noise reduction effect evaluation unit 230 includes a current calculation unit 232 and a current evaluation unit 234. Based on the analysis result 280 and the delay information 250, the current calculation unit 232 calculates the frequency component of the current flowing through the circuit when a delay is given to the switch timing of each buffer.

  The current evaluation unit 234 compares the frequency component of the current calculated by the current calculation unit 232 with the allowable current value 270, and outputs an evaluation result 290 based on the comparison result.

(2. Current prediction method)
From here, the current prediction method of the present invention will be described with reference to FIG. FIG. 3 is a flowchart showing a process performed by the CPU 120 in the current prediction.

  CPU120 acquires circuit information 240 (Step S301). For example, when the circuit information 240 is stored in a storage medium such as the hard disk 124, this process is performed by reading the circuit information 240 from the storage medium. Or you may acquire from an external database via a communication interface.

  Next, the CPU 120 receives the circuit information 240, performs a circuit simulation by a simulator such as SPICE, and obtains a frequency component of the current flowing through the circuit when there is no delay (step S302). Here, one frequency component may be obtained, or frequency components at a plurality of frequencies may be obtained. After obtaining the frequency component, the CPU 120 records the simulation result on the hard disk 124 or the like (step S303).

  Next, the CPU 120 determines the delay information 250 according to the operation of the keyboard 110 or the mouse 120 performed by the user (S304).

  Here, the delay information will be described with reference to FIGS. FIG. 4 is a diagram showing an example of a part of a circuit to be simulated by the present invention. As shown in FIG. 4, the circuit includes a plurality of buffers 420 that output a current in accordance with an operation timing signal generated by the operation timing signal generator 410. The buffer 420 is divided into a plurality of groups, and the delay device 430 gives a delay from the operation timing of the previous group to the operation timing of each group. In addition, these buffers give equal drive voltages and output equal currents when given equal input signals.

  FIG. 4 shows group 1 including two buffers, group 2 including three buffers, and group 3 including one buffer. A delay d2 is provided between the group 1 and the group 2. A delay d3 is given between the group 2 and the group 3.

  As shown in the table of FIG. 5, the delay information 250 includes the number of buffers included in each group and the operation timing delay from the previous group. The CPU 120 determines the delay information 250 according to the user input. Alternatively, the CPU 120 reads a file recorded in advance on the hard disk 124 or the like and determines the delay information 250.

  The total number of groups, the number of buffers included in each group, and the delay between the groups may be set freely. However, the sum of the number of buffers included in each group, that is, the total number of buffers is determined to be constant. Further, the number of buffers included in each group may be set equal. The delay between each group may be set equally.

  After the delay information is determined in step S304, the CPU 120 acquires the determined delay information (step S305). In the flowchart of FIG. 3, the delay information is determined and acquired after the circuit simulation, but the processing order is not limited to this. For example, the CPU 120 may perform circuit simulation after determining and acquiring delay information.

  Based on the acquired delay information, the CPU 120 calculates an amplitude reduction amount (step S306). The amplitude reduction amount is calculated as follows.

First, based on the acquired delay information, the phase difference between the phase of the current output from the buffer included in the group n and the phase of the current output from the buffer included in the group 1 serving as a reference in the vibration of the frequency f is obtained. pn is calculated based on the following equation (1). Where di (i
= 2, 3,..., N) is the difference in current output timing between group i and group i-1. Note that d1 = 0.

  Next, an amplitude that is a ratio of the frequency component at the frequency f of the current flowing through the circuit when the plurality of buffers operate according to the acquired delay information to the frequency component at the frequency f of the current flowing through the circuit when there is no delay The reduction amount L is calculated by the following equation (2) from the number of buffers in each group and the phase difference. Here, M is the total number of groups.

  Finally, the CPU 120 multiplies the amplitude reduction amount calculated in S306 and the frequency component of the current flowing through the circuit for each frequency when there is no delay calculated in S302 and stored in the hard disk 124, according to the delay information. The frequency component of the current flowing in the circuit when the buffer operates is calculated.

  Thus, in the current prediction method of the present invention, the frequency component of the current flowing through the circuit when the buffer operates according to the delay information can be obtained from the current when there is no delay and the delay information. That is, the amplitude of the current flowing in the circuit with the delay can be obtained by a simple method without performing circuit simulation on the circuit with the delay.

(3. Delay information search method)
By using this current simulation method, it is possible to search for a method of giving a delay in which the amount of current is in a desired range. This search method will be described with reference to FIG. FIG. 6 is a flowchart showing processing performed by the CPU 120 when searching for a desired delay.

  First, the CPU 120, initial delay information which is delay information to be given first, change information indicating a change amount when changing the delay information, a search range indicating what kind of delay information the corresponding current is calculated, and The allowable current value P is determined (step S601).

  Next, the CPU 120 acquires delay information (step S602), and calculates the amplitude Id of the current flowing through the circuit when the buffer operates according to the acquired delay information (step S603). The process performed in step S602 is the same as the process performed in step S301. The process performed in step S603 includes the processes performed from step S302 to step S307.

  Next, the CPU 120 compares the calculated current amplitude Id with the allowable current value P, and when Id is equal to or less than P (Yes in S604), it is assumed that a sufficient noise reduction effect is obtained, and Id and Id Is recorded as compatible data in a recording medium such as a hard disk (step S605). When Id is larger than P (No in step S604), recording of delay information corresponding to Id or Id is not performed. Here, when Id is obtained for a plurality of frequencies, the allowable current value may be determined independently for each frequency, and when Id is P or less for each frequency, the conforming data may be recorded. Alternatively, a current allowable value common to each frequency may be determined, Id and P may be compared, and the conforming data may be recorded. When the spectrum over a plurality of frequencies of the current flowing through the circuit when there is no delay is obtained, the conforming data can be recorded when the peak of the current spectrum flowing through the circuit when there is a delay is below an allowable value.

  Furthermore, the CPU 120 determines whether the corresponding Id has been obtained for all delays in the search range (step S606). If it is determined that there is a delay for which the corresponding Id has not yet been obtained, the CPU 120 determines new delay information based on the amount of change (step S607), and repeats the processing from step S602 again.

  If it is determined that Id has been obtained for all delays (Yes in step S606), the CPU 120 ends the search and outputs a list of recorded matching data to the monitor 104 (step S608).

  By performing the above processing and referring to the list of conforming data, it is possible to know in a short time the delay information in which the amount of current is within the desired range, and it can be used as a judgment material for optimal circuit design. it can.

  More specifically, a method for searching for suitable data while changing the delay time will be described with reference to FIG. FIG. 7 is a flowchart showing processing performed by the CPU 120 when searching for a desirable delay by changing the delay information.

  First, the CPU 120 determines a minimum delay value dmin, a maximum delay value dmax, a delay step size dstep, and an allowable current value P (step S701).

  Next, the CPU 120 generates delay information in which all delay values are dmin (step S702), and acquires the generated delay information (step S703). Further, when there is a delay corresponding to the acquired delay information, the amplitude Id of the current flowing through the circuit is calculated (step S704). The processing performed in these steps is the same as the processing performed in each step shown in FIG.

  Next, the CPU 120 compares the calculated current amplitude Id with the allowable current value P, and when Id is equal to or less than P (Yes in step S705), it is assumed that a sufficient noise reduction effect is obtained and Id is The matching data including the corresponding delay information is recorded on a recording medium such as a hard disk (step S706). When Id is larger than P (No in step S705), recording of Id and corresponding delay information is not performed.

  Further, the CPU 120 compares d and dmax (step S707). When it is determined that d ≦ dmax (Yes in step S707), the CPU 120 sets d plus dstep as new delay information (step S708), and repeats the processing from S703 again.

  If it is determined that d> dmax (No in step S707), the CPU 120 ends the search and outputs a list of recorded matching data to the monitor 104 (step S709).

  It is also possible to search for suitable data by changing the number of groups and the number of buffers included in each group. This method will be described with reference to FIG. FIG. 8 is a flowchart showing processing performed by the CPU 120 when searching for a desirable delay by changing the number of groups and the number of buffers included in each group.

  First, the CPU 120 determines a buffer number table and a current allowable value P that store how to change the number of buffers in an array (step S801).

  Here, the buffer number table will be described with reference to FIG. FIG. 9 is a diagram illustrating an example of a buffer number table. The buffer number table shown in FIG. 9 corresponds to the case where the total number of buffers is 60 and the number of buffers in each group is all equal to 1, 2, 4, 6, 10, 12, 15, 20, 30. . In FIG. 9, ki represents the number of buffers included in group i, and K is a label corresponding to ki information.

  Such a buffer number table may be generated by the CPU 120 in response to an input by the user. It may also be given by a file prepared in advance. In this example, the buffers in each group are equal. However, a buffer number table in which the number of buffers in each group is different may be created.

  Next, the CPU 120 generates delay information corresponding to the label K = 1 (step S802). In the case of the example shown in FIG. 9, the CPU 120 divides the buffer group into 60 groups each composed of one buffer, and determines a delay to be given between the groups. Next, the CPU 120 acquires the generated delay information (step S803). Further, the current amplitude Id when there is a delay corresponding to the acquired delay information is calculated (step S804). The process performed in step S802 is the same as the process performed in step S301. The process performed in step S803 includes the processes performed from step S302 to step S307.

  Next, the CPU 120 compares the calculated current amplitude Id with the allowable current value P. When Id is equal to or less than P (Yes in S805), the CPU 120 determines that a sufficient noise reduction effect has been obtained and corresponds to Id. The matching data including the delay information is recorded on a recording medium such as a hard disk (step S806). When Id is larger than P (No in step S805), Id and corresponding delay information are not recorded.

  Furthermore, the CPU 120 determines whether the calculation of Id has been completed for all patterns in the table (step S807). For example, when the buffer table of FIG. 9 is given, if the Id corresponding to K = 9 is calculated, the CPU 120 determines that the calculation of Id has been completed for all patterns. If it is determined that there is a pattern for which the calculation of the corresponding Id has not been completed yet (No in step S807), the CPU 120 generates new delay information corresponding to the label K + 1 (step S808), and starts from step S803. Repeat the process again.

  If it is determined that the calculation of Id has been completed for all the patterns in the table (Yes in step S807), the CPU 120 ends the search and outputs a list of recorded matching data to the monitor 104 (step S809). .

(4. Calculation of transient waveform)
The method for calculating the frequency component of the current according to the present invention has been described so far, but the present invention can also be applied to the calculation of a transient waveform. This will be described with reference to FIG. FIG. 10 is a flowchart showing processing performed by CPU 120 when calculating a transient waveform.

  The CPU 120 acquires circuit information 240 (step S1001), and obtains a transient waveform f (t) of the sum of currents generated from all the buffers when there is no delay by circuit simulation (step S1002). After obtaining the transient waveform f (t), the CPU 120 records the simulation result on the hard disk 124 or the like (step S1003).

  Next, the CPU 120 determines the delay information 250 according to the operation of the user's keyboard 110 or mouse 120 (step S1004). After determining the delay information, the CPU 120 acquires the delay information determined in S304 or given in advance (step S305). In the flowchart of FIG. 10, the delay information is determined and acquired after the circuit simulation, but the processing order is not limited to this.

  Based on the acquired delay information, the CPU 120 calculates a current waveform transient response waveform fn (t) generated from each group n in consideration of the delay (step S1006). fn (t) is calculated according to the following equation (3).

  Finally, the CPU 120 calculates the current transient waveform fd (t) in consideration of the delay information by adding the fn (t) calculated in step S1006 for all the groups. That is, fd (t) is calculated according to the following equation (4).

  Thus, in the current prediction method of the present invention, the current waveform when there is a delay can be obtained from the current waveform when there is no delay and the delay information. That is, the current waveform when there is a delay can be obtained without performing circuit simulation for the circuit with the delay.

  As described above, according to the present invention, it is possible to estimate the spectrum of the current that changes according to the delay information in a short time. As a result, in order to avoid simultaneous switching of a circuit in which a plurality of buffers operate, when the buffer operation timing is intentionally shifted, delay information that reduces the amount of current generated at a predetermined frequency from the buffer can be reduced in a short time. This makes it possible to design high-quality circuits in a short time.

  In the embodiment, the method for predicting the current when the delay is given from the current when all the buffers are operated has been described, but the current when the delay is given from the operating current of a part of the buffer is also the same. It is clear that this is possible.

  Application to semiconductor design is expected.

1 is a block diagram showing a configuration of a simulation apparatus 100 according to the present invention. 2 is a block diagram showing a functional configuration of a CPU 120. FIG. It is a flowchart which shows the process which CPU120 performs in the case of electric current prediction. It is a figure which shows a part of circuit used as the object of simulation by this invention. It is a figure which shows the example of delay information. It is a flowchart which shows the process which CPU120 performs when searching a desirable delay. It is a flowchart which shows the process which CPU120 performs when searching delay desired by changing delay information. It is a flowchart which shows the process which CPU120 performs when searching the desired delay by changing the number of groups and the number of buffers contained in each group. It is a figure which shows the example of a buffer number table. It is a flowchart which shows the process which CPU120 performs when calculating a transient waveform.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Simulation apparatus, 102 Computer main body, 104 Monitor, 105 Bus, 106 FD drive, 108 Optical disk drive, 110 Keyboard, 112 Mouse, 116 FD, 118 CD-ROM, 120 CPU, 122 Memory, 124 Hard disk, 128 Communication interface, 160 Program for executing circuit analysis, 161 program for executing current prediction, 210 circuit simulation unit, 220 delay information update unit, 230 noise reduction effect evaluation unit, 232 current calculation unit, 234 current evaluation unit, 240 circuit information, 250 delay information 260, change information, 270 allowable current value, 280 analysis result, 290 prediction result, 410 operation timing signal generator, 420 buffer, 430 delay device.

Claims (9)

A method for predicting the magnitude of current in a circuit in which a plurality of buffers each outputting equal current operates by a computer having an arithmetic unit ,
A simulation step in which the computer performs a circuit simulation and obtains an amplitude at a predetermined frequency of a current flowing in the circuit when the plurality of buffers operate simultaneously;
Acquisition of the delay information including the number of buffers included in each group and the delay when the computer divides the plurality of buffers into a plurality of groups and gives a delay to the operation timing between the groups. Steps,
The computer assumes that the amplitude of the current obtained in the simulation step divided by the total number of buffers is the amplitude of the current output by each buffer, and the plurality of buffers correspond to the delay information obtained in the obtaining step. A first amplitude reduction amount calculating step for calculating an amplitude reduction amount that is a ratio of the amplitude of the current flowing through the circuit when operating to the amplitude of the current flowing through the circuit when the plurality of buffers are operated simultaneously;
The computer multiplies the amplitude of the current obtained in the simulation step by the amplitude reduction amount calculated in the first amplitude reduction amount calculation step for each frequency, thereby adding to the delay information acquired in the acquisition step. And a first current calculation step of calculating an amplitude of a current flowing through the circuit when the plurality of buffers operate accordingly. The computer assumes that the current amplitude obtained in the simulation step divided by the total number of buffers is the current amplitude output by each buffer, and the plurality of buffers according to different delay information different from the delay information. a second amplitude reduction amount calculating step of calculating an amplitude reduction amount is the ratio but the amplitude of the current flowing in the circuit when operating, for the amplitude of the current flowing through the circuit when the plurality of buffers are simultaneously operated ,
The computer multiplies the amplitude of the current obtained in the simulation step and the amplitude reduction amount calculated in the second amplitude reduction amount calculation step for each frequency, so that the plurality of the plurality of amplitudes according to the different delay information. The current prediction method according to claim 1, further comprising: a second current calculation step of calculating an amplitude of a current flowing through the circuit when the first buffer operates. The computer compares the amplitude of the current calculated in the first current calculation step and the second current calculation step with a predetermined allowable value, and the calculated current amplitude is equal to or less than the allowable value. 3. The current prediction method according to claim 2, further comprising a step of recording delay information when the first current calculation step and the second current calculation step calculate the current amplitude . The current prediction method according to claim 1, wherein the acquiring step includes a step of acquiring delay information in which the number of buffers included in each group is equal. The current prediction method according to claim 1, wherein the acquiring step includes a step of acquiring delay information in which the delay given between the groups is equal. A method of predicting the magnitude of a current in a circuit in which a plurality of buffers that output equal currents in a computer having a calculation unit operate,
The computer performs a circuit simulation and obtains a time response of a current flowing through the circuit when the plurality of buffers operate simultaneously;
The computer divides the plurality of buffers into a plurality of groups, and obtains delay information including the number of buffers included in each group and the delay when delaying operation timing between the groups. When,
The computer obtains the delay information by assuming that the time response of the current output by each buffer is obtained by dividing the time response of the current obtained in the step of obtaining the time response of the current by the total number of buffers. And calculating a time response of a current flowing through the circuit when the plurality of buffers operate according to the delay information. A program for predicting the magnitude of a current in a circuit in which a plurality of buffers that output equal currents to a computer having a calculation unit operates,
The arithmetic unit performs a circuit simulation, and obtains an amplitude at a predetermined frequency of a current flowing through the circuit when the plurality of buffers operate simultaneously;
The arithmetic unit divides the plurality of buffers into a plurality of groups, and acquires delay information including the number of buffers included in each group and the delay when delaying operation timing between the groups. An acquisition step;
The calculation unit assumes that the amplitude of the current obtained in the simulation step divided by the total number of buffers is the amplitude of the current output by each buffer, and the plurality of buffers according to the delay information acquired in the acquisition step an amplitude reduction amount calculating step of calculating an amplitude reduction amount is the ratio but the amplitude of the current flowing in the circuit when operating, for the amplitude of the current flowing through the circuit when the plurality of buffers are simultaneously operated,
According to the delay information acquired in the acquisition step, the arithmetic unit multiplies the amplitude of the current obtained in the simulation step and the amplitude reduction amount calculated in the amplitude reduction amount calculation step for each frequency. And a current calculation step of calculating an amplitude of a current flowing through the circuit when the plurality of buffers operate.   A computer-readable recording medium storing the program according to claim 7. An apparatus for predicting the magnitude of current in a circuit in which a plurality of buffers each outputting equal current operates.
A simulation means for performing a circuit simulation and obtaining an amplitude at a predetermined frequency of a current flowing through the circuit when the plurality of buffers operate simultaneously;
Storage means for storing the amplitude obtained by the simulation means;
Dividing the plurality of buffers into a plurality of set groups, and obtaining delay information including the number of buffers included in each group and the delay when giving a delay set at an operation timing between the groups. Acquisition means to
The amplitude stored in the storage means divided by the total number of buffers is assumed to be the amplitude of the current output by each buffer, and when the plurality of buffers operate according to the delay information acquired in the acquisition step, an amplitude reduction amount calculating means for calculating an amplitude reduction amount is the ratio to the amplitude of the current flowing when the amplitude of the current flowing through the circuit, the plurality of buffers are simultaneously operated to the circuit,
By multiplying the amplitude stored in the storage unit and the amplitude reduction amount calculated in the amplitude reduction amount calculation step for each frequency, the plurality of buffers are set according to the delay information acquired in the acquisition step. A current predicting device comprising: current calculating means for calculating an amplitude of a current flowing through the circuit when operating.

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