JP4835838B2 - Manufacturing method of two-dimensional image detector - Google Patents

Description

The present invention relates to a two-dimensional image detector capable of detecting images such as X-ray radiation, visible light, infrared light, and the like, and a method for manufacturing the same.

As shown in FIG. 8A, the conventional two-dimensional detector includes a semiconductor layer 33 that is sensitive to radiation and directly outputs a charge signal corresponding to an incident dose, and a bias application disposed on the semiconductor layer 33. The bump substrate 4 includes a counter substrate 3 including a counter electrode 35 formed in a grid pattern below the semiconductor layer 33 and an active matrix substrate 2 including pixel electrodes 23 formed in a grid pattern. It has a structure bonded via. As means for realizing such a structure, a technique for connecting the counter substrate and the active matrix substrate with a metal material such as indium formed by a stud bump process is disclosed (for example, see Non-Patent Document 1).
In FIG. 8A, the pixel electrode 23 and the counter electrode 35 are arranged in an array, but only one of them is given a reference numeral and the other electrodes are omitted. Hereinafter, all drawings are similarly omitted.

“F. Glasser et al., Recent developments on a CdTe based X-ray detector for digital radiography / (SPIE Medical Imaging 1997 Proc. Vol./3032 p513-519)”.

  As shown in FIG. 8A, when the active matrix substrate 2 and the counter substrate 3 are bonded together, it is necessary to align the bump electrodes 4 and the counter electrodes 35 so as to be connected one-to-one. However, in general, in a two-dimensional image detector, the pitch of the counter electrodes is 100 to 200 μm, and it is difficult to bond them with high accuracy. If the bump electrode 4 enters the gap between the counter electrodes 35 as shown in FIG. 8B, the adjacent bump electrodes 4 may be short-circuited via the counter electrode 35, and all the counter electrodes may be short-circuited. It is a problem. Furthermore, in order to confirm that the adjacent bump electrodes 4 are not short-circuited, it is necessary to actually detect an image or inspect it using a dedicated inspection device. At this time, even if a short circuit of the bump electrode 4 is found as a result of the inspection, if the active matrix substrate 2 and the counter substrate 3 once bonded are peeled off, various problems such as breakage of the TFT element and peeling of the counter electrode occur. In many cases, it cannot be used by re-bonding.

In order to solve this problem, it may be considered that the bump electrode 4 is brought into direct contact with the semiconductor layer 33 without providing the counter electrode 35. However, another problem arises that the components of the bump electrode 4 diffuse into the semiconductor layer 33 and the photoelectric conversion performance of the semiconductor layer 33 is degraded.

An object of the present invention is to solve the above-mentioned problems and to provide a two-dimensional image detector that does not cause a short-circuit between adjacent bump electrodes without performing alignment when the counter substrate and the active matrix substrate are bonded together. And

In order to achieve the above object, the present invention has the following configuration. In other words, the two-dimensional image detector according to claim 1 is an active matrix substrate having a plurality of switching elements arranged in a grid and pixel electrodes connected to the switching elements, and converts light or radiation into an electrical signal. A counter substrate having a semiconductor layer to be converted, a common electrode formed on one surface of the semiconductor layer, and a plurality of counter electrodes formed on the other surface of the semiconductor layer, the pixel electrode, and the counter electrode A bump electrode to be connected, wherein a diameter of the counter electrode is smaller than a gap between the adjacent bump electrodes, and a gap between the adjacent counter electrodes is smaller than a diameter of the bump electrode.

A two-dimensional image detector according to claim 2 is the two-dimensional image detector according to claim 1, further comprising an insulating member disposed between the counter electrodes.

Further, the two-dimensional image detector according to claim 3 is the two-dimensional image detector according to claim 2, wherein the counter electrode and the insulating member are formed to have substantially the same height. It is characterized by.

A two-dimensional image detector according to claim 4 is the two-dimensional image detector according to any one of claims 1 to 3, wherein the semiconductor layer is CdTe or CdZnTe. To do.

The method for manufacturing a two-dimensional image detector according to claim 5 is a process for producing an active matrix substrate including a plurality of switching elements arranged in a grid pattern and pixel electrodes connected to the switching elements. And a step of disposing a bump electrode on the pixel electrode of the active matrix substrate, a diameter smaller than a gap between the common electrode, the semiconductor layer, and the bump electrode, and a gap smaller than the diameter of the bump electrode. Forming a counter substrate including the counter electrode, and connecting and bonding the counter substrate and the active matrix substrate with the bump electrodes.

Further, the manufacturing method of the two-dimensional image detector according to claim 6 is the manufacturing method of the two-dimensional image detector according to claim 5, wherein in the step of forming the counter substrate, the counter electrodes are arranged. The method further includes the step of disposing an insulating material on the substrate.

The manufacturing method of the two-dimensional image detector according to claim 7 is the manufacturing method of the two-dimensional image detector according to claim 5 or 6, wherein the insulating material is disposed after the step of disposing the insulating material. The method further includes a step of polishing so that the counter electrode and the insulating material have substantially the same height.

The two-dimensional image detector of the present invention operates as follows. That is, since the gap between adjacent counter electrodes is smaller than the diameter of the bump electrodes, each bump electrode is connected to at least one counter electrode. Further, since the diameter of the counter electrode is smaller than the gap between the adjacent bump electrodes, a plurality of bump electrodes are not connected to one counter electrode.

In addition, when an insulating material is provided between the counter electrodes, the bump electrode does not contact the semiconductor layer.

Further, when the counter electrode and the insulating member are set to substantially the same height, the counter electrode and the insulating member form a substantially flat surface, and the surface and the pixel electrode are joined by the bump electrode.

Since the present invention operates as described above, there is no short circuit between adjacent bump electrodes even though alignment is not required when the counter substrate and the active matrix substrate are bonded together.

Further, in the case where an insulating material is provided between the counter electrodes, the material of the bump electrode does not diffuse into the semiconductor layer, so that the photoelectric conversion performance is not deteriorated along with the bonding. Furthermore, the insulation between the counter electrodes can be enhanced. As a result, the gap between the adjacent counter electrodes can be reduced, so that the total area of the counter electrodes can be increased. If the total area can be increased, charges generated by the incidence of light or radiation can be collected efficiently.

In addition, when the counter electrode and the insulating member are made substantially the same height, there is no unevenness due to the counter electrode and the insulating member, and the bump electrodes are evenly contacted, so that the generation of defective pixels due to poor contact can be reduced.

Furthermore, even for materials such as CdTe and CdZnTe that are difficult to deposit directly on the active matrix substrate due to the high deposition temperature, two-dimensional image detection is performed after the active matrix substrate and the counter substrate are created separately. It becomes easy to manufacture the vessel.

As shown in FIG. 1, the two-dimensional image detector according to the present invention includes a switching element 22 arranged in a lattice pattern on an insulating substrate 21, a charge storage capacitor 24 connected to the switching element 22, and a pixel electrode 23. An active matrix substrate 2, a semiconductor layer 33 that converts light or radiation into an electrical signal, a common electrode 31 formed on one surface of the semiconductor layer 33, and a plurality of layers formed on the other surface of the semiconductor layer 33. The counter substrate 3 includes the counter electrode 35, and the bump electrode 4 that connects the pixel electrode 23 and the counter electrode 35.

In such a two-dimensional image detector, the first step of forming the active matrix substrate 2, the second step of forming the counter substrate, and the bump electrodes 4 are arranged on the pixel electrodes 23 of the active matrix substrate 2. It can be manufactured by a third step and a fourth step in which the counter substrate 3 and the active matrix substrate 2 are connected and bonded together by the bump electrodes 4. Each step will be described in detail below.

With reference to FIG. 2, the first step, that is, the step of forming the active matrix substrate 2 will be described. 2A is a cross-sectional view of one pixel of the active matrix substrate 2, and FIG. 3B is a perspective view. A conductive material such as Ta (tantalum), Al (aluminum), or Mo (molybdenum) is formed on the insulating substrate 21 made of alkali-free glass (for example, # 7059 or # 1737 manufactured by Corning) by sputtering to a thickness of about 4000 angstroms. Then, the gate electrode 224 and the reference potential electrode 223 are formed.

Next, SiNx (silicon nitride) or SiOx (silicon oxide) is formed to a thickness of about 3500 angstrom by a CVD (Chemical Vapor Deposition) method to form the first insulating layer 221. The first insulating layer 221 functions as a gate insulating film and forms a charge storage capacitor 24 in relation to the pixel electrode 23 and the reference potential electrode 223. The first insulating layer 221 may be used in combination with not only SiNx and SiOx but also an anodized film obtained by anodizing the gate electrode 224 and the pixel electrode 23.

Next, after a-Si is formed to a thickness of about 1000 angstroms by CVD, impurities are diffused to form an n + layer, and a channel portion 226 is formed by patterning in a desired shape.

Next, a metal film of Ta, Al, Ti (titanium) or the like is formed by sputtering deposition to a thickness of about 4000 angstroms, and the drain electrode 225 and the pixel electrode 23 are formed. The first insulating layer 221, the pixel electrode 23, the gate electrode 224, the drain electrode 225, and the channel portion 226 formed as described above constitute the switching element 22. Note that a transparent electrode such as ITO (Indium Tin Oxide) may be used for the pixel electrode 23.

Further, for the purpose of insulating and protecting the region other than the opening of the pixel electrode 23, an insulating film of SiNx or SiOx is formed by a CVD method to form the second insulating layer 222. In addition to the inorganic film, the second insulating layer 222 may be an organic film such as acrylic or polyimide.

As described above, the active matrix substrate 2 is formed. Here, as the switching element 22, a TFT element having an inverted stagger structure using amorphous silicon (a-Si) is used. However, the present invention is not limited to this, and polysilicon (p-Si) is used. Alternatively, a staggered structure may be used.

Next, the second process, that is, the process of forming the counter substrate 3 will be described with reference to FIG. As shown in FIG. 3A, an upper bias electrode 31 made of a conductive film such as ITO or Au (gold) is formed on almost the entire surface on one side. However, in the case of a two-dimensional image detector that detects an image with visible light, the upper bias electrode 31 needs to use a material that is transparent to visible light, such as ITO.

Next, a polycrystalline film of CdTe or CdZnTe is deposited on almost the entire surface of the upper bias electrode 31 to a thickness of about several hundreds μm by using a MOCVD (Metal Organic Chemical Vapor Deposition) method, thereby forming an i-type semiconductor layer. 33 is formed. As a method for forming a polycrystalline film of CdTe or CdZnTe, a proximity sublimation method, a paste printing / firing method, or the like can be used in addition to the MOCVD method. Further, a conductive film such as ITO or Au (gold) is formed thereon.

A resist layer 36 is formed on the conductive film by a general photolithography process, and exposure is performed by applying a photomask 37 in which a mask 371 is arranged in a matrix.

Thereafter, as shown in FIG. 3B, the exposed portion of the resist layer 36 and the conductive film is removed by etching to form the counter electrode 35.

Here, the maximum diameter Rm of the mask 371 of the photomask 37 is designed to be smaller than the minimum gap Db between adjacent bump electrodes. Further, the maximum gap Dm between the masks is designed to be smaller than the minimum diameter Rb of the bump electrode (Db and Dm are described in FIG. 4B).

The maximum diameter Rm of the mask 371 strictly refers to the length of the diagonal line of the mask 371. However, if the active matrix substrate 2 and the counter substrate 3 are not attached to each other obliquely, the length of the side of the mask 371 may be used. In FIG. 4, the shape of the mask 371 is rectangular, but it may be circular or any other shape. Further, the arrangement is not necessarily limited to a matrix. However, when the masks 371 are arranged in a matrix, it is preferable that the masks 371 have a rectangular shape. This is because when there is a restriction on the minimum gap and the arrangement is made in a matrix, a rectangle can take the widest contact area.

Thereafter, as shown in FIG. 3C, after further vapor-depositing SiNx, SiOx or the like, mechanical / chemical polishing such as dicing or ion mining is performed so that the counter electrode 35 is exposed. An insulating structure 38 may be formed between the counter electrodes 35.

When the insulating structure 38 is formed, the insulation between the counter electrodes 35 can be enhanced. Further, the bump electrode 4 can be prevented from coming into contact with the semiconductor layer 33. Moreover, it can also grind | polish so that the height of the counter electrode 35 and the insulating structure 38 may become uniform, and it can also be set as a flat surface. If the surface is flat, the contact area between each bump electrode 4 and the counter electrode 35 is uniform, and bubbles are less likely to be mixed between the bump electrode 4 and the counter electrode 35, thereby improving the quality of the bonding. it can.

The counter substrate 4 is configured as described above. As shown in FIG. 3D, the first charge blocking layer 32 is formed between the upper bias electrode 31 and the semiconductor layer 33 as a p-type layer made of, for example, ZnTe. A semiconductor layer may be formed, and an n-type semiconductor layer made of, for example, CdS or ZnS may be formed as the second charge blocking layer 34 between the semiconductor layer 33 and the counter electrode 35. A structure in which a photoconductive i-type semiconductor layer 33 is sandwiched between a first charge blocking layer (p-type semiconductor layer) 32 and a second charge blocking layer (n-type semiconductor layer) 34, that is, a PlN junction. By forming a type blocking photodiode structure, dark current when X-rays are not irradiated is reduced, and sensor characteristics with an excellent S / N ratio (sensitivity to X-rays) can be exhibited.

The material and structure of the first charge blocking layer 32 and the second charge blocking layer 34 are not limited, and various materials and structures can be combined as necessary. For example, in addition to a PlN junction, a Schottky junction, an MlS (Metal-Insulator Semiconductor) junction, or the like is possible. Further, depending on the required characteristics, one of the first charge blocking layer 32 or the second charge blocking layer 34 can be omitted.

Next, a third process, that is, a process of bonding the active matrix substrate 2 and the counter substrate 3 will be described.
FIG. 4A is a perspective view of the active matrix substrate 2 created by the first process. The surface of the active matrix substrate 2 is covered with a second insulating layer 222, and a through portion is provided on the pixel electrode 23.
A bump electrode 4 made of a conductive material such as solder is disposed in this penetrating portion (FIG. 4B). Thereafter, the active matrix substrate 2 and the counter substrate 3 are bonded together (FIG. 4C).

If necessary, the bonding strength between the active matrix substrate 2 and the counter substrate 3 can be increased by applying a predetermined pressure in this state or heating to a predetermined temperature. The two-dimensional image detector is completed through the above steps.

At this time, if the diameter Rm of the counter electrode 35 is formed smaller than the gap Db between the adjacent bump electrodes 4, even if a certain counter electrode 35 is located in the middle of the adjacent bump electrodes 4, It is ensured that adjacent bump electrodes 4 are not short-circuited. Further, if the gap Dm between the adjacent counter electrodes 35 is formed to be smaller than the diameter Rb of the bump electrode, at least one of the bump electrodes 4 is located in the middle of the adjacent counter electrode 35. It is ensured that the counter electrode 35 is in contact.
Therefore, no matter how the active matrix substrate 2 and the counter substrate 3 are arranged, the adjacent bump electrodes 4 are not short-circuited, and each bump electrode 4 is in contact with at least one or more counter electrodes 35. Guaranteed.

According to the present invention, the semiconductor layer 33 can be easily bonded after being formed as the counter substrate 3 without being directly deposited on the active matrix substrate 2. Therefore, the active matrix substrate 2 having a low heat resistance temperature and polycrystalline CdTe or CdZnTe that requires a film forming temperature of 400 ° C. or more can be used in combination. As a result, the sensitivity to X-rays is improved compared to a two-dimensional image detector using a-Se as the semiconductor layer 33, and a fluoroscopic image can be acquired at a lower dose.

The present invention is characterized in that the diameter of the counter electrode 35 is smaller than the gap between the bump electrodes 4 and the gap between the counter electrodes 35 is smaller than the diameter of the bump electrode 4. As long as this requirement is satisfied, various diameters and gaps of the counter electrode 35 can be selected.

However, the larger the area of the counter electrode 35 in contact with the second blocking layer 34, the wider the sensitive area for radiation. The sensitive region refers to an area range in which charges generated by incident radiation can be detected.
The relationship between the area of the counter electrode 35 and the sensitive region will be described with reference to FIG. _A bias voltage _VA is applied to the counter substrate 3 via a bias electrode 31. When radiation is incident on the semiconductor layer 33 in a state where the bias voltage _VA is applied, a hole / electron pair is generated according to the amount of incident radiation, and the electron passes through the bias electrode 31 and the hole passes through the counter electrode 35. To the bump electrode 4. At this time, in the portion where the counter electrode 35 does not exist or in the region of the counter electrode 35 not connected to the bump electrode, the electric lines of force 311 are distorted and the generated hole / electron pairs are recombined and disappear without moving. To do. In other words, the sensitivity to light and radiation is reduced in the portion where the counter electrode 35 does not exist. Therefore, the sensitivity can be increased as the total area of the counter electrode 35 in contact with the bump electrode 4 is larger.

Even if there is no bump electrode 4, the electric field lines 311 are only distorted and no electric field is applied, but it is assumed that there is no sensitivity for the sake of simplicity. Quantify the area sensitive to. That is, the sensitive area S is defined as the ratio S of the area of the counter electrode 35 connected to the bump electrode 4 that occupies the entire area where the counter electrode 35 is disposed. However, due to the nature of the present invention, the number N of counter electrodes 35 connected to each bump electrode 4 varies by one. Therefore, the minimum value of the number N of counter electrodes 35 connected to each bump electrode 4 is defined as N _min and the maximum value is defined as N _max , and the sensitive areas S at that time are defined as S _min and S _max , respectively. Further, the maximum value of variation is defined as ρ = S _min −S _max .
S _min = (Rm / Pb) · N _min
S _max = (Rm / Pb) · N _max
ρ = S _max −S _min
Here, N _min and N _max are expressed as follows.
N _min = Floor (Rb / Pm)
N _max = N _min +1
Floor () calculates an integer with the decimal part rounded down. However, when the integer with the decimal point rounded down is 0, it is set to 1.

In general, the shape of the bump electrode 4 is restricted by the shape of the switching element of the active matrix substrate 2 and the like. In order to expand the sensitive area, it is desirable that Rm = Db−Δx (Δx → 0) and Dm → 0. The gap Dm between the counter electrodes 35 is desirably set as small as possible within a range in which insulation between the adjacent counter electrodes 35 can be secured. Further, when the insulating material 38 is formed between the counter electrodes 35, the gap Dm between the counter electrodes 35 can be set smaller than when the insulating material 38 is not provided.

From this point of view, a detailed description will be given assuming that the pixel electrodes 23 are arranged at a pitch of 150 μm and the gap between the counter electrodes 35 is 5 μm. Since the bump electrodes 4 are disposed on the pixel electrodes 23, the pitch Pb of the bump electrodes 4 is also 150 μm.

(Embodiment 1)
6 shows the positional relationship between the counter electrode 35 and the bump electrode 4 when the diameter Rb of the bump electrode 4 is 50 μm, the diameter Rb of the bump electrode 4 is 100 μm, and the diameter Rm of the counter electrode 35 is 45 μm (Pm = 50 μm). FIG. The sensitive area S and the variation ρ are obtained as follows.
N _min = Floor (Rb / Pm) = Floor (100/50) = 2, N _max = 3
S _min = (Rm / Pb) · N _min = (45/150) · 2 = 0.60
S _max = (Rm / Pb) · N _max = (45/150) · 3 = 0.90
ρ = S _max −S _min = 0.30

(Embodiment 2)
FIG. 7 shows the positional relationship between the counter electrode 35 and the bump electrode 4 when the diameter Rb of the bump electrode 4 is 50 μm, the diameter Rb of the bump electrode 4 is 100 μm, and the diameter Rm of the counter electrode 35 is 5 μm (Pm = 10 μm). FIG. The sensitive area S and the variation ρ are obtained as follows.
N _min = Floor (Rb / Pm) = Floor (100/10) = 10, N _max = 11
S _min = (Rm / Pb) · N _min = (5/150) · 10 = 0.333
S _max = (Rm / Pb) · N _max = (5/150) · 11 = 0.367
ρ = S _max −S _min = 0.03
Thus, although the sensitive area is small, the variation can be suppressed.

It is a figure which shows the cross section of the two-dimensional image detector of this invention. It is a figure which shows the 1st manufacturing process which manufactures the two-dimensional image detector of this invention. It is a figure which shows the 2nd manufacturing process which manufactures the two-dimensional image detector of this invention. It is a figure which shows the 3rd manufacturing process which manufactures the two-dimensional image detector of this invention. It is a conceptual diagram explaining the sensitive area | region of the two-dimensional image detector of this invention. It is a conceptual diagram for demonstrating the sensitive area | region of Embodiment 1 of the two-dimensional image detector of this invention. It is a conceptual diagram for demonstrating the sensitive area | region of Embodiment 2 of the two-dimensional image detector of this invention. It is a conceptual diagram explaining the structure of the two-dimensional image detector which concerns on a prior art.

Explanation of symbols

2 Active Matrix Substrate 22 Switching Element 221 First Insulating Layer 222 Second Insulating Layer 223 Reference Potential Electrode 224 Gate Electrode 225 Drain Electrode 226 Channel 3 Opposite Substrate 31 Bias Electrode 331 Electric Field Line 32 First Charge Blocking Layer 33 Semiconductor Layer 34 Second charge blocking layer 32
35 Counter electrode 36 Resist layer 37 Photomask 38 Insulating structure 371 Mask 4 Bump electrode

Claims (2)

A step of creating an active matrix substrate including a plurality of switching elements arranged in a grid and a pixel electrode connected to the switching element; a step of arranging a bump electrode on the pixel electrode of the active matrix substrate; Forming a counter substrate including a common electrode, a semiconductor layer, and a counter electrode having a diameter smaller than a gap between the bump electrodes and a gap smaller than the diameter of the bump electrode; and the counter substrate and the A step of connecting and bonding the active matrix substrate by the bump electrodes,
In the step of creating the counter substrate, after the step of disposing an insulating material between the counter electrodes and the step of disposing the insulating material, polishing is performed so that the counter electrode and the insulating material are at the same height. And a step of forming a flat surface. A method for manufacturing a two-dimensional image detector. The method for manufacturing a two-dimensional image detector according to claim 1, wherein the semiconductor layer is C d T e or C d Z n T e.

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