JP4832185B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring board having various shapes and a method for manufacturing a semiconductor device using the wiring board.

  In recent years, the need for RFID (Radio Frequency Identification) -equipped cards and RFID-equipped tags that can exchange data without contact is increasing in all fields that require automatic recognition, such as management of securities and products. A card equipped with an RFID reads and writes data without contact with an external device via an antenna having a shape adapted to a frequency band used when data is exchanged. Further, since a card equipped with RFID has a large storage capacity and excellent security compared to a magnetic card that records data by a magnetic recording method, recently, a form that can be used in various fields has been proposed. .

  In general, a semiconductor device such as an RFID includes an antenna and an IC chip. The antenna may be formed directly on the IC chip, or may be formed separately from the IC chip and then connected to the IC chip. . In the latter case, the antenna pattern is generally formed on a PCB (Print Circuit Board, glass epoxy resin) substrate called a rigid substrate or an FPC (Flexible Print Circuit, polyimide resin) substrate called a flexible substrate. Conventionally, the antenna pattern is formed by forming a copper foil on a PCB substrate or an FPC substrate and patterning the copper foil by an etching method or a photolithography method (for example, Patent Document 1 and Patent Document 2). ).

In addition, a method is known that uses an electrolytic plating film formed by electrolytic plating on a wiring pattern made of a conductive material as a wiring in order to form fine wiring of a semiconductor element (for example, Patent Document 3). .
JP 2001-284521 A JP 2004-282487 A Japanese Patent Laid-Open No. 2004-87597

  However, when an antenna is formed by patterning a copper foil as described above, it is necessary to treat copper in a region that does not remain as a pattern as waste, and the utilization efficiency of raw materials is poor. Also, copper in areas that do not remain as patterns must be treated as waste, so it cannot be said to be environmentally friendly.

  For example, when a copper foil pattern is processed by a photolithography method, a photoresist, an exposure device, a developing device, a copper etching processing facility, a photoresist removal device, a drying device, and the like are required. Therefore, a large capital investment is required to manufacture the antenna, which hinders a reduction in the manufacturing cost of the antenna.

  In addition, when producing fine wiring by electrolytic plating as in the past, the wiring pattern and the electrolytic plating film are used as wiring. However, if the wiring pattern portion can be reused by using only the electrolytic plating film as wiring. This leads to a reduction in the amount of the conductive material used as the wiring pattern, and it is considered possible to reduce the cost of the semiconductor element and reduce the adverse effects on the environment in the manufacturing process.

  In view of the above problems, an object of the present invention is to provide a method for forming a wiring board and a method for manufacturing a semiconductor device that are low in cost and have little adverse effect on the environment.

  The method for manufacturing a wiring board according to the present invention is characterized in that a conductive pattern is formed on a substrate, a conductive film is formed on the pattern by electrolytic plating, and the pattern and the conductive film are separated. To do.

  In the method for manufacturing a wiring board according to the present invention, a pattern showing conductivity is formed on a substrate, a conductive film is formed on the pattern by electrolytic plating, a base is pasted on the conductive film, and the base is The pattern and the conductive film are separated by peeling from the substrate.

  In the method for manufacturing a semiconductor device of the present invention, a pattern showing conductivity is formed on a first substrate, a conductive film is formed on the pattern by electrolytic plating, the pattern and the conductive film are separated, An IC chip having at least one thin film transistor is formed over a second substrate, and the conductive film and the IC chip are electrically connected.

  In the method for manufacturing a semiconductor device of the present invention, a pattern showing conductivity is formed on a first substrate, a conductive film is formed on the pattern by electrolytic plating, the pattern and the conductive film are separated, Forming an IC chip having at least one thin film transistor over a second substrate, electrically connecting the conductive film and the IC chip, separating the second substrate and the IC chip, The conductive film is covered with a third substrate.

  The third substrate may be polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of a fibrous material, or an antistatic film.

  The third substrate is a polyester, polyamide, inorganic vapor deposition film, or a laminated film of paper and an adhesive synthetic resin made of an acrylic synthetic resin or an epoxy synthetic resin.

  The pattern is iron (Fe), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), tungsten (W), titanium (Ti), magnesium (Mg), niobium (Nb), or It is a material containing tin (Sn).

  The conductive film is made of an alloy of silver (Ag) and gold (Au), an alloy of copper (Cu) and gold (Au), an alloy of nickel (Ni) and gold (Au), cadmium (Cd) and gold. (Au) alloy, cobalt (Co) and gold (Au) alloy, copper (Cu), nickel (Ni), tin (Sn), lead (Pb), chromium (Cr), gold (Au), It contains silver (Ag), rhodium (Rh), cadmium (Cd), or cobalt (Co).

  By using the method for manufacturing a wiring board of the present invention, it is possible to manufacture the wiring board at a low cost by a simple process without performing many complicated steps. Furthermore, in the manufacturing method of the present invention, the conductive resin pattern and the electroplating bath for forming the wiring board can be reused, the adverse influence on the environment can be reduced, and the wiring board can be manufactured at low cost. it can.

  By using the wiring board manufactured according to the present invention, a low-cost semiconductor device can be manufactured by a simple process without performing many complicated steps.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In this embodiment, a method for forming a wiring board by electrolytic plating will be described. FIG. 1 is a cross-sectional view of a manufacturing process of a wiring board in the present embodiment.

  First, as shown in FIG. 1A, a pattern 102 made of a conductive material is formed over a substrate 101. As the substrate 101, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a silicon substrate, or the like can be used. In addition, it is also possible to use a substrate made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. is there.

  The pattern 102 includes a screen printing method, a vacuum deposition method, a sputtering method, a method in which a conductive material is formed on the entire surface of a glass substrate, and then removing unnecessary portions with a laser beam. It is formed by using a method that discharges from a thin tube with an opening, a viscous material typified by the dispensing method, or a method of forming a droplet by extruding it with a dry gas from a thin tube having a diameter of about several millimeters or less. Can do. In addition, conductive films having various shapes can be manufactured by changing the shape of the pattern 102. In FIG. 1, the pattern 102 has a curved surface. In other words, the pattern 102 was formed so that the cross-sectional shape was an arcuate shape. However, the surface and cross-sectional shape of the pattern 102 are not limited to this shape. For example, the cross-sectional shape may be a partially arcuate shape such as a semicircle, or a polygon such as a triangle or a quadrangle.

  Examples of the material of the pattern 102 include iron (Fe), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), tungsten (W), titanium (Ti), magnesium (Mg), and niobium (Nb). ), Or a simple metal such as tin (Sn), iron (Fe), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), tungsten (W), titanium ( A compound containing Ti), magnesium (Mg), niobium (Nb), or tin (Sn) as a main component and containing a small amount of other elements may be used. In addition, iron (Fe), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), tungsten (W), titanium (Ti), magnesium (Mg), niobium (Nb), or tin ( An alloy material mainly containing Sn) may be used. Also, in the metal resin, iron (Fe), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), tungsten (W), titanium (Ti), magnesium (Mg), niobium (Nb) Alternatively, a material in which tin (Sn) is dispersed may be used.

  Next, the substrate 101 on which the pattern 102 is formed is washed. This treatment is performed for the purpose of removing dirt from oils and fats adhering to the substrate surface. There are solvent degreasing method, emulsion degreasing method, alkali degreasing method, electrolytic degreasing method, ultrasonic degreasing method, etc. Degrease and clean.

  Next, electrolytic plating is performed on the cleaned substrate 101 to form a conductive film 103 over the pattern 102 (see FIG. 1B). FIG. 2 shows a schematic diagram during the electrolytic plating process. As shown in FIG. 2, the electrolytic plating treatment is performed by immersing the substrate 101 and the metal plate 202 in an electrolytic plating bath 201, and using the pattern 102 on the substrate 101 as a cathode and the metal plate 202 as an anode, between the pattern 102 and the metal plate 202. As a result, a conductive film having the same conductivity as that of the metal plate is formed on the pattern 102. As a metal plate, copper (Cu), nickel (Ni), tin (Sn), lead (Pb), chromium (Cr), gold (Au), silver (Ag), rhodium (Rh), cobalt (Co), or A single metal such as cadmium (Cd), an alloy of Au, Ag, Cu, Ni, cadmium (Cd), cobalt (Co), or the like can be used. The material of the metal plate 202 and the material of the pattern 102 described in this embodiment can be used in any appropriate combination as long as they are easily peeled off. The pattern 102 and the metal plate 202 may be connected in any way as long as they are electrically connected. After the completion of the electrolytic plating, the substrate 101 is taken out from the electrolytic plating bath, and the substrate is washed with pure water.

  After that, the transfer substrate 104 is attached to the conductive film 103, and the transfer substrate 104 is peeled from the substrate 101, whereby the conductive film 103 and the pattern 102 are separated (see FIGS. 1C and 1D). That is, the conductive film 103 is transferred onto the transfer base 104. Note that it is not necessary to peel off the entire conductive film 103 formed on the pattern 102 and transfer it to the transfer substrate 104. If necessary, a part of the conductive film 103 is separated from the pattern 102 and transferred to the transfer substrate 104. May be. The conductive film 103 thus separated from the pattern 102 is called a wiring board. Note that the surface of the conductive film 103 that is in contact with the pattern 102 has the same shape as the surface of the pattern 102 that is in contact with the conductive film 103. That is, the cross-sectional shape of the conductive film 103 is partially the same as the cross-sectional shape of the pattern 102. As the transfer substrate 104, for example, a slightly adhesive release tape, a heat release tape, an ultraviolet release tape, or the like can be used. Here, the conductive film 103 separated from the pattern 102 can be used as various wirings such as an antenna and a wiring for connecting the elements. For example, when the conductive film 103 manufactured in this embodiment is connected to an IC chip, the conductive film 103 can be used as an antenna of a semiconductor device. In addition, the conductive film 103 manufactured in this embodiment can be used as a wiring of a semiconductor element. Note that in this embodiment mode, since the conductive film 103 is formed by electroplating, the substrate 101 and the conductive film 103 are not bonded to each other. Therefore, the pattern 102 and the conductive film 103 can be easily peeled by using a combination of materials that are easily peeled off as the material of the metal plate 202 (conductive film 103) and the material of the pattern 102 in the electroplating process.

  In the present embodiment, the wiring board can be formed by an easy process called electrolytic plating. Furthermore, various shapes of wiring boards can be easily formed by changing the shape of the pattern. For example, when used as an antenna, antennas of various shapes such as a dipole, a ring (for example, a loop antenna), and a rectangular parallelepiped (for example, a patch antenna) can be formed. In the manufacturing method of this embodiment mode, the substrate 101, the pattern 102 formed thereon, and the electrolytic plating bath 201 for forming the wiring substrate can be reused. Can be produced.

(Embodiment 2)
In this embodiment, an embodiment of a method for connecting the wiring board manufactured in Embodiment 1 and an IC chip will be described. In this embodiment, as illustrated in FIG. 3A, a semiconductor device in which an IC chip 1140 including a plurality of thin film transistor groups and a conductive film 103 are provided over a substrate 1141 will be described. Note that the conductive film 103 is electrically connected to at least one thin film transistor included in the IC chip 1140 by connecting the conductive film and the IC chip. In addition, the semiconductor device can exchange data between the IC chip and an external device (reader / writer) through the conductive film 103 in a non-contact manner. Note that in this specification, an element capable of communicating data by wireless communication is referred to as a semiconductor device. Such a semiconductor device is sometimes called an IC tag, an ID tag, an RF (Radio Frequency) tag, an RFID (Radio Frequency Identification), a wireless tag, an electronic tag, a wireless processor, a wireless memory, a wireless chip, or the like.

  First, as shown in FIG. 3B, a bump 1134 for bonding the IC chip 1140 and the conductive film 103 is formed over the IC chip 1140. The bump 1134 is formed by a screen printing method, a sputtering method, a method in which a conductive material is formed on the entire surface of a glass substrate, and then an unnecessary portion is removed with a laser beam. It is formed using a method of discharging from an air flow, a viscous material typified by the dispensing method, or a method of forming a droplet by extruding it with a dry gas from a narrow tube with a diameter of about several millimeters or less. Can do. In this embodiment mode, a formation method in the case of forming by a screen printing method will be described.

  First, the conductive resin 1135 is placed on the printing plate, and the conductive resin (conductive paste) 1135 is applied to the opening and the entire surface of the printing plate opened in the bump pattern formation portion by the scraper. Here, for example, mesh numbers # 40 to # 400 are used as the printing plate, and silver-containing resin (Nihon Atison Co., Ltd., product name Electrodag 427SS, polyester resin is used as the binder) can be used as the conductive resin. Here, mesh number # represents the number of lines per inch. When a resin containing silver is used as the conductive resin, the resin containing silver is preferably applied at a scraper moving speed of 3 to 300 mm / sec at a position where the scraper and the printing plate are not in contact with each other.

  Next, the conductive resin 1135 is applied to the substrate using a squeegee. At this time, the squeegee is brought into contact with the printing plate, the pressing pressure is preferably 0.14 to 0.175 MPa using compressed air, and the moving speed is preferably 3 to 300 mm / sec. After printing, the printed material is leveled, for example, for 5 minutes in order to remove the unevenness of the resin, and then baked at 75 ° C. to 120 ° C. for 15 minutes to 45 minutes to form bumps. Firing is preferably performed in an indirect heating atmosphere.

  Subsequently, an anisotropic conductive resin 1136 is formed on the conductive resin 1135 by screen printing. For example, mesh numbers # 80 to # 165 are used as a screen printing plate, and, for example, ACP (manufactured by Three Bond Co., Ltd., 3373C) is placed on the printing plate as an anisotropic conductive resin 1136, and a bump pattern forming portion is formed by a scraper. An anisotropic conductive resin 1136 is applied to the printing plate opening and the entire surface corresponding to the above. At that time, the distance between the scraper and the printing plate is preferably non-contact, and the scraper moving speed is preferably 3 to 300 mm / sec. Next, an anisotropic conductive resin is applied to the substrate from the printing plate opening with a squeegee. The squeegee is brought into contact with the printing plate, the pressing pressure is 0.14 to 0.175 MPa using compressed air, and the speed is preferably 30 to 300 mm / sec. After printing, baking is performed at 120 to 160 ° C. for 5 minutes. Firing is preferably performed in an indirect heating atmosphere.

  After that, the conductive film 103 held by the transfer substrate 104 manufactured in Embodiment Mode 1 and the IC chip 1141 are attached (see FIG. 3C). In this embodiment mode, the IC chip 1141 and the conductive film 103 are bonded to each other by applying a pressure 147N to the substrate 101 and maintaining the anisotropic conductive resin at 140 ° C. for 20 seconds.

  Thereafter, the conductive substrate 103 and the transfer substrate 104 can be separated by peeling the transfer substrate 104 from the IC chip 1140. After that, the film is made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of a fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) on the conductive film 103. A protective film such as a laminated film with a synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.) is formed. Accordingly, the semiconductor device illustrated in FIG. 3A can be manufactured.

  By using the wiring substrate manufactured according to Embodiment 1 for a semiconductor device, a low-cost semiconductor device can be manufactured with a simple process without performing many complicated steps. Note that the conditions for forming the conductive resin or the anisotropic conductive resin by the screen printing method are not limited to the conditions shown in this embodiment mode, and a desired conductive resin or anisotropic conductive resin is formed. Any conditions may be used. Note that this embodiment can be freely combined with any of the other embodiments. That is, the materials and formation methods described in the other embodiments can be freely combined and used in this embodiment.

(Embodiment 3)
In this embodiment, one embodiment in which the conductive film described in the above embodiment is used for a semiconductor device will be described in detail with reference to drawings. More specifically, a method for manufacturing a semiconductor device including an IC chip having at least one thin film transistor and at least one memory element and an antenna will be described with reference to drawings. Note that in this embodiment mode, a thin film transistor is an element included in each circuit included in a semiconductor device such as an asynchronous counter and a power supply circuit.

  A separation layer 702 is formed over one surface of a substrate 701 (also referred to as a base) (see FIG. 4A). The substrate 701 has an insulating surface. As the substrate 701, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a silicon substrate, or a metal substrate including stainless steel can be used. In addition, it is also possible to use a substrate made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. is there. In the case where the substrate 701 is made of glass, there is no significant limitation on the area or shape thereof. Therefore, if the substrate 701 is, for example, a rectangle having one side of 1 meter or more and a rectangular shape, productivity can be significantly improved. In the case where the substrate 701 is made of plastic, it is necessary to use heat-resistant plastic that can withstand the processing temperature in the manufacturing process. Preferably, after at least one thin film transistor is provided over a glass substrate 701, the thin film transistor may be peeled off and provided over a plastic substrate.

  Note that although the separation layer 702 is provided over the entire surface of the substrate 701 in this step, the separation layer is provided over the entire surface of the substrate 701 as needed, and then selectively provided by patterning using a photolithography method. May be. In addition, although the separation layer 702 is formed so as to be in contact with the substrate 701, an insulating layer serving as a base is formed so as to be in contact with the substrate 701 as necessary, and the separation layer 702 is formed so as to be in contact with the insulation layer. May be.

  The separation layer 702 is formed by sputtering, plasma CVD, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium. An element selected from (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), etc. A layer made of an alloy material or a compound material is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  Next, an insulating layer 703 serving as a base is formed so as to cover the separation layer 702. The insulating layer 703 is formed as a single layer or a stacked layer including a silicon oxide or a silicon nitride by a sputtering method, a plasma CVD method, or the like. The silicon oxide material is a substance containing silicon (Si) and oxygen (O), and corresponds to silicon oxide, silicon oxide containing nitrogen, and the like. The silicon nitride material is a substance containing silicon and nitrogen (N), and corresponds to silicon nitride, silicon nitride containing oxygen, and the like. The insulating layer serving as a base functions as a blocking film that prevents impurities from entering from the substrate 701.

  Next, an amorphous semiconductor layer 704 is formed over the insulating layer 703. The amorphous semiconductor layer 704 is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. Subsequently, the amorphous semiconductor layer 704 is subjected to laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or metal elements that promote crystallization. A crystalline semiconductor layer is formed by crystallization by a method combining a thermal crystallization method and a laser crystallization method to be used. After that, the obtained crystalline semiconductor layer is patterned into a desired shape to form crystalline semiconductor layers 706 to 710 (see FIG. 4B).

  Here, an example of a manufacturing process of the crystalline semiconductor layers 706 to 710 will be described below. First, an amorphous semiconductor layer 704 is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element for promoting crystallization, is held on the amorphous semiconductor layer, the amorphous semiconductor layer is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor layer. Thereafter, laser light is irradiated as necessary, and crystalline semiconductor layers 706 to 710 are formed by a patterning process using a photolithography method.

In the case of using a laser crystallization method for crystallization of an amorphous semiconductor film, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained. By irradiation with a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher, the surface of the crystallized semiconductor film can be flattened. Accordingly, it is possible to reduce the thickness of a gate insulating film to be formed later, and contribute to improving the breakdown voltage of the gate insulating film.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, a great improvement in output can be expected.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion. When an electronic device is manufactured using a semiconductor film crystallized using a linear beam having a uniform intensity obtained in this way, the characteristics of the electronic device are good and uniform.

  Note that when an amorphous semiconductor layer is crystallized using a metal element that promotes crystallization, crystallization can be performed in a short time at a low temperature and the crystal orientation is aligned. Remains in the crystalline semiconductor layer, resulting in an increase in off-current and unstable characteristics. Therefore, an amorphous semiconductor layer functioning as a gettering site is preferably formed over the crystalline semiconductor layer. Since the amorphous semiconductor layer serving as a gettering site needs to contain an impurity element such as phosphorus or argon, it is preferably formed by a sputtering method in which argon can be contained at a high concentration. After that, heat treatment (RTA method or thermal annealing using a furnace annealing furnace) is performed to diffuse the metal element in the amorphous semiconductor layer, and then the amorphous semiconductor layer containing the metal element is removed. To do. Then, the content of the metal element in the crystalline semiconductor layer can be reduced or removed.

  Next, a gate insulating layer 705 is formed to cover the crystalline semiconductor layers 706 to 710. The gate insulating layer 705 is formed by a single layer or a stack of layers containing silicon oxide or silicon nitride by a plasma CVD method or a sputtering method.

  Note that an oxide film or a nitride film may be formed on the surfaces of the crystalline semiconductor films 706 to 710 by high-density plasma treatment before the gate insulating layer 705 is formed. For example, when Si is used for the crystalline semiconductor films 706 to 710, silicon oxide (SiOx) or silicon nitride (SiNx) is formed on the surface of the semiconductor film. Alternatively, the semiconductor film may be oxidized by high density plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor film, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide.

Note that in the case where the semiconductor film is oxidized by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen is used. Plasma treatment is performed under an atmosphere of hydrogen (H ₂ ) and a rare gas or dinitrogen monoxide and a rare gas. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen Plasma treatment is performed under a hydrogen and rare gas atmosphere or a NH ₃ and rare gas atmosphere. As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating film formed by the plasma treatment includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. For example, when Ar is used, the insulating film formed by plasma treatment contains Ar. When excitation of plasma in this case is performed by introducing microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of an object to be processed (here, a semiconductor film) formed on the substrate is low, damage to the object to be processed due to plasma can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower by 100 degrees or more than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  By such treatment using high-density plasma, an insulating film with a thickness of 1 to 20 nm, typically 5 to 10 nm, is formed over the semiconductor film. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. Such high-density plasma treatment directly oxidizes (or nitrides) a semiconductor film (crystalline silicon or polycrystalline silicon), so that the thickness of the formed insulating film ideally has extremely small variation. can do. In addition, since oxidation is not strengthened even at the crystal grain boundaries of crystalline silicon, a very favorable state is obtained. That is, the surface of the semiconductor film is solid-phase oxidized by the high-density plasma treatment shown here, thereby forming an insulating film with good uniformity and low interface state density without causing an abnormal oxidation reaction at the grain boundaries. can do.

  Note that in the case where an insulating film formed by oxidizing or nitriding a semiconductor film by plasma treatment is sufficient, the gate insulating layer 705 is not necessarily provided and is formed on the surface of the semiconductor film by plasma treatment. The formed insulating film can be used as a gate insulating film. Further, only the insulating film formed by high-density plasma treatment may be used as the gate insulating film, or an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride is formed by a CVD method using plasma or thermal reaction. It may be deposited and laminated. In any case, a transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

  In addition, when the semiconductor film is crystallized, the semiconductor film obtained by scanning the semiconductor film in one direction while irradiating the semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more is The crystal grows in the beam scanning direction. By arranging the transistors in accordance with the scanning direction in the channel length direction (the direction in which carriers flow when the channel formation region is formed) and combining the gate insulating layer formed by the high-density plasma, characteristic variation is reduced. In addition, a transistor (TFT) with high field effect mobility can be obtained.

  Next, a first conductive layer and a second conductive layer are stacked over the gate insulating layer 705. The first conductive layer is formed with a thickness of 20 to 100 nm by a plasma CVD method or a sputtering method. The second conductive layer is formed with a thickness of 100 nm to 400 nm. The first conductive layer and the second conductive layer are made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), etc. A selected element or an alloy material or a compound material containing these elements as a main component is formed. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. As examples of the combination of the first conductive layer and the second conductive layer, a layer made of tantalum nitride and a layer made of tungsten, a layer made of tungsten nitride and a layer made of tungsten, a layer made of molybdenum nitride and a layer made of molybdenum Layer and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the formation of the first conductive layer and the second conductive layer. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a layer made of molybdenum, a layer made of aluminum, and a layer made of molybdenum may be adopted.

  Next, a resist mask is formed by photolithography, and etching treatment for forming gate electrodes and gate lines is performed, so that conductive layers 716 to 725 functioning as gate electrodes are formed.

  Next, a resist mask is formed by photolithography, and an impurity element imparting N-type is added to the crystalline semiconductor layers 706 and 708 to 710 at a low concentration by ion doping or ion implantation. Impurity regions 711 and 713 to 715 and channel formation regions 780 and 782 to 784 are formed. The impurity element imparting N-type may be an element belonging to Group 15, for example, phosphorus (P) or arsenic (As).

  Next, a resist mask is formed by photolithography, and an impurity element imparting p-type conductivity is added to the crystalline semiconductor layer 707 to form an impurity region 712 and a channel formation region 781. For example, boron (B) is used as the impurity element imparting P-type.

  Next, an insulating layer is formed so as to cover the gate insulating layer 705 and the conductive layers 716 to 725. The insulating layer is formed by a single layer or a stack of layers including an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin, by a plasma CVD method or a sputtering method. . Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction to form insulating layers (also referred to as sidewalls) 739 to 743 that are in contact with the side surfaces of the conductive layers 716 to 725 (see FIG. 4 (C)). At the same time as the formation of the insulating layers 739 to 743, the insulating layer 705 is etched to form insulating layers 734 to 738. The insulating layers 739 to 743 are used as a mask for doping when an LDD (Lightly Doped Drain) region is formed later.

  Next, a resist mask is formed by photolithography, and an impurity element imparting N-type is added to the crystalline semiconductor layers 706 and 708 to 710 using the resist mask and the insulating layers 739 to 743 as a mask. Then, first impurity regions (also referred to as LDD regions) 727, 729, 731, and 733 and second impurity regions 726, 728, 730, and 732 are formed. The concentration of the impurity element in the first impurity regions 727, 729, 731, and 733 is lower than the concentration of the impurity element in the second impurity regions 726, 728, 730, and 732. Through the above steps, N-channel thin film transistors 744 and 746 to 748 and a P-channel thin film transistor 745 are completed.

  Note that the structure of the thin film transistor is not limited to the above description. Any structure such as a single drain structure, an offset structure, an LDD structure, or a GOLD (Gate Overlapped Lightly Doped Drain) structure may be used. For example, all transistors may have a structure in which LDD regions are provided, or a structure in which all transistors have no LDD regions and sidewalls (see FIG. 10A) may be employed. Further, the structure of the thin film transistor is not limited to the above-described structure, and may be a single gate structure in which one channel formation region is formed, a plurality of double gate structures in which two channel structures are formed, or a triple gate structure in which three channel structures are formed. A multi-gate TFT having a channel formation region can also be used. Alternatively, a bottom gate type (inverse stagger type) may be used, or a dual gate type having two gate electrodes arranged above and below a channel formation region with a gate insulating film interposed therebetween may be used. Further, the gate electrode may be provided in a stacked structure. In the case where the gate electrode is provided as a stack, as shown in FIG. 10B, a first conductive film 105a formed below the gate electrode and a second conductive film 105b formed over the first conductive film 105a. Alternatively, the first conductive film can be formed in a tapered shape, and an impurity region having a lower concentration than the impurity region functioning as a source or drain region can be provided so as to overlap only with the first conductive film. In the case where the gate electrode is provided in a stacked structure, the first conductive film 225a formed below the gate electrode and the second conductive film 225b formed over the first conductive film 225a are provided. A structure in which a sidewall is provided so as to be in contact with the sidewall of the second conductive film 225b and above the conductive film 225a (FIG. 10C) can also be employed. Note that in the above structure, an impurity region functioning as a source or drain region of the semiconductor films 103a and 103b can be provided using silicide such as Ni, Co, or W.

  Next, an insulating layer is formed as a single layer or a stacked layer so as to cover the thin film transistors 744 to 748 (see FIG. 5A). An insulating layer covering the thin film transistors 744 to 748 is formed by an SOG method, a droplet discharge method, or the like, an inorganic material such as silicon oxide or silicon nitride, or an organic material such as polyimide, polyamide, benzocyclobutene, acrylic, epoxy, or siloxane. Depending on the material or the like, a single layer or a stacked layer is formed. Siloxane corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Further, a fluoro group may be used as a substituent.

  For example, when the insulating layer covering the thin film transistors 744 to 748 has a three-layer structure, a layer containing silicon oxide is formed as the first insulating layer 749, and a layer containing resin is formed as the second insulating layer 750, A layer containing silicon nitride is preferably formed as the third insulating layer 751.

  Note that before the insulating layers 749 to 751 are formed or after one or more of the insulating layers 749 to 751 are formed, the crystallinity of the semiconductor layer is restored and the impurity element added to the semiconductor layer is activated. Heat treatment for the purpose of hydrogenating the semiconductor layer is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  Next, the insulating layers 749 to 751 are etched by photolithography to form openings that expose the second impurity regions 726, 728, 730, and 732, and the impurity region 712. Subsequently, a conductive layer is formed so as to fill the opening, and the conductive layer is patterned to form conductive layers 752 to 761 functioning as a source wiring or a drain wiring.

  The conductive layers 752 to 761 are elements selected from titanium (Ti), aluminum (Al), neodymium (Nd), and the like by plasma CVD or sputtering, or alloy materials or compound materials containing these elements as main components Thus, a single layer or a stacked layer is formed. The alloy material containing aluminum as a main component is, for example, a material containing aluminum as a main component and containing nickel, a material containing aluminum as a main component and containing silicon, and one type selected from nickel, carbon and silicon. Or it corresponds to the material containing multiple types. For example, the conductive layers 752 to 761 may employ a stacked structure of a barrier layer, an aluminum layer containing silicon, and a barrier layer, or a stacked structure of a barrier layer, an aluminum layer containing silicon, a titanium nitride layer, and a barrier layer. Note that silicon contained in aluminum silicon is 0.1 wt% to 5 wt%. The barrier layer corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum containing aluminum or silicon is suitable as a material for forming the conductive layers 752 to 761 because it has low resistance and is inexpensive. In addition, when the upper and lower barrier layers are provided, generation of hillocks of aluminum containing aluminum or silicon can be prevented. Further, when a barrier layer made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the crystalline semiconductor layer and the barrier are reduced in order to reduce the natural oxide film. Occurrence of poor connection of layers can be suppressed.

  Next, an insulating layer 762 is formed so as to cover the conductive layers 752 to 761 (see FIG. 5B). The insulating layer 762 is formed as a single layer or a stacked layer using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 762 is preferably formed with a thickness of 0.75 μm to 3 μm.

  Subsequently, the insulating layer 762 is etched by photolithography to form openings that expose the conductive layers 757, 759, and 761. Subsequently, a conductive layer is formed so as to fill the opening. The conductive layer is formed using a conductive material by a plasma CVD method or a sputtering method. Next, the conductive layer is patterned to form conductive layers 763 to 765. Note that the conductive layers 763 to 764 serve as one of a pair of conductive layers included in the memory element. Therefore, the conductive layers 763 to 765 are preferably formed as a single layer or a stacked layer using titanium, or an alloy material or compound material containing titanium as a main component. Since titanium has a low resistance value, it leads to a reduction in the size of the memory element, and high integration can be realized. In the photolithography process for forming the conductive layers 763 to 765, wet etching may be performed in order to prevent damage to the lower thin film transistors 744 to 748, and the etchant contains hydrogen fluoride or ammonia excess. Use water.

  Next, an insulating layer 766 is formed so as to cover the conductive layers 763 to 765. The insulating layer 766 is formed as a single layer or a stack using an inorganic material or an organic material by an SOG method, a droplet discharge method, or the like. The insulating layer 766 is preferably formed with a thickness of 0.75 μm to 3 μm. Subsequently, the insulating layer 766 is etched by photolithography to form openings 767 to 769 that expose the conductive layers 763 to 765.

  Next, a layer 787 containing an organic compound is formed so as to be in contact with the conductive layers 763 and 764 (see FIG. 6A). The layer 787 containing an organic compound is formed by a droplet discharge method, an evaporation method, or the like. Subsequently, a conductive layer 771 is formed so as to be in contact with the layer 787 containing an organic compound. The conductive layer 771 is formed by a sputtering method, an evaporation method, or the like.

  Through the above steps, the memory element 789 including the conductive layer 763, the layer 787 including the organic compound, and the conductive layer 771, and the memory including the layer including the conductive layer 764, the layer 787 including the organic compound, and the conductive layer 771 are stored. Element 790 is completed. By this step, an IC chip constituting the semiconductor device can be formed. Note that the form of the memory element is not limited to this embodiment mode, and the memory element is not necessarily provided unless necessary.

  Next, an anisotropic conductive resin 777 is formed over the conductive layer 765. Then, a support 778 provided with a conductive film 786 manufactured in the same manner as in the above embodiment is provided over the anisotropic conductive resin 777. Note that the conductive film 786 is a wiring substrate that functions as an antenna. Then, the support 778 and the conductive film 786 can be separated by removing the support 778 (see FIGS. 6B and 7A).

  Next, an insulating layer 772 functioning as a protective layer is formed by an SOG method, a droplet discharge method, or the like so as to cover the memory elements 789 and 790 and the conductive layer 786 (see FIG. 7B). The insulating layer 772 is formed using a layer containing carbon such as DLC (diamond-like carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or an organic material (preferably an epoxy resin).

  Next, the insulating layers 703, 749, 750, 751, 762, 766, and 772 are etched to form openings 773 and 774 so that part of the peeling layer 702 is exposed (see FIG. 8A). ). The openings 773 and 774 can be formed by a photolithography method or a method of removing unnecessary portions using a laser. In this embodiment mode, openings 773 and 774 are formed by irradiation with a laser beam emitted from an ultraviolet laser.

Next, the thin film integrated circuit portion 799 including the thin film transistors 744 to 748, the element groups of the memory elements 789 and 790, and the conductive layer 786 is peeled from the substrate 701. The peeling method is roughly divided into chemical peeling for removing the peeling layer 702 by etching or the like, and physical peeling for separating the thin film integrated circuit portion 799 and the peeling layer 702 by an external action. It is not limited to. In this embodiment mode, chemical peeling is used and an etching agent is introduced into the openings 773 and 774 to remove the peeling layer 702 (see FIG. 8B). As the etchant, a gas or a liquid containing halogen fluoride is used. For example, there are chlorine trifluoride (ClF ₃ ), nitrogen trifluoride (NF ₃ ), bromine trifluoride (BrF ₃ ), and hydrogen fluoride (HF). Note that in the case where hydrogen fluoride is used as the etching agent, a layer made of silicon oxide is used as the peeling layer 702. Note that the peeling layer 702 may be peeled off by a physical method such as pulling the thin film integrated circuit portion 799 from the outside without being chemically removed. When the openings 773 and 774 are formed by a laser, the peeling layer 702 and the thin film integrated circuit portion 799 are easily peeled off, and the thin film integrated circuit portion 799 and the peeling layer can be easily separated by simply pulling the thin film integrated circuit portion 799. be able to. When such a physical method is used, it is not necessary to use an expensive chemical, so that a low-cost semiconductor device can be manufactured.

  The substrate 701 from which the thin film integrated circuit portion 799 is peeled is preferably reused for cost reduction. The insulating layer 772 is provided so that the thin film integrated circuit is not scattered after the separation layer 702 is removed. Since a thin film integrated circuit is small and thin, it is likely to be scattered after the peeling layer 702 is removed because it is not in close contact with the substrate 701. However, when the insulating layer 772 is formed over the thin film integrated circuit, the thin film integrated circuit is weighted and scattering from the substrate 701 can be prevented. In addition, although the thin film integrated circuit is thin and light, the insulating layer 772 is formed, so that a certain degree of strength can be secured without forming a wound shape.

  Next, one surface of the thin film integrated circuit is bonded to the first substrate 776 and completely peeled from the substrate 701 (see FIG. 9). Subsequently, the other surface of the thin film integrated circuit is bonded to the second substrate 775, and then one or both of heat treatment and pressure treatment are performed, so that the thin film integrated circuit is bonded to the first substrate 776 and the second substrate. The semiconductor device is completed by sealing with the substrate 775.

  The first substrate 776 and the second substrate 775 are a film (antistatic film) with antistatic measures, a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like, or paper made of a fibrous material. It corresponds to a laminated film of a base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film on which an antistatic material is attached, and the like. The film with an antistatic material attached may be a film with an antistatic material attached to one side, or a film with an antistatic material attached to both sides. Good. Also, a film with an antistatic material affixed on one side may be affixed so that the surface with the antistatic material affixed is on the inside of the film, or on the outside of the film It may be pasted. The antistatic material may be attached to the entire surface or a part of the film. The antistatic materials include metals such as aluminum, oxides containing ITO and indium (ITO), amphoteric surfactant metal salts, imidazoline-type amphoteric surfactants, carboxyl groups and quaternary ammonium bases in the side chain. Examples thereof include a resin material containing a crosslinkable copolymer polymer having. By using the antistatic films as the first substrate 776 and the second substrate 775, an adverse effect on the integrated circuit due to static electricity from the outside can be prevented.

  The first substrate 776 and the second substrate 775 are bonded to the target object by thermocompression bonding, heat treatment, and pressure treatment. When the heat treatment and the pressure treatment are performed, the adhesive layer provided on the outermost surfaces of the first substrate 776 and the second substrate 775 or the layer provided on the outermost layer (not the adhesive layer) is heated. It melts by processing and adheres by pressing. Further, an adhesive layer may be provided on the surfaces of the first substrate 776 and the second substrate 775, or the adhesive layer may not be provided. Adhesive layer is thermosetting resin, UV curable resin, vinyl acetate resin adhesive, vinyl copolymer resin adhesive, epoxy resin adhesive, urethane resin adhesive, rubber adhesive, acrylic resin adhesive, etc. This corresponds to a layer containing an adhesive.

  In the case where the first substrate 776 and the second substrate 775 are made of plastic, the first substrate 776 and the second substrate 775 are thin, lightweight, and can be bent. Therefore, the first substrate 776 and the second substrate 775 are excellent in design and can be easily processed into a flexible shape. Moreover, it is excellent in impact resistance, and can be easily affixed or embedded in various articles, and can be used in various fields.

  In the above structure, the memory elements 789 and 790 are elements each including a layer containing an organic compound between a pair of conductive layers, and data writing is performed by short-circuiting the pair of conductive layers. Data is read by reading the difference in resistance value between the memory elements 789 and 790. The memory elements 789 and 790 are characterized in that they are nonvolatile, data cannot be rewritten, and data can be additionally written as long as there is a memory element to which data is not written. Moreover, since it consists of a laminated body of 3 layers, it is characterized by the easy production. Further, since the area of the stacked portion can be easily reduced, high integration can be easily realized.

  By using the wiring substrate manufactured according to Embodiment 1 for a semiconductor device, a low-cost semiconductor device can be manufactured with a simple process without performing many complicated steps. Note that this embodiment can be freely combined with any of the other embodiments and examples. That is, the materials and formation methods described in the other embodiments and examples can be freely combined and used in this embodiment.

(Embodiment 4)
One embodiment in which the semiconductor device described in the above embodiment is used as an RFID that can transmit and receive data without contact is described with reference to FIGS.

  The RFID 220 has a function of communicating data without contact, and includes a power supply circuit 211, a clock generation circuit 212, a data demodulation / modulation circuit 213, a control circuit 214 for controlling other circuits, an interface circuit 215, a memory 216, a data bus 217 includes an antenna 218 formed by the manufacturing method of the present invention (FIG. 11A).

  The power supply circuit 211 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device based on the AC signal input from the antenna 218. The clock generation circuit 212 is a circuit that generates various clock signals to be supplied to each circuit in the semiconductor device based on the AC signal input from the antenna 218. The data demodulation / modulation circuit 213 has a function of demodulating / modulating data communicated with the reader / writer 219. The control circuit 214 has a function of controlling the memory 216. The antenna 218 has a function of transmitting and receiving electromagnetic waves or radio waves. The reader / writer 219 controls communication and control with the semiconductor device and processing related to the data. The RFID is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The RFID may be of a type in which power supply voltage is supplied to each circuit by radio waves without mounting a power supply (battery), or power supply (battery) is supplied to each circuit instead of an antenna. It is good also as a type which makes it carry out, and it is good also as a type which supplies power supply voltage with an electromagnetic wave and a power supply.

  When the semiconductor device of the present invention is used for RFID or the like, select a point that performs non-contact communication, a point that multiple reading is possible, a point that data can be written, and a point that can be processed into various shapes Depending on the frequency, there are advantages such as wide directivity and wide recognition range. In addition, by using the wiring substrate manufactured according to Embodiment Mode 1 for a semiconductor device, a low-cost semiconductor device can be manufactured by a simple process without performing many complicated steps. RFID is applied to IC tags that can identify individual information of people and objects by non-contact wireless communication, labels that can be attached to targets by applying label processing, events and amusement wristbands, etc. can do. Further, the RFID may be molded using a resin material, or may be directly fixed to a metal that hinders wireless communication. Further, the RFID can be used for system operation such as an entrance / exit management system and a payment system.

  Next, one mode when the semiconductor device of the present invention is actually used as an RFID will be described. A reader / writer 320 is provided on the side surface of the portable terminal including the display portion 321, and an RFID 323 is provided on the side surface of the article 322 (FIG. 11B). When the reader / writer 320 is held over the RFID 323 included in the product 322, the display unit 321 displays information about the product, such as a description of the product, such as the raw material and origin of the product, the inspection result for each production process, and the history of the distribution process. In addition, when the product 326 is conveyed by a belt conveyor, the product 326 can be inspected using the reader / writer 324 and the RFID 325 provided in the product 326 (FIG. 11C). In this way, by using RFID in the system, information can be easily acquired, and high functionality and high added value are realized.

  By using the wiring substrate manufactured according to Embodiment 1 for a semiconductor device, a low-cost semiconductor device can be manufactured with a simple process without performing many complicated steps. Note that this embodiment can be freely combined with any of the other embodiments and examples. That is, the materials and formation methods described in the other embodiments and examples can be freely combined and used in this embodiment.

(Embodiment 5)
In this embodiment, one embodiment of a mass production method for wiring boards described in the above embodiment is described with reference to drawings. Specifically, a method for transferring a conductive film formed by electrolytic plating on a pattern formed on each of a plurality of glass substrates onto a film by a roll-to-roll method will be described. In this embodiment mode, a method of transferring a conductive film formed by electrolytic plating using a roll-to-roll type transfer apparatus schematically illustrated in FIGS. 12A and 12B onto a film will be described. FIG. 12B is a schematic view of a cross section of the device shown in FIG.

  As shown in FIG. 12A, the roll-to-roll type transfer apparatus of this embodiment rotates the first roll 1306, the second roll 1307, and the third roll 1308 around which a film 1305 is wound. Thus, the film 1305 is wound around the third roll 1308.

  First, the glass substrate 1302 over which the conductive film 1301 is formed is placed over the moving unit 1303 (see FIGS. 12A and 12B). In this embodiment mode, the moving means 1303 moves the glass substrate 1302 in the direction of the arrow. Here, the conductive film 1301 is formed over the pattern 1304 by electrolytic plating as in the first embodiment. As the glass substrate 1302, alkali-free glass, soda glass, lead glass, borosilicate glass, synthetic quartz, fused silica, silicon wafer, other ceramic substrates, or the like may be used.

  The pattern 1304 is formed by a screen printing method, a method in which a conductive material is formed on the entire surface of the glass substrate, and then an unnecessary portion is removed with a laser beam. Use any method such as a method of discharging by air flow, a material with viscosity typified by the dispensing method, or a method of forming droplets by extruding with dry gas from a narrow tube with a diameter of about several millimeters or less. May be. The size of the glass substrate can be appropriately selected as long as it is equal to or larger than the desired size of the wiring substrate as long as it can be handled by the pattern formation method. If an antenna pattern is to be obtained at a lower cost by mass production, a larger glass substrate capable of arranging as many desired patterns as possible may be used. In addition, when a substrate on which a pattern is formed is immersed in an electroplating bath and a conductive film is formed on the pattern by an electrolytic plating process, the conductive film formed by the electrolytic plating process is not limited to Cu, but Ni, Sn, Pb It may be a single metal such as Cr, Au, Ag, rhodium, or an alloy of Ag, Cu, Ni, Cd, Co, etc. and Au.

  Next, by moving the plurality of glass substrates 1302 and rotating the first roll 1306, the second roll 1307, and the third roll 1308, the conductive film 1301 formed over each glass substrate 1302 is formed into a film. 1305. That is, when the conductive film 1301 formed over the glass substrate 1302 and the second roll 1307 are brought into contact with each other through the film 1305, the conductive film 1301 is separated from the pattern 1304, and only the conductive film 1301 is transferred to the film 1305. Is done. The film 1305 is a thermoplastic resin on a base made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. The thing which apply | coated the layer with adhesiveness or adhesiveness, such as these, can be used. Of course, the material of the film 1305 is not limited to these, and there is no particular limitation as long as it is a flexible substrate having adhesiveness. In the roll-to-roll type transfer device according to the present embodiment, the diameter of the roll, the arrangement angle, the running speed of the roll film, the film material to be used, the thickness of the film, the width of the film, and the length of the film are determined by the desired antenna pattern Any material that can be transferred may be used.

  In this embodiment mode, after the conductive film 1301 is transferred, the film 1305 is wound around the third roll 1308, and the pattern 1304 formed over the glass substrate 1302 can be reused.

  Note that this embodiment can be freely combined with any of the other embodiments and examples. That is, the materials and formation methods described in the other embodiments and examples can be freely combined and used in this embodiment.

(Embodiment 6)
In this embodiment, a method for mass production of wiring boards, which is different from the method shown in Embodiment 5, will be described with reference to the drawings.

  In this embodiment mode, the antenna pattern 1402 is formed over the first film 1401 wound around the roll 1403 using the roll-to-roll screen printing apparatus illustrated in FIG. At this time, the first film 1401 used by being wound around the first roll 1403 and the second roll 1404 may be any film that has flexibility and can withstand the highest processing temperature in the subsequent manufacturing process. As the first film, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyether Examples thereof include plastic substrates such as imide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), and polyimide, and substrates made of flexible synthetic resin such as acrylic. The substrate is not very limited in its shape and area, and for example, a substrate having a maximum length of several kilometers can be wound with one roll, so that the productivity is very good. This is a significant advantage compared to a substrate having poor flexibility, such as a silicon substrate, a glass substrate, or a ceramic substrate.

  First, the antenna pattern material 1406 is applied on the printing plate 1405 to form the antenna pattern 1402 while winding the first film 1401 with the second roll 1404. Then, the antenna pattern 1402 is dried in a drying furnace 1407 and fixed on the first film 1401.

  Then, the 1st film 1401 in which the antenna pattern 1402 wound up by the 2nd roll 1404 was formed is installed in the 3rd-6th rolls 1501-1504 shown in FIG. At this time, by uniformly applying tension to the third to sixth rolls 1501 to 1504, the film thickness and electrical characteristics of the conductive film can be made uniform, and the yield of product production can be improved. It is. FIG. 14 is a schematic view of a roll-to-roll transfer apparatus that continuously performs conductive film formation by electrolytic plating, drying, and separation and peeling of the conductive film. By performing these steps continuously using a roll-to-roll transfer device, there are significant advantages in terms of cost reduction and tact improvement compared to individual steps. In this embodiment mode, the process of forming the antenna pattern 1402 on the first film 1401 is performed by another apparatus. However, the process is the same as the process of forming a conductive film by electrolytic plating, drying, and separating / separating the conductive film. You may form using the apparatus of.

  Then, the 2nd film 1508 is installed in the 7th-9th rolls 1505-1507. In this embodiment, a substrate with a thermoplastic resin is used as the second film. The second film is not limited to the thermoplastic resin, and any film having an adhesive or tacky layer on the surface may be used.

  Subsequently, the third to ninth rolls 1501 to 1507 are rotated to move the first film 1401 to perform electrolytic plating treatment. In this embodiment mode, the antenna pattern 1402 is immersed in the electrolytic plating bath 1509 and electrolytic plating is performed, so that the conductive film 1510 is formed over the antenna pattern 1402. Thereafter, the conductive film 1510 is dried in a drying furnace 1511.

  Next, the conductive film 1510 on the fifth roll 1503 and the second film 1508 on the eighth roll 1506 are brought into contact with each other, whereby the conductive film 1510 is separated and peeled from the antenna pattern 1402. That is, the conductive film 1510 is transferred over the second film 1508. The second film 1508 to which the conductive film 1510 is transferred is wound up by the ninth roll 1507. By connecting the conductive film 1510 formed over the second film 1508 to an IC chip or the like, the second film 1508 can be used as a semiconductor device. Further, the first film 1401 from which the conductive film 1510 has been peeled is taken up by the sixth roll 1504. By re-installing the wound first film 1401 on the roll-to-roll transfer apparatus connected to the plating bath again, it is possible to reuse the antenna pattern 1402 to form a conductive film. As the number of reuses of the first film 1401 is increased, the cost of antenna formation can be reduced.

  Note that this embodiment can be freely combined with any of the other embodiments and examples. That is, the materials and formation methods described in the other embodiments and examples can be freely combined and used in this embodiment.

(Embodiment 7)
The antenna of the present invention can be used for a semiconductor device. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, It can be used in foods, clothing, health supplies, daily necessities, medicines, electronic devices and the like. These examples will be described with reference to FIGS.

  FIG. 15A is an example of the state of the finished product of the ID label according to the present invention. A plurality of ID labels 20 incorporating IC chips 110 are formed on a label mount (separate paper) 118. The ID label 20 is stored in the box 119. On the ID label, information on the product and service (product name, brand, trademark, trademark owner, seller, manufacturer, etc.) is written, while the built-in IC chip has An ID number unique to the product (or product type) is attached, and it is possible to easily grasp illegal activities such as forgery, infringement of intellectual property rights such as trademark rights and patent rights, and unfair competition. In addition, in IC chips, a great deal of information that cannot be clearly stated on the container or label of the product, for example, the production area, sales location, quality, raw material, efficacy, application, quantity, shape, price, production method, usage method of the product , Production time, use time, expiration date, instruction, intellectual property information about products, etc. can be entered, and traders and consumers can access such information with a simple reader . In addition, rewriting and erasing can be easily performed from the producer side, but rewriting and erasing etc. are not possible from the trader and the consumer side.

  FIG. 15B shows an ID tag 120 incorporating an IC chip. Product management is facilitated by providing the product with an ID tag. For example, when a product is stolen, the culprit can be quickly grasped by following the route of the product. In this way, by providing an ID tag, if a problem occurs at each stage of so-called traceability (complicated manufacturing and distribution), it is possible to quickly get to know the cause by tracing back the route. )) Can be distributed.

  FIG. 15C is an example of a state of a completed product of the ID card 41 according to the present invention. Examples of the ID card include all cards such as a cash card, a credit card, a prepaid card, an electronic ticket, electronic money, a telephone card, and a membership card.

  FIG. 15D is an example of a state of a completed product of bearer bond 122 according to the present invention. The bearer bonds include, but are not limited to, stamps, tickets, tickets, admission tickets, gift certificates, book tickets, stationery tickets, beer tickets, gift tickets, various gift certificates, various service tickets, etc. It is not a thing. In addition to bearer claims, they can also be placed on securities such as checks, securities, promissory notes, etc., driver's licenses, certificates of residence, etc.

  FIG. 15E shows a packaging film 127 for packaging a product incorporating the IC chip 110. The packaging films 127 can be produced by, for example, arbitrarily dispersing IC chips on a lower layer film and covering with an upper layer film. The packaging films 127 are accommodated in a box 129 and can be used by being cut by a cutter 128 by a desired amount. In addition, the raw material as the packaging films 127 is not particularly limited. For example, thin film resin, aluminum foil, paper, etc. can be used.

  16A and 16B show a book 123 and a plastic bottle 124 to which the ID label 20 according to the present invention is attached. Of course, the present invention is not limited to these, but packaging containers such as wrapping paper for lunch boxes, recording media such as DVD software and video tape, vehicles such as bicycles, vehicles such as ships, personal items such as bags and glasses. , Foods such as food and beverages, clothing such as clothes, footwear, etc., medical supplies, health supplies such as health appliances, furniture, furniture such as lighting fixtures, pharmaceuticals, chemicals such as agricultural chemicals, liquid crystal display devices, It can be provided in various articles such as an electronic device such as an EL display device, a television device (a television receiver, a flat-screen television receiver), or a mobile phone. Since the IC chip used in the present invention is very thin, even if a thin film integrated circuit is mounted on an article such as a book, the function and design are not impaired. Further, in the case of a non-contact type thin film integrated circuit device, the antenna and the chip can be integrally formed, and it becomes easy to directly transfer to a product having a curved surface.

  FIG. 16C shows a state where the ID label 20 is directly attached to the fresh food of the fruits 131. FIG. 16D shows an example in which fresh foods of vegetables 130 are packaged by packaging films 127 incorporating IC chips 110. In addition, if the ID label is attached to the product, it may be peeled off. However, if the product is wrapped with packaging films, it is difficult to remove the packaging films. There are benefits.

  Forgery can be prevented by providing RFID for bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing RFID for personal items such as packaging containers, books, and recording media, foods, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. . By providing RFID for vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicine. As a method of providing the RFID, the RFID is provided on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

  In this way, by providing RFID for packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. . In addition, forgery and theft can be prevented by providing RFID for vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding RFID in a living creature such as livestock, it becomes possible to easily identify the year of birth, sex, type, or the like.

  As described above, a semiconductor device using the wiring board of the present invention can be provided and used for any product. By using the present invention, a low-cost semiconductor device can be manufactured by a simple process without performing many complicated steps. Note that this embodiment can be freely combined with any of the other embodiments and examples.

  In this example, the result of manufacturing the wiring substrate shown in Embodiment Mode 1 is described.

  First, a conductive resin was formed on a glass substrate by screen printing. In this example, the screen printing plate uses a mesh number of # 250, and a resin containing about 100 g of silver on the printing plate as a conductive resin (Japan Atison Co., Ltd., Elctrodag 427SS, polyester resin as a binder) A resin containing silver was applied to the printing plate opening and the entire surface corresponding to the pattern forming portion by a scraper. At that time, the distance between the scraper and the printing plate was non-contact, and the scraper was moved at a speed of 80 mm / sec. Next, a resin containing silver was applied to the base material from the printing plate opening with a squeegee. The squeegee was brought into contact with the printing plate at a speed of 100 mm / sec. The squeegee pushing pressure was set to 0.150 MPa using compressed air. After the resin containing silver was applied to the substrate, the printed matter was leveled for 5 minutes in order to remove the unevenness of the resin, and baked at 200 ° C. for 30 minutes. Firing was performed in an indirect heating atmosphere.

Then, the electrolytic plating process of copper (Cu) was performed with respect to the board | substrate with which resin containing silver was formed. The electrolytic plating bath used in the present example used 146.38 g of copper sulfate pentahydrate, 15 ml of concentrated sulfuric acid, and 150 mg of polyethylene glycol having an average molecular weight of 2000 in 500 ml of water. First, 146.38 g of copper sulfate pentahydrate and 500 ml of water were placed in a beaker, and while stirring with a stirrer, 15 ml of concentrated sulfuric acid and 150 mg of polyethylene glycol were added to dissolve everything. Thereafter, a resin containing silver on the substrate was set on the cathode, a copper plate (phosphorus-containing) was set on the anode, and a current of 0.03 A was applied for 6 minutes while stirring the electrolytic plating bath. A copper film was formed on the resin containing silver. The current density during the electrolytic plating treatment was about 1.0 A / cm ² . After the completion of the electroplating, the substrate was taken out from the electrolytic bath and washed with pure water. FIG. 17A shows an SEM (scanning electron microscope) photograph when a copper film 1203 is formed by electrolytic plating on a resin 1202 containing silver formed on a glass substrate 1201 according to this example. Show.

  Thereafter, a transfer substrate is attached to the copper film, and the transfer substrate is peeled from the substrate to peel the copper film and the resin containing silver. As shown in FIG. 17B, since the copper film and the resin containing silver are easily peeled off, the copper film can be easily manufactured. As described above, the reason why the pattern and the conductive film formed by electrolytic plating easily peel off is that the pattern and the conductive film against the stress of the conductive film generated as the conductive film formed by the electrolytic plating process grows. It is thought that separation / peeling was caused because the adhesive strength at the interface with the surface decreased relatively. The adhesion at the interface between the pattern and the conductive film was formed by the shape of the pattern, the shape of the surface of the pattern (unevenness), the material of the pattern, the electrical characteristics of the pattern, the mechanical characteristics of the pattern, and the electrolytic plating process. Influences the material of the conductive film, the electrical characteristics of the conductive film formed by the electrolytic plating process, the mechanical characteristics of the conductive film formed by the electrolytic plating process, or the paintability (surface characteristics) between the pattern and the electrolytic plating bath It is thought to receive.

4A and 4B illustrate a method for manufacturing a wiring board according to the present invention. 4A and 4B illustrate a method for manufacturing a wiring board according to the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates a mode of a thin film transistor. FIG. 11 shows a usage pattern of a semiconductor device of the invention. The figure which shows the preparation processes of the wiring board of this invention. The figure which shows the preparation processes of the wiring board of this invention. The figure which shows the preparation processes of the wiring board of this invention. FIG. 11 shows a usage pattern of a semiconductor device of the invention. FIG. 11 shows a usage pattern of a semiconductor device of the invention. The figure which shows the preparation results of the wiring board of this invention.

Explanation of symbols

101 substrate 102 pattern 103 conductive film 104 substrate for transfer

Claims (6)

A pattern showing conductivity is formed on the first substrate ,
On the surface having the curved shape of the pattern showing conductivity, a conductive film is formed by electrolytic plating,
A substrate is attached to the conductive film,
By separating the first substrate and the conductive pattern, the conductive film having a curved surface is provided on the base.
On an IC chip provided on a second substrate, forming the IC chip electrically connected to the conductive resin,
The conductive film and the IC chip are electrically connected through the conductive resin by bringing the surface of the conductive resin into contact with the surface of the conductive film having the curved shape. A method for manufacturing a semiconductor device. In claim 1,
A method for manufacturing a semiconductor device, wherein the substrate is removed from the conductive film after the conductive film and the IC chip are electrically connected. In claim 1 or claim 2,
A pattern showing the conductivity is formed on the first substrate by a method of discharging a droplet from a small tube having a small diameter, or a method of extruding a viscous material or a droplet using a dry gas from the capillary. A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 3,
The method for manufacturing a semiconductor device is characterized in that the conductive pattern has an arcuate shape or a partially arcuate shape in cross section. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the conductive pattern includes Fe, Al, Cu, Ag, Ni, W, Ti, Mg, Nb, or Sn. In any one of Claims 1 thru | or 5 ,
The conductive film is made of an alloy of Ag and Au, an alloy of Cu and Au, an alloy of Ni and Au, an alloy of Cd and Au, an alloy of Co and Au, Cu, Ni, Sn, Pb, Cr, A manufacturing method of a semiconductor device including Au, Ag, Rh, Co, or Cd.

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