JP4813180B2 - アドレスバス出力制御用の装置及び方法 - Google Patents
アドレスバス出力制御用の装置及び方法 Download PDFInfo
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- JP4813180B2 JP4813180B2 JP2005508447A JP2005508447A JP4813180B2 JP 4813180 B2 JP4813180 B2 JP 4813180B2 JP 2005508447 A JP2005508447 A JP 2005508447A JP 2005508447 A JP2005508447 A JP 2005508447A JP 4813180 B2 JP4813180 B2 JP 4813180B2
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- JP
- Japan
- Prior art keywords
- bus
- address
- data
- sense amplifier
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Sources (AREA)
- Small-Scale Networks (AREA)
- Selective Calling Equipment (AREA)
- Amplifiers (AREA)
- Dram (AREA)
- Machine Translation (AREA)
- Bus Control (AREA)
- Electrically Operated Instructional Devices (AREA)
- Information Transfer Systems (AREA)
- Microcomputers (AREA)
Description
他の実施例では、異なるシステム構成が使用されてもよいことがわかる。例えば、システム500は単一のCPU300を有するが、他の実施例では(1つ以上のプロセッサが前述のCPU300の構成及び動作と類似し得る)マルチプロセッサシステムが多様な実施例のアドレスバス出力制御手法から恩恵を受けてもよい。例えば、サーバ、ワークステーション、デスクトップコンピュータシステム、ゲームシステム、内蔵コンピュータシステム、ブレードサーバ等のような異なる形式のシステム又は異なる形式のコンピュータシステムが、他の実施例で使用されてもよい。
図9は、中央処理ユニット(CPU)901が使用され得る例示的な単一プロセッサコンピュータシステム900のブロック図である。CPU901に加えて、システム900は、一実施例ではメモリコントロールハブ(MCH:memory control hub)910と呼ばれるメモリコントローラと、一実施例ではI/Oコントロールハブ(ICH:I/O control hub)930と呼ばれる入出力(I/O)コントローラとを有する。複数の半導体チップとして実装されると、MCH910とICH930とを併せてチップセット902と呼ばれることもある。MCH910は、フロントサイドバス(FSB)931を介してCPU901に結合され、バス950を介してICH930に結合されている。メインメモリ920と1つ以上のグラフィックス装置940もMCH910に結合されている。
Claims (3)
- フロントサイドバスのデータバス部分からデータを受信するデータセンス増幅器を有するプロセッサにおいて、
アドレスストローブがアサートされることに応じて前記データセンス増幅器をイネーブルにし、
キューは、前記フロントサイドバスでこれから実行されるトランザクションを追跡し、少なくとも前記キューが空になることに応じて前記データセンス増幅器をディセーブルにすることを有する方法。 - フロントサイドバスのデータバス部分からデータを受信するデータセンス増幅器と、前記フロントサイドバスのアドレスバス部分からアドレスを受信するアドレスセンス増幅器とを有するプロセッサにおいて、
要求指示がアサートされることに応じて前記アドレスセンス増幅器をイネーブルにし、
アドレスストローブがアサートされることに応じて前記データセンス増幅器をイネーブルにし、
前記要求指示がアサート停止されることに応じて前記アドレスセンス増幅器をディセーブルにし、
キューは、前記データバスでこれから実行されるトランザクションを追跡し、少なくとも前記キューが空になることに応じて前記データセンス増幅器をディセーブルにすることを有する方法。 - 複数のプロセッサとメモリコントローラとを有し、前記複数のプロセッサ及び前記メモリコントローラはフロントサイドバスを通じて結合されるマルチプロセッサコンピュータシステムの一部であるプロセッサにおいて、
前記プロセッサは、前記フロントサイドバスのアドレスバス部分からアドレスを受信するアドレスセンス増幅器を有し、
第1の要求指示が前記プロセッサのうち1つからアサートされることに応じて前記アドレスセンス増幅器をイネーブルにし、
前記第1の要求指示がアサート停止される前に前記メモリコントローラから第2の要求指示がアサートされた場合、前記第1の要求指示がアサート停止された後に前記アドレスセンス増幅器をイネーブルにし続け、
前記第2の要求指示がアサート停止されることに応じて前記アドレスセンス増幅器をディセーブルにすることを有する方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/317,798 | 2002-12-11 | ||
US10/317,798 US7216240B2 (en) | 2002-12-11 | 2002-12-11 | Apparatus and method for address bus power control |
US10/436,903 | 2003-05-12 | ||
US10/436,903 US20040128416A1 (en) | 2002-12-11 | 2003-05-12 | Apparatus and method for address bus power control |
PCT/US2003/037614 WO2004053706A2 (en) | 2002-12-11 | 2003-11-24 | An apparatus and method for address bus power control |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006511897A JP2006511897A (ja) | 2006-04-06 |
JP4813180B2 true JP4813180B2 (ja) | 2011-11-09 |
Family
ID=32511034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005508447A Expired - Fee Related JP4813180B2 (ja) | 2002-12-11 | 2003-11-24 | アドレスバス出力制御用の装置及び方法 |
Country Status (11)
Country | Link |
---|---|
US (1) | US20040128416A1 (ja) |
EP (2) | EP2109029B1 (ja) |
JP (1) | JP4813180B2 (ja) |
KR (1) | KR100737549B1 (ja) |
CN (1) | CN100422905C (ja) |
AT (1) | ATE437394T1 (ja) |
AU (1) | AU2003293030A1 (ja) |
DE (1) | DE60328520D1 (ja) |
HK (1) | HK1075949A1 (ja) |
TW (1) | TWI310910B (ja) |
WO (1) | WO2004053706A2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7000065B2 (en) | 2002-01-02 | 2006-02-14 | Intel Corporation | Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers |
US7484016B2 (en) * | 2004-06-30 | 2009-01-27 | Intel Corporation | Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine |
US7822978B2 (en) * | 2005-07-22 | 2010-10-26 | Intel Corporation | Quiescing a manageability engine |
US7870407B2 (en) * | 2007-05-18 | 2011-01-11 | Advanced Micro Devices, Inc. | Dynamic processor power management device and method thereof |
US7477178B1 (en) * | 2007-06-30 | 2009-01-13 | Cirrus Logic, Inc. | Power-optimized analog-to-digital converter (ADC) input circuit |
US8581756B1 (en) | 2012-09-27 | 2013-11-12 | Cirrus Logic, Inc. | Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration |
US11138348B2 (en) * | 2018-10-09 | 2021-10-05 | Intel Corporation | Heterogeneous compute architecture hardware/software co-design for autonomous driving |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
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US4202045A (en) * | 1979-03-05 | 1980-05-06 | Motorola, Inc. | Write circuit for a read/write memory |
JPH0715674B2 (ja) * | 1986-01-20 | 1995-02-22 | 日本電気株式会社 | マイクロコンピユ−タ |
JPH0812756B2 (ja) * | 1987-06-22 | 1996-02-07 | 松下電子工業株式会社 | スタチックram回路 |
US5432944A (en) * | 1991-08-05 | 1995-07-11 | Motorola, Inc. | Data processing system having a dynamically enabled input synchronizer for selectively minimizing power consumption |
US5327394A (en) * | 1992-02-04 | 1994-07-05 | Micron Technology, Inc. | Timing and control circuit for a static RAM responsive to an address transition pulse |
US5430683A (en) * | 1994-03-15 | 1995-07-04 | Intel Corporation | Method and apparatus for reducing power in on-chip tag SRAM |
US5692202A (en) * | 1995-12-29 | 1997-11-25 | Intel Corporation | System, apparatus, and method for managing power in a computer system |
US5911153A (en) * | 1996-10-03 | 1999-06-08 | International Business Machines Corporation | Memory design which facilitates incremental fetch and store requests off applied base address requests |
US5848428A (en) * | 1996-12-19 | 1998-12-08 | Compaq Computer Corporation | Sense amplifier decoding in a memory device to reduce power consumption |
US6141765A (en) * | 1997-05-19 | 2000-10-31 | Gigabus, Inc. | Low power, high speed communications bus |
US6243817B1 (en) * | 1997-12-22 | 2001-06-05 | Compaq Computer Corporation | Device and method for dynamically reducing power consumption within input buffers of a bus interface unit |
US6330679B1 (en) | 1997-12-31 | 2001-12-11 | Intel Corporation | Input buffer circuit with dual power down functions |
JPH11212687A (ja) * | 1998-01-26 | 1999-08-06 | Fujitsu Ltd | バス制御装置 |
US6058059A (en) * | 1999-08-30 | 2000-05-02 | United Microelectronics Corp. | Sense/output circuit for a semiconductor memory device |
JP4216415B2 (ja) * | 1999-08-31 | 2009-01-28 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001167580A (ja) * | 1999-12-07 | 2001-06-22 | Toshiba Corp | 半導体記憶装置 |
US6609171B1 (en) * | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
KR100546184B1 (ko) * | 2000-10-20 | 2006-01-24 | 주식회사 하이닉스반도체 | 센스 앰프 회로 |
US7000065B2 (en) * | 2002-01-02 | 2006-02-14 | Intel Corporation | Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers |
US6961787B2 (en) * | 2002-01-07 | 2005-11-01 | Intel Corporation | Method and apparatus for updating task files |
US7152167B2 (en) * | 2002-12-11 | 2006-12-19 | Intel Corporation | Apparatus and method for data bus power control |
-
2003
- 2003-05-12 US US10/436,903 patent/US20040128416A1/en not_active Abandoned
- 2003-11-24 EP EP09009442A patent/EP2109029B1/en not_active Expired - Lifetime
- 2003-11-24 KR KR1020057010706A patent/KR100737549B1/ko not_active IP Right Cessation
- 2003-11-24 DE DE60328520T patent/DE60328520D1/de not_active Expired - Lifetime
- 2003-11-24 CN CNB2003801058531A patent/CN100422905C/zh not_active Expired - Fee Related
- 2003-11-24 WO PCT/US2003/037614 patent/WO2004053706A2/en active Application Filing
- 2003-11-24 AT AT03790020T patent/ATE437394T1/de not_active IP Right Cessation
- 2003-11-24 EP EP03790020A patent/EP1570335B1/en not_active Expired - Lifetime
- 2003-11-24 JP JP2005508447A patent/JP4813180B2/ja not_active Expired - Fee Related
- 2003-11-24 AU AU2003293030A patent/AU2003293030A1/en not_active Abandoned
- 2003-12-10 TW TW092134895A patent/TWI310910B/zh not_active IP Right Cessation
-
2005
- 2005-09-12 HK HK05107990.0A patent/HK1075949A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100737549B1 (ko) | 2007-07-10 |
WO2004053706A2 (en) | 2004-06-24 |
EP1570335B1 (en) | 2009-07-22 |
CN100422905C (zh) | 2008-10-01 |
HK1075949A1 (en) | 2005-12-30 |
ATE437394T1 (de) | 2009-08-15 |
EP2109029A1 (en) | 2009-10-14 |
TW200428279A (en) | 2004-12-16 |
AU2003293030A1 (en) | 2004-06-30 |
WO2004053706A3 (en) | 2004-11-18 |
EP2109029B1 (en) | 2012-12-26 |
US20040128416A1 (en) | 2004-07-01 |
TWI310910B (en) | 2009-06-11 |
KR20050085590A (ko) | 2005-08-29 |
AU2003293030A8 (en) | 2004-06-30 |
JP2006511897A (ja) | 2006-04-06 |
EP1570335A2 (en) | 2005-09-07 |
DE60328520D1 (de) | 2009-09-03 |
CN1726451A (zh) | 2006-01-25 |
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