JP4804444B2 - Structure of light emitting diode and manufacturing method thereof - Google Patents
Structure of light emitting diode and manufacturing method thereof Download PDFInfo
- Publication number
- JP4804444B2 JP4804444B2 JP2007284034A JP2007284034A JP4804444B2 JP 4804444 B2 JP4804444 B2 JP 4804444B2 JP 2007284034 A JP2007284034 A JP 2007284034A JP 2007284034 A JP2007284034 A JP 2007284034A JP 4804444 B2 JP4804444 B2 JP 4804444B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- substrate
- emitting diode
- light emitting
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Description
本発明は、発光ダイオードの構造及びその製造方法に係り、特に、切削線領域の表面に複数の凹部と凸部を形成した発光ダイオードの構造及びその製造方法に関する。 The present invention relates to a structure of a light emitting diode and a manufacturing method thereof, and more particularly to a structure of a light emitting diode having a plurality of concave portions and convex portions formed on a surface of a cutting line region and a manufacturing method thereof.
ソリッド照明を実現するため、発光効率を向上した発光ダイオードの開発が急がれている。発光ダイオードの発光効率改善の方法は二つの部分に分けられる。その一つは発光ダイオードの内部量子効率を向上することで、もう一つは発光ダイオードの光ピックアップ効率（光取出し率）を増すことである。 In order to realize solid state lighting, development of light emitting diodes with improved luminous efficiency is urgently needed. The method of improving the light emission efficiency of the light emitting diode can be divided into two parts. One is to improve the internal quantum efficiency of the light-emitting diode, and the other is to increase the optical pickup efficiency (light extraction rate) of the light-emitting diode.
外部量子効率方面では、一般に半導体材料とパッケージ材料の屈折率の違いが大きいために、全反射角が小さくなり、ゆえに発光ダイオードの発生する光が空気との界面に到達した時、臨界角より大きい光は全反射されて発光ダイオードダイの内部に戻る。光子の境界面にて半導体を離れる確率は小さくなり、光子はただ内部で全部が吸収されて熱に転成するまで全反射され続けるだけであり、このため、発光効率が悪くなる。 In the external quantum efficiency direction, the difference in refractive index between the semiconductor material and the package material is generally large, so that the total reflection angle is small. Therefore, when the light generated by the light emitting diode reaches the interface with air, it is larger than the critical angle. The light is totally reflected and returns to the inside of the light emitting diode die. The probability of leaving the semiconductor at the interface between photons is reduced, and the photons are only totally reflected until they are completely absorbed and converted into heat, and the light emission efficiency is deteriorated.
このため基板の幾何形状を変化させることが光取出し効率を高めて発光効率をアップする有効な方法の一つである。特許文献１によると、周囲に凹凸幾何形状を具備する半導体発光素子が記載され、発光ダイオード素子の周囲が平坦な形状の場合と較べて、横方向伝播の光はこれら凹部或いは凸部の影響を受けて、散乱或いは回折効果を発生し、大幅に外部量子効率がアップする。 Therefore, changing the geometric shape of the substrate is one of effective methods for increasing the light extraction efficiency and increasing the light emission efficiency. According to Patent Document 1, a semiconductor light emitting device having a concave-convex geometric shape is described, and the light propagating in the lateral direction has an influence of these concave portions or convex portions as compared with a flat shape around the light emitting diode device. In response, a scattering or diffraction effect is generated, and the external quantum efficiency is greatly increased.
但し、この技術の、基板に対して凹部或いは凸部を具備する幾何形状を形成する方法は、先ず鈍化層構造を基板の上方に形成し、更にリソグラフィー方式を利用し、凹部或いは凸部の幾何形状の外形のパターンを画定し、更にドライエッチング或いはウェットエッチングの方式で基板に対して凹部或いは凸部構造を形成する。このような製造過程は煩瑣であり、製造コストが増し、発光ダイオードの商業応用に符合しない。 However, the method of forming a geometrical shape having a concave portion or a convex portion with respect to the substrate of this technique first forms a blunt layer structure above the substrate, and further uses a lithography method to form the geometric shape of the concave portion or the convex portion. A pattern having an outer shape is defined, and a concave or convex structure is formed on the substrate by dry etching or wet etching. Such a manufacturing process is cumbersome, increases the manufacturing cost, and does not match the commercial application of light emitting diodes.
本発明は一種の発光ダイオードの構造及びその製造方法を提供することを目的とし、それは切削線領域の表面に化学反応層を形成し、該化学反応層をエッチングマスクとし、ウェットエッチング或いはドライエッチングにより、凹凸表面を具えた不規則幾何形状を該基板の切削線領域の表面上に形成し、更にエピタキシャル成長方式を利用し、周囲に凹凸幾何形状を具えた半導体発光素子を形成し、発光ダイオードの外部量子効率をアップし、商業上の大量生産に適合する。 An object of the present invention is to provide a structure of a kind of light emitting diode and a manufacturing method thereof, which forms a chemical reaction layer on the surface of a cutting line region, uses the chemical reaction layer as an etching mask, and performs wet etching or dry etching. Forming an irregular geometric shape with an uneven surface on the surface of the cutting line region of the substrate, and further using an epitaxial growth method to form a semiconductor light emitting device with an uneven geometric shape around the outside of the light emitting diode Increases quantum efficiency and suits commercial mass production.
本発明の発光ダイオードの製造方法は、まず基板を提供し、該基板表面に鈍化層を成長させ、並びに該鈍化層をパターン化し、該鈍化層に被覆される素子領域と該基板表面に露出する切削線領域を画定し、そのうち、該基板は、サファイヤ、炭化シリコン、シリコン、ヒ素化ガリウム、窒化アルミニウム、窒化ガリウム基板のいずれかとする。該基板を第１溶液内に置いて反応させ、該切削線領域の基板表面に高密度の化学反応層を形成し、その後、該鈍化層と該化学反応層をマスクとし、該基板の切削線領域に対して選択性エッチングを行い、そのエッチング法はドライエッチング或いはウェットエッチングとし、該切削線領域において該化学反応層のない部分の複数の凹部と上方に該化学反応層を有する凸部を形成する。 The method of manufacturing a light emitting diode according to the present invention first provides a substrate, grows a blunt layer on the surface of the substrate, patterns the blunt layer, and exposes an element region covered by the blunt layer and the substrate surface. A cutting line region is defined, and the substrate is one of a sapphire, silicon carbide, silicon, gallium arsenide, aluminum nitride, and gallium nitride substrate. The substrate is placed in the first solution and reacted to form a high-density chemical reaction layer on the substrate surface in the cutting line region, and then the blunt layer and the chemical reaction layer are used as a mask to cut the substrate cutting line. Selective etching is performed on the region, and the etching method is dry etching or wet etching. In the cutting line region, a plurality of concave portions of the portion without the chemical reaction layer and a convex portion having the chemical reaction layer are formed above. To do.
更に該基板を第２溶液内に置いてエッチングし、該化学反応層を除去し、該基板の切削線領域表面に凹部と凸部を具えた不規則幾何形状を形成し、その後、該鈍化層を除去し、且つ該基板表面をクリーニングする。続いて、該基板の表面の素子領域と切削線領域にエピタキシャル成長技術を利用して、半導体層構造を成長させ、且つ該切削線領域上の半導体層構造の表面に、複数の半導体層凹部と半導体層凸部を具備させる。最後にリソグラフィー工程により、素子領域上の半導体層構造に発光ダイオード素子を形成させる。 Further, the substrate is placed in a second solution and etched to remove the chemical reaction layer, thereby forming an irregular geometric shape having concave and convex portions on the surface of the cutting line region of the substrate, and then the blunt layer And the surface of the substrate is cleaned. Subsequently, a semiconductor layer structure is grown using an epitaxial growth technique on the element region and the cutting line region on the surface of the substrate, and a plurality of semiconductor layer recesses and semiconductors are formed on the surface of the semiconductor layer structure on the cutting line region. A layer convex part is provided. Finally, a light emitting diode element is formed in the semiconductor layer structure on the element region by a lithography process.
該半導体層構造は少なくとも一つのｎ型半導体層、活性層、及び少なくとも一つのｐ型半導体層を順にエピタキシャル成長させて形成し、そのうち、該活性層は発光領域として該ｎ型半導体層と該ｐ型半導体層の間に形成し、且つ該ｐ型半導体層をｐ型オームコンタクト電極と電気的に接続し、該ｎ型半導体層にｎ型オームコンタクト電極を電気的に接続して順方向バイアスを提供し、該切削線領域を該ｎ型半導体層までエッチングし、且つ該ｎ型半導体層表面に複数の半導体層凹部と半導体層凸部を具備させる。 The semiconductor layer structure is formed by epitaxially growing at least one n-type semiconductor layer, an active layer, and at least one p-type semiconductor layer in order, wherein the active layer serves as the light-emitting region and the n-type semiconductor layer and the p-type semiconductor layer. Forming between semiconductor layers, electrically connecting the p-type semiconductor layer to a p-type ohmic contact electrode, and electrically connecting the n-type ohmic contact electrode to the n-type semiconductor layer to provide a forward bias Then, the cutting line region is etched to the n-type semiconductor layer, and a plurality of semiconductor layer concave portions and semiconductor layer convex portions are provided on the surface of the n-type semiconductor layer.
そのうち、第１溶液と第２溶液は酸性溶液グループ、アルカリ性溶液グループから選択された少なくとも一種類及び数種類の組合せのいずれかとされる。該酸性溶液グループは、フッ化水素（ＨＦ）、硫酸（Ｈ2 ＳＯ4 ）、塩酸（ＨＣｌ）、りん酸（Ｈ3 ＰＯ4 ）、硝酸（ＨＮＯ3 ）、王水（Ａｑｕａ ｒｅｇｉａ）、バッファードオキサイドエッチャント（Ｂｕｒｒｅｒｅｄ Ｏｘｉｄｅ Ｅｔｃｈ；ＢＯＥ）、アルミニウムエッチャント（ＡｌＥｔｃｈａｎｔ）、過酸化水素（Ｈ2 Ｏ2 ）、ぎ酸（ＨＣＯＯＨ）、酢酸（ＣＨ3 ＣＯＯＨ）、こはく酸（Ｃ4 Ｈ6 Ｏ4 ）及びクエン酸（Ｃｉｔｒｉｃ Ａｃｉｄ）を包含する。該アルカリ性溶液グループは、水酸化カリウム（ＫＯＨ）、水酸化ナトリウム（ＮａＯＨ）、水酸化カルシウム（Ｃａ（ＯＨ）2 ）、水酸化アンモニウム（ＮＨ4 ＯＨ）、テトラメチルアンモニウムヒドロキサイド（ｔｅｔｒａｍｅｔｈｙｌａｍｍｏｎｉｕｍｈｙｄｒｏｘｉｄｅ；ＴＭＡＨ）を包含する。 Of these, the first solution and the second solution are at least one selected from an acidic solution group and an alkaline solution group and a combination of several types. The acidic solution group includes hydrogen fluoride (HF), sulfuric acid (H 2 SO 4 ), hydrochloric acid (HCl), phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ), aqua regia (Aqua regia), buffered Oxide etchant (Burred Oxide Etch; BOE), aluminum etchant (AlEtchant), hydrogen peroxide (H 2 O 2 ), formic acid (HCOOH), acetic acid (CH 3 COOH), succinic acid (C 4 H 6 O 4 ) and Includes citric acid. The alkaline solution group includes potassium hydroxide (KOH), sodium hydroxide (NaOH), calcium hydroxide (Ca (OH) 2 ), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH). Is included.
該基板を第１溶液と第２溶液中に置く時間はそれぞれ１秒から２００分間とし、該凹部と凸部の高度差は０．１μｍから１５μｍとする。 The time for placing the substrate in the first solution and the second solution is 1 second to 200 minutes, respectively, and the height difference between the concave and convex portions is 0.1 μm to 15 μm.
上述の方法で形成した発光ダイオード構造は、そのうち該基板の表面が素子領域と切削線領域に分けられ、且つ該切削線領域の表面に凹部と凸部を具えた不規則幾何形状が形成され、エピタキシャル成長技術を利用して、該半導体層構造が該基板表面の素子領域と切削線領域に成長させられ、更にリソグラフィー工程により、素子領域上の半導体層構造により該発光ダイオード素子が形成される。 In the light emitting diode structure formed by the above-described method, the surface of the substrate is divided into an element region and a cutting line region, and an irregular geometric shape including a concave portion and a convex portion is formed on the surface of the cutting line region, Using an epitaxial growth technique, the semiconductor layer structure is grown on the element region and the cutting line region on the substrate surface, and the light emitting diode element is formed by the semiconductor layer structure on the element region by a lithography process.
本発明の長所は、新規な製造方法により基板の切削線表面に化学反応層を形成し、該化学反応層をエッチング用マスクとし、ウェットエッチング或いはドライエッチングにより、異なる凹凸面の不規則幾何形状を該基板の切削線表面上に形成し、更にエピタキシャル成長技術により、周囲に凹凸幾何形状を具えた半導体発光素子を形成し、これら凹部と凸部構造により発光ダイオード素子内部の光の散乱、回折効果に対して、半導体層と基板の界面中の光の横向き伝播の状況を減らし、全反射の確率を減らし、発光ダイオードの光取出し効率を向上する。このほか、該基板上方において、エピタキシャル材料を該凹凸面の不規則幾何形状に成長させ、材料中のスレッディングディスロケーション（Ｔｈｒｅａｄｉｎｇ Ｄｉｓｌｏｃａｔｉｏｎ）を減らし、エピタキシャル材料の品質を向上し、これにより内部量子効率をアップする。且つ本発明は製造が簡単で、生産コストを減らせ、大量生産に適合する。 The advantage of the present invention is that a chemical reaction layer is formed on the cutting line surface of the substrate by a novel manufacturing method, the chemical reaction layer is used as an etching mask, and irregular irregular shapes of different uneven surfaces are formed by wet etching or dry etching. Formed on the cutting line surface of the substrate, and further, by epitaxial growth technology, a semiconductor light emitting device having an uneven geometric shape is formed around it, and the concave and convex structures make it possible to scatter and diffract light inside the light emitting diode device. On the other hand, the situation of lateral propagation of light in the interface between the semiconductor layer and the substrate is reduced, the probability of total reflection is reduced, and the light extraction efficiency of the light emitting diode is improved. In addition, above the substrate, the epitaxial material is grown in the irregular geometric shape of the uneven surface, reducing threading dislocation in the material, improving the quality of the epitaxial material, thereby improving the internal quantum efficiency. Up. In addition, the present invention is easy to manufacture, reduces production costs, and is suitable for mass production.
図１から図５に示されるように、本発明の発光ダイオードの製造方法は以下を包含する。 As shown in FIGS. 1 to 5, the method for manufacturing a light emitting diode of the present invention includes the following.
まず、基板（１０）を提供する。該基板（１０）は、サファイヤ、炭化シリコン、シリコン、ヒ素化ガリウム、窒化アルミニウム、窒化ガリウム基板のいずれかとする。該基板（１０）の表面に、鈍化層（１１）を成長させ、並びに該鈍化層（１１）をパターン化し、該鈍化層（１１）に被覆される素子領域（１０１）と該基板（１０）表面において露出する切削線領域（１０２）を画定する（図１）。 First, a substrate (10) is provided. The substrate (10) is one of sapphire, silicon carbide, silicon, gallium arsenide, aluminum nitride, and gallium nitride substrate. A blunt layer (11) is grown on the surface of the substrate (10), and the blunt layer (11) is patterned, and an element region (101) covered with the blunt layer (11) and the substrate (10) A cutting line region (102) exposed at the surface is defined (FIG. 1).
その後、サファイヤ、炭化シリコン、シリコン、ヒ素化ガリウム、窒化アルミニウム、窒化ガリウム基板のいずれかとされる該基板（１０）を第１溶液内に置き反応させ、該切削線領域（１０２）が露出した基板（１０）の表面に高密度の化学反応層（１０３）を形成する。
該第１溶液は酸性溶液グループ、アルカリ性溶液グループの少なくとも一つの材料、或いはそのグループの組合せのいずれかとする。
該酸性溶液グループは、フッ化水素、硫酸、塩酸、りん酸、硝酸、王水、バッファードオキサイドエッチャント、アルミニウムエッチャント、過酸化水素、ぎ酸、酢酸、こはく酸及びクエン酸を包含する。
該アルカリ性溶液グループは、水酸化カリウム、水酸化ナトリウム、水酸化カルシウム、水酸化アンモニウム、テトラメチルアンモニウムヒドロキサイドを包含する。
該基板（１０）を該第１溶液内に置く時間は１秒から２００分間とする。その後、該鈍化層（１１）と該化学反応層（１０３）をマスクとして、該基板（１０）の切削線領域（１０２）に対して選択性エッチングを行い、切削線領域（１０２）の該化学反応層（１０３）の無い部分の複数の凹部（１０４）と、上方に化学反応層（１０３）を具えた凸部（１０５）を形成する（図２）。
本発明は、該第１溶液を使用して、該基板（１０）の切削線領域（１０２）に不連続の該化学反応層を形成し、続いて、選択性エッチングを行ない、このとき、該基板の、該化学反応層により被覆されていない部分に、該半導体凹部が形成され、該化学反応層により被覆された部分は反応しないため、半導体凸部が形成される。その後、さらに該化学反応層を除去し、こうして、該基板の切削線領域表面に凹部と凸部を有する不規則幾何形状を形成する。
Thereafter, the substrate (10), which is one of sapphire, silicon carbide, silicon, gallium arsenide, aluminum nitride, and gallium nitride substrate , is placed in the first solution and reacted to expose the cutting line region (102). A high-density chemical reaction layer (103) is formed on the surface of (10).
The first solution is either an acidic solution group, at least one material of an alkaline solution group, or a combination of the groups.
The acidic solution group includes hydrogen fluoride, sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, aqua regia, buffered oxide etchant, aluminum etchant, hydrogen peroxide, formic acid, acetic acid, succinic acid and citric acid.
The alkaline solution group includes potassium hydroxide, sodium hydroxide, calcium hydroxide, ammonium hydroxide, tetramethylammonium hydroxide.
The time for placing the substrate (10) in the first solution is 1 second to 200 minutes. Thereafter, selective etching is performed on the cutting line region (102) of the substrate (10) using the blunt layer (11) and the chemical reaction layer (103) as a mask, and the chemical of the cutting line region (102) is obtained. A plurality of concave portions (104) in a portion without the reaction layer (103) and a convex portion (105) having a chemical reaction layer (103) above are formed (FIG. 2).
The present invention uses the first solution to form a discontinuous chemically reactive layer in the cutting line region (102) of the substrate (10), followed by selective etching, wherein the The semiconductor concave portion is formed in a portion of the substrate that is not covered with the chemical reaction layer, and the portion covered with the chemical reaction layer does not react, so that a semiconductor convex portion is formed. Thereafter, the chemical reaction layer is further removed, and thus an irregular geometric shape having concave and convex portions is formed on the surface of the cutting line region of the substrate.
該基板（１０）をサファイヤ基板（Ａｌ2 Ｏ3 ）とする場合を例とすると（以下の説明で該基板（１０）はいずれもサファイヤ基板（Ａｌ2 Ｏ3 ）とする）、サファイヤ基板（Ａｌ2 Ｏ3 ）を硫酸（Ｈ2 ＳＯ4 ）（９６％）中に置き（硫酸を第１溶液とする）、液体温度は摂氏約２５〜４００度、反応時間は１秒〜２００分間とし、該基板（１０）の表面に高密度ナノメータレベルの該化学反応層（１０３）（Ａｌ2 （ＳＯ4 ）3 或いはＡｌ2 （ＳＯ4 ）・１７Ｈ2 Ｏ等）を形成する。その後、該化学反応層（１０３）をマスクとし、該基板（１０）に対してドライエッチング或いはウェットエッチングで選択性エッチングを行う。 Taking the substrate (10) as a sapphire substrate (Al 2 O 3 ) as an example (in the following description, the substrate (10) is a sapphire substrate (Al 2 O 3 )), a sapphire substrate (Al 2 O 3 ) in sulfuric acid (H 2 SO 4 ) (96%) (sulfuric acid as the first solution), the liquid temperature is about 25 to 400 degrees Celsius, the reaction time is 1 second to 200 minutes, The high-density nanometer level chemical reaction layer (103) (Al 2 (SO 4 ) 3 or Al 2 (SO 4 ) · 17H 2 O, etc.) is formed on the surface of the substrate (10). Thereafter, selective etching is performed on the substrate (10) by dry etching or wet etching using the chemical reaction layer (103) as a mask.
ウェットエッチングでサファイヤ基板（Ａｌ2 Ｏ3 ）をエッチングする場合、その表面に凹部（１０４）と凸部（１０５）を形成させられる。また、サファイヤ基板を第１溶液例えば硫酸（Ｈ2 ＳＯ4 ）でエッチングする時間を、２．５分間から２０分間の間で変化させると、平均エッチング深さ（ａｖｅｒａｇｅ ｅｔｃｈｉｎｇ ｄｅｅｐ）、平均顆粒サイズ（ａｖｅｒａｇｅ ｇｒａｉｎ ｓｉｚｅ）、密度（ｄｅｎｓｉｔｙ）及びＲＭＳ粗度（ＲＭＳ ｒｏｕｇｈｎｅｓｓ）の異なる基板（１０）が得られる。原子力顕微鏡で基板（１０）表面を観察した結果は、以下の表１のようになる。 When the sapphire substrate (Al 2 O 3 ) is etched by wet etching, the concave portion (104) and the convex portion (105) can be formed on the surface. In addition, when the time for etching the sapphire substrate with the first solution such as sulfuric acid (H 2 SO 4 ) is changed between 2.5 minutes and 20 minutes, the average etching depth (average etching depth) and the average granule size ( Substrates (10) with different average grain size, density and RMS roughness are obtained. The results of observing the surface of the substrate (10) with an atomic force microscope are as shown in Table 1 below.
さらにエッチング後の基板（１０）を第２溶液内に置いてエッチングし、該化学反応層（１０３）を除去し、凹部（１０４）と凸部（１０５）を具えた不規則幾何形状を基板（１０）の切削線領域（１０２）表面に形成する。
該第２溶液は酸性溶液グループ、アルカリ性溶液グループの少なくとも一つの材料、或いはそのグループの組合せのいずれかとする。
該酸性溶液グループは、フッ化水素、硫酸、塩酸、りん酸、硝酸、王水、バッファードオキサイドエッチャント、アルミニウムエッチャント、過酸化水素、ぎ酸、酢酸、こはく酸及びクエン酸を包含する。
該アルカリ性溶液グループは、水酸化カリウム、水酸化ナトリウム、水酸化カルシウム、水酸化アンモニウム、テトラメチルアンモニウムヒドロキサイドを包含する。
該基板（１０）を第２溶液に置く時間は１秒から２００分間とする。
該第２溶液をりん酸（Ｈ3 ＰＯ4 ）とする場合を例として説明すると、該りん酸（Ｈ3ＰＯ4 ）の温度は摂氏２５度〜４００度、該基板（１０）を該第２溶液に置く時間は１秒から２００分間とし、該化学反応層（１０３）を除去してきれいにする。その後、該鈍化層（１１）を除去し、該基板（１０）の表面をクリーニングし、該基板（１０）の素子領域（１０１）表面の平坦性を維持する。
Further, the etched substrate (10) is placed in the second solution for etching, the chemical reaction layer (103) is removed, and an irregular geometric shape having a concave portion (104) and a convex portion (105) is formed on the substrate ( 10) on the surface of the cutting line region (102).
The second solution is either an acidic solution group, at least one material of an alkaline solution group, or a combination of the groups.
The acidic solution group includes hydrogen fluoride, sulfuric acid, hydrochloric acid, phosphoric acid, nitric acid, aqua regia, buffered oxide etchant, aluminum etchant, hydrogen peroxide, formic acid, acetic acid, succinic acid and citric acid.
The alkaline solution group includes potassium hydroxide, sodium hydroxide, calcium hydroxide, ammonium hydroxide, tetramethylammonium hydroxide.
The time for placing the substrate (10) on the second solution is 1 second to 200 minutes.
The case where the second solution is phosphoric acid (H 3 PO 4 ) will be described as an example. The temperature of the phosphoric acid (H 3 PO 4 ) is 25 ° C. to 400 ° C., and the substrate (10) is The time for placing in the solution is from 1 second to 200 minutes, and the chemical reaction layer (103) is removed and cleaned. Thereafter, the blunt layer (11) is removed, the surface of the substrate (10) is cleaned, and the flatness of the surface of the element region (101) of the substrate (10) is maintained.
最後に該基板（１０）の素子領域（１０１）表面に発光ダイオードの半導体発光構造（２０）を形成する。該半導体発光構造（２０）は少なくとも一つのｎ型半導体層（２１）、活性層（２２）及び少なくとも一つのｐ型半導体層（２３）を順にエピタキシャル成長させてなり、該活性層（２２）は発光領域として該ｎ型半導体層（２１）と該ｐ型半導体層（２３）の間に形成する（図４）。該半導体層構造（２０）は該基板（１０）の素子領域（１０１）の表面でその平坦性を維持し、該切削線領域（１０２）の表面の半導体層構造（２０）（ｎ型半導体層（２１）、活性層（２２）、ｐ型半導体層（２３））のエピタキシャル成長の後、該凹部（１０４）と凸部（１０５）の不規則幾何形状により凹凸が不平坦の各層を形成し、これにより複数の半導体層凹部（２０４）と半導体層凸部（２０５）を形成する。 Finally, a semiconductor light emitting structure (20) of a light emitting diode is formed on the surface of the element region (101) of the substrate (10). The semiconductor light emitting structure (20) is formed by epitaxially growing at least one n-type semiconductor layer (21), an active layer (22) and at least one p-type semiconductor layer (23) in order, and the active layer (22) emits light. A region is formed between the n-type semiconductor layer (21) and the p-type semiconductor layer (23) (FIG. 4). The semiconductor layer structure (20) maintains its flatness on the surface of the element region (101) of the substrate (10), and the semiconductor layer structure (20) (n-type semiconductor layer on the surface of the cutting line region (102)). (21) After the epitaxial growth of the active layer (22) and the p-type semiconductor layer (23)), the irregularities of the concave portion (104) and the convex portion (105) are used to form irregular layers. Thereby, a plurality of semiconductor layer concave portions (204) and semiconductor layer convex portions (205) are formed.
最後に、リソグラフィー工程により、該素子領域（１０１）上の半導体層構造（２０）に発光ダイオード素子（３０）を形成させる。すなわち、該素子領域（１０１）上の半導体層構造（２０）上の該ｐ型半導体層（２３）とｐ型オームコンタクト電極（３２）を電気的に接続し、該ｎ型半導体層（２１）にコンタクトウインドウを通してｎ型オームコンタクト電極（３１）を電気的に接続し、該発光ダイオード素子（３０）に順方向バイアスを提供する。該切削線領域（１０２）の半導体層構造（２０）を該ｎ型半導体層（２１）までエッチングし、且つ該ｎ型半導体層（２１）の表面に、複数の、半導体層凹部（２１４）と半導体層凸部（２１５）を具備させる。 Finally, a light emitting diode element (30) is formed in the semiconductor layer structure (20) on the element region (101) by a lithography process. That is, the p-type semiconductor layer (23) on the semiconductor layer structure (20) on the element region (101) and the p-type ohmic contact electrode (32) are electrically connected, and the n-type semiconductor layer (21). The n-type ohmic contact electrode (31) is electrically connected to the light emitting diode element (30) through a contact window to provide a forward bias. The semiconductor layer structure (20) in the cutting line region (102) is etched to the n-type semiconductor layer (21), and a plurality of semiconductor layer recesses (214) are formed on the surface of the n-type semiconductor layer (21). A semiconductor layer convex portion (215) is provided.
該凹部（１０４）、凸部（１０５）、半導体層凹部（２１４）と半導体層凸部（２１５）の構造により、該半導体層構造（２０）内部の活性層（２２）の発射する光は、該基板（１０）上の凹部（１０４）と凸部（１０５）構造、及び該ｎ型半導体層（２１）上の半導体層凹部（２１４）と半導体層凸部（２１５）の構造により、散乱或いは回折し、全反射の確率が減り、該基板（１０）の上方或いは下方に向かう光束が増加し、発光ダイオード３０の光取出し効率が増し、総発光量が増す。
Due to the structure of the concave portion (104), the convex portion (105), the semiconductor layer concave portion (214) and the semiconductor layer convex portion (215), the light emitted from the active layer (22) inside the semiconductor layer structure (20) is Depending on the structure of the recesses (104) and protrusions (105) on the substrate (10) and the structure of the semiconductor layer recesses (214) and semiconductor layer protrusions (215) on the n-type semiconductor layer (21), scattering or The probability of total reflection is reduced, the luminous flux directed upward or downward of the substrate (10) is increased, the light extraction efficiency of the
上述の方法で形成した発光ダイオードの構造は、基板（１０）であって、該基板（１０）の表面が素子領域（１０１）と切削線領域（１０２）に分けられ、且つ切削線領域（１０２）の表面に凹部（１０４）と凸部（１０５）を具えた不規則幾何形状が形成された、上記基板（１０）と、半導体層構造（２０）であって、該基板（１０）の表面の素子領域（１０１）と切削線領域（１０２）にエピタキシャル成長技術を利用して形成され、且つ該切削線領域（１０２）上の該半導体層構造（２０）の表面に複数の半導体層凹部（２０４）と半導体層凸部（２０５）が形成され、更にリソグラフィー工程により、素子領域（１０１）上の半導体層構造（２０）が該発光ダイオード素子（３０）を形成し、該切削線領域（１０２）の半導体層構造（２０）が該ｎ型半導体層（２１）までエッチングされ、且つ該ｎ型半導体層（２１）表面に複数の半導体層凹部（２１４）と半導体層凸部（２１５）を具備する、上記半導体層構造（２０）と、を包含する。 The structure of the light emitting diode formed by the above-described method is a substrate (10), and the surface of the substrate (10) is divided into an element region (101) and a cutting line region (102), and the cutting line region (102 ) On the surface of the substrate (10) and the semiconductor layer structure (20), the surface of the substrate (10) having an irregular geometric shape having concave portions (104) and convex portions (105). The element region (101) and the cutting line region (102) are formed using an epitaxial growth technique, and a plurality of semiconductor layer recesses (204) are formed on the surface of the semiconductor layer structure (20) on the cutting line region (102). ) And a semiconductor layer protrusion (205) are formed, and the semiconductor layer structure (20) on the element region (101) forms the light emitting diode element (30) by a lithography process, and the cutting line region (102) Semiconductor layer structure 20) is etched to the n-type semiconductor layer (21), and has a plurality of semiconductor layer recesses (214) and semiconductor layer protrusions (215) on the surface of the n-type semiconductor layer (21). (20).
本発明の精神は、切削線領域（１０２）の表面に化学反応層（１０３）を形成し、その後、選択性エッチングにより、該基板（１０）の切削線領域（１０２）の表面を凹部（１０４）と凸部（１０５）を具えた構造とし、更にエピタキシャル成長技術を利用し、切削線上の半導体層表面に不規則な凹凸幾何形状を形成する。これら凹部（１０４）と凸部（１０５）構造と、これら半導体層凹部（２１４）と半導体層凸部（２１５）により、該発光ダイオード素子（３０）内部の光はこれら凹部（１０４）、凸部（１０５）、半導体層凹部（２１４）と半導体層凸部（２１５）部分で散乱、回折効果を発生し、該ｎ型半導体層（２１）と該基板（１０）の界面中の光の横方向伝播の状況を減らし、全反射の確率を減らし、該発光ダイオード素子（３０）の光取出し効率を高める。 The spirit of the present invention is that a chemical reaction layer (103) is formed on the surface of the cutting line region (102), and then the surface of the cutting line region (102) of the substrate (10) is recessed (104) by selective etching. ) And protrusions (105), and an irregular growth geometry is formed on the surface of the semiconductor layer on the cutting line by using an epitaxial growth technique. Due to the concave portion (104) and the convex portion (105) structure, and the semiconductor layer concave portion (214) and the semiconductor layer convex portion (215), the light inside the light emitting diode element (30) is reflected by the concave portion (104) and the convex portion. (105) Scattering and diffraction effects are generated in the semiconductor layer concave portion (214) and the semiconductor layer convex portion (215), and the lateral direction of light in the interface between the n-type semiconductor layer (21) and the substrate (10) The propagation situation is reduced, the probability of total reflection is reduced, and the light extraction efficiency of the light emitting diode element (30) is increased.
以上の実施例は本発明の範囲を限定するものではなく、本発明に基づきなし得る細部の修飾或いは変更はいずれも本発明の請求範囲に属するものとする。 The above embodiments do not limit the scope of the present invention, and any modification or change in detail that can be made based on the present invention shall fall within the scope of the claims of the present invention.
１０ 基板 １１ 鈍化層
１０３ 化学反応層
１０１ 素子領域 １０２ 切削線領域
１０４ 凹部 １０５ 凸部
２０４ 半導体層凹部 ２０５ 半導体層凸部
２０ 半導体層構造 ３０発光ダイオード素子
２１４ 半導体層凹部 ２１５ 半導体層凸部
DESCRIPTION OF
Claims (12)
基板（１０）を提供し、その表面に鈍化層（１１）を成長させ、並びに該鈍化層（１１）をパターン化し、該鈍化層（１１）に被覆される素子領域（１０１）と該基板（１０）表面に露出する切削線領域（１０２）を画定する工程、
該基板（１０）を第１溶液内に置いて反応させ、該切削線領域（１０２）の露出した基板（１０）表面に高密度の化学反応層（１０３）を形成する工程、
その後、該鈍化層（１１）と該化学反応層（１０３）をマスクとし、該基板（１０）の切削線領域（１０２）に対して選択性エッチングを行い、該切削線領域（１０２）において該化学反応層（１０３）のない部分の複数の凹部（１０４）と上方に該化学反応層（１０３）を有する凸部（１０５）を形成する工程、
更に該基板（１０）を第２溶液内に置いてエッチングし、該化学反応層（１０３）を除去し、該基板（１０）の切削線領域（１０２）表面に凹部（１０４）と凸部（１０５）を具えた不規則幾何形状を形成する工程、
該鈍化層（１１）を除去し、且つ該基板（１０）表面をクリーニングする工程、
該基板（１０）の表面の素子領域（１０１）と切削線領域（１０２）にエピタキシャル成長技術を利用して、半導体層構造（２０）を成長させ、且つ該切削線領域（１０２）上の半導体層構造（２０）の表面に、複数の半導体層凹部（２０４）と半導体層凸部（２０５）を具備させる工程、
リソグラフィー工程により、素子領域（１０１）上の半導体層構造（２０）に発光ダイオード素子（３０）を形成させる工程、
を包含したことを特徴とする、発光ダイオードの製造方法。 In the method of manufacturing a light emitting diode,
A substrate (10) is provided, a blunt layer (11) is grown on the surface, and the blunt layer (11) is patterned, and an element region (101) covered with the blunt layer (11) and the substrate ( 10) defining a cutting line area (102) exposed on the surface;
Placing the substrate (10) in a first solution and reacting to form a high-density chemical reaction layer (103) on the exposed substrate (10) surface of the cutting line region (102);
Thereafter, selective etching is performed on the cutting line region (102) of the substrate (10) using the blunt layer (11) and the chemical reaction layer (103) as a mask, and the cutting line region (102) Forming a plurality of concave portions (104) in a portion without the chemical reaction layer (103) and a convex portion (105) having the chemical reaction layer (103) above;
Further, the substrate (10) is placed in the second solution and etched to remove the chemical reaction layer (103), and a concave portion (104) and a convex portion (on the surface of the cutting line region (102) of the substrate (10) ( 105) forming an irregular geometry comprising
Removing the blunt layer (11) and cleaning the surface of the substrate (10);
A semiconductor layer structure (20) is grown on the element region (101) and the cutting line region (102) on the surface of the substrate (10) by using an epitaxial growth technique, and the semiconductor layer on the cutting line region (102) is formed. Providing a plurality of semiconductor layer recesses (204) and semiconductor layer protrusions (205) on the surface of the structure (20);
Forming a light emitting diode element (30) in the semiconductor layer structure (20) on the element region (101) by a lithography process;
A method for producing a light emitting diode, comprising:
基板（１０）であって、該基板（１０）の表面が素子領域（１０１）と切削線領域（１０２）に分けられ、且つ切削線領域（１０２）表面に複数の凹部（１０４）と凸部（１０５）を具えた不規則幾何形状が形成された、上記基板（１０）と、
発光ダイオード素子（３０）であって、エピタキシャル成長技術を利用し、半導体層構造（２０）が該基板（１０）表面の素子領域（１０１）と切削線領域（１０２）に形成され、且つ該切削線領域（１０２）上の該半導体層構造（２０）が複数の半導体層凹部（２０４）と半導体層凸部（２０５）を具え、更にリソグラフィー工程によって、素子領域（１０１）上の半導体層構造（２０）で該発光ダイオード素子（３０）が形成された、上記発光ダイオード素子（３０）と、
を包含し、
該半導体発光構造（２０）は、少なくとも一つのｎ型半導体層（２１）、活性層（２２）、及び少なくとも一つのｐ型半導体層（２３）を順にエピタキシャル成長させて形成され、そのうち、該活性層（２２）は発光領域とされ該ｎ型半導体層（２１）と該ｐ型半導体層（２３）の間に形成され、且つリソグラフィー工程により、該ｐ型半導体層（２３）がｐ型オームコンタクト電極（３２）と電気的に接続され、該ｎ型半導体層（２１）にｎ型オームコンタクト電極（３１）が電気的に接続され該発光ダイオード素子（３０）に順方向バイアスが提供され、該切削線領域（１０２）が該ｎ型半導体層（２１）までエッチングされ、且つ該ｎ型半導体層（２１）表面に複数の半導体層凹部（２１４）と半導体層凸部（２１５）を具備することを特徴とする、発光ダイオードの構造。 In the structure of light emitting diode,
A surface of the substrate (10) is divided into an element region (101) and a cutting line region (102), and a plurality of concave portions (104) and convex portions are formed on the surface of the cutting line region (102). The substrate (10) formed with an irregular geometry comprising (105);
A light emitting diode element (30), using an epitaxial growth technique, a semiconductor layer structure (20) is formed in an element region (101) and a cutting line region (102) on the surface of the substrate (10), and the cutting line The semiconductor layer structure (20) on the region (102) includes a plurality of semiconductor layer concave portions (204) and semiconductor layer convex portions (205), and further, a semiconductor layer structure (20 on the element region (101) is formed by a lithography process. The light-emitting diode element (30) in which the light-emitting diode element (30) is formed,
It encompasses,
The semiconductor light emitting structure (20) is formed by epitaxially growing at least one n-type semiconductor layer (21), an active layer (22), and at least one p-type semiconductor layer (23) in order, of which the active layer (22) is a light emitting region, formed between the n-type semiconductor layer (21) and the p-type semiconductor layer (23), and the p-type semiconductor layer (23) is formed into a p-type ohmic contact electrode by a lithography process. The n-type ohmic contact electrode (31) is electrically connected to the n-type semiconductor layer (21), and a forward bias is provided to the light emitting diode element (30). The line region (102) is etched to the n-type semiconductor layer (21), and a plurality of semiconductor layer concave portions (214) and semiconductor layer convex portions (215) are provided on the surface of the n-type semiconductor layer (21). It characterized the structure of a light emitting diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007284034A JP4804444B2 (en) | 2007-10-31 | 2007-10-31 | Structure of light emitting diode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007284034A JP4804444B2 (en) | 2007-10-31 | 2007-10-31 | Structure of light emitting diode and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009111269A JP2009111269A (en) | 2009-05-21 |
| JP4804444B2 true JP4804444B2 (en) | 2011-11-02 |
Family
ID=40779423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007284034A Expired - Fee Related JP4804444B2 (en) | 2007-10-31 | 2007-10-31 | Structure of light emitting diode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4804444B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882659A (en) * | 2010-06-28 | 2010-11-10 | 亚威朗光电(中国)有限公司 | Light-emitting diode chip and method for manufacturing same |
| JP5921091B2 (en) * | 2011-06-03 | 2016-05-24 | 林純薬工業株式会社 | Etching solution composition and etching method |
| CN103378221B (en) * | 2012-04-20 | 2016-06-29 | 东莞市中镓半导体科技有限公司 | A kind of method preparing graphic sapphire substrate for GaN growth |
| KR102013363B1 (en) * | 2012-11-09 | 2019-08-22 | 서울바이오시스 주식회사 | Light emitting device and method of fabricating the same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003197961A (en) * | 2001-12-27 | 2003-07-11 | Toyoda Gosei Co Ltd | Group iii nitride-based compound semiconductor light emitting element |
| JP4201079B2 (en) * | 2002-12-20 | 2008-12-24 | 昭和電工株式会社 | LIGHT EMITTING ELEMENT, MANUFACTURING METHOD THEREOF, AND LED LAMP |
| JP2005354020A (en) * | 2004-05-10 | 2005-12-22 | Univ Meijo | Semiconductor light-emitting device manufacturing method and semiconductor light-emitting device |
| JP2007266577A (en) * | 2006-03-03 | 2007-10-11 | Matsushita Electric Ind Co Ltd | Nitride semiconductor device and manufacturing method thereof |
| KR100828873B1 (en) * | 2006-04-25 | 2008-05-09 | 엘지이노텍 주식회사 | Nitride semiconductor LED and fabrication method thereof |
| JP4957130B2 (en) * | 2006-09-06 | 2012-06-20 | 日立電線株式会社 | Light emitting diode |
| DE102006043400A1 (en) * | 2006-09-15 | 2008-03-27 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor chip |
| JP5176334B2 (en) * | 2007-02-01 | 2013-04-03 | 日亜化学工業株式会社 | Semiconductor light emitting device |
| JP4799528B2 (en) * | 2007-10-31 | 2011-10-26 | 泰谷光電科技股▲ふん▼有限公司 | Structure of light emitting diode and manufacturing method thereof |
-
2007
- 2007-10-31 JP JP2007284034A patent/JP4804444B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009111269A (en) | 2009-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7713769B2 (en) | Method for fabricating light emitting diode structure having irregular serrations | |
| US9082934B2 (en) | Semiconductor optoelectronic structure with increased light extraction efficiency | |
| US7598105B2 (en) | Light emitting diode structure and method for fabricating the same | |
| JP5570697B2 (en) | LED using substrate modification to improve light extraction and method of making the same | |
| EP1983581B1 (en) | Method of fabricating a light emitting diode having improved external light extraction | |
| EP1858090A2 (en) | Light emitting diode having multi-pattern structure | |
| US20140319536A1 (en) | Solid state lighting devices with cellular arrays and associated methods of manufacturing | |
| CN101414653B (en) | LED structure and manufacturing method thereof | |
| JP2008072126A (en) | Optoelectronic semiconductor chip | |
| JP2007168066A (en) | Manufacturing method of substrate with nanostructure formed thereon, light emitting element, and its manufacturing method | |
| JP2012114407A (en) | Method for fabricating vertical light emitting devices and substrate module for the same | |
| JP2012142580A (en) | Method for fabricating light emitting diode chip | |
| JP4804444B2 (en) | Structure of light emitting diode and manufacturing method thereof | |
| CN102255010B (en) | Manufacturing method of gallium nitride light-emitting diode | |
| WO2010021212A1 (en) | Light emitting element, and method for manufacturing the element | |
| KR100593941B1 (en) | Method for manufacturing iii-nitride light emitting device | |
| CN101420003B (en) | Manufacturing method for LED | |
| JP4799528B2 (en) | Structure of light emitting diode and manufacturing method thereof | |
| TW200913311A (en) | A structure of LED and its manufacturing method | |
| JP2009076647A (en) | Manufacturing method of light emitting diode element | |
| JP6724687B2 (en) | Nanorod forming method and semiconductor device manufacturing method | |
| TWI384643B (en) | Manufacturing method of light emitting diode structure | |
| CN102306693A (en) | Graphical nitride-based luminescent epitaxial wafer and luminescent chip, and manufacturing methods thereof | |
| KR20090002313A (en) | Semiconductor light emitting device and method of manufacturing the same | |
| TWI407594B (en) | Method for making light emitting diode chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100831 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101129 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110726 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110809 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4804444 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140819 Year of fee payment: 3 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |