JP4802258B2 - Voltage detection circuit - Google Patents

Description

  The present invention relates to a voltage detection circuit that detects a voltage of an accumulated charge potential with a small consumption current of nA (nanoampere) or less in a system that accumulates a very small amount of natural energy as electric energy.

  To realize a ubiquitous information society, research and development of sensor networks using a large number of information transmission terminals equipped with sensors is progressing. These information transmission terminals are required to be maintenance-free. One of the problems is that the information transmission terminal itself has a generator and eliminates the need for a battery. The generator mounted on such an information transmission terminal converts living space energy such as vibration and heat into electric energy, and the generator is minimized as the information transmission terminal is miniaturized. For this reason, there is a need for a technique for efficiently storing electric charges from a small amount of generated power of nA class.

  In order to store minute electric power from such a generator, it is necessary to detect the accumulated charge potential with a small current consumption. For this reason, conventionally, a low-power reference voltage circuit using the body effect of the MOS transistor shown in FIG. 7 has been used (Non-Patent Document 1).

Jun Pan, et.al, “A low-power sub-1-V low-voltage reference using body effect,” IEICE Trans. Fundamentals, (2007) pp.748-755.

  In the reference voltage circuit shown in FIG. 7, a current of about 1 μA is consumed to operate all the transistors near the threshold voltage. For this reason, there has been a problem that electric charges are not stored in the power generation by the nA class micro power generator using living space energy.

  An object of the present invention is to provide a voltage detection circuit capable of detecting a voltage of a charge potential of a power storage system that stores charges from an nA class micro power generator with an operating current of nA or less.

  According to a first aspect of the present invention, there is provided a voltage detection circuit comprising: a transistor chain configured by connecting a plurality of diode-connected MOS transistors in series between a first power supply terminal for supplying a power supply voltage and a second power supply terminal; The first current source transistor is configured by connecting the above MOS transistors in series, and the source terminal of the MOS transistor at one end thereof is connected to the first power supply terminal, and the first current source transistor has a different polarity. The above-mentioned MOS transistors are connected in series, the source terminal of the MOS transistor at one end thereof is connected to the second power supply terminal, the source terminals and the gate terminals are connected, and the source A first MOS transistor transistor whose terminal is connected to the drain terminal of the MOS transistor at the other end of the first current source transistor. Are different in polarity from the first transistor pair, the source terminals are connected to each other, the gate terminal and the drain terminal are cross-coupled, and the source terminal is connected to the drain terminal of the MOS transistor at the other end of the second current source transistor. A first current source that connects the drain terminals of the MOS transistors of the first MOS transistor pair and the drain terminals of the MOS transistors of the second MOS transistor pair, respectively, The gate terminal of each MOS transistor of the transistor, the gate terminal of the first MOS transistor pair, and the gate terminal of each MOS transistor of the second current source transistor are divided by the gate potential of each MOS transistor in the transistor chain, respectively. Connect in order of potential generated by The gate terminal and drain terminal of one MOS transistor of the first MOS transistor pair are connected to the first output terminal and the second output terminal, respectively, and the first MOS transistor pair and the second MOS transistor pair The gate width or gate length of at least one MOS transistor pair is different from each other, and the magnitude of the power supply voltage is detected based on the magnitude relationship between the output voltages of the first output terminal and the second output terminal.

  According to a second aspect of the present invention, there is provided a voltage detection circuit comprising: a transistor chain configured by connecting a plurality of diode-connected MOS transistors in series between a first power supply terminal for supplying a power supply voltage and a second power supply terminal; The current source transistor is configured by connecting the above MOS transistors in series, the source terminal of the MOS transistor at one end thereof is connected to the first power supply terminal, the source terminals and the gate terminals are connected, and the source terminal is the current. The first MOS transistor pair connected to the drain of the MOS transistor at the other end of the source transistor and the first transistor pair have different polarities, the source terminals are connected, and the gate terminal and the drain terminal are cross-coupled. A second MOS transistor pair having a source terminal connected to a second power supply terminal, The drain terminal of each MOS transistor of the MOS transistor pair is connected to the drain terminal of each MOS transistor of the second MOS transistor pair, and the gate terminal of each MOS transistor of the current source transistor and the gate terminal of the first MOS transistor pair are Are connected to the gate terminal of each MOS transistor of the transistor chain in the order of potentials generated by dividing the power supply potential, and the gate terminal and drain terminal of one MOS transistor of the first MOS transistor pair are respectively connected to the first output terminal. And at least one of the first MOS transistor pair and the second MOS transistor pair is different in gate width or gate length from each other, and the first output terminal and the second output terminal are connected to the second output terminal. Output terminal The magnitude of the force voltage is configured to detect the magnitude of the power supply voltage.

  In the voltage detection circuit of the first invention, at least one set of MOS transistors of which the gate terminals are connected among the MOS transistors of the transistor chain and the first current source transistor and the second current source transistor. Detection voltage setting switch MOS transistors that are connected in parallel and set a power supply voltage to be detected by switching between conduction and non-conduction according to a control signal are provided.

  In the voltage detection circuit of the second invention, the MOS transistors of the transistor chain and the current source transistor are connected in parallel to at least one set of MOS transistors whose gate terminals are connected to each other, and are made conductive by a control signal. Alternatively, a detection voltage setting switch MOS transistor for setting a power supply voltage to be detected by switching non-conduction is provided.

  The voltage detection circuit of the present invention can detect the charge potential of a power storage system that accumulates charges from a minimal power generator having a power generation amount of about nA or less with an operating current of nA or less.

It is a figure which shows the circuit structural example of Example 1 of this invention. It is a figure which shows the output voltage characteristic of output terminal OUT1, OUT2 of Example 1 of this invention. It is a figure which shows the circuit structural example of Example 2 of this invention. It is a figure which shows the circuit structural example of Example 3 of this invention. It is a figure which shows the circuit structural example of Example 4 of this invention. It is a figure which shows the structural example of the electrical storage system using the voltage detection circuit of this invention. It is a figure which shows the structural example of the low power reference voltage circuit using the body effect of a MOS transistor.

FIG. 1 shows a circuit configuration example of Embodiment 1 of the present invention.
In the figure, diode-connected pMOS transistors mpb1 to mpb6 and nMOS transistors mnb7 to mnb9 are connected in series between a power supply potential Vdd and a ground potential Vss to divide the power supply voltage. The gate terminals of the pMOS transistors mpb1 to mpb3 and the nMOS transistors mnb7 to mnb9 are respectively connected to the current source pMOS transistors mpc1 to mpc3 connected in series to the power supply potential Vdd and the current source nMOS transistors mnc4 to mnc6 connected in series to the ground potential Vss. Each potential connected to the gate terminal and generated by dividing the power supply voltage is input to each current source transistor.

  In the pMOS transistor pair mp41, mp42, the source terminals and the gate terminals are connected, the source terminal is connected to the drain terminal of the current source pMOS transistor mpc3, and the gate terminal is connected to the gate terminal of the pMOS transistor mpb4. In the nMOS transistor pair mn41, mn42, the source terminals are connected to each other, the gate terminal and the drain terminal are cross-coupled, and the source terminal is connected to the drain terminal of the current source nMOS transistor mnc4.

  The pMOS transistor pair mp41, mp42 shunts the current from the current source pMOS transistors mpc1 to mpc3 into two, and the cross-coupled nMOS transistor pair mn41, mn42 converts the shunted current into a potential. The output terminal OUT1 is connected to the gate terminal of the pMOS transistor mp41 (pMOS transistor mp42), and the output terminal OUT2 is connected to the drain terminal of the pMOS transistor mp41 (nMOS transistor mn41) (the gate terminal of the nMOS transistor mn42).

Here, regarding the gate width or gate length (gate size) of the pMOS transistor pair mp41, mp42 and the nMOS transistor pair mn41, mn42, mp41 <mp42 and / or mn41> mn42
Set to be. For example, the gate widths of the pMOS transistor pairs mp41 and mp42 are set to 1 to 2.

FIG. 2 shows output voltage characteristics of the output terminals OUT1 and OUT2 according to the first embodiment of the present invention.
When the power supply voltage Vdd is small and the current source pMOS transistors mpc1 to mpc3 and the current source nMOS transistors mnc4 to mnc6 are in the OFF state, the gate potential of each transistor becomes a potential obtained by dividing the power supply potential by the parasitic capacitance of the transistor. Therefore, OUT1> OUT2 is held. Furthermore, when the power supply voltage increases and exceeds a predetermined value (for example, 3.5 V), a current of about 0.1 nA starts to flow through the current source pMOS transistors mpc1 to mpc3. At this time, the gate sizes of the pMOS transistor pair mp41, mp42 and the nMOS transistor pair mn41, mn42 are mp41 <mp42 and / or mn41> mn42.
Therefore, the potential of the output terminal OUT2 changes abruptly and OUT1 <OUT2. Conversely, when the power supply voltage becomes smaller than the predetermined value, the potential relationship returns to OUT1> OUT2 immediately after the current source pMOS transistors mpc1 to mpc3 are turned off.

  Therefore, the magnitude of the power supply voltage can be detected from the magnitude relationship between the output voltages of the output terminals OUT1 and OUT2. Note that when the position of the output terminal OUT2 is changed, it is clear from the symmetry of the circuit that the size relationship of the unevenness of the gate size may be reversed.

  In the first embodiment, an example in which three current source pMOS transistors mpc1 to mpc3 and three current source nMOS transistors mnc4 to mnc6 are connected in series is shown.

  In the first embodiment, nine diode-connected transistors are used for six current source transistors, but the number of diode-connected transistors may be two or more than the current source transistors. Further, when the number of diode-connected transistors is increased, the voltage applied to each transistor is reduced, so that the power supply potential at which current flows through the MOS transistor pair is increased. That is, the detection voltage value increases.

FIG. 3 shows a circuit configuration example of the second embodiment of the present invention.
In the figure, diode-connected pMOS transistors mpb1 to mpb9 are connected in series between a power supply potential Vdd and a ground potential Vss to divide the power supply voltage. The gate terminals of the pMOS transistors mpb1 to mpb6 are connected to the gate terminals of the current source pMOS transistors mpc1 to mpc6 connected in series to the power supply potential Vdd. Is input.

  In the pMOS transistor pair mp41, mp42, the source terminals and the gate terminals are connected to each other, the source terminal is connected to the drain terminal of the current source pMOS transistor mpc6, and the gate terminal is connected to the gate terminal of the pMOS transistor mpb7. In the nMOS transistor pair mn41, mn42, the source terminals are connected to each other, the gate terminal and the drain terminal are cross-coupled, and the source terminal is connected to the ground potential Vss.

  The pMOS transistor pair mp41, mp42 shunts the current from the current source pMOS transistors mpc1 to mpc6 into two, and the cross-coupled nMOS transistor pair mn41, mn42 converts the shunted current into a potential. The output terminal OUT1 is connected to the gate terminal of the pMOS transistor mp41 (pMOS transistor mp42), and the output terminal OUT2 is connected to the drain terminal of the pMOS transistor mp41 (nMOS transistor mn41) (the gate terminal of the nMOS transistor mn42).

  Here, the gate width or the gate length of the pMOS transistor pair mp41, mp42 or the nMOS transistor pair mn41, mn42 is set to be different from each other.

  Since the voltage detection operation in the configuration of the second embodiment is the same as that of the first embodiment and the number of diode-connected transistors is the same, the voltage detection circuit operates as a voltage detection circuit that is completely equivalent to the first embodiment.

FIG. 4 shows a circuit configuration example of the voltage detection circuit according to the third embodiment of the present invention.
In the third embodiment, all the pMOS transistors in the first embodiment are replaced with nMOS transistors, all the nMOS transistors are replaced with pMOS transistors, and the power supply potential and the ground potential are switched. The voltage detection operation in the configuration of the third embodiment is the same as that of the first embodiment. Similarly, all pMOS transistors in the second embodiment may be replaced with nMOS transistors, and all nMOS transistors may be replaced with pMOS transistors.

FIG. 5 shows a circuit configuration example of the voltage detection circuit according to the fourth embodiment of the present invention.
The detection voltage value of the voltage detection circuit of each embodiment described above is affected by transistor threshold value variation. For this reason, in order to set to a predetermined detection voltage value, it is set as the structure which can increase / decrease the number of a diode connection transistor and a corresponding current source transistor. Here, the example applied to the structure of Example 1 is shown.

  In the figure, detection voltage setting switch nMOS transistors mn1 to mn6 are connected in parallel to diode-connected pMOS transistors mnb7 to mnb9 and current source nMOS transistors mnc4 to mnc6, respectively. The gate terminals of the detection voltage setting switch nMOS transistors mn1 and mn4 are connected to the switch terminal sw1, the gate terminals of the detection voltage setting switch nMOS transistors mn2 and mn5 are connected to the switch terminal sw2, and the detection voltage setting switch nMOS transistors mn3 and mn6 are connected. The gate terminal is connected to the switch terminal sw3. By setting the switch terminals sw1 to sw3 to the power supply potential or the ground potential, the corresponding detection voltage setting switch nMOS transistor is turned on or off.

  When the detection voltage setting switch nMOS transistor is turned on, the voltage between the source and drain of the transistor becomes zero, and the number of transistors connected in series decreases. Therefore, since the voltage applied to each transistor connected in series increases, the power supply potential at which current flows through the MOS transistor pair decreases. That is, the detection voltage value can be reduced by increasing the ON setting number of the detection voltage setting switch nMOS transistors by the switch terminals sw1 to sw3, and the detection voltage value can be increased by increasing the OFF setting number.

  Such a detection voltage setting switch transistor is not limited to an nMOS transistor but may be a pMOS transistor or an nMOS transistor and a pMOS transistor.

  In addition, the detection voltage setting switch transistor is not limited to between the cross-coupled nMOS transistor pair mn41 and mn42 and the ground potential Vss, but may be inserted between the pMOS transistor pair mp41 and mp42 and the power supply potential Vdd. The same applies to the circuit configuration examples of the second embodiment shown in FIG. 3 and the third embodiment shown in FIG.

FIG. 6 shows a configuration example of a power storage system using the voltage detection circuit of the present invention.
In the figure, the nA class generator 11 converts energy existing in a living space such as vibration, heat, and light into electrical energy. Here, since the nA class generator 11 converts minute living space energy into electric energy, its output is not a voltage type but a current type. For example, it is an alternating current generator that converts the vibration of an electret created by MEMS technology or the like into a current. The alternating current generator has a size of several hundred micrometers to several centimeters, and generates an alternating current of about 1 nA to several hundred nA depending on the size.

  The output of the nA class generator 11 is connected to the charge storage capacitor 13 via the rectifier diode 12, the charge is gradually stored in the charge storage capacitor 13, and the stored voltage is shown in the first to fourth embodiments. Is detected by the voltage detection circuit 14. The voltage at the output terminals OUT1 and OUT2 of the voltage detection circuit 14 is input to the hysteresis comparator 15. When the predetermined detection voltage is reached, the hysteresis comparator 15 controls the switch 16, and power is supplied to the driven circuit 17 via the switch 16. Is done. Here, the hysteresis comparator 15 also needs to operate at a lower power than the output power of the nA class generator 11. Therefore, the hysteresis comparator 15 is configured to operate in the subthreshold region. The current consumption of the voltage detection circuit 14 and the hysteresis comparator 15 operating in such a subthreshold region is 1 nA or less in total.

  Since the voltage detection circuit of the present invention can detect a voltage with an operating current of nA or less, it is possible to realize a power storage system that efficiently accumulates charges from a minimal power generator with a power generation amount of about nA or less.

mp pMOS transistor mn nMOS transistor 11 nA class generator 12 rectifier diode 13 charge storage capacitor 14 voltage detection circuit 15 hysteresis comparator 16 switch 17 driven circuit

Claims (4)

A transistor chain configured by connecting a plurality of diode-connected MOS transistors in series between a first power supply terminal for supplying a power supply voltage and a second power supply terminal;
A first current source transistor configured by connecting one or more MOS transistors in series, the source terminal of the MOS transistor at one end thereof being connected to the first power supply terminal;
The second current source transistor is configured by connecting in series one or more MOS transistors having different polarities from the first current source transistor, and the source terminal of the MOS transistor at one end thereof is connected to the second power source terminal. When,
A first MOS transistor pair in which source terminals and gate terminals are connected, and a source terminal is connected to a drain terminal of a MOS transistor at the other end of the first current source transistor;
The polarity of the first transistor pair is different, the source terminals are connected to each other, the gate terminal and the drain terminal are cross-coupled, and the source terminal is connected to the drain terminal of the MOS transistor at the other end of the second current source transistor. A second MOS transistor pair connected,
Connecting the drain terminal of each MOS transistor of the first MOS transistor pair and the drain terminal of each MOS transistor of the second MOS transistor pair;
The gate terminal of each MOS transistor of the first current source transistor, the gate terminal of the first MOS transistor pair, and the gate terminal of each MOS transistor of the second current source transistor are respectively MOS transistors of the transistor chain. Connected to the gate terminal of the power supply in the order of potentials generated by dividing the power supply potential,
A gate terminal and a drain terminal of one MOS transistor of the first MOS transistor pair are connected to a first output terminal and a second output terminal, respectively;
The gate width or gate length of at least one of the first MOS transistor pair and the second MOS transistor pair is different from each other, and the output voltages of the first output terminal and the second output terminal are different from each other. A voltage detection circuit characterized in that the magnitude of the power supply voltage is detected based on the magnitude relationship. A transistor chain configured by connecting a plurality of diode-connected MOS transistors in series between a first power supply terminal for supplying a power supply voltage and a second power supply terminal;
A current source transistor configured by connecting one or more MOS transistors in series, the source terminal of the MOS transistor at one end thereof being connected to the first power supply terminal;
A first MOS transistor pair in which the source terminals and the gate terminals are connected, and the source terminal is connected to the drain of the MOS transistor at the other end of the current source transistor;
The second transistor pair has a polarity different from that of the first transistor pair, the source terminals are connected to each other, the gate terminal and the drain terminal are cross-coupled, and the source terminal is connected to the second power supply terminal. With
Connecting the drain terminal of each MOS transistor of the first MOS transistor pair and the drain terminal of each MOS transistor of the second MOS transistor pair;
The gate terminal of each MOS transistor of the current source transistor and the gate terminal of the first MOS transistor pair are respectively connected to the gate terminals of the MOS transistors of the transistor chain in the order of potentials generated by dividing the power supply potential. ,
A gate terminal and a drain terminal of one MOS transistor of the first MOS transistor pair are connected to a first output terminal and a second output terminal, respectively;
The gate width or gate length of at least one of the first MOS transistor pair and the second MOS transistor pair is different from each other, and the output voltages of the first output terminal and the second output terminal are different from each other. A voltage detection circuit characterized in that the magnitude of the power supply voltage is detected based on the magnitude relationship. The voltage detection circuit according to claim 1,
Of the MOS transistors of the transistor chain and the first current source transistor and the second current source transistor, each of the MOS transistors having the gate terminals connected to each other is connected in parallel to each other and controlled in parallel. A voltage detection circuit comprising a detection voltage setting switch MOS transistor for setting a power supply voltage to be detected by switching between conduction and non-conduction according to a signal. The voltage detection circuit according to claim 2,
Of the MOS transistors of the transistor chain and the current source transistor, the MOS transistors are connected in parallel to at least one set of MOS transistors whose gate terminals are connected to each other, and are detected by switching between conduction and non-conduction by a control signal. A voltage detection circuit comprising a detection voltage setting switch MOS transistor for setting a power supply voltage.

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