JP4798117B2 - Semiconductor device and substrate crack detection method - Google Patents

Description

  The present invention relates to a semiconductor device in which a circuit board mounted on a heat sink is sealed with a sealing resin, and a substrate crack detection method for detecting cracks in the circuit board in the semiconductor device.

Conventionally, for example, as disclosed in Patent Document 1, a circuit board and a heat sink on which the circuit board is mounted are provided, and the circuit board and the heat sink are arranged in a mold package formed by resin injection molding. A semiconductor device in which the other surface of the heat sink is exposed from the resin has been proposed.
Japanese Patent Laid-Open No. 2005-328018

  By the way, in the semiconductor device disclosed in Patent Document 1, when forming a mold package, the resin melted and melted is filled in the injection mold while the circuit board and the heat sink are set in the injection mold. . At this time, if the heat sink has warping or surface irregularities, the stress of the resin filled in the injection mold causes a partial stress concentration on the circuit board bonded and fixed to the heat sink. There is a risk of cracking. The crack may cause malfunction of the semiconductor device (for example, leakage). However, in the above configuration, since the circuit board is sealed with resin, it is impossible to confirm cracks (cracking) of the circuit board by visual inspection or the like after forming the mold package.

  On the other hand, the present applicant has proposed in Japanese Patent Application No. 2006-157111 a semiconductor device in which one substrate crack detection wiring pattern for detecting a substrate crack is formed on the surface of a circuit board. When a crack occurs in the wiring pattern for board crack detection (that is, when a crack occurs in the circuit board), the resistance value of the wiring pattern for board crack detection increases significantly. Therefore, by measuring the absolute value of the resistance value of the substrate crack detection wiring pattern, it is possible to detect whether or not the circuit board is cracked.

  However, the resistance value of the circuit board wiring pattern varies greatly due to the influence of manufacturing variations (for example, in the case of screen printing, blurring, film thickness variation, material mixing ratio variation, impurity variation contained in the material, etc.) For example, there is a problem of about ± 20 to 60%. Therefore, in the case of a fine crack that does not break the wiring pattern, it is difficult to determine whether the increase in resistance value is due to a crack or due to manufacturing variations.

  In addition, after the resin that forms the mold package is cured, the compressive stress of the resin acts on the circuit board, and the crack portion of the circuit board is also compressed, so that the resistance value of the wiring pattern for detecting the board cracks The effect of is difficult to appear.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a substrate crack detection method capable of detecting a crack of a circuit board with high accuracy after injection molding.

In order to achieve the above object, the invention according to claim 1 is a circuit board having a wiring pattern, a heat sink on which the circuit board is mounted, and a part of a lead frame, and is electrically connected to the wiring pattern. A semiconductor device comprising: an external connection terminal; at least a part of a heat sink; a connection portion between the external connection terminal and the wiring pattern; and a sealing resin portion that seals the circuit board. , as a wiring pattern, not provide an electrical connection function, a plurality have a crack detection wire pattern for detecting the cracking of the circuit board is mounted on the circuit board, respectively and the ends of the crack detection wire pattern It has a detection circuit to be connected, and the detection circuit has a ratio of measured resistance values of a plurality of crack detection wiring patterns and a resistance value of the plurality of crack detection wiring patterns determined at the time of layout. By taking the difference between the ratio and characterized by detecting whether cracks cracks detection wiring pattern has occurred.

Thus, according to the present invention, a plurality of crack detection wiring patterns are formed on the circuit board mounted on the heat sink. In addition, the detection circuit detects cracks by taking the difference between the ratio of the measured resistance values of the plurality of crack detection wiring patterns and the ratio of the resistance values of the plurality of crack detection wiring patterns determined at the time of layout. It is detected whether or not the wiring pattern is cracked. According to this, it is possible to detect the cracks in the crack detection wiring pattern (circuit board) with high accuracy while suppressing the influence of manufacturing variation of the crack detection wiring pattern. In addition, since the effect of the invention of the new claim 2 is equivalent to the effect of the invention of the claim 1, the description is omitted.

In the invention according to claim 1 or claim 2 , as described in claim 3 , as a plurality of crack detection wiring patterns, one continuous wiring pattern is divided into a plurality of resistance regions, and crack detection is performed. A configuration including a wiring pattern for use may be employed. Further, in the invention described in claim 1 or 2 , as described in claim 4 , the plurality of crack detection wiring patterns are arranged electrically independently from other crack detection wiring patterns. A configuration including a crack detection wiring pattern is also possible.

  In any case, a plurality of crack detection wiring patterns are formed on the circuit board. Therefore, by detecting the resistance values of a plurality of crack detection wiring patterns and comparing the resistance values with each other, the effects of manufacturing variations of the crack detection wiring patterns are suppressed, and crack detection wiring patterns (circuits) are detected. Substrate) can be detected with high accuracy.

In the invention described in claim 3 or claim 4 , as described in claim 5 , as the plurality of crack detection wiring patterns, at least one outer peripheral pattern arranged along the end of the circuit board is provided. It is good to have.

  According to this, since the outer peripheral pattern is arranged along the end of the circuit board, it is possible to detect a crack that occurs at the end of the circuit board. In addition, since a crack is easy to generate | occur | produce in the edge part with weak intensity | strength in a circuit board, most cracks which arise in a circuit board are detectable.

In the invention described in claim 5 , as described in claim 6 , the plurality of crack detection wiring patterns include an outer peripheral pattern and at least one inner peripheral pattern arranged on the inner side of the outer peripheral pattern. It is good also as a structure.

  According to this, the crack which arises in the edge part of a circuit board by an outer periphery pattern can be detected, and the crack which arises inside the outer periphery pattern of a circuit board can also be detected by an inner periphery pattern.

In the invention described in any one of claims 1 to 6 , as described in claim 7 , the heat sink may be configured by a part of the lead frame. According to this, since the heat sink is configured as a part of the lead frame, misalignment between the heat sink (and the circuit board) and the external connection terminal during injection molding can be prevented. In addition, the manufacturing process can be simplified.

In the invention according to any one of claims 1 to 7 , as described in claim 8 , the external connection terminal is connected to the end of the crack detection wiring pattern, and is connected to the sealing resin portion. It is good also as a structure provided with the several terminal for a detection from which a part is exposed.

  According to this, even if the circuit board is sealed by the sealing resin portion, a part of the detection terminal is exposed from the sealing resin portion. Therefore, the plurality of detection terminals can be connected to external detection devices that detect cracks in the circuit board.

In the invention according to any one of claims 1 to 7 , as described in claim 9 , when the detection circuit detects a crack in the crack detection wiring pattern, the circuit board is cracked. Thus, the signal indicating the breakage of the circuit board may be output to the outside via the external connection terminal, and the operation of the circuit unit configured on the circuit board may be stopped.

  According to this, when the detection circuit detects a crack in the circuit board, the operation of the circuit unit configured on the circuit board can be stopped, and an effect as a self-diagnosis function can be expected.

The invention according to claim 10 is a circuit board crack detection method for detecting whether or not a circuit board is cracked in a state where the circuit board mounted on the heat sink is sealed by injection molding of a resin material. Before mounting on the heat sink, do not provide an electrical connection function on the circuit board, and form multiple crack detection wiring patterns in the same process to detect cracks in the circuit board. , The resistance values of the plurality of crack detection wiring patterns are respectively measured, and the ratio of the measured resistance values of the plurality of crack detection wiring patterns to the ratio of the resistance values of the plurality of crack detection wiring patterns determined at the time of layout It is characterized by detecting whether or not a crack has occurred in the crack detection wiring pattern .

Thus, according to the present invention, a plurality of crack detection wiring patterns are formed on the circuit board . In addition, by taking the difference between the ratio of the measured resistance values of the plurality of crack detection wiring patterns and the ratio of the resistance values of the plurality of crack detection wiring patterns determined at the time of layout, the crack detection wiring pattern is cracked. It is detected whether or not the error occurs. According to this, it is possible to detect the cracks in the crack detection wiring pattern (circuit board) with high accuracy while suppressing the influence of manufacturing variation of the crack detection wiring pattern. In addition, since the effect of the invention of the new claim 11 is equivalent to the effect of the invention of claim 10, the description is omitted.

The invention according to claim 1 2, a circuit board mounted on a heat sink, in a state sealed by injection molding of a resin material, there in substrate crack detection method of detecting whether cracks on the circuit board has occurred Before mounting on the heat sink, at least one crack detection wiring pattern for detecting a crack in the circuit board is formed on the circuit board without providing an electrical connection function. In this case, before measuring the resistance value of the crack detection wiring pattern, a current larger than the resistance measurement current is passed through the crack detection wiring pattern.

  As described above, according to the present invention, a crack generated in the circuit board can be grown by flowing a current larger than the resistance measurement current through the crack detection wiring pattern. Therefore, the crack of the circuit board can be detected with higher accuracy by measuring the resistance value after flowing a large current.

The invention according to claim 1 3, a circuit board mounted on a heat sink, in a state sealed by injection molding of a resin material, there in substrate crack detection method of detecting whether cracks on the circuit board has occurred Before mounting on the heat sink, at least one crack detection wiring pattern for detecting a crack in the circuit board is formed on the circuit board without providing an electrical connection function. In the above, the resistance value of the crack detection wiring pattern is measured in a state where the resin material is heated to a degree of softening.

  As described above, according to the present invention, since the resin material is softened by heating, the compressive stress acting on the circuit board from the resin material can be relaxed. That is, the compression state (contact state) of the crack part compressed by the resin material can be loosened. As a result, the effect of cracks is likely to appear in the resistance value of the crack detection wiring pattern, and the cracks in the circuit board can be detected with higher accuracy than in detecting cracks in the circuit board without heating.

In the invention according to claim 1 3, as described in claims 1 to 4, at room temperature state, a state for detecting a resistance value of the crack detection wiring pattern, and heated to the extent that it softens the resin material, cracks The resistance value of the detection wiring pattern may be detected, and the resistance value detected in the room temperature state may be compared with the resistance value detected in the heated state.

  In this way, in the same crack detection wiring pattern, by comparing the resistance values detected before and after heating with each other, the influence of manufacturing variation is suppressed, and cracks in the crack detection wiring pattern (circuit board) are suppressed. It can be detected with high accuracy. That is, it is possible to detect a crack in the circuit board with higher accuracy than detecting the absolute value of the resistance value of the crack detection wiring pattern at a temperature at which the resin softens.

Multiple In the invention according to claim 1 2 or claim 1 3, as described in claim 1 5, on a circuit board, a crack detection wire pattern for detecting a crack in the circuit board in the same process After forming and injection molding, it is preferable to compare the resistance values of the plurality of crack detection wiring patterns with each other.

  According to this, after applying a large current, by comparing the resistance values of a plurality of crack detection wiring patterns formed in the same process, it is possible to suppress the influence of manufacturing variations and the like. That is, since the resistance values of the plurality of crack detection wiring patterns are compared with each other in a state where cracks are promoted as compared with before flowing a large current, cracks generated on the circuit board can be detected with higher accuracy. .

  In addition, in a state where the resin material is softened, by comparing the resistance values of a plurality of crack detection wiring patterns with each other, the influence of manufacturing variations of the crack detection wiring patterns and the influence of the temperature characteristics of the resistance values are suppressed. be able to. That is, it is possible to detect a crack in the circuit board with higher accuracy than comparing resistance values detected before and after heating.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a perspective view illustrating a schematic configuration of the semiconductor device according to the first embodiment. In FIG. 1, for convenience, the sealing resin portion is indicated by a two-dot chain line. 2 is a cross-sectional view taken along the line II-II in FIG.

  As shown in FIG. 1, the semiconductor device 100 includes a circuit board 30 on which a heat sink 10 and crack detection wiring patterns 50 a and 50 b are formed as main parts and mounted on one surface 10 a of the heat sink 10, and a circuit board. 30, an external connection terminal 70 that is electrically connected to 30, at least a part of the heat sink 10, a part of the external connection terminal 70, and a sealing resin portion 90 that seals the circuit board 30.

  As shown in FIGS. 1 and 2, the heat sink 10 is a heat radiating member that releases heat of the electronic elements 31 (particularly power elements) mounted on the circuit board 30 from the circuit board 30. Any material (for example, metal) having better heat dissipation than the circuit board 30 can be employed. In the present embodiment, the circuit board 30 is fixed to the one surface 10 a of the heat sink 10 formed in a flat plate shape via the adhesive member 20. In addition, as the adhesive member 20, an adhesive material including a synthetic resin material (silicon rubber or the like) excellent in thermal conductivity can be employed.

  As shown in FIGS. 1 and 2, the circuit board 30 includes a wiring board in which a wiring pattern is arranged on an insulating base material such as resin or ceramic, and an electronic device that is mounted on the wiring board and constitutes a circuit together with the wiring pattern. And the element 31. In the present embodiment, a wiring substrate having a single layer is adopted as the wiring pattern, and the wiring pattern is formed only on the back surface 30a (hereinafter referred to as the front surface 30a) of the circuit board 30 that is bonded to the heat sink 10. . Then, on the surface 30a of the circuit board 30, control ICs 32 and 33 and electronic components 34 such as resistors and capacitors (four in FIG. 1) are mounted as electronic elements 31, and a hybrid integrated circuit is configured together with a wiring pattern. Has been. Further, as a wiring pattern, not only a wiring pattern (not shown) that provides an electrical connection function (configures a circuit) but also an electrical connection function (does not configure a circuit) occurs on the circuit board 30. A plurality of crack detection wiring patterns 50a and 50b for detecting cracks are provided.

  The control ICs 32 and 33 are electrically connected to the wiring pattern providing the electrical connection function via the bonding wire 35, and the electronic component 34 is electrically connected to the wiring pattern via solder, conductive adhesive, or the like. Connected. The wiring pattern is electrically connected to the lead terminal 71 as the external connection terminal 70 through the bonding wire 36.

  The crack detection wiring patterns 50 a and 50 b are arranged on the surface 30 a of the circuit board 30 in a region excluding a wiring pattern that provides an electrical connection function and an arrangement region of the electronic elements 31. The crack detection wiring patterns 50a and 50b are formed using the same material (in the same process as described later). As the constituent material, it is preferable to employ a material having such a brittleness that the crack is similarly generated when the circuit board 30 is cracked. In the present embodiment, the crack detection wiring patterns 50a and 50b are configured as a printing resistor formed using a screen printing method together with a wiring pattern that provides an electrical connection function.

  In the present embodiment, the plurality of crack detection wiring patterns 50a and 50b include a plurality of (two in the present embodiment, two continuous crack detection wiring patterns 50 that do not provide an electrical connection function. ) Is divided into resistance regions. Specifically, as shown in FIG. 1, in the wiring pattern 50 formed along the end portion of the circuit board 30 with a substantially C-shape (substantially annular) with a slight gap between the end portions, An external connection terminal 72a for resistance detection (hereinafter referred to as a detection terminal 72a) is connected to the end via a bonding wire 37, and a detection terminal 72b is connected to the bonding wire 37 at an intermediate portion between the ends of the wiring pattern 50. The resistance region between the connecting portions to the detection terminals 72a and 72b is a crack detection wiring pattern 50a. Further, a resistance region between connection portions of the detection terminal 72b and the detection terminal 72c connected via the bonding wire 37 is a crack detection wiring pattern 50b. The detection terminals 72 (72 a to 72 c) are different in connection object from the lead terminals 71, and both have the same configuration as the external connection terminals 70. Specifically, it is configured as a part of the lead frame.

  The sealing resin part 90 covers and protects at least a part of the heat sink 10, the circuit board 30, the connection part between the circuit board 30 and the lead terminal 71, and the connection part between the circuit board 30 and the detection terminal 72. Yes, it is formed by injection molding of resin. In the present embodiment, the heat sink 10 is configured such that the back surface 10b of the one surface 10a on which the circuit board 30 is mounted is exposed from the sealing resin portion 90 and exposed to the outside air. Further, the lead terminal 71 and the detection terminal 72 are exposed from the sealing resin portion 90 at the end opposite to the connection portion with the bonding wires 36 and 37, and can be electrically connected to the outside. It has become.

  The semiconductor device 100 configured as described above can be formed by the following procedure. First, the circuit board 30 is fixed to the heat sink 10 via the adhesive member 20. Next, in this fixed state, the lead terminal 71 and the wiring pattern, and the detection terminal 72 and the crack detection wiring pattern 50 are electrically connected by wire bonding. In this state, the semiconductor device 100 can be obtained by placing in an injection mold, injecting molten resin into the mold, and removing unnecessary portions of the lead frame after injection molding. it can. The wire bonding can also be performed before the circuit board 30 is fixed to the heat sink 10.

  As described above, in the semiconductor device 100 according to the present embodiment, in the configuration in which the circuit board 30 bonded and fixed on the heat sink 10 is covered with the sealing resin portion 90 formed by injection molding, the circuit board 30 A plurality of crack detection wiring patterns 50a and 50b are formed on the surface 30a. The ends of the plurality of crack detection wiring patterns 50a and 50b are electrically connected to the detection terminals 72 (72a to 72c), respectively, and a part of the detection terminals 72 (72a to 72c) is sealed. Each of the resin portions 90 is exposed. Then, by connecting the detection terminals 72 (72a to 72c) to an external detection device (not shown), the resistance values of the plurality of crack detection wiring patterns 50a and 50b are measured, and the respective resistance values are compared. It is determined whether or not the circuit board 30 is cracked.

  Therefore, even if a crack (crack) occurs in the circuit board 30 during the injection molding due to the warp of the heat sink 10 or the surface irregularities, the resistance values of the plurality of crack detection wiring patterns 50a and 50b are respectively set after the injection molding. By measuring and comparing the obtained resistance values with each other, the influence of manufacturing variations of the plurality of crack detection wiring patterns 50a and 50b is suppressed, and the crack detection wiring patterns 50a and 50b (circuit board 30) are reduced. Cracks can be detected.

  In the present embodiment, the ratio value (design value) of the resistance values of the plurality (two) of crack detection wiring patterns 50a and 50b determined at the time of layout and the plurality of crack detections measured after injection molding. The crack of the circuit board 30 is detected by taking a difference from the ratio value of the resistance values of the wiring patterns 50a and 50b. Details are as follows.

The resistance values of the plurality of crack detection wiring patterns 50a and 50b are determined by the layout pattern (wiring length and width). Therefore, the ratio I ₀ between the resistance values R _a0 and R _b0 of the plurality of crack detection wiring patterns 50a and 50b determined by the layout pattern is a constant value α as shown in the following equation.

Further, in the present embodiment, since a plurality of crack detection wiring patterns 50a and 50b are formed in the same process, the respective manufacturing variations are substantially equal. However, even when a plurality of crack detection wiring patterns 50a and 50b are formed in the same process, the accuracy of the resistance varies slightly between the plurality of resistors. Therefore, if the accuracy ratio of the plurality of crack detection wiring patterns 50a and 50b (accuracy ratio of manufacturing variation between resistors generated during manufacturing) is p and the manufacturing variation is e, the two resistance values R _a1 , measured after injection molding, The ratio I _{ab of} R _b1 is as shown in the following equation.

Here, from the relationship shown in Formula 1, I _ab can be expressed as the following formula.

The first term of Equation 3 represents the ratio I ₀ of the resistance values R _a0 and R _b0 of the plurality of crack detection wiring patterns 50a and 50b determined by the layout pattern, and the second term represents the plurality of crack detections. This shows the influence of the accuracy ratio p of the wiring patterns 50a and 50b. Here, if the difference between I ₀ shown in Equation 1 and I _ab shown in Equation 3 is taken, only the influence of the accuracy ratio p can be extracted as shown in the following equation.

  From Equation 4, the influence of the accuracy ratio p of the plurality of crack detection wiring patterns 50a and 50b can be expressed as α | p | × 2 in consideration of the error width due to the accuracy ratio p.

Further, when the heat sink 10 is warped and a crack 38a is generated in the crack detection wiring pattern 50a as shown in FIG. 1, the resistance value R _a1Z of the crack detection wiring pattern 50a is a crack measured after injection molding. As compared with the resistance value R _a1 in the absence of the value, it increases by the amount of Z _a . In this case, if the ratio of the two resistance values R _a1Z and R _b1 measured after injection molding is I _abZ , the following equation is obtained.

Here, from the relationship shown in Formula 1, I _abZ can be _expressed as the following formula.

The first term of Formula 6 is the ratio I _ab of the two resistance values R _a1 and R _b1 measured after injection molding in a state where no crack is generated in the crack detection wiring pattern 50a, and the second term is a crack. It is a term which shows the influence by 38a. Here, when the difference between I ₀ shown in Equation 1 and I _abZ shown in Equation 6 is taken, the following equation is obtained.

  According to Equation 7, the first term is a term indicating the effect of the accuracy ratio p of the plurality of crack detection wiring patterns 50a and 50b, and the second term is a term indicating the effect of the crack 38a. That is, if the influence of the crack 38a shown in the second term is larger than the influence of the accuracy ratio p shown in the first term, it can be detected that the crack 38a has occurred in the circuit board 30. As described above, the influence of the first term αp can be expressed as α | p | × 2 in consideration of the error width due to the accuracy ratio p. Therefore, if the following inequality is satisfied, the influence of the crack 38a is detected. Can do.

When Equation 8 is solved for Z _a , the following equation is obtained.

Here, the manufacturing variation e usually has a variation of about ± 20 to 60%, and the accuracy ratio p of the plurality of crack detection wiring patterns 50a and 50b has an empirical value of about ± 5%. Yes. Therefore, the right side R _a0 (1 + e _b ) | p | × 2 of Equation 9 indicates a value of about 4 to 16% of the resistance value R _a0 of the crack detection wiring pattern 50a determined at the time of layout. That is, as shown in the left side of Equation 9, increment Z _a resistance value of the crack detection wiring pattern 50a due to the effect of the crack 38a generated in the circuit board 30 is the resistance of the crack detection wiring patterns 50a which are determined at the time of layout If the value is larger than 0.16 times the value _Ra0 , it can be detected that the circuit board 30 is cracked.

  The present applicant has proposed a semiconductor device in which a single substrate crack detection wiring pattern for detecting a substrate crack is formed on the surface of the wiring substrate in Japanese Patent Application No. 2006-157111. In the case of this configuration, R is the resistance value of the wiring pattern for board crack detection determined at the time of layout, Z is the increase in resistance value of the wiring pattern for board crack detection due to the effect of the crack generated in the wiring board, and If the manufacturing variation of the wiring pattern is e, it is possible to detect that a crack has occurred in the wiring board when the following equation is satisfied.

  Here, as described above, since the manufacturing variation e usually has a variation of about ± 20 to 60%, the right side R | e | × 2 of Expression 9 represents the wiring pattern for detecting a substrate crack determined at the time of layout. The resistance value R is about 40 to 120%. That is, the increase Z of the resistance value of the wiring pattern for detecting a substrate crack due to the influence of a crack generated in the circuit board shown on the left side of Equation 10 is the resistance value R of the wiring pattern for detecting a substrate crack determined at the time of layout. If a value larger than 1.20 times can be shown, it can be detected that a crack has occurred in the circuit board.

  As described above, according to the present embodiment, it is possible to detect a crack in the circuit board 30 with higher accuracy than measuring the absolute value of the resistance of one board crack detection wiring pattern.

  In the case of the semiconductor device proposed by the present applicant (Japanese Patent Application No. 2006-157111), the resistance value of one wiring pattern for substrate crack detection was measured before and after injection molding, and measured before injection molding. By comparing the resistance value and the resistance value measured after injection molding, it is also conceivable to suppress the influence of manufacturing variation and detect cracks in the substrate with high accuracy. However, in the above configuration, as in the present embodiment, the lead terminal and the detection terminal are configured as one lead frame in a state before injection molding. Therefore, the resistance value of the substrate crack detection wiring pattern cannot be measured. Further, although it is possible to directly measure the resistance value of the wiring pattern for substrate crack detection with a tester or the like, the number of work steps increases and the cost increases.

  In the present embodiment, a plurality of crack detection wiring patterns 50 a and 50 b (wiring patterns 50) are formed along the end of the circuit board 30. Since cracks are likely to occur at weak end portions of the circuit board 30, most of the cracks generated in the circuit board 30 can be detected by adopting such a configuration.

Further, in the present embodiment, an example in which the crack of the circuit board 30 is detected when the crack 38a occurs at the end of the circuit board 30 has been described. However, as shown in FIG. 1, it is possible to detect a crack in the circuit board 30 even when a crack 38b occurs across the plurality of crack detection wiring patterns 50a and 50b. If the crack 38b is caused, the resistance value of the crack detection wiring pattern 50a is Z _a fraction rises, the resistance value of the crack detection wiring pattern 50b as compared with the resistance value R _a1 measured after injection molding, after the injection molding and to increase Z _b min compared to the measured resistance value R _b1. Here, if the manufacturing variation is e, the accuracy ratio of the plurality of crack detection wiring patterns 50a and 50b is p, and the ratio of the respective resistance values R _a1Z and R _b1z to which the increment of the crack 38b is added is I _abZZ . As shown in the following equation.

By the way, I _ab shown in Formula 3 indicates a ratio of two resistance values R _a1 and R _b1 measured after injection molding when the circuit board 30 is not cracked. In order to detect the crack 38b, the ratio I _ab may be different from the ratio I _{abZZ of the} two resistance values R _a1Z and R _b1Z affected by the crack 38b measured after injection molding. Specifically, the following Expressions 12 and 13 may be satisfied.

  Here, when formulas 12 and 13 are arranged from the relationships shown in formulas 1, 3, and 11, the following formulas are obtained.

Here, as described above, since the accuracy ratio p of the plurality of crack detection wiring patterns 50a and 50b has a value of about ± 5% empirically, the right side α (1 + p) shown in Equation 14 and Equation 15 is used. ) Indicates a value of about 95 to 105% of the ratio α of the resistance values (specified values) of the crack detection wiring patterns 50a and 50b determined at the time of layout. That is, the increase Z _a of the resistance value of the crack detection wiring pattern 50a due to the influence of the crack 38b generated in the circuit board 30 and the increase of the resistance value of the crack detection wiring pattern 50b shown on the left side of the mathematical expressions 14 and 15. the ratio of the partial Z _b is laid upon the determined crack detection wire pattern 50a, if the ratio 1.05 times larger than the alpha or smaller than 0.95 times the alpha, the resistance of the 50b It is possible to detect that the crack 38b has occurred in the circuit board 30.

Even if the crack 38b occurs across the plurality of crack detection wiring patterns 50a and 50b, the resistance increases Z _a and Z _b due to the influence of the crack 38b generated in each crack detection wiring pattern 50a and 50b are different. Therefore, the ratio of the increments Z _a and Z _b of the resistance value does not show a value of about 95 to 105% of α. Therefore, even if the crack 38b occurs across the plurality of crack detection wiring patterns 50a and 50b, the crack generated in the circuit board 30 can be detected.

  In the present embodiment, the ratio value (design value) of the resistance values of the plurality of crack detection wiring patterns 50a and 50b determined at the time of layout and the plurality of crack detection wiring patterns 50a measured after injection molding. , 50b, the method of taking the difference from the resistance value ratio value was introduced. However, the comparison method is not limited to the above-described example, and any comparison method that suppresses the influence of manufacturing variations in resistance values can be used. Can be adopted.

For example, when the resistance values of the plurality of crack detection wiring patterns 50a and 50b determined at the time of layout are equal, by taking the difference between the resistance values of the plurality of crack detection wiring patterns 50a and 50b measured after injection molding, It is possible to suppress the influence of manufacturing variation of the resistance value, and to detect a crack generated in the circuit board 30 with high accuracy. Specifically, as described above, the resistance values of the plurality of crack detection wiring patterns 50a and 50b determined by the layout pattern are R _a0 and R _b0 , the manufacturing variation is e, and the plurality of crack detection wiring patterns 50a and 50b are the same. Let the precision ratio be p. Also, if the crack 38a is caused to crack detection wire pattern 50a, the the increase in the resistance of crack detection wiring pattern 50a due to the effect of the crack 38a generated in the circuit board 30 and _{Z a,} the resistance value _{R A1z,} The difference I of R _b1 is as shown in the following formula.

Here, since the resistance values R _a0 and R _b0 are equal, Equation 16 is as shown in the following equation.

According to Equation 17, the first term is a term indicating the effect of the accuracy ratio p of the plurality of crack detection wiring patterns 50a and 50b, and the second term is a term indicating the effect of the crack 38a. That is, if the influence of the crack 38a shown in the second term is larger than the influence of the accuracy ratio p shown in the first term, it can be detected that the crack 38a has occurred in the circuit board 30. By the way, since the error due to the accuracy ratio p of the first term can be expressed as R _a0 (1 + e) | p | × 2, the influence of the crack 38a can be detected if the inequality shown in the following equation is satisfied.

Thus, Equation 18 is the same as Equation 9. That is, by detecting the difference between the resistance values of the plurality of crack detection wiring patterns 50a and 50b measured after the injection molding, the crack of the circuit board 30 is detected with the same accuracy as the method of detecting the crack of the circuit board 30 described above. can do. In the case of this method, it is not necessary to store the ratio I ₀ of the resistance values R _a0 and R _b0 of the plurality of crack detection wiring patterns 50a and 50b determined by the layout pattern. Compared with the method of taking, the processing steps can be simplified.

  Moreover, in this embodiment, the back surface 10b of the one surface 10a which mounts the circuit board 30 in the heat sink 10 showed the example exposed from the sealing resin part 90. As shown in FIG. However, the exposed portion of the sealing resin portion 90 in the heat sink 10 is not limited to the above-described example, and other portions may be exposed. The entire heat sink 10 may be sealed by the sealing resin portion 90.

  Further, in the present embodiment, an example in which the wiring pattern is a single-layer wiring board and the wiring pattern is formed only on the back surface 30a of the adhesion surface of the circuit board 30 to the heat sink 10 is shown. However, it is also possible to adopt a configuration in which a wiring board in which wiring patterns are arranged in multiple layers is adopted and the crack detection wiring patterns 50a and 50b are formed in at least one of the wiring pattern layers arranged in multiple layers.

  Further, in the present embodiment, one continuous crack detection wiring pattern 50 is divided into two resistance regions by connection portions with three detection terminals 72 (72a to 72c), and two crack detections are made. The example in which the wiring patterns 50a, 50b are formed is shown. However, by using four or more detection terminals 72, one continuous crack detection wiring pattern 50 may be divided into three or more resistance regions (that is, crack detection wiring patterns).

  Alternatively, a plurality of electrically independent crack detection wiring patterns may be formed. For example, in the example shown in FIG. 3, two electrically independent crack detection wiring patterns 50 a and 50 b are arranged along the end of the circuit board 30. Both ends of the crack detection wiring pattern 50 a are electrically connected to the detection terminals 72 a and 72 b via the bonding wires 37, and both ends of the crack detection wiring pattern 50 b are detected via the bonding wires 37. The terminals 72c and 72d are electrically connected. The detection terminals 72 (72a to 72d) are exposed from the sealing resin portion 90 at the ends opposite to the connection portions with the bonding wires 37, and can be connected to an external detection device (not shown). ing. FIG. 3 is a perspective view showing a modification.

  In the present embodiment, the resistance values of the plurality of crack detection wiring patterns 50a and 50b are measured by an external detection device, and the resistance values are compared to determine whether or not the circuit board 30 is cracked. An example of determining whether or not. However, instead of using an external detection device, a detection circuit configured on the circuit board 30 may be used to detect a crack in the circuit board 30. For example, in the example shown in FIG. 4, the control IC 32 is a detection circuit that detects cracks in the circuit board 30 and is electrically connected to one continuous wiring pattern 50 via bonding wires 39 (39a to 39c). Connected. The bonding wire 39 (39a to 39c) divides one continuous wiring pattern 50 into a plurality (two) of resistance regions, thereby forming a plurality of crack detection wiring patterns 50a and 50b. Specifically, the resistance region between the bonding wires 39a and 39b is a crack detection wiring pattern 50a, and the resistance region between the bonding wires 39a and 39c is a crack detection wiring pattern 50b. The control IC 32 measures the resistance values of the plurality of crack detection wiring patterns 50a and 50b, and compares the obtained resistance values with each other, thereby suppressing the influence of manufacturing variations of the crack detection wiring patterns 50a and 50b. Then, cracks in the crack detection wiring patterns 50a and 50b (circuit board 30) are detected. When a crack is detected in the crack detection wiring patterns 50a and 50b, it is determined that the circuit board 30 is cracked, and a signal indicating the crack in the circuit board 30 is sent via the lead terminal 71 to the semiconductor device. In addition to outputting to the outside of the circuit 100, the operation of the circuit configured on the circuit board 30 is stopped. With such a configuration, an effect as a self-diagnosis function can be expected. FIG. 4 is a perspective view showing a modification.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 5 is a perspective view showing a schematic configuration of the semiconductor device according to the second embodiment, and corresponds to FIG. 1 shown in the first embodiment.

  Since the semiconductor device and the substrate crack detection method according to the second embodiment are in common with those according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be described with emphasis. . In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the first embodiment, the example in which the plurality of crack detection wiring patterns 50 a and 50 b are arranged along the end of the circuit board 30 has been described. On the other hand, in the present embodiment, as shown in FIG. 5, as the crack detection wiring pattern, outer peripheral patterns 51a and 51b arranged along the edge of the circuit board 30, and the outer peripheral patterns 51a, It is characterized by having inner peripheral patterns 52a and 52b arranged inside 51b.

  Specifically, one continuous crack detection wiring pattern 51 that does not provide an electrical connection function is substantially C along the edge of the circuit board 30, like the wiring pattern 50 shown in the first embodiment. It is arranged in a letter shape (substantially annular). In the wiring pattern 51, the detection terminal 72a is connected to one end portion via the bonding wire 37, and the detection terminal 72b is connected to the intermediate portion between the end portions in the wiring pattern 51 via the bonding wire 37. A resistance region between the connection portions with the detection terminals 72a and 72b is an outer peripheral pattern 51a. In addition, a resistance region between connection portions between the detection terminal 72b and the detection terminal 72c connected via the bonding wire 37 is an outer peripheral pattern 51b. That is, the outer peripheral patterns 51a and 51b have the same configuration as the crack detection wiring patterns 50a and 50b shown in the first embodiment.

  Further, one continuous crack detection wiring pattern 52 that does not provide an electrical connection function is arranged in a substantially C-shape (substantially annular) inside the wiring pattern 51. In the wiring pattern 52, the detection terminal 72d is connected to one end portion via the bonding wire 37, and the detection terminal 72e is connected to the intermediate portion between the end portions in the wiring pattern 52 via the bonding wire 37. A resistance region between the connection portions with the detection terminals 72d and 72e is an inner peripheral pattern 52a. In addition, a resistance region between connection portions of the detection terminal 72e and the detection terminal 72f connected via the bonding wire 37 is an inner peripheral pattern 52b.

  According to the semiconductor device 100 configured as described above, it is possible to detect a crack generated at the end portion of the circuit board 30 by the plurality (two) of the outer peripheral patterns 51a and 51b, and to detect the plurality of (two) inner peripheries. Cracks generated inside the outer peripheral patterns 52a and 52b of the circuit board 30 can be detected by the patterns 52a and 52b.

  Specifically, the detection terminals 72 (72a to 72c) are connected to an external detection device (not shown), the resistance values of the outer peripheral patterns 51a and 51b are measured, and the resistance values of the circuit boards 30 are compared with each other. It can be determined whether or not a crack has occurred at the end. Therefore, even if a crack 38a (crack) occurs at the end of the circuit board 30 at the time of injection molding as shown in FIG. 5 due to the warp of the heat sink 10 or surface irregularities, the outer peripheral pattern 51a, The resistance values of 51b and 51b (circuit board 30) are suppressed by measuring the resistance values of 51b and comparing the obtained resistance values with each other to suppress the influence of manufacturing variations of the outer periphery patterns 51a and 51b. Can be detected.

  Similarly, by connecting the detection terminals 72 (72d to 72f) to an external detection device (not shown), measuring the resistance values of the inner peripheral patterns 52a and 52b, and comparing the resistance values of the outer peripheral patterns 51a, It can be determined whether or not there is a crack inside 51b. Therefore, as shown in FIG. 5, even if a crack 38 c occurs inside the outer peripheral patterns 51 a and 51 b of the circuit board 30 at the time of injection molding due to the influence of the warp of the heat sink 10 and the surface unevenness, The resistance values of the peripheral patterns 52a and 52b are measured, and the obtained resistance values are compared with each other, thereby suppressing the influence of manufacturing variations of the inner peripheral patterns 52a and 52b and the inner peripheral patterns 52a and 52b (circuits). Cracks in the substrate 30) can be detected.

  As described above, in the present embodiment, by forming the inner peripheral patterns 52a and 52b on the inner side of the outer peripheral patterns 51a and 51b, it is possible to detect cracks generated on the inner side of the outer peripheral patterns 51a and 51b with high accuracy. it can.

  In this embodiment, by using the comparison method shown in the first embodiment, the resistance values of the outer peripheral patterns 51a and 51b are compared with each other, and the resistance values of the inner peripheral patterns 52a and 52b are compared with each other. An example in which it is determined whether or not the substrate 30 is cracked has been shown. However, for example, if the wiring pattern 51 is one outer peripheral pattern, the wiring pattern 52 is one inner peripheral pattern, and the resistance values of the wiring pattern 51 and the wiring pattern 52 are compared with each other, is the circuit board 30 cracked? It may be determined whether or not.

  Moreover, in this embodiment, the example which judges whether the crack was produced in the circuit board 30 by the external detection apparatus which is not shown in figure was shown. However, as shown in the modification of the first embodiment, instead of using an external detection device, a detection circuit configured on the circuit board 30 may be used to detect a crack in the circuit board 30. .

  In the present embodiment, the wiring pattern 51 is divided into two resistance regions by connecting portions with the three detection terminals 72 (72a to 72c) to form two outer peripheral patterns 51a and 51b. Indicated. However, the wiring pattern 51 may be partitioned into three or more resistance regions (that is, crack detection wiring patterns) by using four or more detection terminals. Similarly, in the present embodiment, the wiring pattern 52 is divided into two resistance regions by connecting portions with the three detection terminals 72 (72d to 72f), thereby forming two inner peripheral patterns 52a and 52b. showed that. However, the wiring pattern 52 may be partitioned into three or more resistance regions (that is, crack detection wiring patterns) by using four or more detection terminals.

  In the present embodiment, the wiring pattern 51 is divided into two resistance regions by connecting portions with the three detection terminals 72 (72a to 72c) to form two outer peripheral patterns 51a and 51b. Indicated. However, for example, two electrically independent outer peripheral patterns 51 a and 51 b may be arranged along the end portion of the circuit board 30. In the present embodiment, the wiring pattern 52 is divided into two resistance regions by connecting portions with the three detection terminals 72 (72d to 72f) to form two inner peripheral patterns 52a and 52b. showed that. However, for example, two electrically independent inner peripheral patterns 52 a and 52 b may be arranged inside the wiring pattern 51.

  In the present embodiment, an example in which one wiring pattern 52 is arranged inside the wiring pattern 51 is shown. However, a plurality of wiring patterns 52 may be arranged inside the wiring pattern 51. For example, a configuration in which a plurality of wiring patterns 52 are arranged in parallel in one wiring pattern 51 may be adopted. Or it is good also as a structure by which the wiring pattern 52 is arrange | positioned in multiple in the one wiring pattern 51 (three or more layers).

(Third embodiment)
Next, 3rd Embodiment of this invention is described based on FIGS. FIG. 6 is a perspective view showing a schematic configuration of the semiconductor device according to the third embodiment, and corresponds to FIG. 1 shown in the first embodiment. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 showing a state before a large current is applied to the semiconductor device. FIG. 8 is a cross-sectional view showing a state after a large current is applied to the semiconductor device, and corresponds to FIG.

  Since the semiconductor device and the substrate crack detection method according to the third embodiment are in common with those according to each of the above-described embodiments, detailed description of the common parts will be omitted, and different parts will be mainly described below. To do. In addition, the same code | symbol shall be provided to the element same as the element shown to each above-mentioned embodiment.

  In the semiconductor device 100 shown in FIG. 6, one crack detection wiring pattern 53 that does not provide an electrical connection function is arranged in a substantially C shape (substantially annular shape) along the end of the circuit board 30. In this crack detection wiring pattern 53, a detection terminal 72 a is connected to one end via a bonding wire 37, and a detection terminal 72 b is connected to the other end via a bonding wire 37. The detection terminal 72 (72a, 72b) has an end opposite to the connection portion with the bonding wire 37 exposed from the sealing resin portion 90, and is electrically connected to an external detection device (not shown). Can be connected to.

  In the semiconductor device 100 configured as described above, in this embodiment, after injection molding, the detection terminals 72 (72a, 72b) are connected to an external detection device (not shown), and the resistance value of the crack detection wiring pattern 53 is determined. Is measured, a current larger than that of resistance measurement (hereinafter referred to as a large current) is passed through the crack detection wiring pattern 53. The large current is a current that does not exceed the allowable current. When such a large current flows, for example, when a fine crack 38a (crack) as shown in FIG. 7 is generated in the circuit board 30, the crack 38a grows (largely) as shown in FIG. Can be encouraged). Thereby, the influence of the crack 38a on the resistance of the crack detection wiring pattern 53 is increased. Therefore, by measuring the resistance of the crack detection wiring pattern 53 after flowing a large current after injection molding, it is possible to detect the crack of the circuit board 30 with higher accuracy than simply measuring the absolute value of the resistance. .

  In the present embodiment, an example is shown in which the resistance value of the crack detection wiring pattern 53 is measured by an external detection device (not shown) to determine whether or not the circuit board 30 is cracked. However, as shown in the modification of the first embodiment, it is determined whether or not the circuit board 30 is cracked by using the detection circuit configured on the circuit board 30 instead of using an external detection device. It is good also as a structure to judge.

  Further, in the present embodiment, after flowing a large current through the crack detection wiring pattern 53, the absolute value of the resistance of the crack detection wiring pattern 53 is measured to detect a crack (crack) of the circuit board 30. An example is shown. However, in the semiconductor device 100 in which a plurality (two) of crack detection wiring patterns 50a and 50b are arranged on the circuit board 30 as in the configuration shown in the first embodiment, the above-described large current is applied to the crack detection wiring. After flowing through the patterns 50a and 50b, the crack 38a of the circuit board 30 may be detected by comparing the resistance values of the crack detection wiring patterns 50a and 50b. In this case, since the resistance values of the plural (two) crack detection wiring patterns 50a and 50b can be compared with each other in a state where the crack is promoted, manufacturing variations can be suppressed. Therefore, it is possible to detect a crack generated in the circuit board 30 with higher accuracy than measuring the absolute value of the resistance of one crack detection wiring pattern 53 after flowing a large current.

(Fourth embodiment)
Next, 4th Embodiment of this invention is described based on FIGS. FIG. 9 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment, and shows a room temperature state. FIG. 9 corresponds to FIG. FIG. 10 is a cross-sectional view showing a schematic configuration of the semiconductor device in a heated state, and corresponds to FIG. FIG. 11 is a diagram showing the temperature dependence of the resistance value of the crack detection wiring pattern.

Since the semiconductor device and the substrate crack detection method according to the fourth embodiment are in common with those according to each of the above-described embodiments, detailed description of the common parts will be omitted below, and different parts will be mainly described. To do. In addition, in the same element as the element shown in each above-mentioned embodiment,
In the present embodiment, the semiconductor device 100 shown in the third embodiment (see FIG. 6) is adopted as the semiconductor device. In such a semiconductor device 100, if the heat sink 10 is warped or has surface irregularities, the circuit board 30 may be cracked due to the compressive stress caused by the resin during injection molding. After the injection molding, in a state where the resin (sealing resin portion 90) is cured, as shown in FIG. 9, the compressive stress (white in FIG. 9) is applied to the crack 38a generated in the circuit board 30. (Extract arrow) is working. That is, the crack 38a is in a compressed state (contact state) due to the compressive stress of the resin, and the crack 38a is less likely to affect the resistance of the crack detection wiring pattern 53.

  On the other hand, in this embodiment, it heats to such an extent that the sealing resin part 90 is softened after injection molding. Therefore, the compressive stress (open arrow in FIG. 10) acting on the crack 38a is alleviated, and the contact state of the crack 38a is alleviated. That is, as shown in FIG. 11, the crack 38 a is likely to be affected by the resistance of the crack detection wiring pattern 53. Then, by measuring the resistance value of the crack detection wiring pattern 53 in this state (heated state), it is possible to detect a crack in the circuit board 30 with higher accuracy than simply measuring the absolute value of the resistance.

  In the present embodiment, an example is shown in which the resistance value of the crack detection wiring pattern 53 is measured by an external detection device (not shown) to determine whether or not the circuit board 30 is cracked. However, as shown in the modification of the first embodiment, it is determined whether or not the circuit board 30 is cracked by using the detection circuit configured on the circuit board 30 instead of using an external detection device. It is good also as a structure to judge.

  Further, in the present embodiment, the crack of the circuit board 30 is detected by measuring the absolute value of the resistance of the crack detection wiring pattern 53 in a state where the sealing resin portion 90 is heated to a degree of softening after injection molding. An example to do. However, the resistance value of the crack detection wiring pattern 53 measured in a room temperature state after injection molding and the resistance value of the crack detection wiring pattern 53 measured in a state heated to the extent that the sealing resin portion 90 is softened after injection molding. A crack in the circuit board 30 may be detected by comparison. In this case, the influence of manufacturing variation can be suppressed by comparing the resistance values of the same crack detection wiring pattern 53. Therefore, the crack of the circuit board 30 can be detected with higher accuracy than the absolute value of the resistance value of the crack detection wiring pattern 53 at the temperature at which the resin softens.

  Further, in the semiconductor device 100 in which a plurality (two) of crack detection wiring patterns 50a and 50b are arranged on the circuit board 30 as in the configuration shown in the first embodiment, the sealing resin portion 90 is formed after injection molding. The crack 38a of the circuit board 30 may be detected by comparing the resistance values of the plural (two) crack detection wiring patterns 50a and 50b in a state where the circuit board 30 is heated to a degree of softening. As shown in FIG. 11, due to the temperature characteristics of the resistance, the resistance values of a plurality (two) of crack detection wiring patterns 50a and 50b change depending on the temperature. By comparing the resistance values of the (two) crack detection wiring patterns 50a and 50b, it is possible to suppress the influence of manufacturing variation and the influence of the temperature characteristic of the resistance. Therefore, it is possible to detect cracks in the circuit board 30 with higher accuracy than when comparing the resistance values of the same crack detection wiring pattern 53 before and after heating.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a perspective view illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is sectional drawing which follows the II-II line | wire of FIG. It is a perspective view which shows the modification of the semiconductor device which concerns on 1st Embodiment. It is a perspective view which shows the modification of the semiconductor device which concerns on 1st Embodiment. It is a perspective view which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is a perspective view which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment and 4th Embodiment. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 before a large current is applied to the semiconductor device. It is sectional drawing after a large electric current is applied to the semiconductor device. It is sectional drawing which shows schematic structure of the semiconductor device concerning this embodiment, and has shown the room temperature state. It is sectional drawing which shows schematic structure of the semiconductor device in a heating state. It is a figure which shows the temperature dependence of the resistance value of the wiring pattern for a crack detection.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Heat sink 30 ... Circuit board 38a ... Crack 50a, 50b ... Crack detection wiring pattern 70 ... External connection terminal 71 ... Lead terminal 72 ... Detection terminal 90- ..Encapsulating resin part 100: semiconductor device

Claims (15)

A circuit board having a wiring pattern;
A heat sink on which the circuit board is mounted;
A part of a lead frame, and an external connection terminal electrically connected to the wiring pattern;
A semiconductor device comprising at least a part of the heat sink, a connection portion between the external connection terminal and the wiring pattern, and a sealing resin portion that seals the circuit board,
The circuit board as the wiring pattern does not provide an electrical connection function, the crack detection wire pattern for detecting a crack in the circuit board and a plurality Yes,
A detection circuit mounted on the circuit board and connected to each end of the crack detection wiring pattern,
The detection circuit takes the difference between the measured ratio of the resistance values of the plurality of crack detection wiring patterns and the ratio of the resistance values of the plurality of crack detection wiring patterns determined at the time of layout. A semiconductor device that detects whether or not a crack is generated in a detection wiring pattern . A circuit board having a wiring pattern;
A heat sink on which the circuit board is mounted;
A part of a lead frame, and an external connection terminal electrically connected to the wiring pattern;
A semiconductor device comprising at least a part of the heat sink, a connection portion between the external connection terminal and the wiring pattern, and a sealing resin portion that seals the circuit board,
The circuit board does not provide an electrical connection function as the wiring pattern, and has a plurality of crack detection wiring patterns for detecting cracks in the circuit board,
The resistance values of the plurality of crack detection wiring patterns determined at the time of layout are equal,
A detection circuit mounted on the circuit board and connected to each end of the crack detection wiring pattern,
The detection circuit by taking the difference between the resistance value of the measured plurality of crack detection wiring pattern, you and detecting whether cracks on the crack detection wiring pattern occurs semiconductors apparatus. As the plurality of crack detection wire pattern, a semiconductor device according to claim 1 or claim 2, characterized in that it comprises a single continuous crack detection wiring pattern formed by the wiring pattern is divided into a plurality of resistive regions . The semiconductor according as the plurality of crack detection wire pattern, to claim 1 or claim 2, characterized in that it comprises other crack detection wiring pattern electrically independently arranged crack detection wiring pattern apparatus. 5. The semiconductor device according to claim 3, wherein the plurality of crack detection wiring patterns include at least one outer peripheral pattern arranged along an end portion of the circuit board . 6. Wherein a plurality of crack detection wiring pattern, and the peripheral pattern, a semiconductor device according to claim 5, characterized in Rukoto that have a at least one of the inner circumferential pattern disposed inside the outer peripheral pattern. The heat sink, the semiconductor device according to claim 6 any one, wherein part der Rukoto of the lead frame. As the external connection terminal, respectively connected to the end of the crack detection wiring pattern,
The semiconductor device according to claim 1 to 7 any one, characterized in Rukoto comprises a plurality of detection terminals partially exposed from the sealing resin portion. When the detection circuit detects a crack in the crack detection wiring pattern, the detection circuit determines that the circuit board is cracked, and sends a signal indicating the crack in the circuit board via the external connection terminal. and outputs to the outside, the semiconductor device according to any one of claims 1 to 7, wherein Rukoto stops the operation of the circuit portion configured on the circuit board. A circuit board detection method for detecting whether or not the circuit board is cracked in a state where the circuit board mounted on the heat sink is sealed by injection molding of a resin material,
Before mounting on the heat sink, without providing an electrical connection function on the circuit board, a plurality of crack detection wiring patterns for detecting cracks in the circuit board are formed in the same process,
After the injection molding, the resistance values of the plurality of crack detection wiring patterns are respectively measured , and the ratio of the measured resistance values of the plurality of crack detection wiring patterns and the plurality of crack detection determined at the time of layout are measured . A substrate crack detection method comprising: detecting a crack in the crack detection wiring pattern by taking a difference from a resistance value ratio of the wiring pattern . A circuit board detection method for detecting whether or not the circuit board is cracked in a state where the circuit board mounted on the heat sink is sealed by injection molding of a resin material,
Before mounting on the heat sink, the resistance value determined at the time of layout is equal for the crack detection wiring pattern for detecting the crack of the circuit board without providing an electrical connection function on the circuit board. As you can see, multiple formations in the same process,
After the injection molding, the resistance values of the plurality of crack detection wiring patterns are respectively measured, and the difference in the resistance values of the plurality of crack detection wiring patterns thus measured is taken to crack the crack detection wiring pattern. A method for detecting a crack in a substrate, characterized in that it is detected whether or not an error has occurred . A circuit board detection method for detecting whether or not the circuit board is cracked in a state where the circuit board mounted on the heat sink is sealed by injection molding of a resin material,
Before mounting on the heat sink, on the circuit board, without providing an electrical connection function, at least one crack detection wiring pattern for detecting cracks in the circuit board is formed,
Wherein after the injection molding, before measuring the resistance value of the crack detection wire pattern, board crack detection method you characterized by a large current than the current of the resistance measurement to the crack detection wiring pattern . A circuit board detection method for detecting whether or not the circuit board is cracked in a state where the circuit board mounted on the heat sink is sealed by injection molding of a resin material,
Before mounting on the heat sink, on the circuit board, without providing an electrical connection function, at least one crack detection wiring pattern for detecting cracks in the circuit board is formed,
Wherein after the injection molding, the resin material in a state of being heated to the extent that it softens, board crack detection method you characterized by measuring the resistance value of the crack detection wiring pattern. At room temperature, detect the resistance value of the crack detection wiring pattern,
In a state where the resin material is heated to a degree of softening, the resistance value of the crack detection wiring pattern is detected,
The resistance value detected in a room temperature state is compared with the resistance value detected in a heated state, The substrate crack detection method of Claim 13 characterized by the above-mentioned. A plurality of crack detection wiring patterns for detecting cracks in the circuit board are formed in the same process on the circuit board,
14. The substrate crack detection method according to claim 12, wherein resistance values of the plurality of crack detection wiring patterns are compared with each other after the injection molding.

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