JP4793138B2 - Signal transmission system, signal transmission method and program - Google Patents

Description

  The present invention relates to a signal transmission system, a signal transmission method, and a program for transferring data between one-to-many nodes using a serial transmission line.

  In recent years, the data processing speed of LSI has been dramatically increased due to improvements in semiconductor integration technology. Along with this, an improvement in signal transmission capability is required for a wiring board on which a semiconductor integrated circuit is mounted. In particular, recently, a so-called parallel processing architecture including a plurality of high-speed CPU chips has been adopted in a personal computer as well, in a server type system corresponding to a higher model.

  For example, Non-Patent Document 1 discloses a parallel processing architecture technology.

  According to this, when configuring a system including a plurality of modules that perform data processing such as a CPU, the coupling method between modules is classified into a bus coupling type, a switch coupling type, and a coupling network type. Of these, the bus coupling type is not suitable for coupling a large number of modules, but has advantages such as a simple structure, a small amount of hardware, and excellent extensibility compared to other modules. It is widely used in commercial computers such as personal computers and computer application products such as page printers.

  The mounting of the inter-module coupling part of the parallel processing system requires a large number of connection connectors and wirings, so that the communication capacity and wiring density have been improved by multilayering and miniaturization of the wirings. However, the limit is being reached due to signal delay and transmission waveform distortion caused by inter-wiring capacitance and connection wiring resistance. Moreover, electromagnetic noise (EMI: Electro Magnetic Interference) becomes a big problem due to the increase in operating speed.

  As described above, the processing capability of the data processing apparatus is often limited by the transmission capability of the wiring board bus. In order to overcome the limitations of electric buses, the use of an in-system optical connection technology called optical interconnection has been studied.

  As the outline of the optical interconnection technology, various forms have been proposed depending on the contents of the system configuration (for example, see Non-Patent Documents 2 and 3).

  According to this technology, it is possible to reduce electromagnetic noise while being able to operate at a higher frequency than electric, eliminating the need for physical connection of bus signal lines, and transmission bandwidth by multiplexing using wavelength, strength, etc. Can be expanded, and simultaneous bidirectional communication is possible.

  In particular, unlike the optical fiber transmission technology, the spatial optical transmission technology enables simultaneous communication between multiple nodes, and therefore has good consistency with the above-described bus-coupled parallel processing architecture. As a related technique, it is described in Patent Document 1.

  This technology realizes optical communication between nodes installed on the end face of a flat light guide, and diffuses incident signal light and transmits it to the opposite end face to realize broadcast communication. By using multiple transmissions, multiple independent broadcast communications are performed simultaneously.

As a signal transmission system technology that applies such spatial light transmission, in order to alleviate the problem of transmission skew between signals and reduce the number of transmission lines, a plurality of electric signal lines are converted in parallel and serially. A serial bus system has been proposed in which a serial signal (serial data signal) is optically transmitted through a spatial light transmission medium.
Hideharu Amano, “Parallel Computer”, Shosodo, pp. 6-13 Junji Uchida, “9th Circuit Packaging Conference”, 15C01, pp. 201-202 H. Tomimura, et al., “Packaging Technology for Optical Interconnects”, IEEE Tokyo, No. 33, pp. 81-86, 1994 JP-A-10-123350

  In general, in serial transmission, a clock signal is embedded in a data signal by an encoding technique such as 8B10B code and transmitted, and a clock data recovery circuit extracts a clock signal and a data signal in a receiving circuit, thereby synchronizing clock to data. It has been realized.

  However, when signal transmission is performed from a plurality of slave nodes to one master node via a serial bus, the receiving circuit on the master node side needs to selectively receive serial signals from different slave nodes. When the transmission node is switched in the serial bus transmission, there is a problem that the overhead for re-extracting the clock signal in the reception node occurs from several tens of microseconds to several milliseconds, during which the signal transmission is interrupted.

  Accordingly, an object of the present invention is to provide a signal transmission system, a signal transmission method, and a program that can solve the above-mentioned problems and can perform data transfer between one-to-many nodes using a serial transmission line with a simple configuration. It is to provide.

  In order to achieve the above object, one aspect of the present invention provides the following signal transmission system.

[1] In a signal transmission system including a master node and a plurality of slave nodes that perform data transfer between the master node, the master node operates in synchronization with a reference clock signal, and the plurality of slave nodes A clock data recovery unit that extracts a clock signal embedded in the serial data signal from the signal, and a phase difference detection unit that detects a phase difference between the reference clock signal and the clock signal, and the plurality of slave nodes Each comprising a transmission timing control section for adjusting the transmission timing of the serial data signal so that the phase difference detected by the phase difference detection section is equal to or less than a predetermined value. .

  According to the signal transmission system having the above configuration, the phase of the clock signal embedded in the serial data signal transmitted from the slave node can be matched with the reference clock signal generated at the master node, so that the signal transmission is interrupted. Without switching, the slave node can be switched.

[2] The signal transmission system according to [1], wherein the master node and the plurality of slave nodes transmit and receive the serial data signal via a serial bus. According to this configuration, the number of signal lines can be reduced and the band can be increased.

[3] The signal transmission system according to [1], wherein the transmission timing control unit of the plurality of slave nodes sequentially adjusts the transmission timing of the serial data signal.

[4] A reception adjustment sequence in which the master node individually sets the adjustment of the reception timing of the serial data signal output from the master node for each slave node during a period when data transfer is not performed, and the slave A master timing adjustment unit that executes a transmission adjustment sequence for individually setting the transmission timing of the serial data signal output by the node for each slave node, the slave node according to a command from the master timing adjustment unit, A slave timing adjustment unit that adjusts transmission timing by adjusting reception timing during execution of the reception adjustment sequence and instructing the transmission timing control unit to change transmission timing during execution of the transmission adjustment sequence. The signal transmission according to the above [1], characterized by comprising: System.

[5] The signal transmission system according to [4], wherein the master timing adjustment unit performs processing in the order of the reception adjustment sequence and the transmission adjustment sequence.

[6] The signal transmission system according to [1], wherein data transfer between the master node and the slave node is performed via an optical transmission medium. According to this configuration, noise resistance is improved and multiplex transmission is possible.

[7] The signal transmission system according to [1], wherein the reference clock signal and the clock signal embedded in the serial data signal from the slave node are generated from the same oscillation source. According to this configuration, the phase of the clock signal can be matched with the reference clock signal with high accuracy.

[8] A first step of transmitting a serial data signal in which a reference clock signal is embedded from a master node to a slave node; and a clock signal embedded in the serial data signal transmitted from the slave node to the master node; A second step of detecting a phase difference with respect to the reference clock signal; and a third step of adjusting a transmission timing of the serial data signal from the slave node to the master node so that the phase difference is not more than a predetermined value. The signal transmission method characterized by including these steps.

[9] A program for causing a computer to execute the first to third steps according to [8].

  According to the present invention, since the phase of the clock signal embedded in the serial data signal transmitted from the slave node can be matched with the reference clock signal generated by the master node, the one-to-many node using the serial transmission path The data transfer between them can be satisfactorily performed with a simple configuration. By using the configuration of the present invention, when a plurality of slave nodes sequentially transfer data to the master node, no overhead occurs even when the slave node is switched, so that the transfer time can be shortened. For example, it is assumed that the transmission band of the serial transmission path is 1 GB / second, and 32 KB data is transferred from the first slave node and the second slave node to the master node. Here, the numerical value of 32 KB refers to a general block size that is set in a data transfer with a storage device by a commercially available database. Assuming that the overhead in the conventional method is 500 μsec, the total transfer time takes 564 μsec (= 32 KB / 1 GB × 2 + 500 μ), whereas in the present invention, 64 μsec (= 32 KB / 1 GB × 2) is sufficient.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the signal transmission system according to the first embodiment of the present invention.

  In the signal transmission system according to the present embodiment, between one master node 1 provided in the CPU 2 and slave nodes 3b, 3c, and 3d provided in a plurality of (for example, three) memories 5A to 5C, respectively. Data transfer is performed via the serial bus 4.

(Master node)
The master node 1 includes a parallel / serial conversion unit 10a, a transmission PLL (Phase Locked Loop) 12a, a serial / parallel conversion unit 11a, a frequency dividing circuit 13a, a phase difference detection unit 19a, a CDR unit (clock data recovery unit) 23a, and a master timing. An adjustment unit 20a is provided.

  The master node 1 is an interface with an external circuit, and receives the parallel data signal 100a, the synchronization signal (reference clock signal) 102a, and the timing adjustment control signal 110a, and receives the parallel data signal 101a and the timing adjustment status signal. 111a is output. In addition, the serial data signal 201a is input through the interface with the serial bus 4, and the serial data signal 200a is output.

  The transmission PLL 12a receives the synchronization signal 202a from the master timing adjustment unit 20a, and outputs a serial synchronization signal 250a obtained by multiplying the frequency.

  The parallel / serial conversion unit 10a receives the parallel data signal, the synchronization signal 202a, and the serial synchronization signal 250a, converts the parallel data signal into the serial data signal 200a, and outputs the serial data signal 200a. For example, if the parallel data signal is 40 bits and 50 Mbps, the synchronization signal 202a is 50 MHz, and the serial synchronization signal 250a is 500 MHz, the output serial data signal is 4 bits and each signal is 500 Mbps.

  The CDR unit 23a receives the serial data signal 201a, extracts a serial synchronization signal therefrom, and outputs it. In this embodiment, only the serial data signal 201a is input, but a reference clock signal can be separately input and extracted.

  The frequency dividing circuit 13a receives the serial synchronization signal from the CDR unit 23a and outputs the result of frequency division until the frequency becomes equal to the synchronization signal 202a.

  The serial / parallel converter 11a receives the serial data signal 201a, the output signal of the CDR unit 23a, and the output signal of the frequency divider circuit 13a, converts the serial data signal 201a into a parallel data signal, and outputs the parallel data signal. For example, if the serial data signal 201a is 4 bits and 500 Mbps, the synchronization signal is 50 MHz, and the serial synchronization signal is 500 MHz, the output parallel data signal is 40 bits and 50 Mbps each.

  The phase difference detection unit 19a detects a phase difference between the output signal of the CDR unit 23a and the serial synchronization signal that is the output of the transmission PLL 12a, and outputs the result to the master timing adjustment unit 20a. In this embodiment, the phase difference is detected from the serial synchronization signal, but a method of detecting the phase difference after dividing both input signals can also be applied.

  The master timing adjustment unit 20a outputs no parallel data signal 100a to the parallel-serial conversion unit 10a without performing any processing during the period of data transfer according to the instruction of the control signal 110a. When the output is connected to the parallel data signal 101a, the synchronization signal 102a and the synchronization signal 202a are connected, and the timing adjustment is started by the instruction of the control signal 110a, among the flowcharts shown in FIGS. The process corresponding to the master node 1 is executed.

(Slave node)
On the other hand, the slave nodes 3b, 3c, 3d are parallel-serial converters 10b, 10c, 10d, transmission PLLs 12b, 12c, 12d, serial-parallel converters 11b, 11c, 11d, frequency dividers 13b, 13c, 13d, slaves, respectively. Timing adjustment units 22b, 22c, 22d, CDR units 23b, 23c, 23d, transmission timing control units 24b, 24c, 24d, reception aligners 31b, 31c, 31d, and transmission aligners 32b, 32c, 32d are provided. With respect to the parallel / serial conversion units 10b, 10c, and 10d, the transmission PLLs 12b, 12c, and 12d, the serial / parallel conversion units 11b, 11c, and 11d, the frequency dividing circuits 13b, 13c, and 13d, and the CDR units 23b, 23c, and 23d, 1 is the same as the module included in FIG.

  The slave nodes 3b, 3c, and 3d are interfaces with external circuits, and receive parallel data signals 100b, 100c, and 100d and timing adjustment control signals 110b, 110c, and 110d, respectively, and parallel data signals 101b, 101c. , 101d and status signals 111b, 111c, 111d for timing adjustment are output. In addition, serial data signals 201b, 201c, and 201d are input through the interface with the serial bus 4, and serial data signals 200b, 200c, and 200d are output.

  The control signals 110b, 110c, and 110d are transmitted from the CPU 2 via a transmission path different from that of the serial bus 4.

  The transmission timing control units 24b, 24c, and 24d receive the synchronization signals 203b, 203c, and 203d extracted from the frequency dividing circuits 13b, 13c, and 13d, respectively, and shift the phases in accordance with instructions from the slave timing adjustment units 22b, 22c, and 22d. The signal obtained is output. Each phase shift amount is given independently.

  Although the phase of the frequency-divided signal is adjusted here, a method of adjusting the phase of the signal before frequency division and frequency-dividing the resulting signal may be used.

  Receiving aligners 31b, 31c, and 31d receive the output signals of the serial-to-parallel converters 11b, 11c, and 11d, respectively, and perform word alignment processing in accordance with instructions from the slave timing adjusters 22b, 22c, and 22d. Output to the adjusting units 22b, 22c, and 22d.

  The transmission aligners 32b, 32c, and 32d input transmission data from the slave timing adjustment units 22b, 22c, and 22d, respectively, and perform word alignment processing in accordance with instructions from the slave timing adjustment units 22b, 22c, and 22d. The data is output to the conversion units 10b, 10c, and 10d.

  The slave timing adjustment units 22b, 22c, and 22d transmit parallel data signals 100b, 100c, and 100d without performing any processing during the period of data transfer in accordance with the instructions of the control signals 110b, 110c, and 110d, respectively. Output to the aligner 32b, 32c, 32d, connect the output of the receive aligner 31b, 31c, 31d to the parallel data signal 101b, 101c, 101d, and the timing adjustment is activated by the instruction of the control signal 110b, 110c, 110d In this case, processing corresponding to the slave node 3 is executed in the flowcharts shown in FIGS.

(Alignment processing)
2A shows an example of an alignment sequence at the time of reception, FIG. 2B shows an example of an alignment sequence at the time of transmission, and FIG. 2C shows an example of the configuration of the aligner.

  When data is received by the slave node 3, alignment processing is performed as follows. First, as shown in FIG. 2A, the parallel data signal “1/2 /... / 10” in the master node 1 is converted into a serial data signal “1-2” by the parallel-serial converter (P / S). ... -10 "and transmitted. The serial data signal “1-2... -10” received by the slave node 3 is converted into a parallel data signal by the serial / parallel converter (S / P). At this time, if the phase of the synchronization signal and the serial data signal are different, the bit order of the original parallel data signal is shifted. For example, the parallel data signal is “5/6 /... Become. In response to an instruction from the slave timing adjustment unit 22, the reception aligner 31 performs alignment processing so that the data signal is aligned with the original parallel data signal “1/2 /... / 10”.

  At the time of data transmission in the slave node 3, alignment processing is performed as shown in FIG. The serial transmission path is the same as that shown in FIG. 2A, and the serial data signal is received with a shift of 4 bits due to the transmission delay time difference between the synchronization signal and the serial data signal. The master node 1 transmits the alignment information due to this shift to the slave node 3 in advance using a timing adjustment sequence described later. In response to this, the slave timing adjustment unit 22 instructs the transmission aligner 32 to perform a predetermined alignment process. First, the parallel data signal “1/2 /... / 10” in the slave node 3 is subjected to alignment processing by the transmission aligner 32 so that the signal becomes “5/6 /. It is converted into a serial data signal “5-6... -4” by a parallel / serial converter (P / S) and transmitted. The serial data signal “5-6... -4” received by the master node 1 is converted into the original parallel data signal “1/2 /... / 10” by the serial / parallel converter (S / P). Aligned.

  Thus, by performing the word alignment process at each transmitting node, the receiving node can receive data without being aware of switching of the transmitting node, so that the circuit configuration is simplified.

  In this example, the transmission aligner 32 and the reception aligner 31 can be configured using a 10-bit register 30a, a branch circuit 30b, and 10-input 1-output selectors SL1 to SL10 as shown in FIG. . With this circuit, a continuous 10-bit signal can be output from the 19-bit signal for two consecutive words transmitted on the serial bus 4. The register 30a holds the input 1-10 signals in synchronization with the clock. The branch circuit 30b receives a total of 19 bits of a signal 11-19 obtained by copying the input signals 1-9 and a signal 1-10 output from the register 30a, and outputs the signals to the selectors SL1 to SL10. Generate an input signal. Each of the selectors SL1 to SL10 is given a selection signal, and according to this, one output is output from each of the selectors SL1 to SL10, and a predetermined alignment process is executed. These selection signals are given from the slave timing adjustment unit 22.

(Operation of the first embodiment)
Next, a timing adjustment sequence other than the above will be described with reference to FIGS. All of these are executed by the master timing adjustment unit 20a and the slave timing adjustment units 22b to 22d. All or part of the timing adjustment sequence can be realized by a program.

(Overall flow)
FIG. 3 shows a flowchart of the entire sequence. When the processing is started (ST30) and the timing adjustment control signal 110a (110b to 110d) is detected (ST31), the status signal 111a (111b to 111d) is activated and a busy state is notified to the outside (ST31). ST32). Thus, input / output of the parallel data signals 100a (100b to 100d) and 101a (101b to 101d) is prohibited during the timing adjustment process.

  Next, a reception adjustment sequence is executed (ST33), and then a transmission adjustment sequence is executed (ST34). When these are finished, the busy state for the outside is canceled (ST35), and the whole is finished (ST36).

(Reception adjustment sequence)
FIG. 4 shows a flowchart of the reception adjustment sequence. In the following FIGS. 4 to 6, each processing block name starting with M represents a process performed by the master timing adjustment unit 20 a, and one starting with S represents a process performed by the slave timing adjustment units 22 b to 22 d. A thick arrow represents a signal exchange between the master node 1 and the slave node 3.

  When the reception adjustment sequence is started in the master timing adjustment unit 20a of the master node 1 (M40), the master timing adjustment unit 20a is activated and transmits a test pattern signal from the parallel / serial conversion unit 10a to all the slave nodes 3 (M41). ). It is assumed that this test pattern is stored in advance in a storage unit such as a memory in both the master timing adjustment unit 20a and the slave timing adjustment units 22b to 22d.

As a test pattern, for example, in the case of a 10-bit signal, the following repetitive pattern can be used.
Bit string “0001110101”
Bit string 2. “0011010101”
The conditions required for the test pattern depend on the transmission path specifications, but for example, the following is required.
Condition 1. 1. The logical value “1” occupies 40% to 60% in the bit string. It can be determined from the pattern itself which bit is the first bit. Bit strings 1 and 2 both satisfy conditions 1 and 2. In addition, a bit string for comma detection used for establishing Ethernet (registered trademark) communication is also applicable.

  Next, the master timing adjustment unit 20a continues to transmit the test pattern signal for a predetermined time (M42), and then ends the process (M43). Here, the fixed time represents a time sufficiently longer than the processing times of the processes S41 to S52 of the slave timing adjustment units 22b to 22d described below.

  Next, processing of the slave timing adjustment units 22b to 22d will be described. The following is executed in all slave nodes 3.

  When the process is started (S40), the test pattern signal transmitted by the process M41 is received (S41).

Optimal signal reception timing is set by the CDR units 23b to 23d (S42), the received test pattern is collated with the correct pattern stored in advance, and the collation result is stored in the memory. Here, for example, when the above bit string 1 is a correct pattern, the received test pattern is:
2. Bit string “10000111010”
Suppose that In this case, each bit is received correctly, but the position of the first bit is only shifted to the lower side by 1 bit, and a correct answer is obtained if word alignment is performed. Therefore, the following two are stored as the collation results.
Result 1. Whether all individual bits are received correctly.
Result 2. If the result 1 is OK, how many bits should be shifted to get the correct answer?

If the reception result is NG, it is determined that the reception timing cannot be set, and an error signal is output to the outside (S50). In the case of OK, the above result 2 (number of shifts) corresponding to the optimal reception timing is set for the reception aligners 31b, 31c, and 31d.
This completes the processing of the slave timing adjustment units 22b to 22d.

(Transmission adjustment sequence)
Next, the transmission adjustment sequence will be described with reference to FIGS. FIG. 5 shows the master node 1 and FIG. 6 shows the slave node 3, and both figures are connected by “A”, “B”, and “C” in each figure.

  When the transmission adjustment sequence is started in the master timing adjustment unit 20a of the master node 1 (M80), the master timing adjustment unit 20a is activated and an ID signal (= ID number set in advance to identify each slave node 3). Is transmitted as a data signal) from the parallel-serial converter 10a to all the slave nodes 3 (M81). Since the transmission adjustment sequence is executed by one-to-one transmission between each slave node 3 and the master node 1, a process M81 is required to designate the slave nodes 3 one by one from the master node 1 side.

  The master timing adjustment unit 20a continues to transmit the ID signal for a predetermined time (M82), and then receives the test pattern transmitted from the slave node 3 (M83). Here, the fixed time represents a time sufficiently longer than the processing times of the processes S81 to S85 by the slave timing adjustment units 22b to 22d described below. Next, processing of the slave timing adjustment units 22b to 22d will be described. The following processes of the slave timing adjustment units 22b to 22d are executed in all the slave nodes 3.

  In FIG. 6, when processing is started (S80), transmission timing is first initialized (S92). The ID signal transmitted by the process M81 is received (S81), and it is determined whether it is an ID signal or an end notification signal. If an end notification signal is received, the process ends (S91). When the ID signal is received, the ID number of each slave node 3 is collated (S82), and it is determined whether or not the own node is designated (S83). This determination result is held by storage means such as a register.

  As a result of the process S83, the slave node 3 designated by the ID signal transmits a test pattern signal to the master node 1 (S84). The test pattern signal is the same as the process M41 in FIG. Further, the slave node 3 not designated by the ID signal transmits a test pattern signal having all logical values “0” (S85). Process S84 and process S85 are executed at the same timing, and the signals are joined on the serial bus. Therefore, it is necessary to select the signal of the process S85 so that the test pattern signal of the process S84 is not affected by the merge and is correctly transmitted to the master node 1.

  Next, processing of the master timing adjustment unit 20a will be described. When the master timing adjustment unit 20a receives the test pattern (M83), the CDR unit 23a sets an optimum signal reception timing (M84), and collates the received test pattern with the stored correct pattern. The collation result is stored in the memory.

  Next, for the currently designated slave node 3, it is determined whether or not the output value of the phase difference detector 19a is equal to or less than a predetermined value (M86). It transmits to the slave node 3 together with the value of the phase difference (M90). Here, the timing change instruction signal is an instruction signal for changing the transmission timing from the slave node 3 and performing the test again. Next, after continuing to transmit the timing change instruction signal for a predetermined time (M95), the process returns to the process M83, and the processes M83 to M86 are executed. The fixed time in the process M95 is a time sufficiently longer than the process times of processes S86 to S87 and S83 to S85 by the slave timing adjustment units 22b to 22d described later.

  On the other hand, when the phase difference is equal to or smaller than the predetermined value by the process M86, a timing fixing instruction signal is transmitted (M89).

  Subsequently, it is determined whether or not the transmission timing adjustment has been completed for all slave nodes 3 (M91). If not finished yet, the ID number of the slave node 3 is updated (M92), and the transmission timing of the next slave node 3 is adjusted (M81). In the case of the end of adjustment, the end notification signal is continuously transmitted to the slave node 3 for a predetermined time by the processes M96 and M97. Here, the fixed time indicates a time sufficiently longer than the processing time of S81 by the slave timing adjustment units 22b to 22d. Finally, the final result and status are output (M93), and the process ends (M94).

  The slave timing adjustment units 22b to 22d receive the signal transmitted by the process M89 or M90 by the master timing adjustment unit 20a (S86).

  When the received signal is a timing change instruction signal, the transmission timing control units 24b to 24d are instructed to change the data transmission timing based on the phase difference (S87), and the process returns to step S83.

  If the received signal is a timing fixing instruction signal, the result is stored in the memory (S88) and set for the transmission timing control units 24b to 24d (S89). Further, after stopping the transmission of the test pattern to the master node 1 (S90), the process returns to S81.

  If a signal other than the above is received in process S86, the process returns to process S83 and the transmission of the test pattern signal is continued.

(Transmission timing)
FIG. 7 is a diagram showing the improvement effect of the transmission timing by the timing adjustment sequence executed by the signal transmission system of the present invention. The transmission timing between the slave node 3b and the master node 1 is shown as an example, but the same applies to the other slave nodes 3c and 3d.

  FIG. 7A shows a time chart when the timing adjustment is not performed. In this case, a phase difference is generated between the serial synchronization signal 250a and the serial data signal 201a due to a signal propagation delay from the slave node 3 to the master node 1, an element passage delay, and the like. Since this phase difference is different for each slave node 3, if the transmitting slave node 3 is switched, the CDR section 23a of the master node 1 must extract the serial synchronization signal each time, and the transmission between them is interrupted. The

  FIG. 7B shows a time chart after timing adjustment. By adjusting the phase of the serial synchronization signal 250b, the master node 1 eliminates the phase difference between the serial synchronization signal 250a and the serial data signal 201a. The CDR unit 23a can receive any signal from any slave node 3 at the same timing as the serial synchronization signal 250a. Therefore, even if the slave node 3 is switched, transmission is not interrupted.

  In the present embodiment, the timing is adjusted so that the phase of the signal 201a is approximately the same as that of the signal 250a regardless of which slave node 3 transmits, but it is not always necessary to match the signal 250a. . Any method can be applied as long as the phase difference between the signal as a reference and the signal 201a is approximately the same.

(Effects of the first embodiment)
According to the first embodiment described above, signal transmission between one-to-many nodes can be realized by the serial bus 4. In particular, in serial data transmission from the plurality of slave nodes 3 to the master node 1 side, the phase of the clock signal embedded in the serial data signal is matched with the reference clock signal on the master node side in advance, whereby the master node 1 Can receive data without interrupting transmission even when the slave node 3 is switched.

[Second Embodiment]
FIG. 8 is a block diagram showing a configuration of a signal transmission system according to the second embodiment of the present invention. In this embodiment, the serial bus portion in the first embodiment is divided into an optical demultiplexer 60, an optical multiplexer 61, an electro-optical converter 62 (62a to 62d), and an opto-electric converter 63 (63a to 63d). ). The other master node 1, slave nodes 3b to 3d, and signals in the respective units are the same as those in the first embodiment, and thus description thereof is omitted.

  In the second embodiment, serial data signals and frame signals transmitted from the respective units are converted into optical signals, which are respectively transmitted via optical transmission media such as optical fibers and an optical bus described later, and are electrically transmitted on the receiving side. Converted to a signal.

  The optical demultiplexer 60 includes one optical signal incident port and three output ports. The light guide is configured so that an optical signal having the same amount of light can be obtained at each exit port when an optical signal enters from the entrance port. As the optical demultiplexer 60, for example, a star coupler or the like can be used, and an optical bus described in JP-A-10-123350 or JP-A-10-123374 can also be used. These optical buses obtain signal light having a uniform light intensity level at the exit end face by diffusing the signal light inside the sheet-like optical transmission medium or at the entrance end face.

  The optical multiplexer 61 includes three optical signal incident ports and one outgoing port. The light guide is configured so that an optical signal having a similar light quantity can be obtained at the exit port regardless of which optical signal is incident from any of the entrance ports. As the optical multiplexer 61, a star coupler or an optical bus can be used as in the optical demultiplexer 60 described above.

  The electro-optical converter 62 converts an electrical signal output from each node into an optical signal and outputs the optical signal, and includes a light-emitting element such as a light-emitting diode or an LED and a drive circuit thereof.

  The photoelectric conversion unit 63 converts the optical signal output from the optical demultiplexer 60 and the optical multiplexer 61 into an electrical signal and connects it to each node. The light receiving element such as a photodiode and its output signal The amplifier circuit is configured.

  According to the second embodiment, since the optical transmission medium is used for the serial transmission path, noise resistance is improved and multiplex transmission is possible.

  In FIG. 8, the electro-optic converter 62 and the opto-electric converter 63 are separate blocks from each node, but each may be included in each node.

[Other embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. In addition, the constituent elements between the respective embodiments can be arbitrarily combined within the scope not changing the gist of the invention.

1 is a block diagram of a signal transmission system according to a first embodiment of the present invention. (A) is an example of the alignment sequence at the time of reception, (b) is an example of the alignment sequence at the time of transmission, and (c) is a diagram showing an example of the configuration of the aligner. It is a whole processing flow figure of the timing adjustment sequence which the signal transmission system concerning a 1st embodiment of the present invention performs. It is a processing flow figure of a reception adjustment sequence included in the timing adjustment sequence which the signal transmission system concerning a 1st embodiment of the present invention performs. It is a processing flowchart of a transmission adjustment sequence (master node) included in the timing adjustment sequence executed by the signal transmission system according to the first embodiment of the present invention. It is a processing flow figure of a transmission adjustment sequence (slave node) included in the timing adjustment sequence which the signal transmission system concerning a 1st embodiment of the present invention performs. (A) is a figure which shows a comparative example, (b) is a figure which shows the improvement effect of the transmission timing by the timing adjustment sequence which the signal transmission system which concerns on the 1st Embodiment of this invention performs. It is a block diagram of the signal transmission system which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Master node 3, b-3d Slave node 4 Serial bus 5A-5C Memory 10, 10a-10d Parallel serial converter 11a-11d Serial parallel converter 12a-12d Transmission PLL
13a to 13d Frequency dividing circuit 19a Phase difference detection unit 20a Master timing adjustment unit 22, 22b to 22d Slave timing adjustment unit 23a to 23d CDR unit 24b to 24d Transmission timing control unit 30a Register 30b Branch circuit 31, 31b Reception aligner 32, 32b Transmission aligner 60 Optical demultiplexer 61 Optical multiplexers 62a-62d Electro-optical converters 63a-63d Photo-electric converters 100a-100d, 101a-101d Parallel data signal 102a Synchronization signals 110a-110d Control signals 111a-111d Status signals 200a, 200b serial data signal 201a, 201b serial data signal 202a synchronous signal 203b synchronous signal 250a, 250b serial synchronous signal SL1-SL10 selector

Claims (9)

In a signal transmission system having a master node and a plurality of slave nodes that perform data transfer between the master node,
The master node operates in synchronization with a reference clock signal, extracts a clock signal embedded in serial data signals from the plurality of slave nodes, and includes a reference clock signal and the clock signal. A phase difference detection unit that detects a phase difference between
Each of the plurality of slave nodes includes a transmission timing control unit that adjusts the transmission timing of the serial data signal so that the phase difference detected by the phase difference detection unit is a predetermined value or less. Signal transmission system.   The signal transmission system according to claim 1, wherein the master node and the plurality of slave nodes transmit and receive the serial data signal via a serial bus.   The signal transmission system according to claim 1, wherein the transmission timing control unit of the plurality of slave nodes sequentially adjusts the transmission timing of the serial data signal. The master node outputs a reception adjustment sequence for individually setting the adjustment of the reception timing of the serial data signal output from the master node for each slave node during a period when data transfer is not performed, and the slave node outputs A master timing adjustment unit that executes a transmission adjustment sequence for individually setting the transmission timing of the serial data signal for each slave node;
The slave node adjusts a reception timing during execution of the reception adjustment sequence according to a command from the master timing adjustment unit, and changes a transmission timing to the transmission timing control unit during the execution of the transmission adjustment sequence. The signal transmission system according to claim 1, further comprising a slave timing adjustment unit that instructs transmission of the transmission timing.   The signal transmission system according to claim 4, wherein the master timing adjustment unit performs processing in the order of the reception adjustment sequence and the transmission adjustment sequence.   The signal transmission system according to claim 1, wherein data transfer between the master node and the slave node is performed via an optical transmission medium.   The signal transmission system according to claim 1, wherein the reference clock signal and the clock signal embedded in the serial data signal from the slave node are generated from the same oscillation source. A first step of transmitting a serial data signal in which a reference clock signal is embedded from a master node to a slave node;
A second step of detecting a phase difference between the clock signal embedded in the serial data signal transmitted from the slave node to the master node and the reference clock signal;
And a third step of adjusting a transmission timing of the serial data signal from the slave node to the master node so that the phase difference is equal to or less than a predetermined value.   A program for causing a computer to execute the first to third steps according to claim 8.

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