JP4788081B2 - Packet data output device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention identifies whether each piece of packet data constituting an input transport stream is a predetermined processing target, and if corresponding, performs the predetermined processing and then outputs the data in a predetermined format. More particularly, the present invention relates to a packet data output device that is incorporated in a transport stream decoder and provides a data interface such as data output, data replacement, and data insertion in units of packet data.
[0002]
[Prior art]
Conventionally, a request for performing secondary processing by performing various processes and editing on digital content has been limited only to content production or distribution sources such as broadcasting stations. However, due to recent advances in digital technology, the quality and quantity of digital distribution systems as infrastructure is enriched every day. In other words, a transport stream that has been implemented only by a broadcasting station or the like in the past due to the enhancement of the transport stream that provides digital content, the improvement of the hardware performance necessary for processing by the user, and the reduction of the cost. Environmental conditions are being prepared for users to enjoy editing and editing of packet data constituting a transport stream.
[0003]
However, in order to perform desired processing for each digital content on the user side, individual packet data constituting a transport stream that is sequentially input is selected, and further, processing corresponding to the selected packet data or In order to store digital content that has undergone desired processing, the packet data that has undergone processing or processing is reconstructed as a transport stream and output to an external data storage device. There is a need.
[0004]
As an example of such means, FIG. 15 shows a conventionally implemented device having a function of identifying, selectively extracting and outputting individual packet data constituting a transport stream. The transport decoder shown in the figure extracts only a packet data group constituting a specific single program from a single transport stream composed of packet data sequences forming each of a plurality of programs (Program). Output. In other words, as will be described later, the transport decoder has means for selectively extracting only specific packet data from a plurality of packet data constituting a single transport stream and outputting it at a predetermined timing. Is provided.
[0005]
The transport stream decoder TDAc includes a stream input device 500C that receives a transport stream TS supplied from an external transport stream source (not shown), a program packet filter PCF, a packet data processor 650C, and a main memory controller 700C. , A main memory 900C, a transport stream output unit 850C, and a TD controller TDCc that controls the operation of the entire transport stream decoder TDAc.
[0006]
First, the transport stream TS supplied from an external transport stream source (not shown) will be described with reference to FIG. The transport stream TS is composed of a plurality of packet data P each displayed as one frame. Each of these packet data P is given a unique packet identifier (Packet ID) PID and used for identification.
[0007]
These packet data P describe a plurality of program content packet data Pc forming the content for each α type program (α is an integer of 1 or more), and a packet identifier PID of the program content packet data Pc for each program. The program content packet data management table (Program Map Table) PMT, the program content packet data management table PMT corresponding to each program, and the program content management table (Program Association Table) PAT.
[0008]
The program content management table PAT and the program content packet data management table PMT having information for managing the program content packet data Pc are collectively referred to as management packet data PcA. FIG. 7 illustrates the configuration of the transport stream TS when at least three different programs 1, 2 and 3 are provided (α ≧ 3).
[0009]
Program content packet data Pc101_1, Pc101_2,... Is video data of program 1, and program content packet data Pc111_1, Pc111_2,. Similarly, program content packet data Pc201_1, Pc201_2,... Is video data of program 2, and program content packet data Pc211_1, Pc211_2,.
[0010]
Further, program content packet data Pc301_1, Pc301_2,... Are video data of program 3, and program content packet data Pc311_1, Pc311_2,. As described above, program content packet data Pc having video data is generically referred to as program video content packet data PcV, and program content packet data Pc having audio data is collectively referred to as program audio content packet data PcS.
[0011]
Needless to say, the number of programs (α) that can be provided is not limited to 3, and the transport stream TS includes only the necessary program content packet data Pc corresponding to the number of programs to be provided. Furthermore, depending on the contents of the program, program content packet data Pc corresponding to information (for example, character information) other than video and audio is also included.
[0012]
More specifically, in the transport stream TS, a program content management table PAT and a program content packet data management table PMT are arranged between the program content packet data Pc at a frequency determined from the transmission path and processing factors. Composed. In FIG. 7, among a plurality of program content packet data Pc forming all three types of programs 1, 2, and 3, program content packet data Pc101_1, Pc111_1, Pc201_1, Pc211_1, Pc301_1, and Pc311_1 are preceded. The program content packet data management tables PMT1, PMT2, and PMT3 in which the packet identifier PID of the program content packet data Pc for each program is described, and the programs corresponding to the respective packet identifiers PID of these program content packet data management tables PMT Management packet data PcA consisting of a program content management table PAT showing
[0013]
In this specification, the same member or signal is expressed by adding a common numeral or alphabetical code as an identifier, and even if the same member or signal is individually identified, The identifier is further expressed with a numerical or alphabetic suffix as an individual identifier. Therefore, when it is not necessary to individually identify the same member or signal, the identifier is represented without a suffix. Specifically, the program content packet data Pc101 is a general term for the program content packet data Pc101_1, Pc101_2,... Pc101_β (β is an arbitrary natural number). The same applies to the above-mentioned program content packet data Pc111, Pc201, Pc211, Pc301, and Pc401.
[0014]
The program content management table PAT describes packet identifiers PID of the program content packet data management table PMT for all programs included in the transport stream TS. That is, the packet identifier PID of the program content packet data management table PMT of program 1 is 100, the packet identifier PID of the program content packet data management table PMT of program 2 is 200, and the program content packet data management table PMT of program 3 The packet identifier PID is 300,..., And the packet identifier PID of the program content packet data management table PMT of the program α is described as α00.
[0015]
Further, before the program content packet data Pc101_2, Pc111_2, Pc201_2, Pc211_2, Pc301_2, and Pc311_2, the management packet data PcA composed of the above-mentioned program content packet data management tables PMT1, PMT2, and PMT3 and the program content management table PAT Has been placed again. If the transport stream TS includes four or more programs (α ≧ 4), the management packet data PcA includes program content packet data management tables PMT4 to PMTα, which are not clearly shown in FIG. Needless to say, the transport stream TS includes program content packet data Pc corresponding to each program.
[0016]
The arrangement frequency of the management packet data PcA varies depending on the type of packet data P included in the transport stream TS. Furthermore, the management packet data PcA is not necessarily arranged as a group of packet data P as illustrated in FIG. In some cases, other packet data P may be confused between the program content management table PAT, the program content packet data management table PMT, and the program content packet data Pc, which are constituent units of the management packet data PcA. is there.
[0017]
Next, each component of the transport stream decoder TDAc to which the above-described transport stream TS is input will be described with reference to FIG. The stream input device 500C receives a transport stream TS input from an external transport stream source (not shown), detects the head of the packet based on a synchronization byte or a synchronization signal in the stream, and programs the program sequentially from the head of the packet. Transfer to packet filter PCF.
[0018]
The program packet filter PCF, based on the packet identifier PID assigned to each of all the program content packet data Pc transferred from the stream input device 500C, the program video content packet data PcV of the specific program, the specific program The program audio content packet data PcS and the management packet data PcA of the specific program are selectively output. The packet identifier PID of the packet data to be output is instructed to the program packet filter PCF by the TD controller TDCc.
[0019]
The management packet data PcA extracted from all packet data P included in the input transport stream TS and the program content packet data Pc (PcV, PcA) forming the content of a specific program are selected together. Collectively called one program packet data string Pes.
[0020]
Among the program content packet data Pc constituting a plurality of programs included in the transport stream TS, management packet data PcA (PAT, PMT1), program video content packet data PcV constituting the program 1 (Pc101_1, Pc101_2,... ) And program audio content packet data PcS (Pc111_1, Pc111_2,...) Are extracted by the program packet filter PCF in the order of arrival at the transport stream decoder TDAc.
[0021]
The extracted program content management table PAT, program content packet data management tables PMT1 and PMT2, and program content packet data Pc101_1, Pc111_1, Pc101_2, Pc111_2,... Are in the order of arrival at the transport stream decoder TDAc. The selected single program packet data string Pes is output to the packet data processor 650C.
[0022]
The packet data processor 650C processes and processes each packet data in accordance with an instruction from the TD controller TDCc, and outputs the packet data string Pesd. The content of the processing is, for example, decoding of scrambled data in pay broadcasting, but the specific processing content is a known fact and will not be described here.
[0023]
The main memory controller 700C controls the main memory 900C to change the packet data string Pesd input from the packet data processor 650C into the management packet data PcA, the single program video content packet data string PssV, and the single program audio. Each content packet data string PssS is stored in a predetermined area of the main memory 900C.
[0024]
That is, the main memory 900C converts the packet data P included in the packet data string Pesd input from the packet data processor 650C via the main memory controller 700C into the management packet data PcA, the program video content packet data PcV, and Any one of the program audio content packet data PcA is selected and stored as management packet data PcA, single program video content packet data sequence PssV, and single program audio content packet data sequence PssS.
[0025]
Further, the main memory controller 700C reads out the video content packet data string PssV and the audio content packet data string PssS from the main memory 900C, and outputs them to the external device represented by the AV decoder 2000C as the packet data string Pss.
[0026]
The stream output unit 850C reconfigures the packet data string Pesd input from the packet data processor 650C as a transport stream, and outputs it to an external device (not shown).
[0027]
Note that the transport stream decoder TDAc generates a state signal SrWC indicating the operation state of each of the above-described components and outputs the state signal SrWC to the TD controller TDCc. Based on the status signal SrWC, the TD controller TDCc generates a control signal ScWC that controls the operation of each component of the transport stream decoder TDAc, and outputs the control signal ScWC to the transport stream decoder TDAc.
[0028]
In this way, the TD controller TDCc controls the entire operation of the transport stream decoder TDAc, and only the program content packet data Pc constituting a specific program from the transport stream TS input to the transport stream decoder TDAc. The data is extracted in the input order and output to an external device such as the AV decoder 2000C as the program packet data string Pss. The AV decoder 2000C sequentially decodes the program video content packet data PcV and the program audio content packet data PcS included in the input single program packet data sequence Pss to generate a video / audio signal Sav for viewing by the user. .
[0029]
Further, program content packet data Pc and management packet data PcA constituting a specific program are extracted from the transport stream TS input to the transport stream decoder TDAc, and reconfigured as a transport stream HSD for secondary use. Thereafter, the data is output to an external device such as a data storage device.
[0030]
The transport stream output from the stream output unit 850C will be described with reference to FIG. TS is an input transport stream, and each frame indicates a packet constituting the transport stream. As described above, the program content management table PAT, the program content packet data management tables PMT1, PMT2 and PMT3 for each program, the packet data Pc101 and Pc111 for program 1, the packet data Pc201 and Pc211 for program 2, and the packet data Pc301 for program 3 And Pc311 are arranged.
[0031]
In FIG. 11, among TS packets input to the transport decoder TDAc, packets constituting the program 1 and PMT1 and PAT are selected, processed and processed, and then output as a transport stream HSD.
[0032]
A specific example of processing / processing is descrambling. Descrambling refers to a process of decrypting content that has been encrypted so that only contracted subscribers can view paid program content.
[0033]
Packets that have been processed / processed are shown with a single quote “′” in the notation before processing / processing.
[0034]
The time T (HSDelay) from when packet data is input until it is output is determined by the data processing time in the transport decoder TDAc, and all packet data is output after T (HSDelay) time after input.
The frame enclosed by the dotted line is stuffed and output.
[0035]
In the output transport stream HSD, since the packets constituting the program 2 and the program 3 are deleted from the input transport stream TS, the PAT ′ of the output transport stream HSD is the same as the PAT of the input transport stream TS. Is different.
[0036]
That is, the PAT of PMT1, PMT2, and PMT3 corresponding to programs 1, 2, and 3 is written in the PAT of the input transport stream TS, but PMT1 corresponding to program 1 is written in the PAT 'of the output transport stream HSD. Only the PID must be listed.
[0037]
In this way, a method of outputting by replacing the PAT will be described with reference to FIG. Based on the PAT information stored in the main memory 900C, the TD controller TDCc generates a PAT ′ in which only the PID corresponding to the program 1 is written, and stores it in another area of the main memory 900.
[0038]
When the PAT is input from the packet data processor 650C, the stream output unit 850C requests the main memory controller 700C to read out the PAT ′ stored in the main memory 900C and output it instead of outputting the PAT. To do.
[0039]
This packet data replacement is not limited to PAT replacement, and packet data of a specific PID or packet data input at a specific timing can be replaced with data stored in the main memory 900C and output.
[0040]
For example, although the packet data string becomes discontinuous when the program is switched, packet data DIT (Discontinuity Information Table) indicating the discontinuity point can be inserted.
[0041]
FIG. 8 shows an example of the storage state of each program content packet data Pc in the main memory 900C. The main memory 900C has a video packet storage area A (video) for storing program content packet data Pc101_1, Pc101_2, Pc101_3, Pc101_4,... Which are program video content packet data PcV, and a program which is program audio content packet data PcS. And an audio packet storage area A (audio) for storing content packet data Pc111_1, Pc111_2, Pc111_3, Pc111_4,.
[0042]
Further, a PAT storage area A (PAT) for storing information of the program content management table PAT, a PAT 'storage area A (PAT') for storing information obtained by changing the program content management table PAT by the TD controller TDCc, a packet It has a DIT storage area A (DIT) for storing information indicating discontinuous points of the data string, and a PMT storage area A (PMTα) for storing information of the program content packet data management table PMT. Specifically, the program content packet data management table PMT1 for program 1 is stored in the program content packet data management table PMT storage area A (PMT1).
[0043]
The program content packet data Pc101_1, Pc101_2, Pc101_3, Pc101_4,... Are stored in the video packet storage area A (video) without any gap, thereby forming the program video content packet data string PssV. Similarly, the program content packet data Pc111_1, Pc111_2, Pc111_3, Pc111_4,... Are stored in the audio packet storage area A (audio) without any gap, thereby forming the program audio content packet data sequence PssS.
[0044]
As described above, the program video content packet data sequence PssV and the program audio content packet data sequence PssS configured in the main memory 900C are read as the program packet data sequence Pss as illustrated in FIG. 9 by the main memory controller 700C. And output to the AV decoder 2000C.
[0045]
[Problems to be solved by the invention]
The conventional transport stream decoder configured as described above, when a single transport stream is input, reproduces a program from the transport stream and presents it to the user, or processes and processes packet data. Therefore, it is sufficient for the purpose of outputting to an external data storage device or the like.
[0046]
However, in the case where a plurality of transport streams are input, in order to process a plurality of transport streams at the same time, the number of transport decoders described above is required as many as the number of input transport streams, which increases the scale of the apparatus. In other words, the structure becomes complicated, the processing load increases, the specification or the required processing cannot be changed, and the cost increases.
[0047]
The present invention is input in view of the above problems. plural It is an object of the present invention to provide a packet data output device that identifies whether each piece of packet data constituting a transport stream is a predetermined processing target, and outputs the packet data after performing the predetermined processing.
[0048]
[Means for Solving the Problems]
A first invention is a transport stream processing device that performs predetermined processing on a transport stream when a transport stream composed of a plurality of continuous packet data each having identification information attached thereto is input A packet data output device that is reconfigured and output as a transport stream after being subjected to predetermined processing,
Identification information input means for inputting output target packet data identification information for identifying packet data to be output;
Packet data holding means for holding each of the packet data for a predetermined time in the order of input;
The identification information given to the packet data held in the packet data holding means is read, and compared with the output target packet data identification information, the held packet data is the target of the output specified in advance. Output target packet data selection means for selecting whether there is,
A stream output unit configured to reconfigure and output a packet to be output as a transport stream.
[0049]
As described above, in the first invention, each packet data of the transport stream that is sequentially input is temporarily stored, and the stored packet data is subjected to predetermined processing / processing. Thereafter, stream output processing in units of packet data is enabled.
[0050]
A second invention is characterized in that, in the first invention, after the completion of the output process is detected, the packet data holding means is released for storing other packet data.
[0051]
According to a third aspect, in the first aspect, output processing is prohibited while data processing / processing to be performed before output processing of the packet data is not completed.
[0052]
A fourth invention is characterized in that, in the first invention, output processing is permitted after completion of data processing / processing to be performed before output processing of the packet data.
[0053]
In a fifth aspect based on the first aspect, the present invention further comprises an output buffer cell pointer indicating a buffer cell that is outputting packet data among the plurality of buffer cells, and the buffer cell allocator includes: The buffer cell shown is not assigned to packet data storage.
[0054]
A sixth invention includes a timer for generating time information when each input of the continuous packet data is started, the packet data holding means for storing the time information in a buffer cell together with packet data, and the packet data holding Output start instructing means for determining the timing to start outputting the stream based on the time information read from the means, and stream output means for reconfiguring and outputting the packet data as a transport stream.
[0055]
As described above, the sixth invention is characterized in that the packet data is output after a delay of a predetermined time with respect to the time information, so that the time interval of each input packet data is maintained and output. .
[0056]
A seventh aspect of the invention is a timer for generating time information when the end of each successive packet data is input, the packet data holding means for storing the time information in a buffer cell together with packet data, and the packet data holding Output start instructing means for determining the timing to start outputting the stream based on the time information read from the means, and stream output means for reconfiguring and outputting the packet data as a transport stream.
[0057]
As described above, in the seventh invention, by outputting packet data after a delay of a predetermined time with respect to the time information, the fixed delay value can be determined without depending on the input bit rate. Features.
[0058]
DETAILED DESCRIPTION OF THE INVENTION
(First Embodiment)
The packet data processing apparatus according to the first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, 5, 7, and 8. FIG.
[0059]
The packet data processing apparatus according to the present invention is a data output used in a transport stream decoder that selectively extracts and outputs content data of a plurality of programs included in a single transport stream TS in this embodiment. Configured as a device.
[0060]
In the present embodiment, all the packet data P constituting the transport stream TS that is sequentially input are individually buffered, and the individually buffered packet data P is identified, and the packet data P is identified. On the other hand, a packet data processing device having a function of outputting after processing desired by a user is newly devised.
[0061]
FIG. 1 shows a transport stream decoder TD1 incorporating the packet data processing apparatus DBA1 according to this example. The transport stream decoder TD1 includes a stream input unit TSR that receives a transport stream TS supplied in units of packets from an external transport stream source (not shown), a packet data processing device DBA1, a main memory controller 700, and a main memory. 900, a timer 510, and a controller PBAC1.
[0062]
The stream input unit TSR temporarily holds a transport stream TS supplied in units of packets from an external transport stream source (not shown) in an input buffer provided therein, and for each predetermined transfer unit TSd. Transfer to the packet data processing device DBA1. In this example, the transfer unit TSd is set to 8 bytes, but can be arbitrarily determined in consideration of the arbitration load and transmission efficiency in the packet data processing device DBA1.
[0063]
When the packet head is detected, a time stamp St indicating the arrival time of the packet data P and a transport stream identifier TSi indicating that the packet data P is the first transport stream TS are generated.
[0064]
The packet data processing device DBA1 manages and accumulates the transport stream TS of the transfer unit TSd sequentially supplied from the stream input device TSR in units of packet data P, and at the same time the program content packet data Pc included in the transport stream TS. Output individually and selectively. In the present embodiment, an example in which only the program content packet data Pc of one program is extracted from the transport stream TS including three programs and output as the selected multiple program packet data string Pem will be described.
[0065]
The main memory 900 temporarily stores the program packet data string Pem output from the packet data processing device DBA1 via the main memory controller 700, and stores the program packet data string Pms (program video content packet data string PmsV, The program audio content packet data string PmsS) is output to an external device (not shown) typified by an AV decoder.
[0066]
Also, the replacement packet data RD input from the TD controller TDC1 is temporarily stored via the main memory controller 700 and output to the stream output device 500.
[0067]
The main memory controller 700 temporarily holds the program packet data string Pem input from the packet data processing apparatus DBA1, controls the operation of the main memory 900, and stores the temporarily held program packet data string Pem as the main. In addition to outputting to the memory 900, the main memory 900 is controlled to form a program video content packet data string PmsV and a program audio content packet data string PmsS therein.
[0068]
The main memory controller 700 temporarily holds the data input from the TD controller TDC1, controls the operation of the main memory 900, outputs the temporarily held data to the main memory 900, and The main memory 900 is controlled to form replacement packet data RD therein.
[0069]
The timer 510 outputs time information St. Specifically, the counter is incremented when a predetermined time elapses, and the count value is output. The predetermined time is determined by the accuracy of the required time information. The maximum count value is large enough to ensure the uniqueness of time information.
[0070]
The TD controller TDC1 stores data structure information for each type of transport stream TS input to the transport stream decoder TD1 in advance. The TD controller TDC1 generates a transport stream structure signal STS indicating the data structure of the transport stream TS that is actually input, and outputs the transport stream structure signal STS to the stream input device TSR. Accordingly, the stream input device TSR is controlled to operate properly. In this case, the user may instruct the structure information stored in the TD controller TDC1 using the secondary processing request input device APR or the like.
[0071]
Instead of storing the data structure information of the transport stream TS in the TD controller TDC1 in advance, the user can use the secondary processing request input device APR to store the structure information of the transport stream TS that is actually input. You may make it instruct | indicate to TD controller TDC1. Further, the transport stream decoder TD1 may be configured to read the actually input transport stream TS and detect the data structure.
[0072]
The TD controller TDC1 controls the operation of the entire transport stream decoder TD1. The transport stream decoder TD1 generates a state signal SrW indicating the operation state of each component described above and outputs it to the TD controller TDC1. The TD controller TDC1 generates a control signal ScW for controlling the operation of each component of the transport stream decoder TD1 based on the state signal SrW, and outputs the control signal ScW to the transport stream decoder TD1. The generation of the status signal SrW and the control signal ScW and the control of the transport stream decoder TD1 are well-known techniques and will not be described.
[0073]
The packet data processor DBA1 includes a DMA bus arbitrator 210, a packet input start detector 220, a buffer cell allocator 230, a buffer cell allocation information storage 240, a write destination buffer cell designator 250, a packet buffer controller 260, a packet Buffer 270, storage completion buffer cell number memory controller 280, storage completion buffer cell number memory 290, packet access device 300, packet data processor 410, output order buffer cell number memory controller 530, output order buffer cell number memory 540, A stream output unit 500 and a packet selector 400 that determines whether the buffered packet data P is the desired packet data P are included.
[0074]
The DMA bus arbitrator 210 inputs / outputs packet data P between the stream input device TSR, the packet buffer controller 260, the packet selector 400, the packet data processor 410, the stream output device 500, and the main memory controller 700. Mediate.
[0075]
That is, the DMA bus arbitrator 210 arbitrates data access to the packet buffer 270 via the packet buffer controller 260. In particular,
Data transfer from the stream input device TSR to the packet buffer 270, data transfer from the packet buffer 270 to the packet selector 400, data transfer from the packet buffer 270 to the packet data processor 410, and from the packet data processor 410 to the packet buffer 270 The data transfer from the packet buffer 270 to the stream output device 500 and the data transfer from the packet buffer 270 to the main memory controller 700 are arbitrated.
[0076]
When the request signal Srq input from the stream input unit TSR is selected by arbitration, the DMA bus arbitrator 210 supplies the packet input start detector 220 with the packet head detection signal Sps and the transfer unit TSd.
[0077]
The packet input start detector 220 detects that the input of the transfer unit TSd is started for each packet data P based on the packet head detection signal Sps and the transfer unit TSd, and the input transfer unit TSd is stored in the packet buffer. This is supplied to the controller 260. Then, the packet input start detector 220 requests to allocate one of a plurality of buffer cells constituting the packet buffer 270 in order to store the packet data P that has been input in the transfer unit TSd. A request signal Sba is generated and output to the buffer cell allocator 230. Further, if buffer cell Bc is allocated, a write permission signal Sw is generated to indicate that writing of program content packet data Pc can be started with respect to the buffer cell, and write destination buffer cell designator 250 is designated. Output to.
[0078]
In response to the buffer cell request signal Sba, the buffer cell allocator 230 allocates a buffer cell to be used for storing packet data P that has been input based on allocation buffer cell information Iab described later. Then, buffer cell allocation information Iba indicating the allocated buffer cell is generated and output to the buffer cell allocation information storage 240.
[0079]
The buffer cell allocation information storage 240 stores the buffer cell allocation information Iba input from the buffer cell allocation unit 230. Further, the buffer cell allocation information storage unit 240 supplies the buffer cell allocation information Iba to the write destination buffer cell designator 250 and the storage completion buffer cell number memory controller 280. Further, the buffer cell allocation information storage unit 240 generates allocation buffer cell information Iab indicating the allocation status of each buffer cell Bc constituting the packet buffer 270 based on the buffer cell allocation information Iba and generates the buffer cell allocation unit 230. To give feedback.
[0080]
The write destination buffer cell designator 250 is indicated by buffer cell allocation information Iba input from the buffer cell allocation information storage 240 in response to the write permission signal Sw input from the packet input start detector 220. A write request signal Swd for instructing writing of the transfer unit TSd to the assigned buffer cell is generated and output to the packet buffer controller 260.
[0081]
The packet buffer controller 260 writes the transfer unit TSd supplied from the packet input start detector 220 in the buffer cell to which the packet buffer 270 is allocated in response to the write request signal Swd. Further, the packet buffer controller 260 detects that data for one packet data P has been written by counting the number of bytes of data written to the allocated buffer cell, and packetizes the one packet data P. A transfer end signal Stf indicating completion of accumulation in the buffer 270 is generated and output to the accumulation completion buffer cell number memory controller 280. As described above, the data size of one packet data P of the input transport stream TS is included in the data structure information stored in advance in the transport stream decoder TD1.
[0082]
Based on the buffer cell allocation information Iba input from the buffer cell allocation information storage 240 and the transfer end signal Stf input from the packet buffer controller 260, the accumulation completion buffer cell number memory controller 280 The buffer cell number signal Sbn indicating the buffer cell to which the data P has been written and the write point update signal Swp for advancing the write pointer PWP indicating the storage area to which the buffer cell number Nbc is written by one are generated, and the accumulation completion buffer cell number memory 290 is generated. Output to.
[0083]
The accumulation completion buffer cell number memory 290 records the buffer cell number Nbc indicated by the buffer cell number signal Sbn in the storage area indicated by the write pointer PWP, and then advances the position of the write pointer PWP in the accumulation completion buffer cell number memory by one. Thus, the area next to the area where the buffer cell number Nbc is recorded is indicated. In the present embodiment, the accumulation completion buffer cell number memory 290 is preferably composed of a ring memory, as will be described later with reference to FIG. 2, so that each time writing to the buffer cell is completed in this way. Then, the buffer cell number Nbc stored in the storage area of the accumulation completion buffer cell number memory 290 can be appropriately updated by advancing the write pointer PWP of the accumulation completion buffer cell number memory one by one.
[0084]
The packet access device 300 selectively accesses the packet data P stored in the buffer cell of the packet buffer 270 via the packet buffer controller 260 and the DMA bus arbitrator 210, and reads, references, edits, etc. After the above processing is performed, the original packet data P is overwritten and updated via the DMA bus arbitrator 210 and the packet buffer controller 260.
[0085]
The packet buffer controller 260 reads a packet identifier PID of packet data P stored in a buffer cell indicated by a read pointer PRP described later, extracts buffer packet identification information PIDe, and passes through the DMA bus arbitrator 210. To the packet selector 400.
[0086]
The packet data processor 410 receives the packet data P stored in the packet buffer 270 for each transfer unit TSd via the packet buffer controller 260 and the DMA bus arbitrator 210, and performs a predetermined process on the input data. Data processing is performed. Further, the data after the predetermined processing is written back to a predetermined area of the packet buffer 270.
[0087]
For example, processing such as descrambling of packet data in pay broadcasting is a known technique, and detailed description thereof is omitted.
[0088]
The packet data processing device DBA1 generates a state signal Sr indicating the operation state of each component described above and outputs it to the controller PBAC1. The controller PBAC1 generates a control signal Sc for controlling the operation of each component of the packet data processing device DBA1 based on the state signal Sr1, and outputs the control signal Sc to the packet data processing device DBA1. The control of the controller PBAC1 generated by the status signal Sr and the control signal Sc is a known technique and will not be described.
[0089]
Next, stream output will be described with reference to FIG.
[0090]
TS is an input transport stream, and one frame indicates a packet constituting the transport stream.
[0091]
The time information TS1 generated by the timer 510 at the time when the input of the packet packet1 is started is stored as the management information IM together with the stream identifier TSi together with the packet data in the buffer cell by the stream input unit TSR_1.
[0092]
When the packet selector 400 determines that the packet is a processing target, the controller PBAC1 checks the content of processing to be performed on the packet. As a result, when outputting the packet as a transport stream, the controller PBAC1 writes the buffer cell number Hbn and the buffer cell number Hbn in which the packet is stored in the packet output order buffer cell number memory controller 530. An area where the write pointer HWP indicating the storage area of the packet output order buffer cell number memory 540 is output and the write pointer HWP indicating the storage area of the packet output order buffer cell number memory 540 is advanced by 1 to record the buffer cell number Hbn Point to the next area. Note that the packet output order buffer cell number memory 540 is preferably formed of a ring memory, and buffer cell designation areas Hc1 to HcM are recorded continuously and cyclically.
[0093]
The packet output order buffer cell number memory controller 530 outputs the buffer cell number Hbn and the write pointer HWP of the packet output order buffer cell number memory 540 to the packet output order buffer cell number memory 540. Also, 1 is added to the write pointer HWP to indicate the area where the next buffer cell number is written.
[0094]
The packet output order buffer cell number memory 540 writes the buffer cell number Hbn to the storage area indicated by the write pointer HWP. Further, the buffer cell number SHr written in the recording area indicated by the read pointer HRP of the output order buffer cell number memory 540 is output to the stream output device 500.
[0095]
The packet buffer controller 260 detects the end of the transfer of the packet data P for one packet by counting the number of bytes output from the packet buffer 270 to the stream output device 500, and outputs the stream from the packet buffer 270. A transfer end signal Shf indicating that data transfer to the device 500 has been completed is output to the packet output order buffer cell number memory controller 530.
[0096]
When receiving the transfer end signal Shf, the packet output order buffer cell number memory controller 530 adds 1 to the read pointer HRP, and points to the recording area in which the buffer cell number to be output next is recorded.
[0097]
As described above, the data size of one packet data P is included in the data structure information stored in advance in the transport stream decoder TD1.
[0098]
When the stream output unit 500 receives the buffer number SHr of the packet output from the transport stream, the stream output unit 500 outputs a data signal Prq for requesting the packet data of the buffer number SHr to the DMA bus arbitrator 210. On the other hand, the DMA bus arbitrator 210 outputs the data PD of the buffer number SHr of the packet buffer 270 to the stream output device 500 for each transfer unit TSd via the packet buffer controller 260.
[0099]
The stream output device 500 outputs the management information IM of the received packet data to the output start instruction device 520.
[0100]
The output start instruction device 520 outputs the output start instruction signal ReqST when the time indicated by the timer 510 becomes equal to the value obtained by adding the time T (HSDelay) set by the TD controller TDC1 to the time stamp St extracted from the management information IM. Is output.
[0101]
When receiving the output start instruction signal ReqST, the stream output device 500 starts outputting the stream HSD. The stream output unit 500 outputs a data signal Prq for requesting packet data to the DMA bus arbiter 210 in order to obtain output data. On the other hand, the DMA bus arbitrator 210 outputs the data PD of the buffer number SHr of the packet buffer 270 to the stream output device 500 for each transfer unit TSd via the packet buffer controller 260.
[0102]
Thereafter, similar processing continues until the stream output for one packet is completed.
[0103]
Next, with reference to FIG. 2, the relationship among the buffer cell allocation information storage 240, the packet buffer 270, the accumulation completion buffer cell number memory 290, and the output order buffer cell number memory 540 will be briefly described. The packet buffer 270 includes N buffer cells Bc1 to BcN (N is a natural number of 2 or more) for temporarily storing the packet data P input via the packet input start detector 220. This is because one different buffer cell Bc is required for storing the packet data P and for reading the stored packet data P.
[0104]
Each of the buffer cells Bc can temporarily store, that is, buffer, data of a predetermined size. The capacity of the buffer cell Bc necessary for this is called the minimum buffer capacity MBU. The minimum buffer capacity MBU is appropriately set according to the data size of the packet data P constituting the packet data P. If the minimum buffer capacity MBU is set smaller than the packet size, the extraction of the program content packet data Pc can be controlled more finely. Increases the processing efficiency.
[0105]
On the other hand, if the minimum buffer capacity MBU is set larger than the packet size, for example, about several times, a plurality of packet data P can be stored in one buffer cell Bc. However, in this case, since a plurality of packet data P stored in one buffer cell Bc cannot be distinguished, control or access in units of packet data P cannot be performed.
[0106]
Therefore, the minimum buffer capacity MBU should be appropriately set based on the internal processing speed of the transport stream decoder, the input rate of the packet data P, the packet size, and the access frequency to the packet data P. In this example, the minimum buffer capacity MBU is determined so that one packet data P can be stored, and is specifically 188 bytes. If necessary, auxiliary data having a predetermined number of bytes for identifying or managing the packet data P may be added to the one packet data P and stored.
[0107]
However, if necessary, it may be set smaller than the packet size as described above, that is, one packet may be divided into a plurality of buffer cells Bc and stored. In this case, the minimum buffer capacity MBU is obtained by adding the management bytes corresponding to the management information for recording and managing the division information indicating the division state to the maximum data size after the division of the packet data P.
[0108]
The buffer cell allocation information storage 240 has buffer cell allocation information areas Ac1 to AcN corresponding to the buffer cells Bc1 to BcN of the packet buffer 270, respectively. The buffer cell allocation information storage 240 is based on the buffer cell allocation information Iba supplied from the buffer cell allocator 230k, and the buffer cell allocation corresponding to the allocated buffer cell Bcn (n is a natural number of 1 or more and N or less). Allocation identification data indicating the presence / absence of allocation is written in the information area Acn. That is, the buffer cell allocation information storage 240 is prepared with the same number of buffer cell allocation information areas Ac1 to AcN as the buffer cells Bc1 to BcN of the packet buffer 270.
[0109]
For example, the assignment identification data is binary data of 1 and 0, and the initial value is 0. When the buffer cell Bc1 is allocated, 1 is written in the buffer cell allocation information area Ac1 corresponding to the buffer cell Bc1. On the other hand, after the data written in the buffer cell Bc1 is read, 0 is written in the buffer cell allocation information area Ac1 based on the control signal Sc output from the controller PBAC1, and the buffer cell Bc1 is released. . In this way, the allocation status of each of the buffer cells Bc1 to BcN of the packet buffer 270 is expressed as a set of values in the buffer cell allocation information areas Ac1 to AcN, and is assigned to the buffer cell allocator 230 as allocation buffer cell information Iab. Supplied.
[0110]
The accumulation completion buffer cell number memory 290 has a buffer cell designation region Rc (Rc1 to RcM) for storing a buffer cell number Nbcn indicating a specific one of the buffer cells Bc1 to BcN of the packet buffer 270. Note that M is a natural number of 2 or more and N or less. Accumulation completion buffer cell number memory 290 is preferably formed of a ring memory, and buffer cell designation areas Rc1 to RcM are recorded continuously and cyclically. As a result, unlike the buffer cell allocation information storage unit 240, it is not necessary to prepare the same number of buffer cells Bc1 to BcN of the buffer cell allocation information storage unit 240. If M buffer cell designation areas Rc1 to RcM are prepared, good.
[0111]
The buffer cell designation region Rcm (m is a natural number between 1 and M) in which the buffer cell number Nbcn is to be written is indicated by the write pointer PWP of the storage completion buffer cell number memory. The buffer cell designation area Rcm from which the entered buffer cell number Nbcn is to be read is indicated by the read pointer PRP. The write pointer PWP of the storage completion buffer cell number memory is advanced based on the write point update signal Swp output from the storage completion buffer cell number memory controller 280 as described above, but the read pointer PRP is output from the controller PBAC1. On the basis of the control signal Sc.
[0112]
When the write pointer PWP of the accumulation completion buffer cell number memory has advanced from the position of the read pointer PRP, the buffer cell Bcn indicated in the buffer cell designation area Rcm indicated by the read pointer PRP has finished storing data and read it. It means that it is possible. When the write pointer PWP and the read pointer PRP of the storage completion buffer cell number memory indicate the same position, it means that there is no buffer cell Bcn in which data can be read.
[0113]
The output order buffer cell number memory 540 has a buffer cell designation area Hc (Hc1 to HcL) for storing a buffer cell number Nbcn indicating a specific one of the buffer cells Bc1 to BcN of the packet buffer 270. Note that L is a natural number of 2 or more and N or less. The output order buffer cell number memory 540 is preferably formed of a ring memory, and the buffer cell designation areas Hc1 to HcL are recorded continuously and cyclically. As a result, unlike the buffer cell allocation information storage unit 240, it is not necessary to prepare the same number of buffer cells Bc1 to BcN of the buffer cell allocation information storage unit 240. If L buffer cell designation areas Hc1 to HcL are prepared, good.
[0114]
The buffer cell designation region Lcl (l is a natural number between 1 and L) in which the buffer cell number Nbcn is to be written is indicated by the write pointer HWP of the output order buffer cell number memory. The buffer cell designation area Hcl from which the entered buffer cell number Nbcn is to be read is indicated by the read pointer HRP. The read pointer HRP of the output order buffer cell number memory is advanced based on the read pointer update signal Hrp output from the output order buffer cell number memory controller 530 as described above, but the write pointer HWP is output from the controller PBAC1. On the basis of the control signal Sc.
[0115]
When the write pointer HWP of the output order buffer cell number memory 540 is advanced from the position of the read pointer HRP, the buffer cell Bcn indicated in the buffer cell designation area Hcl indicated by the read pointer HRP is packet data to be output as a stream. Is in a state that exists. When the write pointer HWP and the read pointer HRP in the output order buffer cell number memory indicate the same position, it means that there is no packet data to be output as a stream.
[0116]
Next, operations of the stream input device TSR, the DMA bus arbitrator 210, and the packet buffer controller 260 will be briefly described with reference to the waveform diagram shown in FIG. As shown in FIG. 3, a transport stream TS made up of packet data P each consisting of 188 bytes of data is streamed from the external transport stream source one byte at a time in synchronization with the input transfer clock Ck. It is sequentially input to the TSR. In some cases, input is performed in 1-bit units instead of 1-byte units. However, since the processing contents are basically the same regardless of the input data units, the following is input in 1-byte units. Only will be described.
[0117]
The stream input unit TSR detects, for each packet data P, the packet head of the packet data P when the first 1-byte synchronous data is detected. Each time the head of the packet is detected, a packet head detection signal Sps is generated and output to the DMA bus arbitrator 210.
[0118]
The first stream input unit TSR further detects the time stamp St indicating the arrival time of the packet data P and the transport stream indicating that the packet data P is the first transport stream TS when the head of the packet is detected. An identifier TSi is generated. In other words, the transport stream identifier TSi indicates that the transport stream TS is input to the first input port group of the DMA bus arbitrator 210r, and is further input from the first stream input device TSR_1. It shows that.
[0119]
Note that the number of bytes of the time stamp St can be arbitrarily determined according to the accuracy of the time required in the transport stream decoder TD1, but in this example, it is preferably expressed by 3 bytes. Further, the number of bytes of the transport stream identifier TSi only needs to be sufficient to identify all the transport streams TS input to the transport stream decoder TD1, and is represented by 1 byte in this example. The first stream input device TSR_1 generates the management information IM by combining the time stamp St and the transport stream identifier TSi, and adds it to the head of the input packet data P.
[0120]
As described above, by assigning the time stamp St and the transport stream identifier TSi to the packet data P as the management information IM, the packet data P included in each different transport stream TS is correctly stored even after being stored in the packet buffer 270. It becomes possible to identify.
[0121]
If it is necessary to identify each of the plurality of transport streams TS, the time stamp Stε, the transport stream identifier TSiε, and the management information IMε are displayed. ε is a natural number indicating the number of the plurality of transport streams TS input to the stream input device TSR. Specifically, for the first transport stream TS1, the first packet head detection signal Sps1, the first request signal Srq1, the first data valid signal Sde1, the first transfer unit TSd1, the time stamp St1, It is expressed as a transport stream identifier TSi1 and a first stream input device TSR_1.
[0122]
Similarly, for the second transport stream TS2, the second packet head detection signal Sps2, the second request signal Srq2, the second data valid signal Sde2, the second transfer unit TSd2, the time stamp St2, the second Are expressed as a packet head detection signal Sps2, a transport stream identifier TSi2, and a stream input device TSR_2.
[0123]
Further, the stream input unit TSR generates a request signal Srq for requesting the DMA bus arbiter 210 to accept an input for each transfer unit TSd counting from the head of the packet, and outputs the request signal Srq to the DMA bus arbiter 210. .
[0124]
In response to the request signal Srq, the DMA bus arbitrator 210 arbitrates its input / output to prepare for input of the transfer unit TSd from the stream input unit TSR. When the preparation is completed, that is, after a predetermined time Ta from the request signal Srq, a data valid signal Sde is generated and output to the stream input device TSR. This time Ta is naturally determined due to the internal processing time including the packet data processing device DBA1, and some variation is allowed depending on the state of the packet data processing device DBA1.
[0125]
In response to the data valid signal Sde, the stream input unit TSR outputs the data of the packet data P stored in the internal buffer to the DMA bus arbitrator 210 for each transfer unit TSd.
[0126]
The packet buffer controller 260 converts the transfer unit TSd input via the DMA bus arbitrator 210 and the packet input start detector 220 based on the write request signal Swd to the buffer cell Bc to which the packet buffer 270 is assigned. Write to. When the packet data P for one packet is written, a transfer end signal Stf is generated and output to the storage completion buffer cell number memory controller 280.
[0127]
Next, the operation of the above-described transport stream decoder TD1 will be described in detail with reference to FIG. 4, FIG. 5, and FIG. As shown in the main flow in FIG. 4, the transport stream decoder TD1 starts its operation when the power is turned on.
[0128]
First, in the initialization subroutine of step # 100, the values of the write pointer PWP and the read pointer PRP in the accumulation completion buffer cell number memory 290 are both set to zero.
Further, the values of the write pointer HWP and the read pointer HRP in the output order buffer cell number memory 540 are both set to 0.
[0129]
In the “provide program and possible processing presentation of transport stream TS” subroutine at step # 200, the distributed program and the possible processing for each program are presented to the user. As will be described in detail later, the TD controller TDC1 reads the program content management table PAT stored in the PAT storage area A (PAT) of the main memory 900, and the program to be distributed and the transport stream decoder TD1 provide to the user A program content presentation signal Sp representing a processing function that can be generated is generated and output to the secondary processing request input unit APR. The secondary processing request input unit APR displays a list of distribution programs and provided processing functions to the user using appropriate display means such as a display based on the program content presentation signal Sp1. The user operates the secondary processing request input unit APR to select a desired program and processing function among the presented programs and processing functions.
[0130]
In the “process request detection for transport stream TS” subroutine at step # 300, the subsidiary process request input unit APR detects a user process request. Specifically, the secondary processing request input unit APR generates a processing request signal Se1 representing the user's selection contents based on the user's operation and outputs the processing request signal Se1 to the TD controller TDC1.
[0131]
In the “determination of processing contents for transport stream TS” subroutine at step # 400, specific processing contents to be performed on the transport stream decoder TD1 side are determined in response to a user processing request. Specifically, the TD controller TDC1 determines the program to be processed, the processing method for the program, the device required for the processing, and the like based on the processing request signal Se input from the secondary processing request input unit APR. Processing content information represented by information is generated.
[0132]
In this step, it is determined whether or not to perform stream output.
[0133]
In the “generate target packet data identification information PIDd” subroutine of step # 500, the target packet data identification information PIDd representing the packet data P to be processed is generated. Specifically, the TD controller TDC1 determines the packet identifier of the packet data P to be actually processed among the packet data P constituting the selected program based on the processing content information determined in step # 400. The PID is specified, and the processing target packet data identification information PIDd is generated.
[0134]
In step # 600, “packet data P accumulation of transport stream TS” subroutine, buffering of packet data P included in transport stream TS sequentially input to transport stream decoder TD1 to packet data processing apparatus DBA1 is started. Is done. The packet data P is stored in each packet data P / n unit (n is a natural number) in each of the buffer cells Bc of the packet data processing apparatus DBA1.
[0135]
The processing in this step will be described in detail later with reference to FIG. When the accumulation of the predetermined number of packet data P is completed, the processing of the next step # 700 is started. In other words, the process of step # 700 starts with the packet data P being accumulated in each of the predetermined number of buffer cells Bc among the plurality of buffer cells Bc of the data buffering device DBA1.
[0136]
In the “select packet data P to be processed in transport stream TS” subroutine at step # 700, the packet data P sequentially stored in the buffer cell Bc of the packet data processing apparatus DBA1 is selected. Specifically, it is determined whether the packet data P stored in one buffer cell Bc is the packet data P specified in step # 400 or whether it has the packet identifier PID determined in step # 500. Thus, selection as the processing target packet data P is performed. The processing in this step will be described in detail later with reference to FIG.
[0137]
In the “execute request processing for packet data P of transport stream TS” subroutine in step # 800, the user request processing of the content determined in step # 400 is executed for the packet data P selected in step # 700. Is done. In the present embodiment, only the program content packet data Pc of the specific program selected in step # 700 is extracted from the packet data P of the transport stream TS sequentially stored in the buffer cell Bc, and the stream is output. An example is shown, which will be described in detail later with reference to FIG. Needless to say, the request processing is not limited to the selective extraction of the program content packet data Pc constituting a specific program, and various digital processing can be applied.
[0138]
In the “stream output of post-process packet data P” subroutine of # 900, the packet data P processed in step # 800 is output as a transport stream.
[0139]
As described above, step # 600 is mainly passive processing by hardware, and steps # 700 to # 900 are mainly active processing by software. Therefore, step # 600 and steps # 700 to # 900 are preferably configured as parallel processing. For this purpose, it is desirable that the packet data P is stored in an appropriate number of buffer cells Bc in step # 600 before starting the target processing packet data P selection subroutine in step # 700. This will be described later with reference to FIG.
[0140]
As described above, in the present embodiment, only the program content packet data Pc having the packet identifier PID in the 100s out of all the packet data P stored in the buffer cell Bc and the management packet data PcA are selected in step # 700. Is done. In step # 800, the selected program content packet data Pc and management packet data PcA are directly output from the buffer cell Bc to the outside of the packet data processing device DBA1 as a selected program packet data string Pem.
[0141]
In addition, the data PD read from the buffer cell Bc in the stream output device 500 is reconstructed as a transport stream and output as a transport stream output HSD.
[0142]
If the user request processing is processing of specific program content packet data Pc, in the above-described example, the program content packet that forms a specific program among the selected management packet data PcA and program content packet data Pc. Only the data Pc is processed. This will be briefly described later with reference to FIG.
[0143]
Next, with reference to FIG. 5, the details of the packet data P accumulation operation of the transport stream TS by the packet buffer 270 in step # 600 will be described.
[0144]
First, in step S602, the transport stream TS is input from the external transport stream supply source to the stream input unit TSR. Then, the process proceeds to the next step S604.
[0145]
In step S604, the stream input device TSR detects the packet head of the input transport stream TS. Specifically, the stream input device TSR is based on the transport stream structure signal STS input from the TD controller TDC1, and based on the structure of the input transport stream TS, Detect the beginning. Then, the process proceeds to the next step S606.
[0146]
In step S606, the stream input unit TSR outputs the packet head detection signal Sps and the request signal Srq to the DMA bus arbitrator 210. The packet head detection signal Sps is output to the packet input start detector 220 via the DMA bus arbiter 210. Then, the process proceeds to the next step S608.
[0147]
In step S608, the DMA bus arbitrator 210 performs arbitration in preparation for input of the packet data P from the stream input unit TSR in the transfer unit TSd based on the request signal Srq. Then, the process proceeds to the next step S610.
[0148]
In step S610, the DMA bus arbitrator 210 outputs the data valid signal Sde to the stream input unit TSR. Then, the process proceeds to the next step S612.
[0149]
In step S612, in response to the data valid signal Sde, transfer of the packet data P from the stream input unit TSR to the DMA bus arbitrator 210 in the transfer unit TSd is started. The transfer unit TSd is output to the packet input start detector 220 via the DMA bus arbiter 210. Then, the process proceeds to the next step S614.
[0150]
In step S614, the packet input start detector 220 detects that the input of the transfer unit TSd is started based on the packet head detection signal Sps input in step S606. That is, since the data for one packet data P is transferred to the packet buffer 270 from the stream input device TSR a plurality of times for each transfer unit TSd, the transfer unit TSd input after the input of the packet head detection signal Sps is changed. By detecting this, the start of packet input is detected. Then, the process proceeds to the next step S616.
[0151]
In step S616, the packet input start detector 220 generates a buffer cell request signal Sba and outputs it to the buffer cell allocator 230, and also generates a write enable signal Sw and outputs it to the write destination buffer cell designator 250. . Then, the process proceeds to the next step S618.
[0152]
In step S618, the buffer cell allocator 230 uses the buffer cell information Iab supplied from the buffer cell allocation information storage 240 to buffer the transfer unit TSd for which the transfer has been started in step S612. Cell Bc is assigned. Then, the process proceeds to the next step S620.
[0153]
In step S620, the buffer cell allocator 230 generates buffer cell allocation information Iba indicating the buffer cell Bc allocated in step S612, and outputs it to the buffer cell allocation information storage 240. Then, the process proceeds to the next step S622.
[0154]
In step S622, the buffer cell allocation information storage unit 240 generates and stores allocation buffer cell information Iab based on the buffer cell allocation information Iba. Then, the process proceeds to the next step S624.
[0155]
In step S624, the buffer cell allocation information storage unit 240 outputs the buffer cell allocation information Iba input from the buffer cell allocation unit 230 to the write destination buffer cell designator 250 and the storage completion buffer cell number memory controller 280. Then, the process proceeds to the next step S626.
[0156]
In step S 626, the packet input start detector 220 generates a write permission signal Sw that permits writing of the transfer unit TSd to the buffer cell Bc of the packet buffer 270 and outputs it to the write destination buffer cell designator 250. To do. Then, the process proceeds to the next step S628.
[0157]
In step S628, in response to the write permission signal Sw, the write destination buffer cell designator 250 requests writing (accumulation) for the allocated buffer cell Bc indicated by the buffer cell allocation information Iba. A request signal Swd is generated and output to the packet buffer controller 260. Then, the process proceeds to the next step S630.
[0158]
In step S630, the packet buffer controller 260 converts the transfer unit TSd supplied from the packet input start detector 220 into a packet to the buffer cell Bc indicated by the write request signal Swd (buffer cell allocation information Iba). Writing (accumulation) of data P in the transfer unit TSd is started. Then, the process proceeds to the next step S632.
[0159]
In step S632, the request signal Srq is output from the stream input unit TSR to the DMA bus arbitrator 210 for each transfer unit TSd (step S606), and the DMA bus arbitrator 210 performs arbitration in response to the request signal Srq (step S608). The data valid signal Sde is output to the stream input device TSR (step S610), and the stream input device TSR starts transferring the next transfer unit TSd of the packet data P in response to the data valid signal Sde (step S614). The above-described operation is repeated.
[0160]
During this time, the packet buffer controller 260 counts the number of bytes of data written to the buffer cell Bc, and detects that the accumulation of the packet data P for one packet in the buffer cell has been completed. Further, a transfer end signal Stf is generated and output to the storage completion buffer cell number memory controller 280. The count number is obtained from the data size of the packet data P of the input transport stream TS indicated by the transport stream structure information stored in advance in the TD controller TDC1. The packet buffer controller 260 then proceeds to the next step S634.
[0161]
In step S634, the storage completion buffer cell number memory controller 280, based on the transfer end signal Stf and the buffer cell allocation information Iba, stores the buffer cell number signal indicating the buffer cell Bc that has completed storing the packet data P for one packet. Sbn is generated. That is, the buffer cell number signal Sbn corresponds to the buffer cell number Nbc of the buffer cell Bc indicated by the buffer cell allocation information Iba when the transfer end signal Stf is input. Then, the process proceeds to the next step S636.
[0162]
In step S636, the accumulation completion buffer cell number memory 290 records the buffer cell number Nbc indicated by the buffer cell number signal Sbn in the area indicated by the write point WP. Then, the process proceeds to the next step S638.
[0163]
In step S638, the accumulation completion buffer cell number memory controller 280 outputs the write point update signal Swp to the accumulation completion buffer cell number memory controller 280, and sets the write pointer PWP of the accumulation completion buffer cell number memory controller 280 to 1. Go forward.
[0164]
Next, details of request processing execution by the packet data processing apparatus DBA1 in step # 800 will be described with reference to the flowchart shown in FIG. In addition, in this figure, as described with reference to FIG. 4, a configuration that can be applied to the case where step # 600 and steps # 700 to # 900 are parallel processing or continuous processing is shown.
[0165]
First, in step S802, the TD controller TDC1 reads the values of the write pointer PWP and the read pointer PRP from the accumulation completion buffer cell number memory 290. The write pointer PWP of the storage completion buffer cell number memory is a parameter that alternatively indicates a buffer cell Bc to which the packet data P of the transport stream TS that is sequentially input is written, and the read pointer PRP is a buffer from which data is to be read. This is a parameter indicating a cell. Then, the process proceeds to the next step S804.
[0166]
In step S804, the TD controller TDC1 determines whether or not the values of the write pointer PWP and the read pointer PRP of the storage completion buffer cell number memory read in step S802 are the same. If they are the same, it is determined that there is no buffer cell Bc in which the accumulation of packet data for one packet has been completed, and the process returns to step S804 described above. This is to prevent access to the packet data P not completely stored in the buffer cell.
[0167]
On the other hand, if they are not identical in step S804, it means No, that is, there is a buffer cell Bc in which the packet data P is stored in a complete form. In other words, the packet data P means that at least one packet data P that is a candidate for processing for a user request is stored in the packet buffer 270. Then, the process proceeds to the next step S806.
[0168]
As described above, when the appropriate number of packet data P is not accumulated in the packet buffer 270 (worst, the packet data P is not completely stored in any buffer cell Bc), the processing requested by the user is performed. It is possible to avoid the situation of trying to execute. In addition, when an abnormality occurs in the accumulation of packet data P due to a reason on the transmission path of the transport stream TS, it is possible to prevent a processing abnormality due to an underflow.
[0169]
In step S806, a buffer cell Bc to be accessed is determined in order to check whether or not the stored packet data P as a processing target is actually a processing target. Specifically, the TD controller TDC1 reads the buffer cell number Nbcn from the buffer cell designation area Rc indicated by the read pointer PRP. If it is determined in step S810 to be processed later, the buffer cell Bc is accessed again in order to perform processing based on the user's request for the packet data P in later-described step S814. The Then, the process proceeds to the next step S808.
[0170]
In step S808, the packet identifier PID of the packet data P is read out from the packet data P stored in the buffer cell Bcn (packet buffer 270) corresponding to the buffer cell number Nbcn read out in step S806 and buffered. Packet identification information PIDe is generated. Then, the process proceeds to the next step S810.
[0171]
In step S810, the buffer packet identification information PIDe generated in step S808 matches the processing target packet data identification information PIDd generated in step # 500, and the transport stream identification information TSie is the processing target transport stream identification. It is determined whether or not the information TSid matches.
[0172]
The match in this case means that the packet identifier PID defined in the buffer packet identification information PIDe is indicated in the processing target packet data identification information PIDd but is included in the packet identifier PID.
[0173]
On the other hand, if Yes, that is, the currently accessed packet data P is a target of processing based on the above-described user request, the processing proceeds to the next step S812. At this time, the packet data P stored in the buffer cell Bc is confirmed as a processing target candidate from the processing target candidates.
[0174]
In step S812, the process determined in step # 400 described above is performed on the currently accessed packet data P. Then, the process proceeds to the next step S814.
[0175]
In step S814, the packet data P appropriately processed according to the user's request through the above-described steps S810 and S812 is read from the buffer cell BcN for each transfer unit TSd, and the packet buffer controller 260 is read. Via, the transfer to the DMA bus arbiter 210 is started. Then, the process proceeds to the next step S816.
[0176]
In step S816, the TD controller TDC1 repeatedly determines whether or not the data transfer to the DMA bus arbitrator 210 has been completed by counting the number of bits for each transfer unit TSd started in step S800. Note that when the data transfer is completed, the process proceeds to the next step S818. In this way, the user's request processing is completed for one packet data P through the above-described steps S802 to S816. Then, the process proceeds to the next step S818.
[0177]
In step S818, it is determined whether to perform stream output with reference to the result of determining whether to perform stream output in step # 400 of FIG. 4 described above.
[0178]
If stream output is to be performed, that is, if YES, the process proceeds to step S820.
[0179]
If stream output is not performed, that is, if NO, the process skips steps S820 and S822 and proceeds to the next step S824.
[0180]
In step S820, the packet determined to be stream output in step S818 is designated as a stream output target packet. That is, the buffer cell number of the corresponding packet is written in the area indicated by the write pointer HWP of the output order buffer cell number memory 540, and 1 is added to the write pointer HWP to write to the next output order buffer cell number memory 540. Prepare. Then, the process proceeds to the next step S826.
[0181]
On the other hand, if it is determined that the packet data P currently being accessed is No in step S810 described above, that is, if it is determined that the packet data P currently being accessed is not a target of processing based on the above-described user request, the processing is performed in the above-described steps Go directly to step S824, bypassing S820. As described above, in step S810, all the packet data P included in the sequentially input transport stream TS are individually processed based on matching between the buffer packet identification information PIDe and the processing target packet data identification information PIDd. Identify if there is. Then, only the packet data P to be processed is selected, the process based on the user's request is performed in step S812, and the packet data P obtained as a result of the process in steps S814 and S816 is outside the packet data processing apparatus DBA1. Output.
[0182]
In step S824, the TD controller TDC1 releases the buffer cell corresponding to the buffer cell number Nbcn indicated by the read pointer PRP. Specifically, the allocation identification data written in the buffer cell allocation information area Acn corresponding to the buffer cell number Nbcn read in step S806 is rewritten without allocation. Then, the process proceeds to the next step S826.
[0183]
In step S826, the TD controller TDC1 advances the value of the read pointer PRP in the accumulation completion buffer cell number memory 290. As a result, the next packet data P is set as a request processing candidate for the user.
[0184]
As described above, in order to selectively perform a desired process on a program included in a transport stream TS that is sequentially input, among all packet data P included in the transport stream TS, Only the corresponding packet data P is selectively processed. For this purpose, it is necessary to guarantee that the processing is performed for a predetermined time with respect to each packet data P that is sequentially input. Therefore, in the present embodiment, the process of confining the packet data P in a predetermined buffer cell Bc for a predetermined time is managed in the order in which each packet data P is input by the write pointer PWP of the storage completion buffer cell number memory.
[0185]
Then, the process of identifying whether the confined packet data P is a processing target by using the read pointer PRP and managing the process after being processed is managed. This series of operations is controlled and guaranteed by a hybrid configuration of hardware and software.
[0186]
Next, the details of the stream output by the stream output device 500 in step # 900 described above will be described with reference to the flowchart shown in FIG.
[0187]
First, in step 902,
It is determined whether or not the values of the write pointer HWP and the read pointer HRP in the output order buffer cell number memory are the same. If they are identical, it is determined that there is no buffer cell Bc in which processing and processing of packet data for one packet has been completed, and the processing returns to step S902 described above. This is to prevent access to the packet data P that has not been processed and processed completely in the buffer cell.
[0188]
On the other hand, if they are not identical in step S902, it means No, that is, there is a buffer cell Bc in which the packet data P is processed and processed in a complete form. In other words, it means that at least one packet data P which is a stream output processing target candidate for the user request exists in the packet buffer 270. Then, the process proceeds to the next step S904.
[0189]
As described above, when there is no appropriate number of packet data P in the packet buffer 270 (worst case, the packet data P is not completely processed or processed in any buffer cell Bc), the stream output is to be executed. You can avoid the situation.
[0190]
In step S904, the buffer cell Bc is determined in order to access the stored packet data P of the stream output target candidate. Specifically, the stream output device 500 reads the buffer cell number Nbcn from the buffer cell designation area Hc indicated by the read pointer HRP.
Then, the process proceeds to the next step S906.
[0191]
In step S906, the stream output device 500 reads the management information IM from the predetermined position of the packet data P stored in the buffer cell Bcn (packet buffer 270) corresponding to the buffer cell number Nbcn read in step S904. To the output start indicator 520.
[0192]
Then, the process proceeds to the next step S908.
[0193]
In step S908, the output start indicator 520 extracts time information St from the management information IM, adds the time information St to the delay T (HSDelay) instructed from the TD controller TDC1, and starts the stream output. Generate and maintain information. The predetermined time delay T (HSDelay) is a value determined by the processing time in the packet data output device TD1, such as processing / processing of packet data.
[0194]
Then, the process proceeds to the next step S910.
[0195]
In step S910, the output start indicator 520 compares the time information for starting the stream output with the current time information indicated by the timer 510.
[0196]
While the current time information does not match the stream output start time information, nothing is done and the process waits until they match. If the current time information matches the stream output start time information, the output start instruction signal ReqST is generated for the stream output device 500 to instruct the start of stream output.
[0197]
Then, the process proceeds to the next step S912.
[0198]
In step S912, the stream output device 500 outputs a data request signal Prq1 to the DMA bus arbitrator 210 in order to read out the data to be output from the stream stored in the packet buffer 260. The DMA bus arbitrator 210 performs bus arbitration in response to a data request, reads out data stream-outputted from the buffer cell BcN via the packet buffer controller 260 for each transfer unit TSd, and sends it to the stream output device 500. The data PD is output together with the data acknowledge signal Pde.
[0199]
The stream output device 500 takes in the stream output data PD when the data acknowledge signal Pde is active.
[0200]
That is, since the data received by the stream output device 500 is discrete, the data is stored once in an internal buffer, and then smoothed for reading at a predetermined interval to output the transport stream HSD.
[0201]
Then, the process proceeds to the next step S914.
[0202]
In step S914, the packet buffer controller 260 counts the number of transfer bits to determine whether or not the data transfer to the stream output device 500 has been completed. Note that when the data transfer is completed, the process proceeds to the next step S916.
[0203]
In step S916, the value of the read pointer HRP in the output order buffer cell number memory 540 is advanced. As a result, the buffer cell number written in the area of the output order buffer cell number memory 540 indicated by the read pointer HRP is set as the next stream output target packet.
[0204]
Then, the process proceeds to the next step S918.
[0205]
In step S918, the controller PBAC1 releases the buffer cell corresponding to the buffer cell number Nbcn indicated by the read pointer HRP. Specifically, the allocation identification data written in the buffer cell allocation information area Acn corresponding to the buffer cell number Nbcn read in step S904 is rewritten without allocation.
[0206]
(Second Embodiment)
A packet data output apparatus according to the second embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, as in the first embodiment, the packet data P of the plurality of input transport streams TS1 to TSε is individually subjected to specific processing, and then reconfigured as a transport stream. In addition to the output, measures are taken to reduce costs by reducing the packet buffer capacity.
[0207]
Therefore, except for the points described below, it has basically the same structure as the transport stream decoder TD1 shown in FIG.
[0208]
That is, in this embodiment, as shown in FIG. 13, the only difference is that the time stamp TS ′ added to the packet is a time stamp at the time when the rear end of the packet arrived.
[0209]
The advantage of using the time stamp at the time when the rear end of the packet arrives will be described with reference to FIG. 12 over the case of using the time stamp at the time when the front end of the packet arrived.
[0210]
FIG. 12 is a timing chart in the case where the input rate of the input stream is slower than that in FIG. When the input rate is low in this way, the time required to store packet data for one packet in the packet buffer and the time required to perform processing / processing required for the packet (T (TP)) The value of T (HSDelay) must be set larger than the added value.
[0211]
This is because if the value of T (HSDelay) is smaller than this, invalid data before necessary processing / processing is output. That is, the value of T (HSDelay) is determined by the stream input rate and the time required for processing and processing in the stream output apparatus of the present invention.
[0212]
Therefore, in order to correctly output a stream after performing processing and processing necessary for fluctuations in the input rate, it is necessary to set the value of T (HSDelay) sufficiently large with respect to the fluctuation range of the input rate. .
[0213]
However, if the value of T (HSDelay) is increased, the timing for releasing the buffer cell is delayed, and the number of buffer cells used increases. For this reason, it is necessary to increase the number N of buffer cells so that the packet buffer does not overflow, leading to an increase in cost.
[0214]
On the other hand, when the time stamp at the time when the rear end of the packet arrives is used, the value of T (HSDelay) does not depend on the input rate of the stream and is necessary for processing / processing in the stream output device of the present invention. It is determined only by time.
[0215]
Therefore, it is possible to cope with a change in input rate without increasing the number N of buffer cells.
[0216]
【The invention's effect】
The present invention is used for a transport stream processing apparatus that performs predetermined processing on a transport stream when a transport stream composed of a plurality of continuous packet data each having identification information attached thereto is input. Is a packet data output device that is reconfigured and output as a transport stream after being subjected to predetermined processing, and is input identification information for inputting output target packet data identification information for identifying packet data to be output Means, a packet data holding means for holding each of the packet data for a predetermined time in the order of input, and reading identification information given to the packet data held in the packet data holding means, Compared with output target packet data identification information, Output packet data selecting means for selecting whether or not the stored packet data is a predetermined output target, and stream output means for reconfiguring and outputting the packet to be output as a transport stream It was decided to prepare.
[0217]
With the above configuration, each piece of packet data of a transport stream that is sequentially input is temporarily stored, and after processing and processing prescribed in advance for the stored packet data, The stream output process can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the structure of a transport stream decoder device incorporating a packet data output device according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing the interrelationship between the buffer cell allocation information storage, the packet buffer, the storage completion buffer cell number memory, and the output order buffer cell number memory shown in FIG.
FIG. 3 is a waveform diagram showing various signals in the transport stream decoder shown in FIG. 1;
FIG. 4 is a flowchart showing main operations of the transport stream decoder shown in FIG. 1;
FIG. 5 is a flowchart showing detailed operations in the packet data P accumulation subroutine of the transport stream TS shown in FIG. 4;
6 is a flowchart showing detailed operations in a processing target packet data P selection subroutine of the transport stream TS shown in FIG. 4;
7 is an explanatory diagram showing a configuration of a transport stream input to the transport stream decoder shown in FIG.
8 is a schematic diagram showing an example of a packet data string input / output to / from the main memory shown in FIG.
FIG. 9 is an explanatory diagram showing a configuration of a single program packet data string output from the main memory shown in FIG. 1 via the main memory controller.
10 is a flowchart showing detailed operations in the stream output of post-process packet data P shown in FIG. 4;
11 is an explanatory diagram showing the configuration of the stream output HSD shown in FIG.
12 is an explanatory diagram showing the configuration of the stream output HSD when the bit rate of the input transport stream TS is slow compared to the configuration of the stream output HSD shown in FIG.
13 is a waveform diagram in the case where the time information time stamp TS given to the management information IM is the arrival time at the end of the packet data with respect to the waveform diagram shown in FIG.
14 is a waveform diagram showing various signals in the stream output device for the configuration of the stream output HSD shown in FIG.
FIG. 15 is a block diagram showing an example of the configuration of a conventional transport stream decoder
[Explanation of symbols]
TD1, TDAc transport stream decoder
TSR_1 Stream input device
DBA1 packet data processing device
PBAC1 controller
PCF packet filter
210 DMA bus arbiter
220 TSd input start detector
230 Buffer cell allocator
240 Buffer cell allocation information storage
250 Destination buffer cell designator
260 Packet buffer controller
270 packet buffer
280 Storage completion buffer cell number memory controller
290 Accumulation completion buffer cell number memory
300 packet access device
500 stream output device
510 timer
520 Output start indicator
700 Main memory controller
900 Main memory
TDC1 TD controller
Ac1 to AcN Buffer cell allocation information area
Bc1 to BcN buffer cells
Nbc1 to NbcN Buffer cell number
MBU Minimum buffer capacity
Rc, Rc1 to RcM Buffer cell designation area
ReqST output start instruction signal
Sbn Buffer cell number signal
Sc control signal
ScW control signal
Sde data valid signal
Sps packet head detection signal
Sr status signal
Srq request signal
SrW status signal
Stf Transfer end signal
Shf stream output end signal
Sw Write enable signal
Swd write request signal
Swp light point update signal
TS1 transport stream
TSd Transfer unit

Claims (3)

Identification information input means for inputting output target packet data identification information for identifying packet data to be output from a plurality of transport streams constituted by a plurality of continuous packet data to which identification information is assigned ;
A plurality of buffer cells for individually storing packet data constituting the plurality of transport streams, and a buffer cell selected as an output target by the output target packet data selection means to be described later in the plurality of buffer cells; And an output target buffer cell pointer indicating a buffer cell being output among the plurality of buffer cells, and the output selection buffer cell pointer has the same buffer cell as the output target buffer cell pointer. While the data is shown, access to the buffer cell by the stream output means to be described later is prohibited. When the output selection buffer cell pointer indicates a buffer cell different from the output target buffer cell pointer, access to the buffer cell by the stream output means to be described later is performed. Allow,
Accumulated in the buffer cell together with corresponding packet data time information that is output of a timer described later
A packet data holding means for releasing the buffer cell for storing other packet data after a prescribed output process completion detecting means described later detects the completion of the output process ;
The identification information given to the packet data held in the packet data holding means is read, and compared with the output target packet data identification information that is the output of the identification information input means , the held packet data is Output target packet data selection means for selecting whether or not the output target is defined in advance;
A timer for generating time information when each of the continuous packet data is input;
An output start instruction means for determining a timing for starting output of a stream based on the time information read from the packet data holding means;
The packet data holding means is accessed to reconstruct the packet data to be output as a reconstructed transport stream, and the reconstructed transport stream is output based on the output start instruction signal output from the output start instruction means and stream output means for
Prescribed output processing completion detection means for detecting completion of the prescribed output processing executed on the packet data stored in the packet data holding means ;
A packet data output device. The timer generates time information when each leading edge of the continuous packet data is input,
The output start instruction means outputs the stream after a time delay determined based on the stream input rate and the time required for processing and processing in the stream output means for the time information read from the packet data holding means. The packet data output device according to claim 1, wherein an instruction signal for starting is output . The timer generates time information when each trailing end of the continuous packet data is input,
The output start instruction means is an instruction signal for starting output of a stream after a time delay determined based on a time required for processing and processing in the stream output means with respect to the time information read from the packet data holding means The packet data output device according to claim 1, wherein:

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