JP4786855B2 - Memory film structure, memory element, semiconductor device and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory film structure, a memory element, a semiconductor device, and an electronic apparatus.
[0002]
[Prior art]
A conventional memory device is shown in FIG. 13 (see S. Tiwari and F. Rana et al, IEDM Dig., P521 (1995)). This memory element is a nanocrystal floating gate type memory element, and has a thickness of about 2 nm formed by thermal oxidation on the channel region between the source and drain regions 601 and 601 formed in the p-type silicon substrate 101. Tunnel oxide film 201, quantum dots 301 made of silicon fine particles having a particle diameter of about 5 nm, control oxide film 401 about 10 nm thick formed by low pressure CVD (chemical vapor deposition), and gate electrode 501 made of n + polysilicon. With. In this memory element, the relatively thin tunnel oxide film 201 formed in a plate shape, the quantum dots 301, the control oxide film 401, and the gate electrode 501 constitute a memory film structure.
[0003]
When writing information into the conventional memory device, a positive voltage is applied to the gate electrode 501 and electrons in the inversion layer formed in the channel region are injected into the quantum dots 301 through the tunnel oxide film 201. To capture.
[0004]
When reading information from the memory element, a positive voltage is applied to the gate electrode 501 and a potential difference is applied between the source and drain regions 601 and 601 to detect a drain current. Detecting the state of trapping electrons.
[0005]
When erasing information in the memory element, a negative voltage is applied to the gate electrode 501 so that electrons captured by the quantum dots 301 are transmitted through the tunnel oxide film 201 and emitted to the channel region.
[0006]
[Problems to be solved by the invention]
However, in the conventional memory element, electrons are transmitted through the tunnel oxide film 201 located on the channel side of the quantum dots 301 when writing and erasing information, so that the tunnel oxide film 201 is easily deteriorated and the tunnel oxide film 201 is easily deteriorated. There is a problem that electrons are trapped in the oxide film 201 and the memory operation tends to be inaccurate.
[0007]
Accordingly, an object of the present invention is to provide a memory film structure in which a gate insulating film can be prevented from being deteriorated and a memory element capable of stable operation can be configured.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a memory film structure of the present invention comprises an insulating film formed on a semiconductor substrate and containing conductive fine particles, and a conductive film formed on the insulating film. The fine particles are arranged in the vicinity of the conductor film. The insulating film includes a convex film portion that covers the conductor film side of the conductor fine particles and protrudes toward the conductor film side. Since the convex film portion covers the conductive fine particles in the vicinity of the conductive film and protrudes toward the conductive film side, the conductive fine particles and the conductive film are interposed via the convex film portion. The contacting part becomes relatively large. Therefore, the conductive fine particles and the conductive film can transfer a relatively large amount of charge in a shorter time than when the boundary surface between the insulating film containing the conductive fine particles and the conductive film is formed flat. . As a result, a memory film structure capable of memory operation at a relatively high speed is obtained.
[0009]
Since the conductive fine particles are arranged in the vicinity of the conductive film side, charge transfer is performed between the conductive fine particles and the conductive film. Therefore, since almost no charge is transmitted through the semiconductor substrate side of the insulating film, deterioration of the insulating film on the semiconductor substrate side is effectively prevented, and deterioration of hysteresis characteristics of the memory film structure is effectively prevented. Therefore, a memory film structure that can be rewritten at high speed and has stable performance can be obtained.
[0010]
Here, the convex film portion of the insulating film that covers the conductor film side of the conductor fine particles and protrudes toward the conductor film side has a shape that follows the shape of the conductor fine particles on the conductor film side. It is preferable to have. As a result, a portion where the conductive fine particles are in contact with the conductive film through the convex film portion of the insulating film can be effectively increased in area. In addition, since the thickness of the convex film portion of the insulating film can be set to a predetermined thickness, a memory film structure with little variation in characteristics can be obtained.
[0011]
In the present specification, the fine particles mean particles having dimensions of nanometer (nm) order or less.
[0012]
Furthermore, the present invention In the memory film structure, the thickness of the convex film portion of the insulating film is made thinner than the thickness of the insulating film on the side of the semiconductor substrate with respect to the conductive fine particles. When a potential difference is applied between the semiconductor substrate and the conductor film, charges are transferred between the conductor fine particles and the conductor film. Therefore, since the portion of the insulating film between the conductive fine particles and the semiconductor substrate has less charge transmission, deterioration of the insulating film on the semiconductor substrate side can be prevented. As a result, a highly reliable memory film structure can be obtained.
[0013]
In addition, since the insulator portion between the conductive fine particles to which the charge is transferred and the conductive film is relatively thin, the time required for the transfer of the charge can be made relatively short, and the charge can be transferred. The potential difference to be applied between the semiconductor substrate and the conductor film can be made relatively small. Therefore, a memory film structure with high speed operation and low power consumption can be obtained.
[0014]
[0015]
In the memory film structure of one embodiment, a second conductor film is provided in the insulating film so as to be located closer to the semiconductor substrate than the conductor fine particles, and the conductor is provided on the second conductor film. The electric charge captured by the fine particles is retained. Since the second conductor film has less variation in charge distribution when holding charges, a memory film structure with less variation in characteristics than holding charges in the conductor fine particles can be obtained.
[0016]
In the memory film structure of one embodiment, second conductive fine particles are provided in the insulating film so as to be located closer to the semiconductor substrate than the conductive fine particles, and the conductive material is provided on the second conductive fine particles. Charges captured by the conductive fine particles on the film side are retained. Since the conductive fine particles on the conductive film side exhibit a Coulomb blockade effect, this memory film structure has a remarkable hysteresis characteristic, and as a result, an improvement in charge reading characteristics and an improvement in charge retention characteristics can be realized. .
[0017]
Since the memory element according to one embodiment includes the field effect transistor formed using the memory film structure, the gate insulating film of the transistor can be hardly deteriorated, and charge trapping in the gate insulating film can be reduced. Therefore, it is possible to obtain a memory element having stable characteristics, high reliability, and low power consumption and capable of operating at high speed.
[0018]
In the memory device of one embodiment, since the memory film structure is formed on an SOI (Silicon on Insulator) substrate, the junction capacitance between the source region and the drain region of the transistor formed using the memory film structure and the body is increased. As a result, a memory element having good characteristics can be formed. Further, since the source region and the drain region can be formed shallowly on the SOI substrate, the memory element can be miniaturized while suppressing the short channel effect.
[0019]
Since the semiconductor device of one embodiment includes a memory circuit in which the memory elements are integrated, a semiconductor device that can operate at a low power supply voltage and has low power consumption can be obtained.
[0020]
The semiconductor device according to one embodiment includes a logic circuit and the memory circuit mixedly, and the memory circuit can operate at a low electric voltage. Therefore, the power supply of the memory circuit and the power supply of the logic circuit can be made common. Therefore, a conventional booster circuit for a memory circuit can be eliminated, and a small semiconductor device can be obtained. In addition, since the memory circuit of the present invention is integrated, the memory circuit can be more highly integrated than ever. Therefore, in the semiconductor device of this embodiment, the ratio of the memory circuit and the logic circuit portion related to the memory circuit to the entire integrated circuit can be reduced. Therefore, it is possible to obtain a semiconductor device which is smaller than the conventional one, has the same storage capacity, and is highly functional. Alternatively, a semiconductor device having the same dimensions as the conventional one and a larger storage capacity than the conventional one can be obtained.
[0021]
Since the electronic device according to one embodiment includes the semiconductor device with high functionality and low power consumption, an electronic device with high functionality and low power consumption can be obtained. Therefore, for example, a mobile phone having a high function and a long battery life can be configured.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0023]
(First embodiment)
1A and 1B are cross-sectional views showing the memory film structure of the first embodiment of the present invention. FIG. 1A is a cross-sectional view of the entire memory film structure, and FIG. 1B is an enlarged cross-sectional view of a portion of the memory film structure of FIG. In this memory film structure, a silicon oxide film 202 as an insulating film containing silicon fine particles 302 as conductive fine particles is formed on a semiconductor substrate 102 as a first electrode. On this silicon oxide film 202, a polysilicon film 502 is formed as a conductor film which is a second electrode. The silicon fine particles 302 are arranged in the vicinity of the polysilicon film 502 in the silicon oxide film 202. The silicon oxide film 202 includes a convex film portion 202a that covers the polysilicon film 502 side of the silicon fine particles 302 and protrudes toward the polysilicon film 502 side. The convex film portion 202a of the silicon oxide film has a substantially dome shape following the shape of the silicon fine particles 302.
[0024]
The convex film portion 202a of the silicon oxide film is formed to a thickness of d2, while the portion of the silicon oxide film 202 closer to the semiconductor substrate 102 than the silicon fine particles 302 is formed to a thickness of d1 or more. The thickness d2 above the silicon fine particles 302 of the silicon oxide film 202, the thickness d1 below the silicon fine particles 302 of the silicon oxide film 202, and the particle size of the silicon fine particles 302 are on the order of 1 nm to 10 nm. The dimensions are formed.
[0025]
However, when d1 and d2 are excessively small with respect to the dimensions of the respective parts of the silicon oxide film 202, the tunnel current increases due to the tunnel effect, and the function of the silicon oxide film 202 as an insulating film is lost. On the other hand, when d2 is excessively large, the transmission of charges is hindered, and it is necessary to apply a high voltage when rewriting charges. In this case, there is a risk of causing dielectric breakdown between the silicon fine particles 302 and the polysilicon film 502. is there. Accordingly, the d1 is preferably about 2.5 nm to 8 nm, and the d2 is preferably about 1.5 nm to 4 nm.
[0026]
The silicon fine particle 302 has a large quantum size effect when the particle size is too small, and a large current is required for charge injection / discharge. On the other hand, when the particle size is too large, the memory film structure is formed. When the element used is miniaturized, the variation in the number of silicon fine particles from element to element may increase and the element characteristics may vary, and the element miniaturization itself becomes difficult. Therefore, the particle diameter of the silicon fine particles is preferably about 1 nm to 7 nm. In the present embodiment, the silicon fine particles 302 have a particle size of about 3 to 6 nm.
[0027]
Further, the silicon insulating film 202 is formed such that the thickness d1 of the lower part of the silicon fine particle 302 is larger than the thickness d2 of the upper part of the silicon fine particle 302 so that d1> d2. Specifically, d1 is about 3 to 5 nm, and d2 is about 1 to 3 nm. With this configuration, in the silicon insulating film 202, the lower part of the silicon fine particles 302 is thicker than the upper part to reduce the tunnel probability, thereby suppressing the movement of charges. That is, when a potential difference is applied between the semiconductor substrate 102 and the polysilicon film 502, the silicon fine particles 302 and the polysilicon film 502 mainly transfer charges, while the silicon fine particles 302 and the semiconductor substrate 102 Almost no charge is exchanged.
[0028]
Here, with respect to the insulating film containing silicon fine particles, the upper portion of the silicon fine particles and the lower portion of the silicon fine particles are made of different materials, so that the electric potential of the lower portion of the insulating film is higher than that of the upper portion. May be.
[0029]
When injecting charges into the memory film structure having the above structure, a negative voltage is applied to the polysilicon film 502 serving as the second electrode with respect to the semiconductor substrate 102 serving as the first electrode. As a result, as shown by arrows A, A... In FIG. 2A, electrons pass through the upper portion of the silicon oxide film 202 from the polysilicon film 502 and are injected into the silicon fine particles 302. Arrows A, A... Schematically show how electrons are injected into the silicon microparticles 302.
[0030]
FIG. 2B shows a memory film structure in which the surface of the silicon oxide film 1202 is formed flat for comparison. In the memory film structure of FIG. 2B, when a negative charge is applied to the polysilicon film 1502 with respect to the semiconductor substrate 1102, electrons injected from the polysilicon film 1502 into the silicon microparticles 1302 are indicated by an arrow B. Only the narrowest portion between the polysilicon film 1502 and the silicon fine particles 1302 of the silicon oxide film 1202 is transmitted. Therefore, it takes time to inject electrons into the silicon fine particles 1302.
[0031]
On the other hand, in the memory film structure of this embodiment, as shown by arrows A, A... In FIG. 2A, electrons pass through a relatively wide range above the silicon fine particles 302 of the silicon oxide film 202. Electrons are injected into the silicon fine particles 302 in a short time.
[0032]
In the memory film structure, when discharging charges from the silicon fine particles 302, a positive voltage is applied to the polysilicon film 502 with respect to the semiconductor substrate 102. As a result, in a direction opposite to the arrows A, A... In FIG. 2A, the silicon fine particles 302 are directed from the silicon fine particles 302 toward the polysilicon film 502 in a relatively wide range above the silicon fine particles 302 of the silicon oxide film 202. The electrons are transmitted. This electron emission is also performed in a short time, similar to the electron injection.
[0033]
When electrons are injected into and emitted from the silicon fine particles 302, when a voltage is applied to the polysilicon film 502 with respect to the semiconductor substrate 102, almost no charge enters and leaves between the semiconductor substrate 102 and the silicon fine particles 302. . Therefore, defects and charge traps in the vicinity of the interface between the semiconductor substrate 102 and the silicon oxide film 202 can be prevented. In addition, since almost no electric charge enters and exits between the semiconductor substrate 102 and the silicon fine particles 302, the injection and emission of electrons between the polysilicon film 502 and the silicon fine particles 302 can be executed efficiently. Therefore, the memory film structure of the present embodiment can realize high speed operation and low power consumption.
[0034]
With respect to the memory film structure, the change in capacitance when the applied voltage between the semiconductor substrate 102 and the polysilicon film 502 was changed was measured. Specifically, the applied voltage was decreased from + 3V to −3V, and then increased from −3V to + 3V. The change in capacity in this case was measured, and the horizontal axis represents the applied voltage and the vertical axis represents the capacity. As a result, the curve that appears when the applied voltage increases from -3V to + 3V shifts in the positive direction of the voltage, and exhibits a hysteresis characteristic, rather than the curve that appears when the applied voltage decreases from + 3V to -3V. . The amount of shift of the curve in this case was an amount corresponding to about 0.2 V at the maximum. Therefore, it is possible to determine the information writing state and the erasing state by applying a voltage in a voltage region exhibiting hysteresis characteristics and measuring the capacitance at that time. For example, since the capacity when electrons are injected is larger than the capacity when electrons are emitted, if the measured capacitance value is larger than a predetermined value, the writing state and the measured capacitance value are predetermined. When the value is smaller than the value, it can be determined that the data is erased. Further, from the result of measuring the capacitance by changing the applied voltage from -3V to + 3V, it was found that information was written when the applied voltage was -3V, and information was erased when the applied voltage was + 3V.
[0035]
In the present embodiment, the convex film portion 202a of the silicon oxide film has a substantially dome shape following the shape of the silicon fine particle 302. The convex film portion of the silicon oxide film is contained in the silicon oxide film. It may have other shapes corresponding to the shape of the silicon fine particles. In short, the convex film portion of the insulating film has a shape corresponding to the shape of the conductive fine particles contained in the insulating film, and the conductive fine particles are in contact with the conductor film via the convex film portion. It is only necessary that the portion has a relatively large area and the distance between the conductive fine particles and the conductive film is a predetermined distance.
[0036]
( First reference example )
3 (a) and 3 (b) As a first reference example It is sectional drawing which shows the memory film structure. 3A is a cross-sectional view of the entire memory film structure, and FIG. 3B is an enlarged cross-sectional view of a portion of the memory film structure of FIG. In this memory film structure, on a semiconductor substrate 103 as a first electrode, a silicon oxide film 203 as an insulating film containing silicon fine particles 303 as conductive fine particles, and polysilicon as a conductive film as a second electrode A film 503 is formed. The polysilicon film 503 includes a protruding portion 503 a that protrudes toward the silicon oxide film 203 toward the silicon fine particles 303.
[0037]
When a potential difference is applied to the first electrode and the second electrode, electric field concentration is caused in the protruding portion 503a of the polysilicon film, and the polysilicon film 503 and the silicon fine particle 303 pass through the protruding portion 503a. It is designed to send and receive electrons.
[0038]
Further, the distance d4 between the upper surface of the silicon fine particles 303 and the protrusion 503a of the polysilicon film, the lower surface of the silicon fine particles 303, and between the semiconductor substrate 103 and the silicon oxide film 203. The distance d3 between the boundary surfaces is set to satisfy the relationship d3> d4. Specifically, d3 is 4 nm and d4 is 3 nm. This ensures that charge is transferred between the silicon fine particles 303 and the polysilicon film 503.
[0039]
Here, even when the d3 and d4 are formed to be substantially the same as 4 nm, for example, the polysilicon film 503 includes the protruding portion 503a. Therefore, the polysilicon film 503 and the silicon fine particles 303 perform charge transfer. Can do.
[0040]
The distance d4 between the upper surface of the silicon fine particles 303 and the protruding portion 503a of the polysilicon film can be formed in a relatively wide range of about 1 nm to 5 nm. This is because the electric field concentration is effectively generated in the protruding portion 503a. Therefore, even if d4 is slightly increased, charges are likely to be injected from the polysilicon film 503 into the silicon fine particles 303, while d4. This is because it is difficult for charges to be discharged from the silicon fine particles 303 to the polysilicon film 503 even in the case where is slightly reduced. Therefore, even if the distance d4 varies somewhat, there is little influence on the performance of the memory film structure. Therefore, the allowable range of the distance d4 becomes relatively wide, and the yield at the time of manufacturing the memory film structure can be improved.
[0041]
The silicon fine particles 303 are preferably formed to have a particle size of about 2 nm to 6 nm. By forming in this dimension, the quantum size effect is appropriately achieved. The distance d3 between the lower surface of the silicon fine particles 303 and the boundary surface between the semiconductor substrate 103 and the silicon oxide film 203 is preferably 3 nm to 5 nm. The distance d4 between the upper surface of the silicon fine particles 303 and the protruding portion 503a of the polysilicon film is preferably about 2 nm to 3 nm.
[0042]
The memory film structure configured as described above performs charge injection / discharge in the following manner. That is, a negative voltage is applied to the polysilicon film 503 serving as the second electrode with respect to the semiconductor substrate 103 serving as the first electrode. Then, as indicated by an arrow C in FIG. 4A, electrons are injected from the protruding portion 503a of the polysilicon film toward the silicon fine particles 303 through the silicon oxide film 203. At this time, since electric field concentration occurs in the polysilicon film 503, electrons move relatively easily. On the other hand, when a positive voltage is applied to the polysilicon film 503 with respect to the semiconductor substrate 103, as shown by an arrow D in FIG. 4A, electrons of the silicon fine particles 303 are emitted toward the protruding portion 503a of the polysilicon film. Is done. At this time, since electric field concentration does not occur during injection, electrons are relatively difficult to move. In FIG. 4A, the length of the arrows C and D indicates the ease of movement of electrons. FIG. 4B is a diagram showing a memory film structure in which the boundary surface between the polysilicon film 1503 and the silicon oxide film 1203 is formed flat for comparison. In this memory film structure, a negative charge is applied to the polysilicon film 1503 with respect to the semiconductor substrate 1103 and electrons are injected into the silicon fine particles 1303 as indicated by an arrow E, and a polysilicon film is applied to the semiconductor substrate 1103. In the case where a positive charge is applied to 1503 and electrons are emitted from the silicon fine particles 1303 as indicated by an arrow F, the ease of movement of electrons is substantially the same. Therefore, the memory film structure of this comparative example requires a relatively high voltage for electron injection, while electron emission is performed at a relatively low voltage. That is, the power consumption is relatively large and the electron retention characteristics are relatively poor.
[0043]
Further, as shown in FIG. 4A, it is preferable to sharply sharpen the tip of the protruding portion 503a of the polysilicon film. As a result, the electric field concentration effect on the protrusion 503a of the polysilicon film when a negative charge is applied to the second electrode is increased.
[0044]
As above, the book Reference example In this memory film structure, electrons are injected into the silicon fine particles 303 by utilizing the electric field concentration at the protrusion 503a of the polysilicon film, so that the electron injection can be executed at a high speed with a low voltage. Therefore, it is possible to realize high-speed information writing / erasing operation and low power consumption. In addition, since electrons injected into the silicon fine particles 303 are relatively difficult to emit, an improvement in information retention characteristics can be realized.
[0045]
Also book Reference example In the memory film structure, since charges are hardly transferred between the semiconductor substrate 103 and the silicon fine particles 303, defects caused by charge injection / release are formed near the boundary surface between the semiconductor substrate 103 and the silicon oxide film 203. It is possible to effectively prevent the occurrence of charge trapping. Further, since the silicon oxide film 203 can be formed to have a relatively thick portion other than the portion where the protruding portion 503a of the polysilicon film is formed, the silicon oxide film 203 is the semiconductor substrate 103 as the first electrode and the second electrode. Leakage current between the polysilicon film 503 can be effectively prevented. As a result, the information retention characteristic of the memory film structure can be improved.
[0046]
Also book Reference example In the memory film structure of FIG. 1, when the applied voltage was decreased from +3 V to −3 V and then increased from −3 V to +3 V, the change in capacitance was measured, and the measurement result is shown in the graph. It was found that the same hysteresis characteristics can be obtained. The amount of shift in the voltage direction between the curve when the applied voltage was reduced and the curve when the applied voltage was increased was an amount corresponding to about 0.25 V at the maximum. Therefore, it is possible to determine the information writing state and the erasing state by applying a voltage in a voltage region exhibiting hysteresis characteristics and measuring the capacitance at that time.
[0047]
( Second embodiment and second reference example )
FIGS. 5 (a) and 5 (b) show the first of the present invention. Second embodiment and second reference example It is sectional drawing which shows the memory film structure. The memory film structure of this embodiment is the same as that of the first embodiment and First reference example Compared with the memory film structure, the second conductive film is provided closer to the semiconductor substrate than the conductive fine particles in the insulating film.
[0048]
The memory film structure in FIG. 5A includes a silicon film 314 as a second conductor film between the silicon fine particles 304 and the semiconductor substrate 104 with insulating layers 204 and 214 interposed therebetween. The silicon film 314 is made of polysilicon and has a thickness of about 4 nm to 6 nm. Above the silicon film 314, an upper silicon oxide film 204 is formed as an insulating layer containing the silicon fine particles 304. Under the silicon film 314, a lower silicon oxide film 214 as an insulating layer is formed with the lower surface in contact with the semiconductor substrate 104. The upper silicon oxide film 204 includes a convex film portion 204a that covers the silicon fine particles 304 and protrudes toward the polysilicon film 504 side.
[0049]
The memory film structure in FIG. 5B includes a silicon film 315 as a second conductor film between the silicon fine particles 305 and the semiconductor substrate 105 with insulating layers 205 and 215 interposed therebetween. The silicon film 315 is made of polysilicon and has a thickness of about 4 nm to 6 nm. On the upper side of the silicon film 315, an upper silicon oxide film 205 as an insulating layer containing the silicon fine particles 305 is formed. A lower silicon oxide film 215 as an insulating layer is formed below the silicon film 315 so that the lower surface thereof is in contact with the semiconductor substrate 105. The polysilicon film 505 includes a protruding portion 505 a that protrudes toward the upper silicon oxide film 205 toward the silicon fine particles 305.
[0050]
In the memory film structure of FIGS. 5A and 5B, a predetermined potential difference is applied between the semiconductor substrates 104 and 105 and the polysilicon films 504 and 505. Then, in the memory film structure of FIG. 5A, charges are injected from the polysilicon film 504 through the convex film portion 204a into the silicon fine particles 304, and the injected charges are accumulated in the silicon film 314. Is done. In the memory film structure of FIG. 5B, charges are injected from the polysilicon film 505 into the silicon fine particles 305 through the protrusions 505a, and the injected charges are accumulated in the silicon film 315.
[0051]
This embodiment And this reference example In this memory film structure, since the charges are distributed substantially uniformly in the silicon films 314 and 315, the first Embodiment and First reference example Unlike the case where charges are accumulated in the silicon fine particles 304 and 305 as in FIG. 1, the variation in the distribution of the fine particles does not cause the variation in the charge distribution. That is, the memory film structure according to the present embodiment does not accumulate charges in the fine particles whose distribution variation is relatively likely to occur at the time of manufacture, but accumulates charges in the silicon films 314 and 315, and thus has a stable characteristic. However, it can be manufactured easily and stably. When the charge is accumulated in the fine particles, the variation in characteristics due to the variation in the distribution of the fine particles becomes more significant as the degree of miniaturization of the memory film structure increases. However, since the memory film structure of the present embodiment accumulates charges in the silicon films 314 and 315 without accumulating charges in the fine particles, the distribution of charges can be kept substantially uniform even if miniaturization proceeds. That is, the memory film structure of this embodiment can be easily miniaturized without degrading the characteristics.
[0052]
In addition, the injection and release of electric charges to and from the silicon films 314 and 315 are performed through the silicon fine particles 304 and 305, and the silicon fine particles 304 and 305 have a Coulomb blockade effect. The charge retention characteristic to 315 is improved. Accordingly, if the thickness of the upper silicon oxide films 204 and 205 between the silicon films 314 and 315 and the polysilicon films 504 and 505 as the second electrodes and containing the silicon fine particles 304 and 305 is reduced, the charge is increased. Can be obtained, and a memory film structure having a high writing speed can be obtained.
[0053]
For the memory film structure of the present embodiment, the change in capacitance was measured when the applied voltage was decreased from +3 V to -3 V and then increased from -3 V to +3 V, and the measurement results are shown in the graph. Hysteresis characteristics similar to those of one embodiment were obtained. The amount of shift in the voltage direction between the curve when the applied voltage was reduced and the curve when the applied voltage was increased was an amount corresponding to about 0.35 V at maximum. Therefore, it is possible to determine the information writing state and the erasing state by applying a voltage in a voltage region exhibiting hysteresis characteristics and measuring the capacitance at that time.
[0054]
In the present embodiment, the upper silicon oxide film 204 and the lower silicon oxide film 214 may be formed of different materials. Further, the upper silicon oxide film 205 and the lower silicon oxide film 214 may be formed of different materials.
[0055]
( Third embodiment and third reference example )
FIGS. 6 (a) and 6 (b) show the first of the present invention. Third embodiment and third reference example It is sectional drawing which shows the memory film structure. This embodiment And this reference example The memory film structure of the first embodiment and First reference example Compared with this memory film structure, the second conductive fine particles are different from the conductive fine particles in the insulating film on the semiconductor substrate side.
[0056]
The memory film structure of FIG. 6A includes a first silicon fine particle 306a and a second silicon fine particle 306b in a silicon oxide film 206 as an insulating film. The first silicon fine particles 306a are arranged in the vicinity of the polysilicon film 506 as the second electrode, and the second silicon fine particles 306b are closer to the semiconductor substrate 106 as the first electrode than the first silicon fine particles 306a. Is arranged. A portion of the silicon oxide film 206 between the first silicon fine particles 306a and the polysilicon film 506 is formed in a convex film portion 206a protruding toward the polysilicon film 506 side.
[0057]
The memory film structure of FIG. 6B includes first silicon fine particles 307a and second silicon fine particles 307b in a silicon oxide film 207 as an insulating film. The first silicon fine particles 307a are disposed in the vicinity of the polysilicon film 507 as the second electrode, and the second silicon fine particles 307b are closer to the semiconductor substrate 107 as the first electrode than the first silicon fine particles 307a. Is arranged. The polysilicon film 507 includes a protruding portion 507a protruding toward the silicon oxide film 207 toward the first silicon fine particles 307a.
[0058]
In the memory film structure shown in FIGS. 6A and 6B, a predetermined potential difference is applied between the semiconductor substrates 106 and 107 and the polysilicon films 506 and 507. Then, in the memory structure of FIG. 6A, charges are injected into the first silicon fine particles 306a through the convex film portion 206a of the silicon oxide film. In the memory structure of FIG. 5B, electric field concentration occurs in the protrusion 507a of the polysilicon film, and charges are injected into the first silicon fine particles 307a facing the protrusion 507a. The first silicon fine particles 306a and 307a into which the charges have been injected pass charges to the second silicon fine particles 306b and 307b, and the charges are accumulated in the second silicon fine particles 306b and 307b. Since the first silicon fine particles 306a and 307a exhibit a Coulomb blockade effect, the accumulated charges are not easily released. Therefore, this memory structure can inject charges at a high speed with a low voltage, and obtain good charge retention characteristics.
[0059]
In addition, since the second silicon fine particles 306b and 307b for holding the charge are discretely contained in the insulating film 207, even if a portion where the charge holding ability is inferior occurs in the vicinity, Only the charge accumulated in leaks. Therefore, the memory film structure of this embodiment does not leak all charges through some defective portions as in the conventional floating gate type memory, and high reliability is obtained.
[0060]
FIG. 7 is an enlarged comparative view showing a part of each memory film structure in order to compare the memory film structure of FIG. 6A and the memory film structure of FIG. 6B. In FIG. 7, the left side is a part of the memory film structure 1 of FIG. 6A provided with the convex film part 206a of the silicon oxide film, and the right side is provided with a protruding part 507a of the polysilicon film in FIG. ) Of the memory film structure 2. The memory film structure 1 including the convex film portion 206a and the memory film structure 2 including the protruding portion 507a are formed to have substantially the same thickness.
[0061]
As can be seen from FIG. 7, the distance d8 between the first electrode 107 and the second electrode 507 in the memory film structure 2 is larger than the distance d7 between the first electrode 106 and the second electrode 506 in the memory film structure 1. large. Therefore, the direct memory leak between the first and second electrodes can be more effectively prevented in the two memory film structures provided with the protrusions 507a than in the one memory film structure provided with the convex film parts 206a. Further, the distance d6 between the second electrode 507 and the second silicon fine particle 307b in the memory film structure 2 is larger than the distance d5 between the second electrode 506 and the second silicon fine particle 306b in the memory film structure 1. Therefore, the two memory film structures can more effectively prevent the direct leakage between the second electrode and the second silicon fine particles than the first memory film structure. That is, it can be said that the reliability of the two memory film structures including the protruding portions 507a is higher than that of the one memory film structure including the convex film portions 206a.
[0062]
This embodiment And this reference example The second silicon fine particles 306b and 307b are arranged at substantially the same position as the first silicon fine particles 306a and 307a in the width direction of the semiconductor substrates 106 and 107, but the second silicon fine particles are arranged in the width direction of the semiconductor substrate. You may arrange | position in the position different from a 1st silicon microparticle. That is, as shown in FIG. 8, in the width direction of the semiconductor substrate 117, the first silicon fine particles 317a are arranged at substantially the same position as the protrusions 517a of the polysilicon film 517, and the first silicon fine particles 317a are on the side of the semiconductor substrate 117. In addition, the memory film structure may be configured by disposing the second silicon fine particles 317b in the width direction of the semiconductor substrate 117 so as to be shifted from the first silicon fine particles 317a. According to this memory film structure, in addition to the effects obtained by the memory film structure of FIG. 6B, the thickness of the entire memory film structure can be reduced and the capacitance can be increased. Therefore, when this memory film structure is used for a field effect transistor, the gate insulating film can be made thin, the short channel effect can be suppressed, and the memory element can be miniaturized.
[0063]
( Fourth embodiment and fourth reference example )
FIG. Fourth reference example It is the figure which showed this memory element. This memory element First reference example A field effect transistor is configured using the above memory film structure. In the memory element, a silicon oxide film 208 containing silicon fine particles 308 is formed on a silicon substrate 108 as in the memory film structure of the second embodiment, and polysilicon having a protrusion 508a formed on the oxide film 208 is formed. A film 508. A source region 608 and a drain region 708 are formed near the surface of the silicon substrate 108, and the silicon oxide film 208 is formed on the channel region between the source region 608 and the drain region 708. The silicon oxide film 208 functions as a gate insulating film, and the polysilicon film 508 functions as a gate electrode. The silicon substrate 108 has a P-type conductivity type, and the source region 608 and the drain region 708 have an N-type conductivity type to form an N-channel field effect transistor. The silicon substrate 108 may be N-type conductivity, and the source region 608 and the drain region 708 may be P-type conductivity to constitute a P-channel field effect transistor. The gate electrode is not limited to polysilicon but may be formed of metal.
[0064]
Book Reference example In this memory element, charges are transferred between the silicon fine particles 308 contained in the silicon oxide film 208 as the gate insulating film and the polysilicon film 508 as the gate electrode on the silicon oxide film 208. Therefore, it can be avoided that the interface between the semiconductor substrate and the gate insulating film as in the prior art is deteriorated due to the transmission of electric charges. In addition, since the interface between the silicon substrate 108 and the silicon oxide film 208 can be formed flat, good transistor characteristics can be obtained. Therefore, especially during reading, characteristic fluctuations and shortage of channel current can be suppressed, so that highly accurate reading can be performed. Therefore, this memory element does not require an unnecessarily large memory window, and since the drain voltage may be relatively low, low voltage operation and low power consumption can be realized, and high reliability can be achieved.
[0065]
Book Reference example In First reference example The memory film structure of As an example of the fourth embodiment, You may comprise a memory element using the memory film structure of 1st Embodiment. In this case, a high-speed rewritable memory element can be obtained. Also, As another example of the fourth embodiment, First 2 Or second 3 You may comprise a memory element using the memory film structure of embodiment.
[0066]
( Fifth embodiment and fifth reference example )
FIG. 5th reference example It is a figure which shows this memory element. This memory element is formed on an SOI substrate. First reference example The memory film structure is formed. That is, a source region 609, a drain region 709 and a body 909 are formed on a buried oxide film 809 on the silicon substrate 109, and a silicon oxide film 208 containing silicon fine particles 308 and this oxide film are formed on the body 909. And a polysilicon film 508 formed on 208 and having a protrusion 508a. The silicon oxide film 208 functions as a gate insulating film, and the polysilicon film 508 functions as a gate electrode.
[0067]
Book Reference example The memory device 4 Reference examples In addition to the effects obtained with this memory element, the junction capacitance between the source region 609 and the body 909 and the junction capacitance between the drain region 709 and the body 909 can be made extremely small. Therefore, the operation of the memory element can be further speeded up and the power consumption can be reduced. In addition, since the source region 609 and the drain region 709 are formed over the SOI substrate, the thickness can be easily reduced, so that the short channel effect can be suppressed and the memory element can be further miniaturized.
[0068]
As a fifth embodiment of the present invention, Book Reference example The memory film structure of the first embodiment or the 2 Or second 3 The memory film structure of the embodiment may be formed on an SOI substrate.
[0069]
Further, although a fully depleted memory element as shown in FIG. 10 is formed, a partially depleted memory element may be formed.
[0070]
(No. 6 Embodiment)
First of the present invention 6 The embodiment 5 This is a semiconductor device in which a memory circuit in which the memory elements of the embodiment are integrated and a logic circuit are mounted together. FIG. 11A is a schematic plan view showing the semiconductor device of this embodiment. In this semiconductor device, a memory cell region 100 in which the memory circuit is formed, a peripheral circuit region 200 in which a peripheral circuit as a logic circuit is formed, and a functional circuit having functions other than the memory circuit and the peripheral circuit are formed. Functional circuit region 300.
[0071]
FIG. 11B is a schematic plan view showing a conventional semiconductor device for comparison, and a conventional flash memory is integrated in the memory circuit of the memory cell region 110. In this conventional semiconductor device, since the driving voltage of the flash memory is higher than the driving voltage of the logic circuit, a booster circuit, a control circuit, etc. are required in the peripheral circuit, and the high driving voltage of the memory circuit is tolerated. Therefore, it is necessary to increase the thickness of the gate oxide film of the transistor in the peripheral circuit, and the area of the peripheral circuit region 210 is large. Therefore, it is difficult to reduce the size of the semiconductor device. Further, since the memory cell region 110 and the peripheral circuit region 210 are large, the ratio of forming the functional circuit region 310 for other functions is small.
[0072]
On the other hand, in the semiconductor device of this embodiment, the memory circuit in the memory cell region 100 is the first. 5 Since the memory element according to the embodiment is operable with a low voltage, it can be operated with the same power supply voltage as that of the peripheral circuit. Therefore, the memory circuit and the peripheral circuit can share the power source, and the conventional booster circuit and control circuit can be deleted, so that the area of the peripheral circuit region 200 can be reduced. Further, since the driving voltage of the memory circuit is low, the gate oxide film of the transistor in the peripheral circuit can be thinned, and the area of the peripheral circuit region 200 can be reduced. Further, since the memory circuit can be highly integrated, the area of the memory cell region 100 can be reduced. Therefore, as shown in FIG. 11A, the semiconductor device of the present embodiment can be made smaller than the conventional semiconductor device of FIG. 11B, and an area for circuits other than the memory circuit and the peripheral circuit. As a result, a higher-performance semiconductor device can be formed.
[0073]
Alternatively, the memory capacity of the semiconductor device can be made larger than in the past by integrating more memory elements than in the past in the same size semiconductor device. This makes it possible to temporarily load a large-scale program, hold the program even after the power is turned off, and execute the program after the power is turned on again. It can be replaced with a program.
[0074]
(No. 7 Embodiment)
FIG. 12 shows the first of the present invention. 7 It is a figure which shows the mobile telephone device as an electronic device of embodiment. This cellular phone is connected to the control circuit 911 by the second 6 The semiconductor device of the embodiment is incorporated. The semiconductor device incorporated in the control circuit 911 is an LSI (Large Scale Integrated circuit) in which a memory circuit and a logic circuit are mixed. Power is supplied to the battery 912 to control the RF circuit portion 913 and the display portion 914. is doing. Reference numeral 915 denotes an antenna portion, 916 denotes a signal line, and 917 denotes a power supply line. Since the control circuit 911 incorporates the semiconductor device of this embodiment, the mobile phone can be enhanced in function, and the power consumption can be reduced and the battery life can be greatly extended.
[0075]
In the present embodiment, the mobile phone is configured using the semiconductor device, but other electronic devices such as a portable information terminal and a game device may be configured.
[0076]
【The invention's effect】
As is clear from the above, according to the present invention, a memory film structure comprising an insulating film containing conductive fine particles and a conductive film formed on the insulating film, the conductive fine particles are connected to the conductive film. Disposed in the vicinity of the side, and the insulating film is provided with a convex film part that covers the conductive film side of the conductive fine particles and protrudes toward the conductive film side. Charges can be transferred between the fine particles and the conductor film at high speed and at a low voltage. Therefore, the deterioration of the insulating film can be reduced, and a memory structure film with high speed operation and low power consumption can be obtained.
[0077]
[Brief description of the drawings]
FIG. 1A is a cross-sectional view of the entire memory film structure according to the first embodiment of the present invention, and FIG. 1B is an enlarged view of a portion of the memory film structure of FIG. It is sectional drawing.
FIG. 2A is a diagram showing a state in which charges are injected into the memory film structure of FIG. 1B, and FIG. 2B is a diagram in which the surface of the silicon oxide film is formed flat. It is the comparison figure which shows the memory film structure which was done.
FIG. 3 (a) As a first reference example FIG. 3B is an enlarged cross-sectional view of a portion of the memory film structure of FIG. 3A.
FIG. 4A is a diagram showing a state of charge injection / discharge in the memory film structure of FIG. 3B, and FIG. 4B is a diagram showing a flat surface of the silicon oxide film. It is a comparison figure which shows the formed memory film structure.
FIGS. 5 (a) and 5 (b) show the first embodiment of the present invention. 2 Embodiment And second reference example It is sectional drawing which shows the memory film structure.
FIGS. 6 (a) and 6 (b) show the first embodiment of the present invention. 3 Embodiment And the third reference example It is sectional drawing which shows the memory film structure.
7 is an enlarged comparative view showing a part of the memory film structure of FIG. 6A and a part of the memory film structure of FIG. 6B.
FIG. 8 3 Reference examples It is a figure which shows the modification of the memory film structure of this.
FIG. 9 shows the first of the present invention. 4 Reference examples It is the figure which showed this memory element.
FIG. 10 shows the first of the present invention. 5 Reference examples It is a figure which shows this memory element.
FIG. 11 (a) shows the first embodiment of the present invention. 6 FIG. 11B is a schematic plan view showing the semiconductor device of the embodiment, and FIG. 11B is a schematic plan view showing the conventional semiconductor device.
FIG. 12 shows the first of the present invention. 7 It is a figure which shows the mobile telephone device as an electronic device of embodiment.
FIG. 13 is a diagram illustrating a conventional memory device.
[Explanation of symbols]
102 Semiconductor substrate
202 Silicon oxide film
202a Convex film part
302 Silicon fine particles
502 Polysilicon film

Claims (9)

An insulating film formed on a semiconductor substrate and containing conductive fine particles;
A conductor film formed on the insulating film,
The conductor fine particles are disposed in the vicinity of the conductor film,
The insulating film includes a convex film portion that covers the conductor film side of the conductive fine particles and protrudes toward the conductor film side, and the thickness of the convex film portion of the insulating film is the same as that of the insulating film. A memory film structure, wherein the memory film structure is formed to be thinner than a thickness of a portion closer to the semiconductor substrate than the conductive fine particles . The memory film structure according to claim 1,
The particle diameter of the conductive fine particles is 1 to 7 nm, the thickness of the convex film portion of the insulating film is 1 to 3 nm, and the thickness of the insulating film on the semiconductor substrate side from the conductive fine particles is 3 to 5 nm. A memory film structure characterized by The memory film structure according to claim 1 or 2 ,
A memory film structure comprising a second conductor film provided in the insulating film so as to be positioned closer to the semiconductor substrate than the conductor fine particles. The memory film structure according to any one of claims 1 to 3 ,
2. A memory film structure comprising a second conductive fine particle provided in the insulating film so as to be positioned closer to a semiconductor substrate than the conductive fine particle. Memory device, characterized in that it comprises a field effect transistor formed by using a memory film structure according to any one of claims 1 to 4. The memory device according to claim 5 , wherein
A memory element, wherein the memory film structure is formed on an SOI substrate. A semiconductor device comprising: a memory circuit in which memory elements are integrated according to claim 5 or 6. The semiconductor device according to claim 7 ,
A semiconductor device in which a logic circuit and the memory circuit are mixedly mounted. An electronic apparatus comprising the semiconductor device according to claim 8 .

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