JP4779387B2 - Display device - Google Patents

Description

  The present invention relates to a display device that is connected in series by inputting a display data signal and a control signal from a front stage and outputting a signal to a rear stage.

  There is a display device in which light sources are arranged in a dot matrix. For example, a display device in which LEDs (Light Emitting Diodes) are arranged in 16 columns and 16 rows is arranged in columns and rows to provide a single display screen in a facility such as a stadium or stadium, or on the wall of a building. For example, text information and images are projected. Such conventional display devices are described in Patent Documents 1 and 2.

  The display device described in Patent Document 1 is configured by combining a plurality of digits in a plurality of stages, a data distributor is connected to the display device in each stage, and a display data signal is distributed from the data distributor, thereby transmitting display data. Since the distance can be shortened, the influence of noise is reduced.

The display device described in Patent Document 2 latches an input control signal and an input display data signal with a first latch means, and latches the output of the first latch means with the opposite phase of the input clock, By providing the second latch means for outputting as an output display data signal, a margin between control devices for the control signal and the display data signal can be sufficiently secured.
JP-A-8-101666 JP 9-22273 A

  However, since the display device described in Patent Document 1 is provided with a data distributor at each stage, the number of data distributors corresponding to the number of stages is required, and the overall size is increased.

  In addition, in the display devices described in Patent Documents 1 and 2, since the clock signal that is a reference for the display data signal and the control signal is output as it is to the next display device connected in series as it is, as the line length increases, There is a concern that the clock signal may become thin and distortion due to noise may occur.

  In each display device, it may be possible to insert a buffer into the clock signal. However, although the state is eased, the thinning and delay of the clock signal will not be integrated. A delay of the clock signal occurs. Therefore, in the display device connected to the last stage, the delay of the clock signal is maximized, and there is a possibility that normal display cannot be performed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that can reliably display a large number even when connected in series.

In the display device of the present invention, a display data signal indicating display information, a control signal indicating the timing of the display data signal, and a clock signal serving as a reference timing of the display data signal and the control signal are input from the previous stage to the subsequent stage. In a display device having a signal transmission / reception circuit for output and a display unit for displaying based on each signal input from the signal transmission / reception circuit, the signal transmission / reception circuit latches the display data signal and the control signal. a first latch portion, together with the reproduction waveform of the clock signal inputted from the preceding stage to output to the subsequent stage, and a clock recovery circuit for outputting a latch signal of the first latch portion, the clock recovery circuit, said front A frequency dividing circuit that divides the clock signal input from the frequency dividing circuit by 2, an integrating circuit that integrates an output of the frequency dividing circuit, and the frequency dividing circuit Characterized by comprising the exclusive OR circuit to output and the clock signal obtained by reproducing the Enter waveform and the output of the integrator circuit.

  In the present invention, even if the line length of the clock signal becomes long and the waveform becomes dull and thin due to the addition of the capacitance, the clock signal is reproduced by each display device, and the clock signal is reliably transmitted to the final display device. Therefore, even if many are connected in series, they can be displayed reliably.

In the first invention of the present application, a display data signal indicating display information, a control signal indicating the timing of the display data signal, and a clock signal serving as a reference timing of the display data signal and the control signal are input from the previous stage and output to the subsequent stage. In a display device having a signal transmission / reception circuit and a display unit that displays based on each signal input from the signal transmission / reception circuit, the signal transmission / reception circuit includes a first latch unit that latches a display data signal and a control signal, And a clock signal recovery circuit for outputting the waveform of the clock signal input from the first stage as a latch signal of the first latch unit , and the clock signal recovery circuit divides the clock signal input from the previous stage by 2 Reproduce the waveform by inputting the divider circuit that integrates, the integrator circuit that integrates the output of the divider circuit, the output of the divider circuit and the output of the integrator circuit And it is obtained by comprising the exclusive OR circuit to the clock signal.

The signal transmission / reception circuit is equipped with a clock signal recovery circuit that regenerates the waveform of the clock signal input from the previous stage and outputs it to the subsequent stage, so that the line length of the clock signal has become longer and the waveform has become duller and thinner due to the addition of capacitance. However, since the clock signal is reproduced by each display device, it is possible to reliably transmit the clock signal to the last display device. Further, by using the output signal of the clock signal reproduction circuit as the latch signal of the first latch unit that latches the display data signal and the control signal, the clock signal, the display data signal, and the control signal are synchronized in each display device. Therefore, it is possible to prevent a synchronization error between signals.
In addition, the output of the clock signal recovery circuit is the exclusive OR of the frequency dividing circuit that divides the clock signal input from the previous stage by 2 and the integration circuit that integrates the output of the frequency dividing circuit, thereby reproducing the waveform. Clock signal. In addition, an arbitrary waveform width can be obtained by using an integrating circuit.

According to a second aspect of the present invention, the signal transmission / reception circuit includes a second latch unit that latches the output of the first latch unit in a phase opposite to that of the latch signal and serves as a display data signal and a control signal for the subsequent stage. It is what.

  When the timing at which the display data signal and the control signal change changes at the opposite phase of the clock signal, the display data signal and the control signal latched by the first latch unit are delayed by a half cycle. Therefore, the output of the first latch unit can be output to the subsequent stage without changing the changing timing by providing the second latch unit that latches the clock signal in the opposite phase and outputs it to the subsequent stage.

(Embodiment)
A configuration of a display device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a display device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the clock signal reproduction circuit.

  As shown in FIG. 1, the display device 1 includes a display unit 2 that performs display, and a signal transmission / reception circuit 3 that inputs a signal from the previous stage, outputs the signal to the subsequent stage, and outputs the signal to the display unit 2.

  The display unit 2 controls the display drive circuit 5 on the basis of the panel unit 4 in which LEDs are arranged in a dot matrix, a display drive circuit 5 that drives signals in columns and rows on the panel unit 4, and each input signal. The display control circuit 6 is provided.

  The signal transmission / reception circuit 3 inputs a signal from a front display device (not shown) or a control device that generates each signal, and outputs the signal to a rear display device. As a signal, a clock signal (CLOCK_A), a display data signal (DATA_A), and a control signal (control signal_A) are input. DATA_A is output as DATA_C, control signal_A is output as control signal_C, and CLOCK_A is output as CLOCK_C. .

  The clock signal is a signal serving as a reference for the output timing of the display data signal and the control signal. In this embodiment, the signal has a period of 10 MHz. The display data signal is data that is displayed on the panel unit 4 as serial data, and is a signal synchronized with the fall of the clock signal. The control signal indicates the timing of the display data signal, is a signal synchronized with the falling edge of the clock signal, and includes a vertical synchronization signal and a horizontal synchronization signal.

  The signal transmission / reception circuit 3 includes a latch A (first latch unit) 7 that latches the control signal _A and DATA_A input from the previous stage, and a latch B (second latch unit) 8 that latches an output from the latch A. A clock signal reproduction circuit 9 and an inverter 10 are provided.

  The latch A7 receives the control signal _A and DATA_A, latches the output signal of the clock signal reproduction circuit 9 as a latch signal (clock) at the rising timing, outputs the control signal _B and DATA_B to the latch B8, and displays Output to part 2.

  The latch B8 receives the control signal _B and DATA_B, latches the output signal of the clock signal regeneration circuit 9 as a latch signal (clock) with a signal whose phase is reversed by the inverter 10, and latches the control signal _C and DATA_C. Is output to the subsequent stage.

  The clock signal reproduction circuit 9 reproduces the waveform of the clock signal input from the previous stage, outputs it to the subsequent stage, and outputs it to the latch A7 as a latch signal. Here, the clock signal reproduction circuit 9 will be described in detail with reference to FIG.

  As shown in FIG. 2, the clock signal reproduction circuit 9 includes a D-FF 15, an inverter 16, a CR circuit 17, and an XOR (exclusive OR) 18.

  The D-FF 15 is a latch circuit that is connected to CLOCK_A as a clock signal, connected to the output of the inverter 16 as input data, and latches input data at the rising edge of CLOCK_A. The output is connected to the input of the inverter 16. In this way, the D-FF 15 and the inverter 16 are connected to operate as a frequency dividing circuit that divides the cycle of CLOCK_A by two.

  The CR circuit 17 is an integrating circuit that integrates the output of the D-FF 15. This integrating circuit is composed of a resistor 17a and a capacitor 17b. For example, when CLOCK_A is a 10 MHz clock, it is desirable to set the resistor 17a to 15Ω and the capacitor 17b to 10 pF, but it may be changed as appropriate according to the time constant.

  The XOR 18 is a circuit that performs an exclusive OR of the output of the D-FF 15 and the output of the CR circuit 17.

  The operation of the display device according to the embodiment of the present invention configured as described above will be described with reference to FIGS. FIG. 3 is a timing chart for explaining the operation of the display device according to the embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of the clock signal reproduction circuit.

  As shown in FIG. 3, CLOCK_A, which is an input of a clock signal, is input at a cycle of 10 MHz, and at the falling edge, the control signal_B changes from L level to H level to indicate notification of transmission of a display data signal. Then, DATA_A becomes L level or H level according to the display after one clock, and the display data is inputted.

  As shown in FIG. 4, the inputted CLOCK_A is divided by 2 by the D-FF 15 and the inverter 16, and the output of the D-FF 15 becomes a signal of 5 MHz.

  When the D-FF 15 outputs an H level, the CR circuit 17 that receives the output of the D-FF 15 is charged into the capacitor 17b via the resistor 17a, so that the output voltage gradually increases.

  Since the XOR 18 performs an exclusive OR operation between the output of the D-FF 15 and the output of the CR circuit 17, the XOR 18 remains “H” until the output voltage of the CR circuit 17 exceeds the threshold level of the input level “H”. Output. When the threshold level of the input level “H” is exceeded, “L” is output. This output signal is output to the subsequent stage as CLOCK_C.

  In this way, since the exclusive OR of the signal obtained by dividing CLOCK_A by 2 and the signal obtained by integrating this signal is obtained, the pulse width of the clock signal is determined by the constants of the capacitance value and resistance value of the integration circuit (CR circuit 17). Determined by Since the signal transmission / reception circuit 3 is mounted for each display device 1, even if a large number of display devices 1 are connected, the thinness of the clock signal does not accumulate.

  As shown in FIG. 1 and FIG. 3, CLOCK_C in which this waveform is reproduced is input as a latch signal to the latch A7, and the control signal A and DATA_A are latched at the rising edge to obtain the control signal B and DATA_B. Since the control signals A and DATA_A are signals converted at a timing opposite to that of CLOCK_A, the control signals B and DATA_B are signals delayed by half a clock from the control signals A and DATA_A.

  The control signals B and DATA_B become CLOCK_B having the opposite phase by the inverter 10 and are latched by the latch B8 to be the control signals C and DATA_C. The control signals C and DATA_C are a control signal and a display data signal output to the subsequent stage.

  Since the latch B8 is latched by the clock signal having the reverse phase in this way, even if the timing at which the control signals A and DATA_A change is changed at the timing at the reverse phase of CLOCK_A, the change timing is changed. And output to the subsequent stage. In addition, the CLOCK_A is reproduced, and the control signal A and DATA_A are latched by the latch A7 and the latch B8 by the CLOCK_A, so that the delay between the signals can be reduced.

  Since the present invention can surely display a large number even when connected in series, a display data signal or a control signal is input from the front stage and output to the rear stage to be connected in series. Is preferred.

FIG. 7 is a block diagram illustrating a display device according to an embodiment of the present invention. Circuit diagram showing an example of a clock signal recovery circuit FIG. 5 is a timing chart illustrating the operation of the display device according to the embodiment of the invention. Timing chart explaining operation of clock signal recovery circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display part 3 Signal transmission / reception circuit 4 Panel part 5 Display drive circuit 6 Display control circuit 7 Latch A
8 Latch B
9 Clock signal regeneration circuit 10 Inverter 15 D-FF
16 Inverter 17 CR circuit 17a Resistor 17b Capacitor 18 XOR
CLOCK_A, CLOCK_B, CLOCK_C Clock signal DATA_A, DATA_B, DATA_C Display data signal Control signal_A, Control signal_B, Control signal_C Control signal

Claims (2)

A signal transmission / reception circuit for inputting a display data signal indicating display information, a control signal indicating the timing of the display data signal, a clock signal serving as a reference timing of the display data signal and the control signal from the previous stage, and outputting to the subsequent stage; In a display device having a display unit that displays based on each signal input from the signal transmission / reception circuit,
The signal transmission / reception circuit latches the display data signal and the control signal, reproduces the waveform of the clock signal input from the previous stage, outputs it to the subsequent stage, and serves as a latch signal for the first latch section. A clock signal recovery circuit for output ,
The clock signal reproduction circuit includes a frequency dividing circuit that divides the clock signal input from the previous stage by 2, an integration circuit that integrates an output of the frequency dividing circuit, an output of the frequency dividing circuit, and an output of the integrating circuit; And an exclusive OR circuit that receives the signal and reproduces the waveform as a clock signal . The signal transmitting and receiving circuit latches the output of the first latch unit in the opposite phase of the latch signal, claim 1 comprising the second latch section to display data and control signals to the subsequent stage serial mounting of the display device.

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