JP4773748B2 - Multilayer circuit board - Google Patents

Description

  The present invention relates to a laminated circuit board, and more particularly to a laminated circuit board having a structure in which a semiconductor memory circuit board and a control circuit board are joined via a conductor.

  A typical example of the laminated circuit board is one in which a control circuit board and a semiconductor memory circuit board on which a semiconductor memory chip is mounted are joined via a conductor. Such a structure is often used in semiconductor memory cards. The types of memory cards include SD (Secure Digital) memory cards, memory sticks, multimedia cards, smart media, and compact flash (registered trademark). Those that are commercially available are well known. These memory cards are recognized for their light weight, thinness, and small size in the market, and their applications are expanding in combination with an increase in memory capacity. Currently, it is widely used as a memory medium for portable information terminal devices such as electronic still cameras, notebook computers, mobile phones, video cameras, and electronic reading terminals, but it also supports video content with a large amount of information. The market needs for high-capacity memory cards with high data transmission speeds are increasing year by year. Thus, attempts have been made to increase the capacity by increasing the number of semiconductor memories.

  However, all of the commercially available memory cards have the casing dimensions and volume defined by the standard, and increasing the number of semiconductor memories increases the size of the laminated circuit board and increases the volume. It is necessary to reduce the thickness of the substrate and the thickness of the substrate. When the memory capacity is small, the mechanical strength is ensured by increasing the thickness of the housing and board so that the laminated circuit board does not deform due to external force. There arises a problem that the solder that short-circuits the connection terminal (hereinafter referred to as a terminal) of the semiconductor circuit board and the terminal of the control circuit board is peeled off due to the shear strain caused by the twist of the circuit board. Therefore, various proposals have been made as methods for solving such solder peeling in a structure having low rigidity.

For example, in a semiconductor memory package mounted on a control circuit board, a plurality of flat external connection terminals are provided in an encircled state from a semiconductor body having an integrated circuit, and slits are provided in the terminals, thereby There are measures such as making the structure to follow the deformation of the connected control circuit board with a greater degree of freedom.
JP-A-9-331011

  However, it is difficult to apply the method disclosed in Patent Document 1 to a small and high-density mounted structure such as a semiconductor memory circuit board or a laminated circuit board of a memory card including the semiconductor memory circuit board. The reason is that the above method cannot provide a space that can be applied to a device having a small pitch between terminals because a slit is provided between the terminals. This is particularly noticeable when the memory card is a small structure, and when considering the safety of the wiring, etc., the distance from the outer edge to the terminal or wiring is 0.3 mm to 0. It must have about 5 mm, and when considering the pitch between terminals, it must have a space for slitting in addition to 0.6 mm that is twice that.

  In addition, it is particularly difficult when the object to be slit is a substrate containing reinforcing fibers. When the fiber is pulled out when the reinforcing fiber is cut, or when the tool hits the fiber, the phenomenon is that the resin around the fiber is damaged and the accuracy is on the order of 1 mm or less as shown above. It is very difficult to put out. For the above reasons, Patent Document 1 is not suitable for a structure in which terminals are formed at a small pitch of 1 mm or less.

  Therefore, the present invention provides a multilayer circuit board that solves these problems and can be applied to a board on which terminals are arranged at a small pitch, and realizes the mechanical strength of a solder joint.

The laminated circuit board of the present invention is provided with a semiconductor memory substrate having a semiconductor memory and first terminals arranged at a predetermined pitch, and opposed to the first terminal, at a predetermined pitch. A control circuit board having a second terminal disposed; and a conductor that joins the first terminal and the second terminal, wherein the semiconductor memory board includes the semiconductor memory and the first terminal. And at least one slit formed by cutting from an end portion of the semiconductor memory substrate .

  By using the structure of the laminated circuit board according to the present invention, when an external force such as twisting or bending is applied to the control circuit board, only the terminal portion of the semiconductor memory circuit board laminated thereon follows the deformation, and the control is performed. The peeling of the conductor that short-circuits the circuit board and the semiconductor memory circuit board can be suppressed, and as a result, the structural reliability of the laminated circuit board can be ensured.

  The present invention relates to a laminated circuit board in which a terminal of a control circuit board and a terminal of a semiconductor memory circuit board are joined via a plurality of conductors provided at a predetermined pitch, of which a semiconductor memory chip is mounted on the surface. In a semiconductor memory circuit board on which wiring and terminals are printed, a slit is provided between the semiconductor memory chip and the terminal substantially in parallel with a terminal arrangement direction, and the slit is cut from the end of the substrate. ing. Thereby, only the peripheral portion of the memory circuit board follows the deformation of the control circuit board due to an external force, and as a result, an effect of reducing the stress applied to the conductor joint can be realized.

  A plurality of semiconductor memory circuit boards may be stacked on the control circuit board, and the slit may be provided in at least one of the stacked semiconductor memory circuit boards.

  A slit on the semiconductor memory circuit board in the multilayer circuit board is provided between a terminal on one side and a terminal on the opposite side across the semiconductor memory provided in the intermediate part, and the slit is an end of the board It may be cut out from.

  The corner of the slit notch tip may be rounded in an arc shape.

  Further, in addition to the slit structure, a slit is provided by cutting in a direction from the end of the substrate toward the semiconductor memory between the terminals at the center of the terminals arranged in a predetermined pitch. May be.

  An embodiment according to the present invention will be described with reference to FIGS. In addition, the same code | symbol is provided to the component with the same function in description of a figure.

(Embodiment 1)
FIG. 1A is a schematic plan view of the laminated circuit board 101 of the present embodiment, and FIG. 1B is a front view thereof. The laminated circuit board 101 has a laminated structure in which a control circuit board 102 and a semiconductor memory circuit board 103 are joined by a conductor 105. As the conductor 105, any of well-known solder alloys, conductive pastes in which conductive metal powder such as Ag or carbon substance is dispersed in a resin adhesive can be used. Among these, a solder alloy is preferable in terms of excellent adhesion and strong mechanical strength. A semiconductor memory 107 (electronic component) such as a flash memory is mounted on the semiconductor memory circuit board 103, and a circuit is formed on the semiconductor memory circuit board 103 from the semiconductor memory chip 105 to a terminal 104 for joining the boards. Is formed. The terminals 104 are formed at a single row pitch, and are formed on the control circuit board 102 so as to be opposed to the terminals formed on the semiconductor memory circuit board as a first terminal. The second terminals are connected by a conductor 105. The control circuit board 101 and the semiconductor memory circuit board 103 are generally materials capable of printing electrical circuit patterns such as glass fiber reinforced plastic (GFRP) in which glass fiber is filled in resin, other fiber reinforced composite materials, and ceramic substrates. Is applicable. In the laminated circuit board 101 configured as described above, in this embodiment, a slit 106 is provided between the semiconductor memory 107 on the semiconductor memory circuit board 103 and the terminal 104 as shown in FIGS.

  The slit 106 is inserted in a shape that is cut substantially in parallel with the direction in which the terminals are arranged from the end of the semiconductor memory circuit board. In addition, it is preferable that both the slit width and the slit length are large, but the size must be changed depending on the number of size terminals of the semiconductor memory, the size of the substrate, and the circuit formation pattern. This size is not limited. When forming the shape as a slit, a process of making a cut after forming a rectangular substrate is required, but this also applies to the case of forming a substrate shape without forming a slit and forming the shape from the substrate forming stage. This corresponds to the present embodiment.

  By inserting slits as described above, only the substrate portion on which the terminals are disposed can be deformed with a degree of freedom in a state close to a beam. In general, when the semiconductor memory 105 is a silicon chip, its Young's modulus is about 160 GPa, and when the semiconductor memory circuit board 103 is a base material made of GFRP, which is often used as a substrate material such as FR-4, its Young's modulus is about 30 GPa. By mounting these two materials with different Young's moduli by bare chip mounting etc., the part where the silicon chip is mounted becomes highly rigid and difficult to deform, and the part without the silicon chip becomes low rigidity and easy to deform. It becomes a state. Even in a portion where the chip is not mounted, the influence of the rigidity of the chip is dominant in the very vicinity of the chip, and it is difficult to be deformed even when stress is applied. Here, it is a point of the invention that the slit is inserted in the above-mentioned cut shape, and the structure of the slit is provided in the form of penetrating the substrate like a hole (for example, there is a slit but a memory circuit board) If the terminal area and the chip side are connected in the end area 111), the terminal at the end is eventually constrained from the chip side, and it is difficult to deform with flexibility in a state close to the beam. It becomes. For the above reasons, a slit is cut in a shape cut from the end of the substrate, and the terminal on the end which is likely to cause peeling of the conductor 105 is most separated from the chip, so that the end is more affected by the chip. The point of the present invention lies in realizing the effect of making the rigidity difficult to receive. With this low rigidity state, as described above, the substrate near the terminal at the end can be deformed with more flexibility than when no slit is inserted, and as a result, the conductor 105 is loaded. Stress can be reduced, peeling of the conductor can be suppressed, and an effect of ensuring the structural reliability of the entire laminated circuit board can be obtained. In addition, the environment in which this embodiment is particularly effective is effective for a laminated circuit board that is less likely to be deformed by mounting a highly rigid material such as a chip on the semiconductor memory circuit board side than on the control circuit board side. is there. However, the area 108 is a problem when the slits described above are inserted. This area becomes an important part because the wiring concentrates, but at the same time, it becomes a dangerous area where stress concentration occurs due to the slit. Due to this, if only the slit is inserted, there is a possibility that the wiring or the like may break due to stress concentration. Therefore, it is desirable to form a round structure with no corners at the end of the slit in the notch direction. As the round structure without corners described here, the slit front end portion 109 shown in FIG. 1C and the slit front end portion 110 shown in FIG. 1D can be applied. As a result, stress concentration at the corners can be avoided, and the starting point of fracture can be eliminated, which is preferable.

  Next, the molding method for realizing the present embodiment does not require a notch between the terminals as in the prior art, and even if the distance between the terminals is a small pitch, the slits are not different from this. It is possible to put.

  In addition, the present invention is particularly effective when applied to a semiconductor component such as an SD memory card. Portable recording media such as SD memory cards must ensure structural reliability in environments where various load stresses such as twisting and bending are applied, such as in pockets and bags. In particular, in the case of an SD memory card, the amount of deformation increases due to its thin structure with respect to bending and twisting, and the solder that bonds the substrates to each other is peeled off. When the memory card is twisted, the curvature is particularly large near the center of the structure, and there is a problem that the solder at the center is easily peeled off. The present invention can also be applied to solve this, and an example in the case where the present embodiment is applied to a laminated circuit board of an SD memory card will be described below.

(Embodiment 2)
3A-B, 4A-B, and 5A-B are external views of the laminated circuit board according to the second embodiment of the present invention, and the second embodiment will be described using these figures. In these figures, the basic component parts are the same as those shown in FIGS. 1A-B, so the same part numbers are used.

  The configuration of the laminated circuit board of the present embodiment is basically the same as that of the first embodiment, but the way of providing slits is different. This embodiment is effective when a slit having a sufficient length cannot be formed between the terminal 104 and the semiconductor memory 107 due to wiring or the like as shown in FIGS. 3A and 3B. A slit 306 is provided between this terminal and the other terminal with the semiconductor memory 107 interposed therebetween. Although this embodiment does not provide the same effect as the first embodiment, the principle is the same, and it is desirable in that the degree of freedom of deformation of the substrate near the end portion is increased. Moreover, the slit of this Embodiment is not limited to a rectangle, The same effect is acquired even if it is the structure cut out diagonally as shown to FIG. 4A-B. Further, as shown in FIGS. 5A and 5B, the terminals 104 are gathered on one side, and a slit 501 is inserted into the “U” shape between the terminal arrangement row and the terminal arrangement row from the end of the substrate. A structure with a higher degree of freedom when the terminal portion is deformed is also desirable. In such a case, there is no portion supporting the semiconductor memory 107, but by mounting the semiconductor memory on the back side of the substrate and using the conductor 105 having a thickness approximately equal to the thickness of the semiconductor memory, the control circuit substrate 102 is formed. The stacked memory circuit board is in a stable state. The semiconductor memory 107 and the control circuit board in FIG. 5 do not necessarily have to be bonded with resin or the like, and may have a structure that is not bonded by adjusting the thickness of the conductor 105 as described above. . In this case as well, the effect is the same, and the terminal portion can be deformed with a greater degree of freedom as the control circuit board is deformed. In addition, the semiconductor memory 105 has a structure in which stress is not easily applied. This also provides a robust effect in terms of mounting reliability on the circuit board 103.

  The structure of the laminated circuit board as described above can be applied to a structure having terminals arranged at a low pitch, and as a result, an effect of suppressing the peeling of the conductor corresponding to the joint portion between the laminated layers is obtained. The effect of solving such a problem was realized.

(Embodiment 3)
External views of the laminated circuit board of this embodiment are shown in FIGS. 6A-B. Also in this figure, the basic component parts are the same as those shown in FIGS. 1A-B, so the same part numbers are used.

  The configuration of the laminated circuit board of the present embodiment is basically the same as that of the first embodiment, but in addition to the structure of the first embodiment, a slit 601 is newly provided. When the structure shown in the first embodiment is used as described above, stress concentration occurs in the vicinity of the area 108 and a risk such as breakage of the wiring occurs. Therefore, a slit 601 is provided to solve this. The slit 601 is provided by cutting in the direction from the end of the substrate toward the semiconductor memory between the terminals in the center of the arrangement direction of the terminals arranged at a predetermined pitch. This is preferable in that the degree of freedom with respect to the deformation of 108 is widened and the deformation of the area 108 can follow the deformation of the control circuit board 102. As described above, the stress concentration in the area 108 moves to the vicinity of the highly rigid semiconductor memory 107, and an effect of suppressing the breakage of the wiring near the area 108 and the peeling of the conductor 105 can be realized.

Example 1
In this example, the first embodiment is used for a laminated circuit board of a memory card and will be described with reference to FIGS. 2A to 2C.

  FIG. 2A is an outline of a housing defined by the SD memory card standard, FIG. 2B is a plan view of a laminated circuit board provided therein, and FIG. 2C is a front view thereof. In the outer shape of the housing of FIG. 2A, the numerical values shown in the figure indicate the dimensions (unit: mm) of each part. The case 201 has a thickness of 2.1 mm and a volume of 1.6 cc. The casing 201 is formed with a notch 202 for mounting an erroneous erasure prevention lock.

The laminated circuit board shown in FIGS. 2B-C provided in the housing is a control circuit board 203 (plate thickness 0.35 mm: glass fiber woven epoxy resin impregnated sheet) and Sn ₃ Ag ₃ In _0.5 Bi on the control circuit board 203. A semiconductor memory circuit board 204 (plate thickness 0.15 mm: glass epoxy) laminated with a solder alloy 206 (composition: 3 Wt% Ag, 3 Wt% In, 3 Wt% Bi, remaining Sn), and further on the solder alloy 207 The same memory circuit board is laminated, and terminals are provided on the surfaces facing each of the boards, and the solder alloy 207 joins the terminals. Of these, bare chips are mounted on both sides of the semiconductor memory chip 205 on the semiconductor memory circuit board 203, and two (2 stages) on the upper side of the control circuit board and 2 sheets (2 stages) on the lower side as viewed in the drawing. A total of four semiconductor memory circuit boards are stacked, and each of them has a total of eight semiconductor memory chips (flash memory: 9.8 mm × 11.28 mm) with a memory capacity of 256 MB. 1GB memory capacity. Further, a control electronic component 211 such as a microprocessor or CSP is provided on the back surface of the control circuit board. As shown in the figure, each memory circuit board has four slits 210 (width 1 mm × length 4 mm) so that the longitudinal direction is parallel to the terminal arrangement direction. As described above, a laminated circuit board was provided in a polycarbonate casing 201 to produce an SD memory card with a memory capacity of 1 GB.

  In order to demonstrate the robustness of this SD memory card, we conducted a comparative analysis with an SD memory card that does not have slits in the conventional semiconductor memory circuit board. The outer shape of the memory card used for comparison is not the same as the SD memory card shown in FIGS. The finite element method was used for the analysis, and a torsional stress of 6 kg · cm was applied to the two types of memory cards for evaluation. The constraint conditions and weighting conditions at the time of analysis were the same for both types, and area 208 was fixed and torsional stress was applied to area 9 in FIG. 2A. As shown in the figure, the torsional stress applies torque around the Y axis when the X, Y, and Z axes are given. As a result, the memory card with the slit according to the present embodiment has an effect of reducing the maximum stress applied to the solder alloy 206 from 360 MPa to 256 MPa by about 29%, compared with the SD memory card having the laminated substrate without the conventional slit. .

  From this result, it was confirmed that the structure in which the slit was provided between the memory chip and the terminal of this example could secure a higher solder joint reliability than the conventional one with a simple configuration.

  The multilayer circuit board according to the present invention can be used for a multilayer circuit board of a mobile electronic device represented by a memory card, and can be used for a digital camera, a personal computer, a mobile phone, a video camera, an electronic reading terminal, an information portable terminal, a car navigation system, etc. Applicable to portable storage media.

1A is a schematic plan view of a multilayer circuit board according to Embodiment 1 of the present invention, FIG. 1B is a front view thereof, and FIGS. 1C and 1D are external views showing the slit tip shape. FIG. 2A is a schematic external plan view in which the laminated circuit board in Example 1 of the present invention is used for an SD memory card, FIG. 2B is a developed plan view, and FIG. 2C is a front view thereof. 3A is a schematic plan view of the multilayer circuit board according to Embodiment 2 of the present invention, and FIG. 3B is a front view thereof. 4A is a schematic plan view of a multilayer circuit board according to Embodiment 2 of the present invention, and FIG. 4B is a front view thereof. FIG. 5A is a schematic plan view of a laminated circuit board according to Embodiment 2 of the present invention, and FIG. 5B is a front view thereof. 6A is a schematic plan view of a multilayer circuit board according to Embodiment 3 of the present invention, and FIG. 6B is a front view thereof.

Explanation of symbols

101 multilayer circuit board
102,203 Control circuit board
103,204 Semiconductor memory circuit board
104,206 terminals
105,207 Conductor
106,210,306,406,501,601 Slit
107,205 Semiconductor memory
108 Wiring concentration area
109,110 Slit tip
201 case
202 Anti-erase lock
208 Area 1 (Fixed part during analysis)
209 Area 2 (Torsional stress loading part during analysis)
211 Control parts

Claims (4)

A semiconductor memory substrate having a semiconductor memory and first terminals arranged at a predetermined pitch;
A control circuit board having second terminals provided opposite to the first terminals and disposed at a predetermined pitch;
A conductor that joins the first terminal and the second terminal;
The semiconductor memory substrate is provided between the semiconductor memory and the first terminal in a direction in which the first terminal is disposed, and is formed by cutting from an end of the semiconductor memory substrate. A laminated circuit board having one slit.   A plurality of semiconductor memory circuit boards are stacked on the control circuit board, and the slit according to claim 1 is provided on at least one of the stacked semiconductor memory circuit boards. Laminated circuit board.   The laminated circuit board according to claim 1 or 2, wherein a corner of the slit notch tip portion is rounded in an arc shape. A slit formed by cutting in a direction from the end of the semiconductor memory substrate toward the semiconductor memory between the terminals at the center in the arrangement direction of the first terminals arranged at the predetermined pitch. The laminated circuit board according to any one of claims 1 to 3 , further comprising:

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