JP4763472B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a read-only semiconductor memory device.
A read-only semiconductor memory device (ROM) has a number of memory cells connected to a bit line, and the cell information stored in the memory cell is bit-selected by the operation of the memory cell selected based on the selection of the word line. Read out to the line and output the cell information from the IO circuit. In such a ROM, it is necessary to prevent an increase in power consumption due to leakage current or occurrence of malfunction due to miniaturization of elements due to recent high integration.

  FIG. 6 shows an example of a ROM cell. FIG. 5A shows a memory cell storing cell information of “0”, the source of the cell transistor Tr11 composed of an N channel MOS transistor is connected to the low potential side power supply Vss, and the gate is connected to the word line WL. The drain is connected to the bit line BL. Therefore, when the word line WL is selected and the cell transistor Tr11 is turned on, the bit line becomes L level, and cell information of “0” is read out.

  FIG. 6B shows a memory cell storing cell information “1”. The source of the cell transistor Tr12 formed of an N-channel MOS transistor is open, the gate is connected to the word line WL, the drain Is connected to the bit line BL. Therefore, when the word line WL is selected and the cell transistor Tr12 is turned on, the bit line BL becomes the precharge level, and the cell information of “1” is read out.

  FIG. 7 shows a conventional example of a readout circuit. A large number of memory cells 1 and discharge cells 2 are connected to the bit line BL, and are connected to the main bit line MBL via the column selector 3. In the figure, a memory cell 1 is a memory cell storing cell information of “1”. The discharge cell 2 sets the bit line BL to the power supply Vss level prior to the read operation.

  A precharge circuit 4 is connected to the main bit line MBL, the main bit line MBL is precharged to the power supply Vcc level prior to the read operation, and the bit line BL is also precharged by the column selector 3 which is turned on by the column selection signal CL. Charged. The precharge level of the bit line BL is Vcc−Vth if the threshold of the column selector 3 is Vth.

  When the memory cell 1 storing the cell information “1” is selected in the state in which the column selector 3 is turned on during the read operation, the main bit line MBL is maintained substantially at the power supply Vcc level, that is, the H level. Then, the cell information “1” is read, and the cell information is output via the data determination unit 5, the transfer circuit 6, and the output latch circuit 7.

  When the memory cell storing the cell information “0” is selected, the main bit line MBL is almost at the power supply Vss level, that is, the L level, and the cell information “0” is read out. The data is output via the data determination unit 5, the transfer circuit 6 and the output latch circuit 7.

Patent Document 1 discloses a configuration in which a drive amplifier that forms a read circuit of a semiconductor memory device has an amplitude limiting function to reduce power consumption by reducing charge / discharge current flowing through a conductive line.
Japanese Patent Laid-Open No. 7-230690 (FIG. 1)

  In the read circuit shown in FIG. 7, after the precharge circuit 4 causes the main bit line MBL to finish the precharge operation, the potential of the main bit line MBL decreases to an intermediate level, and passes through the inverter circuit 8 constituting the data determination unit 5. There is a problem that the current continues to flow and power consumption is increased.

  That is, as the number of memory cells connected to the bit line BL increases and the length of the bit line BL increases as the ROM is highly integrated and increased in capacity, the load on the precharge circuit 4 increases. The precharge level of main bit line MBL is lowered.

  Further, after the cell information “1” is read from the main bit line MBL, the column selector 3 is turned off, and the discharge cell 2 discharges the bit line BL to almost the power supply Vss level.

  In such a situation, the main bit line is caused by the leakage current of the column selector 3, that is, the leakage current flowing from the main bit line MLB to the bit line BL through the column selector 3 until the next precharge operation is started. The potential of MLB gradually decreases.

  The leakage current has a current value comparable to the current driving capability of the data determination unit 5 as the ROM is highly integrated. As a result, the through current continues to flow through the inverter circuit 8 constituting the data determination unit 5. In addition, there is a problem in that power consumption increases due to this through current, the characteristics of the inverter circuit 8 deteriorate, and destruction may occur.

Patent Document 1 does not disclose a configuration for preventing a through current caused by a leak current of a column selector in a ROM read circuit.
An object of the present invention is to provide a semiconductor memory device capable of preventing an increase in power consumption due to a through current of a data determination unit connected to a main bit line.

  The object is to provide a memory cell connected to a bit line, a discharge circuit for discharging the bit line after cell information is read from the memory cell to the bit line, and a read operation of the cell information. The main bit line and a precharge circuit for precharging the bit line, and interposed between the bit line and the main bit line, during the cell information read operation and the precharge operation prior to the read operation. A column selector that connects the main bit lines to each other, a data determination unit that determines whether cell information read to the main bit line via the column selector is at an H level or an L level, and the data An output latch circuit that latches and outputs the output signal of the determination unit, and the bit line display During chromatography di operation is achieved by a semiconductor memory device including a clamp circuit for clamping the main bit line to the supply voltage.

  According to the present invention, it is possible to provide a semiconductor memory device that can prevent an increase in power consumption due to a through current of a data determination unit connected to a main bit line.

(First embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows the configuration of the ROM. The decoder unit 11 receives an address signal Address including a row address and a column address, an enable signal CE, and a clock signal CK.

  The decoder unit 11 operates based on the clock signal CK. Then, a row address signal is output to the row decoder 12 during a read operation. The row decoder 12 selects a memory cell 13 by outputting a word line selection signal to the word line WL based on the row address signal.

  The decoder unit 11 outputs a discharge signal GI to the discharge circuit 14 to operate the discharge circuit 14. The decoder unit 11 outputs a column selection signal CL to the column selector 15 to select a bit line corresponding to the column address signal.

  The decoder unit 11 outputs a precharge signal CH to the precharge circuit 16 to operate the precharge circuit 16. The decoder unit 11 outputs the latch signals LT and LT to the output latch circuit 17 to operate the output latch circuit 17.

  FIG. 1 shows a cell information reading circuit of the ROM. The discharge circuit 14 and a number of memory cells 13 are connected to the bit line BL. The memory cell 13 is composed of an N-channel MOS transistor, a word line is connected to the gate of the memory cell 13, a word line selection signal is input, and a drain is connected to the bit line BL. The source of the memory cell 13 storing the cell information “1” is in an open state, and the source of the memory cell storing the cell information “0” is connected to the power source Vss. FIG. 1 illustrates one memory cell 13 storing cell information “1”.

  The discharge circuit 14 is composed of an N-channel MOS transistor similar to a memory cell, and the discharge signal GI is input to the gate, the drain is connected to the bit line BL, and the source is connected to the power supply Vss. Therefore, when the H level discharge signal GI is input, the bit line BL is discharged to the power supply Vss level.

  A column selector 15 is interposed between the bit line BL and the main bit line MBL. The column selector 15 is composed of an N-channel MOS transistor, and a column selection signal CL is input to its gate, and its drain and source are connected to the bit line BL and the main bit line MBL. When the H level column selection signal CL is input, the bit line BL and the main bit line MBL are brought into conduction.

  A precharge circuit 16 is connected to the main bit line MBL. The precharge circuit 16 is composed of a P-channel MOS transistor, the precharge signal CH is inputted to the gate, the power supply Vcc is supplied to the source, and the drain is connected to the main bit line MBL.

When the L level precharge signal CH is input, the main bit line MBL is precharged to the power supply Vcc level.
A data determination unit 18 is connected to the main bit line MBL. The data determination unit 18 is a latch circuit composed of inverter circuits 28a and 28b, determines the potential of the main bit line MBL, and outputs it to the output latch circuit 17 as H-level or L-level cell information.

  The output latch circuit 17 includes a transfer circuit 19, a latch circuit 20, and an inverter circuit 21. In the transfer circuit 19, the output signal of the data determination unit 18 is input to the gates of the P-channel MOS transistor Tr1 and the N-channel MOS transistor Tr2, the source of the transistor Tr1 is connected to the power supply Vcc, and the source of the transistor Tr2 is connected to the power supply Vss. Has been.

  A P-channel MOS transistor Tr3 and an N-channel MOS transistor Tr4 are connected between the drains of the transistors Tr1 and Tr2, and the latch signal bars LT and LT are input to their gates. The drains of the transistors Tr3 and Tr4 are connected to the latch circuit 20. The latch signals LT and LT are complementary signals.

  Accordingly, when the latch signal LT becomes H level and the latch signal bar LT becomes L level, the transistors Tr3 and Tr4 are turned on, and an inverted signal of the output signal of the data determination unit 18 is output to the latch circuit 20. Further, when the latch signal LT becomes L level and the latch signal bar LT becomes H level, the data determination unit 18 and the latch circuit 20 are cut off.

  The latch circuit 20 includes inverter circuits 22 a and 22 b and a transfer gate 23. A transfer gate 23 is interposed between the output terminal of the inverter circuit 22b and the input terminal of the inverter circuit 22a.

  The transfer gate 23 is formed by connecting a P channel MOS transistor and an N channel MOS transistor in parallel. The latch signal LT is input to the P channel side gate, and the latch signal bar LT is input to the N channel side gate. Is done.

Then, when the transistors Tr3 and Tr4 are turned on, the transfer gate 23 becomes non-conductive, and when the transistors Tr3 and Tr4 are turned off, the transfer gate 23 becomes conductive.
From the time when the clock signal CK rises from the L level to the H level and the read operation is started until the latch signal LT becomes the H level, the cell information reaches the data determination unit 18 via the column selector 15. Since 19 is non-conductive, it does not reach the latch circuit 20. Therefore, the latch circuit 20 holds the read data of the previous cycle.

  Thereafter, when the latch signal LT becomes H level, the transfer circuit 19 becomes conductive and the read data reaches the latch circuit 20, but since the transfer gate 23 is nonconductive, the read data is not yet latched by the latch circuit 20.

  Next, when the latch signal LT becomes L level again, the transfer circuit 19 becomes immobile and the transfer gate 23 becomes conductive, so that the read data input to the latch circuit 20 is latched. This read data is held until the latch signal LT becomes H level in the next cycle.

  A clamp circuit 24 is connected to the main bit line MBL. The clamp circuit 24 is composed of an N-channel MOS transistor, the drain of the transistor is connected to the main bit line MBL, the source is connected to the power supply Vss, and the control signal MBC is input to the gate.

  The control signal MBC is generated by the control signal generation circuit 25 shown in FIG. In the control signal generation circuit 25, the discharge signal GI is input to the NAND circuit 26, the latch signal LT is input to the inverter circuit 27a, and the output signal of the inverter circuit 27a is input to the NAND circuit 26.

The output signal of the NAND circuit 26 is inverted by the inverter circuit 27b and output as the control signal MBC.
Therefore, the control signal generation circuit 25 outputs the control signal MBC at the H level when the discharge signal GI is at the H level and the latch signal LT is at the L level. Further, when the discharge signal GI is at the H level or the latch signal LT is at the H level, the L level control signal MBC is output.

  Next, the operation of the ROM configured as described above will be described with reference to FIG. The decoder unit 11 operates based on the clock signal CK. First, when the read operation is completed in the previous cycle of the read operation, the discharge signal GI becomes H level. Then, the discharge circuit 14 is turned on, and the bit line BL is discharged.

  Next, the discharge signal GI becomes L level, the discharge operation is finished, and the precharge signal CH becomes H level. Then, the main bit line MBL is precharged to the power supply Vcc level.

  Next, the column selection signal CL becomes H level, the column selector 15 is turned on, the main bit line MBL and the bit line BL become conductive, and the bit line BL is precharged.

  In this state, the memory cell 13 is selected and turned on by the word line selection signal. When the memory cell 13 storing the cell information “1” is selected, the main bit line MBL is maintained at the precharge level, and the cell information reaches the data determination unit 18. After the cell information reaches the data determination unit 18, an H-level one-shot pulse signal is input as the latch signal LT.

  Then, it is inverted by the transfer circuit 19 and output to the latch circuit 20, and the read data A is output via the inverter circuit 22 a and the inverter circuit 21 of the latch circuit 20. When the transfer circuit 19 is cut off, the read data A is latched by the operation of the latch circuit 20.

  When the memory cell 13 in which “0” cell information is stored is selected, the main bit line MBL is substantially at the power supply Vss level, and the cell information is similarly output as read data A.

  After the memory cell 13 is selected, after a predetermined time, that is, when read data reaches the latch circuit 20 from the memory cell 13, the column selection signal CL becomes L level, and the conduction between the bit line BL and the main bit line MBL is established. Blocked. In this state, the discharge signal GI becomes H level, and the bit line BL is discharged.

  When the reading operation of the cell information from the memory cell 13 is finished, the discharging operation is started, and when the transfer circuit 19 is shut off and the reading operation for one cycle is finished, the discharging signal GI is at the H level, and the latch signal LT Becomes L level, the control signal MBC becomes H level.

  Then, the clamp circuit 24 is turned on, and the main bit line MBL is clamped at the power supply Vss level. When the discharge operation ends in the next cycle, the control signal MBC becomes L level and the clamp circuit 24 is also turned off.

In the ROM as described above, the following operational effects can be obtained.
(1) When the bit line BL is discharged, the main bit line MBL is clamped at the power supply Vss level. Therefore, after the cell information “1” is read, the main bit line MBL does not become the intermediate level. Therefore, generation of a through current in the data determination unit 18 can be prevented.
(2) Since generation of a through current in the data determination unit 18 can be prevented, power consumption can be reduced, and destruction of the data determination unit can be prevented before the durability and reliability of the read circuit. Can be improved.
(3) Since the bit line BL and the main bit line MBL can be set to the same potential during the discharge operation of the bit line BL, it is possible to prevent generation of a leak current in the column selector 15.
(4) By providing the clamp circuit 24, the inverter circuit 28b of the data determination unit 18 can be omitted. Accordingly, the area of the readout circuit can be reduced.
(Second embodiment)
FIG. 5 shows a second embodiment. In this embodiment, a P-channel MOS transistor is connected as the clamp circuit 24 between the main bit line MBL and the power supply Vcc, and a control signal MBCX is input to the gate thereof. The control signal MBCX is an inverted signal of the control signal MBC of the first embodiment.

  With such a configuration, when the bit line BL is discharged, the main bit line MBL is clamped at the power supply Vcc level, so that the main bit line MBL does not become an intermediate level after reading the cell information of “1”. . Therefore, the same effects as (1), (2) and (4) obtained in the first embodiment can be obtained.

You may implement the said embodiment in the following aspects.
The control signal for operating the clamp circuit 24 may be generated based on a signal other than the discharge signal and the latch signal.

It is a circuit diagram showing a first embodiment. It is a circuit diagram which shows a control signal generation circuit. It is a block diagram which shows ROM. It is a timing waveform diagram which shows operation | movement of 1st embodiment. It is a circuit diagram which shows 2nd embodiment. (A) and (b) are circuit diagrams showing a memory cell. It is a circuit diagram which shows a prior art example.

Explanation of symbols

13 Memory Cell 14 Discharge Circuit 15 Column Selector 16 Precharge Circuit 17 Output Latch Circuit 18 Data Determination Unit 24 Clamp Circuit BL Bit Line MBL Main Bit Line

Claims (5)

A memory cell connected to the bit line;
A discharge circuit for discharging the bit line after cell information is read from the memory cell to the bit line;
A precharge circuit for precharging the main bit line and the bit line prior to the cell information read operation;
A column selector that is interposed between the bit line and the main bit line and connects the main bit line and the bit line at the time of reading the cell information and at the time of precharging prior to the reading operation;
A data determination unit for determining whether the cell information read to the main bit line via the column selector is at the H level or the L level;
An output latch circuit that latches and outputs an output signal of the data determination unit;
A semiconductor memory device comprising: a clamp circuit that clamps the main bit line to a power supply voltage during a discharge operation of the bit line.   2. The semiconductor memory device according to claim 1, wherein the clamp circuit clamps the main bit line at the same potential as the bit line.   2. The semiconductor memory device according to claim 1, wherein the clamp circuit clamps the main bit line to a low-potential side power supply voltage.   2. The semiconductor memory device according to claim 1, wherein the clamp circuit clamps the main bit line to a high-potential side power supply voltage.   5. The control signal for activating the clamp circuit is generated based on a discharge signal for activating the discharge circuit and a latch signal for activating the output latch circuit. 2. A semiconductor memory device according to claim 1.

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