JP4761773B2 - Display device, inspection method thereof, and inspection system of display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a circuit for inspecting pixel defects in a display device and a method for inspecting pixel defects in a display device.

  In recent years, a liquid crystal display device employing a CG silicon liquid crystal (Continuous Grain Silicon Liquid Crystal) panel has been developed. The CG silicon liquid crystal panel is a liquid crystal panel that employs a TFT (Thin Film Transistor) formed of a CG silicon film as a switching element. CG silicon has a regular arrangement of crystal interfaces and a continuous structure at the atomic level. For this reason, since electrons can move at high speed in CG silicon, a driving integrated circuit can be mounted on the substrate of the liquid crystal panel. As a result, costs are reduced by reducing the number of necessary parts, and miniaturization of devices is progressing.

  In the manufacturing process of such a liquid crystal display device, it is not realistic to completely eliminate the occurrence of defective products. For this reason, various inspections are performed in order to confirm whether or not the liquid crystal display device operates normally after the liquid crystal display devices are manufactured and before they are shipped as products. Among such inspections, in an inspection for examining a defect of a pixel TFT in a liquid crystal panel (hereinafter, a defect of a pixel TFT is referred to as a “pixel defect”), the presence or absence of the pixel defect is visually checked by an inspector. Confirmation has been made. For example, when a test signal for inspection is input to the liquid crystal panel, a portion where a pixel defect exists becomes a bright spot. The inspector checked the presence / absence of the bright spot by visual observation, and discriminated whether the liquid crystal panel was a good product or a defective product.

However, when the inspection is performed as described above, the inspection accuracy varies depending on the work experience of the inspector. For this reason, the reliability of the product after completion of the inspection cannot be said to be sufficient. Therefore, after the pixel capacitor is once charged, the charge accumulated in the pixel capacitor is read, and the presence or absence of a pixel defect is quantitatively checked by a voltage detected by the reading (hereinafter referred to as “detected charge voltage” for convenience). Liquid crystal panels that can be used have been proposed. Hereinafter, the inspection for checking the presence or absence of a pixel defect is referred to as “pixel defect inspection”.
JP-A-5-5866 JP-A-9-15645

  However, even in the above-described liquid crystal panel, the accuracy of the inspection result for the pixel defect inspection is not sufficient for the following reason. In the pixel defect inspection of the liquid crystal panel, a test signal amplified by an analog buffer is applied to each video signal line. However, these analog buffers have characteristic variations, so that the amplification factor of the test signal by the analog buffer differs for each source driver. Therefore, the voltage of the test signal applied to the video signal line is different for each source driver. As a result, the detected charge voltage is also different for each source driver. However, in the above-described pixel defect inspection of the liquid crystal panel, such a variation in the characteristics of the analog buffer is not taken into consideration, and pixel defects are detected by comparing the above-described detected charge voltage with a predetermined reference voltage. The presence / absence is determined. Therefore, high-accuracy inspection results are not obtained, and improvement in inspection accuracy is desired.

  Accordingly, an object of the present invention is to provide a liquid crystal display device capable of obtaining good inspection accuracy while suppressing an increase in cost for pixel defect inspection.

In order to detect a pixel defect in the display unit, the first invention includes a display unit including a plurality of pixel formation units each including a pixel capacitance for holding a voltage of a signal amplified by the amplification unit as a pixel value. A display device having the defect detection means of
The display unit
A plurality of video signal lines for transmitting signals amplified by the amplifying means to the plurality of pixel forming portions;
A plurality of scanning signal lines that intersect with the plurality of video signal lines and are selectively driven;
Including
The plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
Each pixel forming unit includes a switching element that electrically connects a video signal line passing through a corresponding intersection and a pixel capacitor in the pixel forming unit when a scanning signal line passing through the corresponding intersection is selected. Including
The defect detection means includes
A comparator having first and second input terminals for comparing a voltage applied to the first input terminal with a voltage applied to the second input terminal;
When detecting a voltage held in a pixel capacitor in each pixel formation portion, the video signal line electrically connected to the pixel capacitor in the pixel formation portion by the switching element included in the pixel formation portion is connected to the first signal line. And a connection circuit for connecting the amplifying means to the second input terminal so that the signal amplified by the amplifying means is applied to the second input terminal.
Including
The pixel defect is detected by detecting the voltage held in the pixel capacitance in each pixel forming unit and comparing the detected charge voltage, which is the detected voltage, with the voltage of the signal amplified by the amplification means. And
The connection circuit includes a plurality of switching means corresponding to the plurality of video signal lines to switch the transmission destination of the signal amplified by the amplification means,
When each switching means holds the voltage of the signal amplified by the amplifying means in the pixel capacitance in each pixel forming portion, the amplified signal is given to the corresponding video signal line, and the pixel capacitance in each pixel forming portion When detecting the voltage held at the second input terminal, the destination of the signal amplified by the amplifying means is transmitted to the corresponding video signal line and the second signal so that the amplified signal is supplied to the second input terminal. It is characterized in that it switches between the input terminals .

According to a second invention, in the first invention,
Only one amplification means is provided,
The defect detection means includes only one comparator .

According to a third invention, in the first invention,
Only one amplification means is provided,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the voltage held in the pixel capacitance in each pixel formation unit and the amplification Means for connecting to the second input terminal of the comparator corresponding to the video signal line;
The switching unit switches a transmission destination of the signal amplified by the amplification unit between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. .

According to a fourth invention, in the first invention,
A plurality of the amplifying means are provided so as to correspond one-to-one with the plurality of video signal lines,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the video when the voltage held in the pixel capacitance in each pixel forming unit is detected. Amplifying means corresponding to the signal line is connected to the second input terminal of the comparator corresponding to the video signal line;
The switching means determines a transmission destination of the signal amplified by the amplifying means corresponding to the video signal line between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. It is characterized by switching .

According to a fifth invention, in any one of the first to fourth inventions,
The defect detection means outputs a difference voltage indicating a difference between the detected charge voltage and a voltage of a signal amplified by the amplification means.

According to a sixth invention, in the fifth invention,
The difference voltage is output to the outside so that a predetermined discrimination process is performed by an external defect discrimination means.

According to a seventh invention, in the fifth invention,
A difference display unit that displays an image based on the difference voltage is further provided.

According to an eighth invention, in any one of the first to seventh inventions,
A driver monolithic liquid crystal panel is used for the display unit.

According to a ninth aspect of the invention, there is provided a display unit including a plurality of pixel formation units each including a pixel capacitance for holding a voltage of a signal amplified by the amplification unit as a pixel value, for detecting a pixel defect in the display unit An inspection system for a display device, comprising: a display device having a defect detection means; and a defect determination means for determining the presence or absence of a pixel defect in the display unit based on an output from the defect detection means,
The display unit
A plurality of video signal lines for transmitting signals amplified by the amplifying means to the plurality of pixel forming portions;
A plurality of scanning signal lines that intersect with the plurality of video signal lines and are selectively driven;
Including
The plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
Each pixel forming unit includes a switching element that electrically connects a video signal line passing through a corresponding intersection and a pixel capacitor in the pixel forming unit when a scanning signal line passing through the corresponding intersection is selected. Including
The defect detection means includes
A comparator having first and second input terminals for comparing a voltage applied to the first input terminal with a voltage applied to the second input terminal;
When detecting a voltage held in a pixel capacitor in each pixel formation portion, the video signal line electrically connected to the pixel capacitor in the pixel formation portion by the switching element included in the pixel formation portion is connected to the first signal line. And a connection circuit for connecting the amplifying means to the second input terminal so that the signal amplified by the amplifying means is applied to the second input terminal.
Including
The pixel defect is detected by detecting the voltage held in the pixel capacitance in each pixel forming unit and comparing the detected charge voltage, which is the detected voltage, with the voltage of the signal amplified by the amplification means. And
The connection circuit includes a plurality of switching means corresponding to the plurality of video signal lines to switch the transmission destination of the signal amplified by the amplification means,
When each switching means holds the voltage of the signal amplified by the amplifying means in the pixel capacitance in each pixel forming portion, the amplified signal is given to the corresponding video signal line, and the pixel capacitance in each pixel forming portion When detecting the voltage held at the second input terminal, the destination of the signal amplified by the amplifying means is transmitted to the corresponding video signal line and the second signal so that the amplified signal is supplied to the second input terminal. It is characterized in that it switches between the input terminals .

A tenth invention is the ninth invention,
Only one amplification means is provided,
The defect detection means includes only one comparator .

In an eleventh aspect based on the ninth aspect ,
Only one amplification means is provided,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the voltage held in the pixel capacitance in each pixel formation unit and the amplification Means for connecting to the second input terminal of the comparator corresponding to the video signal line;
The switching unit switches a transmission destination of the signal amplified by the amplification unit between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. .

In a twelfth aspect based on the ninth aspect ,
A plurality of the amplifying means are provided so as to correspond one-to-one with the plurality of video signal lines,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the video when the voltage held in the pixel capacitance in each pixel forming unit is detected. Amplifying means corresponding to the signal line is connected to the second input terminal of the comparator corresponding to the video signal line;
The switching means determines a transmission destination of the signal amplified by the amplifying means corresponding to the video signal line between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. It is characterized by switching .

In a thirteenth invention according to any of the ninth to twelfth inventions,
A driver monolithic liquid crystal panel is used for the display unit.

According to the first aspect, the voltage of the video signal output from the amplifying means for charging the pixel capacitor included in the pixel formation portion of the display device under inspection and the voltage (detection) held in the pixel capacitor. Charge voltage). For this reason, the voltage to be compared with the detected charge voltage corresponds to the amplification means of the display device under inspection. In addition, a comparator for comparing two voltages respectively applied to the two input terminals is provided, and in the period in which the voltage held in the pixel capacitor included in each pixel formation portion is to be detected, the pixel formation is performed. The video signal line connected to the unit and the amplifying means for outputting the voltage used for charging the pixel capacitor included in the pixel formation unit are connected to the two input terminals of the comparator, respectively. As a result, the voltage of the video signal used for charging the pixel capacitor and the voltage held in the pixel capacitor are compared for each pixel forming unit without being affected by variations in characteristics of each amplification means. As a result, each pixel forming portion can be accurately inspected for the presence of pixel defects. Further, the transmission destination of the video signal output from the amplifying unit depends on whether the pixel capacitance included in each pixel formation portion is to be charged or whether the voltage held in the pixel capacitance is to be detected. And switching between the video signal line and the comparator. For this reason, the video signal amplified by the same amplifying means can be effectively used for charging the pixel capacitance or for comparison by the comparator.

According to the second aspect , as in the first aspect, it is possible to accurately inspect for the presence or absence of pixel defects without being affected by variations in characteristics of each amplification means. Further, since only one amplifying means is provided, the present invention can be applied effectively even when the amplifying means is provided outside the drive circuit.

According to the third aspect , as in the first aspect, it is possible to accurately inspect for the presence or absence of pixel defects without being affected by variations in characteristics of each amplification means. In addition, since only one amplifying means is provided, the present invention can be effectively applied even when the amplifying means is provided outside the drive circuit, and the comparator is provided corresponding to each video signal line. The present invention can also be applied to display devices that employ not only dot sequential driving but also line sequential driving.

According to the fourth aspect , similarly to the first aspect, it is possible to accurately inspect for the presence or absence of a pixel defect without being affected by variations in characteristics of each amplification unit. Further, since the comparator and the amplifying means are provided corresponding to each video signal line, the present invention can be effectively applied not only to the dot sequential drive but also to the display device adopting the line sequential drive.

According to the fifth aspect of the invention, the difference voltage indicating the difference between the voltage of the video signal used for charging the pixel capacitor and the voltage held in the pixel capacitor is output from the comparator for each pixel forming unit. . Further, as in the first invention, the differential voltage is not affected by variations in the characteristics of each amplification means. For this reason, it is possible to determine the presence / absence of a pixel defect in each pixel formation portion based on the differential voltage detected with high accuracy.

According to the sixth aspect of the invention, on the basis of the difference voltage indicating the difference between the voltage of the video signal used for charging the pixel capacitance and the voltage held in the pixel capacitance, It is determined whether or not there is a pixel defect in the pixel formation portion. For this reason, it is possible to quantitatively determine the presence or absence of pixel defects, and the accuracy of inspection is greatly improved.

According to the seventh aspect , an image based on the difference voltage indicating the difference between the voltage of the video signal used for charging the pixel capacitor and the voltage held in the pixel capacitor is displayed on the difference display unit. As a result, it is possible to easily confirm the result of the pixel defect inspection for each pixel forming portion performed with high accuracy.

According to the eighth aspect , a circuit for inspecting a pixel defect and a display unit can be integrally manufactured.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 1 is a block diagram showing the overall configuration of a CG silicon liquid crystal panel according to the first embodiment of the present invention. The liquid crystal panel includes a display unit 200, a source driver (video signal line driving circuit) 300, and a gate driver (scanning signal line driving circuit) 400. A source driver 300 and a gate driver 400 are formed on a substrate 100 that constitutes the display unit 200, and has a configuration called a monolithic type. Inside the display unit 200, a plurality of scanning signal lines GL1 to GLm and a plurality of video signal lines SL1 to SLn are provided in a grid pattern, and at the intersections of the plurality of scanning signal lines and video signal lines. A pixel formation portion is provided corresponding to each. The scanning signal lines GL1 to GLm are connected to the gate driver 400, and the video signal lines SL1 to SLn are connected to the source driver 300. Each pixel formation portion includes a TFT 51 as a switching element, a pixel electrode 52 connected to the TFT 51, a common electrode 53 provided in common to each pixel formation portion, and between the pixel electrode 52 and the common electrode 53. The liquid crystal layer 54 includes a liquid crystal capacitor 54 formed by the pixel electrode 52 and the common electrode 53, and a charge holding capacitor (not shown) formed in parallel with the liquid crystal capacitor 54. The liquid crystal capacitor 54 and the charge storage capacitor constitute a pixel capacitor, and a voltage indicating a pixel value is held in the pixel capacitor. The source driver 300 includes a pixel defect inspection circuit (defect detection means) 30, a shift register 31, and an analog buffer (amplification means) for amplifying an analog video signal for test (external input signal) AV input from the outside. Driving video signal control switches SW1 to SWn for controlling application of the BF and the amplified signal of the test analog video signal AV (hereinafter referred to as “driving video signal”) to the video signal lines SL1 to SLn. And are included. The detailed configuration of the pixel defect inspection circuit 30 will be described later.

  The source driver 300 controls the test analog video signal AV, the source start pulse signal SSP and the source clock signal SCK for controlling the timing of displaying an image on the display unit 200, and the operation of the pixel defect inspection circuit 30. A pixel defect inspection circuit control signal SG is input from the outside. Of these signals, the shift register 31 receives the source start pulse signal SSP and the source clock signal SCK. Then, the source start pulse signal SSP is sequentially shifted to the subsequent stage in accordance with the rising edge of the pulse of the source clock signal SCK. As a result, the sampling pulses SM1 to SMn are sequentially output from the shift register 31. These sampling pulses SM <b> 1 to SMn are input to the pixel defect inspection circuit 30. The test analog video signal AV input from the outside is amplified by the analog buffer BF and input to the pixel defect inspection circuit 30 as a drive video signal. The pixel defect inspection circuit 30 receives the drive video signal, the sampling pulses SM1 to SMn, and the pixel defect inspection circuit control signal SG, outputs the received sampling pulses SM1 to SMn, and is included in each pixel forming unit. During the period when the pixel capacitor is to be charged, the driving video signal is output, and during the period when the charge accumulated in the pixel capacitor included in each pixel formation portion is to be read, the voltage of the driving video signal and the charge of the pixel capacitor are A difference voltage VS indicating a difference from a voltage (detected charge voltage) detected by reading out is output. The driving video signal control switches SW1 to SWn are turned on during the period in which the sampling pulses SM1 to SMn are output from the pixel defect inspection circuit 30. Then, based on the on / off states of the drive video signal control switches SW1 to SWn, the drive video signal output from the pixel defect inspection circuit 30 is applied to the video signal lines SL1 to SLn. A gate start pulse signal GSP and a gate clock signal GCK for controlling the timing for displaying an image on the display unit 200 are input to the gate driver 400 from the outside. Based on these signals, the gate driver 400 sequentially selects each of the scanning signal lines GL1 to GLm by one horizontal scanning period, so that an active scanning signal (in this embodiment, the logic level is high). ) Is repeated with one vertical scanning period as a cycle. As described above, when the driving video signal is applied to the video signal lines SL1 to SLn and the scanning signal is applied to the scanning signal lines GL1 to GLm, an image based on the test analog video signal AV is displayed on the display unit 200. Is displayed.

  In addition, a pixel defect determination unit (defect determination unit) 600 that determines the presence or absence of a pixel defect in each pixel formation unit is provided outside the liquid crystal panel. The pixel defect determination unit 600 includes an A / D converter 61 and a digital processing device 62. The A / D converter 61 receives the difference voltage VS that is an analog signal output from the pixel defect inspection circuit 30 and converts it into a digital signal. The digital processing device 62 receives the differential voltage VS converted into a digital signal, determines the presence / absence of a pixel defect based on a predetermined program, and displays the result on a screen, for example.

<1.2 Configuration and Operation of Pixel Defect Inspection Circuit>
FIG. 2 is a circuit diagram showing a detailed configuration of the pixel defect inspection circuit 30 in the source driver 300 in the present embodiment. FIG. 2 shows only the portions corresponding to the video signal lines SL1 and SL2 in the first and second columns. The pixel defect inspection circuit 30 includes a differential voltage output buffer (comparator) CMP, AND gates AND1 to ANDn corresponding to the video signal lines SL1 to SLn, and first changeover switches (switching means) SA1 to SAn. , Second changeover switches SB1 to SBn. Note that a connection circuit is realized by the AND gates AND1 to ANDn, the first changeover switches SA1 to SAn, and the second changeover switches SB1 to SBn.

  The AND gates AND1 to ANDn output changeover switch control signals SK1 to SKn based on the sampling pulses SM1 to SMn output from the shift register 31 and the pixel defect inspection circuit control signal SG. Here, the logical product gate outputs a signal indicating the logical product of a plurality of input signals. In the present embodiment, the AND gate AND1 is only in the period when the logic level of the pixel defect inspection circuit control signal SG is high and the AND gates AND1 to ANDn receive the sampling pulses SM1 to SMn from the shift register 31. The logic level of the changeover switch control signals SK1 to SKn output from .about.ANDn becomes high level. The difference voltage output buffer CMP calculates a voltage difference between two input signals applied to the two input terminals, amplifies the voltage difference, and outputs the difference voltage VS from the output terminal.

  FIG. 3 illustrates operations of the first changeover switch SAi and the second changeover switch SBi provided in correspondence with the video signal line SLi in the i-th column (1 ≦ i ≦ n) in the present embodiment. FIG. When the logical level of the changeover switch control signal SKi output from the AND gate ANDi is low, the analog buffer BF and the video signal line SLi are connected as shown in FIG. On the other hand, when the logic level of the changeover switch control signal SKi is high, as shown in FIG. 3B, one input terminal (second input terminal) of the differential voltage output buffer CMP is connected to the analog buffer BF. Then, the other input terminal (first input terminal) of the differential voltage output buffer CMP is connected to the video signal line SL. Since the sampling pulses SM1 to SMn are sequentially output from the shift register 31, at most one of the changeover switch control signals SK1 to SKn has a logic level of high in any period. is there. Accordingly, the output buffer BF and the differential voltage output buffer CMP are not simultaneously connected by two or more first changeover switches, and two or more video signal lines and the differential voltage output buffer CMP are simultaneously connected. There is nothing.

<1.3 Operation during LCD panel inspection>
Next, with reference to FIG. 4 to FIG. 9, the operation of the liquid crystal panel during pixel defect inspection will be described. In the pixel defect inspection, first, the pixel capacitors of all the pixel forming portions in the display unit 200 of the liquid crystal panel are sequentially charged. When charging of all the pixel capacitors is completed, the charge accumulated in each pixel capacitor is sequentially read. Then, the presence / absence of a pixel defect is determined based on the detected charge voltage detected by reading the charges. As described above, during the period in which the pixel defect inspection is performed in the present embodiment, the charging period for sequentially charging the pixel capacities of the pixel forming units in the display unit 200 and the pixel capacities of the pixel forming units. There is a charge readout period for sequentially reading out the accumulated charges.

  FIG. 4 is a signal waveform diagram of the scanning signals G1 to Gm output from the gate driver 400 and the pixel defect inspection circuit control signal SG input from the outside in the present embodiment. As described above, during the pixel defect inspection period, there are a charging period and a charge reading period. First, in the charging period, the logical levels of the scanning signals G1 to Gm sequentially become high level for each horizontal scanning period. As for the pixel defect inspection circuit control signal SG, the logic level is maintained at a low level during the charging period. After the end of the charging period, a charge reading period is started, and the logic levels of the scanning signals G1 to Gm are sequentially changed to a high level for each horizontal scanning period again. The pixel defect inspection circuit control signal SG is maintained at a high logic level during the charge readout period.

  FIG. 5 is a signal waveform diagram for explaining the operation of the liquid crystal panel during the period in which the pixel defect inspection is performed in this embodiment. V (P11) represents the waveform of the voltage held in the pixel capacitance of the pixel formation portion provided corresponding to the intersection of the scanning signal line GL1 in the first row and the video signal line SL1 in the first column. ing. V (P12) represents a waveform of a voltage held in the pixel capacitance of the pixel formation portion provided corresponding to the intersection of the scanning signal line GL1 in the first row and the video signal line SL2 in the second column. .

  FIG. 6 is a circuit diagram for explaining the operation of the liquid crystal panel in the period indicated by reference numeral T11 in FIG. During this period, the sampling pulse SM1 is output from the shift register 31, and the logic level of the pixel defect inspection circuit control signal SG is low. Therefore, the logic level of the changeover switch control signal SK1 output from the AND gate AND1. Becomes low level. For this reason, the analog buffer BF and the video signal line SL1 are connected. Further, since the driving video signal control switch SW1 is turned on by the sampling pulse SM1, the driving video signal output from the analog buffer BF is applied to the video signal line SL1 in the display unit 200, and the video signal line SL1 is set. Charged. At this time, since the logic level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL1. The capacity is charged. Further, during this period, the driving video signal control switches SW2 to SWn are in an off state, so that the driving video signal is not applied to the video signal lines SL2 to SLn from the second column to the nth column.

  FIG. 7 is a circuit diagram for explaining the operation of the liquid crystal panel during the period indicated by reference numeral T12 in FIG. During this period, the sampling pulse SM2 is output from the shift register 31, and the logical level of the pixel defect inspection circuit control signal SG is low. Therefore, the logical level of the changeover switch control signal SK2 output from the AND gate AND2. Becomes low level. For this reason, the analog buffer BF and the video signal line SL2 are connected. Further, since the driving video signal control switch SW2 is turned on by the sampling pulse SM2, the driving video signal output from the analog buffer BF is applied to the video signal line SL2 in the display unit 200, and the video signal line SL2 is set. Charged. At this time, since the logical level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL2 The capacity is charged. Further, during this period, the driving video signal control switches SW1, SW3 to SWn are in an off state, so that the video signal lines SL1, SL3 to SLn from the first column and the third column to the nth column are driven. No video signal is applied.

  As described above, the video signal lines SL1 to SLn from the first column to the n-th column are sequentially charged and the scanning signal lines GL1 and 1 in the first row to which the scanning signal having the high logic level is supplied. Pixel capacitors included in pixel formation portions provided corresponding to the intersections with the video signal lines SL1 to SLn from the column to the n-th column are sequentially charged. Further, as shown in FIG. 4, the scanning signals G1 to Gm are sequentially activated for each horizontal scanning period, so that the pixel capacitors included in all the pixel forming portions are sequentially charged.

  When the charging period ends, the charge reading period starts. FIG. 8 is a circuit diagram for explaining the operation of the liquid crystal panel during the period indicated by T21 in FIG. During this period, the sampling pulse SM1 is output from the shift register 31, and the logic level of the pixel defect inspection circuit control signal SG is high. Therefore, the logic level of the changeover switch control signal SK1 output from the AND gate AND1. Becomes high level. Therefore, one input terminal of the difference voltage output buffer CMP and the analog buffer BF are connected by the first changeover switch SA1, and the other input terminal of the difference voltage output buffer CMP and the video signal line SL1 are changed to the second changeover. Connected by the switch SB1. Further, the driving video signal control switch SW1 is turned on by the sampling pulse SM1. At this time, since the logic level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL1. The charge accumulated in the capacitor is read out. As a result, the drive video signal output from the analog buffer BF is input to one input terminal of the differential voltage output buffer CMP, and the detected charge voltage obtained by reading the charge is input to the other input terminal. As a result, from the output terminal of the differential voltage output buffer CMP, the voltage of the driving video signal and the pixel capacitance included in the pixel formation portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL1. A difference voltage VS indicating a difference from the detected charge voltage due to reading of the accumulated charge is output.

  FIG. 9 is a circuit diagram for explaining the operation of the liquid crystal panel during the period indicated by reference numeral T22 in FIG. During this period, the sampling pulse SM2 is output from the shift register 31, and the logical level of the pixel defect inspection circuit control signal SG is high. Therefore, the logical level of the changeover switch control signal SK2 output from the AND gate AND2 Becomes high level. Therefore, one input terminal of the difference voltage output buffer CMP and the analog buffer BF are connected by the first changeover switch SA2, and the other input terminal of the difference voltage output buffer CMP and the video signal line SL2 are changed to the second changeover. Connected by the switch SB2. Further, the driving video signal control switch SW2 is turned on by the sampling pulse SM2. At this time, since the logical level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL2 The charge accumulated in the capacitor is read out. As a result, the drive video signal output from the analog buffer BF is input to one input terminal of the differential voltage output buffer CMP, and the detected charge voltage obtained by reading the charge is input to the other input terminal. As a result, from the output terminal of the differential voltage output buffer CMP, the voltage of the driving video signal and the pixel capacitance included in the pixel formation portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL2 are supplied. A difference voltage VS indicating a difference from the detected charge voltage due to reading of the accumulated charge is output.

  As described above, corresponding to the intersections of the scanning signal line GL1 in the first row to which the scanning signal having the high logic level is supplied and the video signal lines SL1 to SLn from the first column to the n-th column. The charges accumulated in the pixel capacitors included in the provided pixel formation portion are sequentially read out. Then, based on the difference voltage VS between the detected charge voltage and the voltage of the driving video signal output from the analog buffer BF, the pixel formation portion provided corresponding to the scanning signal line GL1 in the first row. The pixel defect determination unit 600 sequentially determines whether or not there is a pixel defect. Further, when the scanning signals G1 to Gm are sequentially activated for each horizontal scanning period, it is sequentially determined whether or not there is a pixel defect in all the pixel forming portions in the display unit 200.

<1.4 Effect>
As described above, according to the present embodiment, detection is performed by reading the voltage of the driving video signal for charging the pixel capacitor included in the pixel formation unit in the display unit 200 and the charge accumulated in the pixel capacitor. A difference voltage VS indicating a difference from the detected charge voltage is generated, and based on the difference voltage VS, the pixel defect determination unit 600 provided outside the liquid crystal panel determines whether there is a pixel defect in each pixel formation unit. . In each pixel formation portion, the driving video signal used for charging the pixel capacitance and the driving video signal to be compared with the detected charge voltage are amplified by the same analog buffer. For this reason, the difference voltage VS between the voltage used for charging the pixel capacitance and the detected charge voltage is detected for each pixel formation portion without being affected by variations in the characteristics of the analog buffer. Further, in the pixel defect determination unit 600, quantitative determination based on the difference voltage VS is performed regarding the presence or absence of a pixel defect. Thereby, compared with visual confirmation, an inspection precision becomes high significantly and the reliability with respect to an inspection result improves significantly. In addition, by adopting the CG silicon liquid crystal panel, a circuit for inspecting pixel defects (the above-described pixel defect inspection circuit) can be manufactured in the panel, which greatly increases the cost for manufacturing the inspection apparatus. Can be suppressed.

<2. Second Embodiment>
<2.1 Overall configuration>
Next, a second embodiment of the present invention will be described. FIG. 10 is a block diagram showing an overall configuration of a liquid crystal panel according to the second embodiment of the present invention. In the present embodiment, unlike the configuration of the first embodiment shown in FIG. 1, analog buffers (amplifying means) BF1 to BFn are provided corresponding to the video signal lines SL1 to SLn, respectively. The driving video signal control switches SW1 to SWn are provided between the analog buffers BF1 to BFn and the pixel defect inspection circuit 30, respectively. Furthermore, processing for determining the presence or absence of pixel defects in each pixel forming portion is performed inside the liquid crystal panel. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the same reference numerals are given to the same components, and detailed description thereof is omitted.

<2.2 Configuration and Operation of Pixel Defect Inspection Circuit>
FIG. 11 is a circuit diagram showing a detailed configuration of the pixel defect inspection circuit 30 in the source driver 300 in the present embodiment. FIG. 11 shows only portions corresponding to the video signal lines SL1 and SL2 in the first and second columns. The pixel defect inspection circuit (defect detection means) 30 includes difference voltage output buffers (comparators) CMP1 to CMPn, AND gates AND1 to ANDn, and first changeover switches corresponding to the video signal lines SL1 to SLn, respectively. (Switching means) SA1 to SAn, second changeover switches SB1 to SBn, and pixel forming portions for displaying the results of pixel defect inspection (hereinafter referred to as “inspection result display pixel forming portions”) GA1 to GAn. And. The inspection result display pixel formation portions GA1 to GAn include TFTs and pixel capacitors. Note that a connection circuit is realized by the AND gates AND1 to ANDn, the first changeover switches SA1 to SAn, and the second changeover switches SB1 to SBn.

  The AND gates AND1 to ANDn output the changeover switch control signals SK1 to SKn based on the sampling pulses SM1 to SMn output from the shift register 31 and the pixel defect inspection circuit control signal SG, as in the first embodiment. . The difference voltage output buffers CMP1 to CMPn calculate the voltage difference between the voltages of the two input signals applied to the two input terminals, amplify the voltage difference, and output the difference voltage from the output terminal. The TFTs of the inspection result display pixel formation portions GA1 to GAn are turned on when the logic level of the pixel defect inspection circuit control signal SG is high. For this reason, the pixel capacities of the inspection result display pixel forming portions GA1 to GAn are based on the difference voltages output from the difference voltage output buffers CMP1 to CMPn when the logic level of the pixel defect inspection circuit control signal SG is high. Charged.

  FIG. 12 illustrates operations of the first changeover switch SAi and the second changeover switch SBi provided in correspondence with the video signal line SLi in the i-th column (1 ≦ i ≦ n) in the present embodiment. FIG. It is assumed that the drive video signal control switch SWi is in an on state. When the logic level of the changeover switch control signal SKi output from the AND gate ANDi is low, as shown in FIG. 12A, the analog buffer BFi and the video signal line SLi are connected, and the difference voltage output buffer CMPi. The two input terminals are open. On the other hand, when the logical level of the changeover switch control signal SKi is high, as shown in FIG. 12B, one input terminal (second input terminal) of the differential voltage output buffer CMPi and the analog buffer BFi are connected. Then, the other input terminal (first input terminal) of the differential voltage output buffer CMPi and the video signal line SLi are connected.

<2.3 Operation during LCD panel inspection>
Next, with reference to FIGS. 13 to 17, the operation of the liquid crystal panel during pixel defect inspection will be described. FIG. 13 is a signal waveform diagram for explaining the operation of the liquid crystal panel during the period in which the pixel defect inspection is performed in the present embodiment. Also in the present embodiment, as in the first embodiment, the charging period for sequentially charging the pixel capacitances of the pixel forming portions in the display unit 200 and the charges accumulated in the pixel capacitors of the pixel forming portions are sequentially set. There is a charge readout period to read out. V (GA1) indicates the waveform of the voltage held in the pixel capacitance of the inspection result display pixel formation portion GA1 provided corresponding to the video signal line SL1 in the first column. V (GA2) indicates the waveform of the voltage held in the pixel capacitance of the inspection result display pixel formation portion GA2 provided corresponding to the video signal line SL2 in the second column.

  FIG. 14 is a circuit diagram for explaining the operation of the liquid crystal panel in the period indicated by T11 in FIG. During this period, the sampling pulse SM1 is output from the shift register 31, and the logic level of the pixel defect inspection circuit control signal SG is low. Therefore, the logic level of the changeover switch control signal SK1 output from the AND gate AND1. Becomes low level. Further, the driving video signal control switch SW1 is turned on by the sampling pulse SM1. For this reason, the analog buffer BF1 and the video signal line SL1 are connected. Thus, the test analog video signal AV is amplified by the analog buffer BF1, and the drive video signal output from the analog buffer BF1 is applied to the video signal line SL1. At this time, since the logic level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL1. The capacity is charged. Further, during this period, the driving video signal control switches SW2 to SWn are in an off state, so that the driving video signal is not applied to the video signal lines SL2 to SLn from the second column to the nth column.

  FIG. 15 is a circuit diagram for explaining the operation of the liquid crystal panel in the period indicated by T12 in FIG. During this period, the sampling pulse SM2 is output from the shift register 31, and the logical level of the pixel defect inspection circuit control signal SG is low. Therefore, the logical level of the changeover switch control signal SK2 output from the AND gate AND2. Becomes low level. Further, the driving video signal control switch SW2 is turned on by the sampling pulse SM2. For this reason, the analog buffer BF2 and the video signal line SL2 are connected. As a result, the test analog video signal AV is amplified by the analog buffer BF2, and the driving video signal output from the analog buffer BF2 is applied to the video signal line SL2. At this time, since the logical level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL2 The capacity is charged. Further, during this period, the driving video signal control switches SW1, SW3 to SWn are in an off state, so that the video signal lines SL1, SL3 to SLn from the first column and the third column to the nth column are driven. No video signal is applied.

  As described above, the video signal lines SL1 to SLn from the first column to the n-th column are sequentially charged and the scanning signal lines GL1 and 1 in the first row to which the scanning signal having the high logic level is supplied. Pixel capacitors included in pixel formation portions provided corresponding to the intersections with the video signal lines SL1 to SLn from the column to the n-th column are sequentially charged. Furthermore, as in the first embodiment, the scanning signals G1 to Gm are sequentially activated for each horizontal scanning period, whereby the pixel capacitors included in all the pixel forming portions are sequentially charged.

  When the charging period ends, the charge reading period starts. FIG. 16 is a circuit diagram for explaining the operation of the liquid crystal panel in the period indicated by T21 in FIG. During this period, the sampling pulse SM1 is output from the shift register 31, and the logic level of the pixel defect inspection circuit control signal SG is high. Therefore, the logic level of the changeover switch control signal SK1 output from the AND gate AND1. Becomes high level. Further, the driving video signal control switch SW1 is turned on by the sampling pulse SM1. For this reason, one input terminal of the differential voltage output buffer CMP1 is connected to the analog buffer BF1, and the other input terminal of the differential voltage output buffer CMP1 is connected to the video signal line SL1. At this time, since the logic level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL1. The charge accumulated in the capacitor is read out. As a result, the drive video signal output from the analog buffer BF1 is input to one input terminal of the differential voltage output buffer CMP1, and the detected charge voltage obtained by reading the charge is input to the other input terminal. As a result, from the output terminal of the differential voltage output buffer CMP1, the pixel formation provided corresponding to the voltage of the driving video signal output from the analog buffer BF1 and the intersection of the scanning signal line GL1 and the video signal line SL1. A difference voltage indicating a difference from the detected charge voltage due to reading of the charge accumulated in the pixel capacitor included in the unit is output. Further, as described above, since the logic level of the pixel defect inspection circuit control signal SG is high, the TFT of the inspection result display pixel formation portion GA1 connected to the output terminal of the differential voltage output buffer CMP1 is in the ON state. Thus, the pixel capacitance of the inspection / inspection result display pixel forming portion GA1 is charged based on the difference voltage.

  FIG. 17 is a circuit diagram for explaining the operation of the liquid crystal panel in the period indicated by reference numeral T22 in FIG. During this period, the sampling pulse SM2 is output from the shift register 31, and the logical level of the pixel defect inspection circuit control signal SG is high. Therefore, the logical level of the changeover switch control signal SK2 output from the AND gate AND2 Becomes high level. Further, the driving video signal control switch SW2 is turned on by the sampling pulse SM2. For this reason, one input terminal of the differential voltage output buffer CMP2 and the analog buffer BF2 are connected, and the other input terminal of the differential voltage output buffer CMP2 is connected to the video signal line SL2. At this time, since the logical level of the scanning signal G1 supplied to the scanning signal line GL1 is high, the pixels of the pixel forming portion provided corresponding to the intersection of the scanning signal line GL1 and the video signal line SL2 The charge accumulated in the capacitor is read out. As a result, the drive video signal output from the analog buffer BF2 is input to one input terminal of the differential voltage output buffer CMP2, and the detected charge voltage obtained by reading the charge is input to the other input terminal. As a result, from the output terminal of the differential voltage output buffer CMP2, the pixel formation provided corresponding to the voltage of the driving video signal output from the analog buffer BF2 and the intersection of the scanning signal line GL1 and the video signal line SL2 A difference voltage indicating a difference from the detected charge voltage due to reading of the charge accumulated in the pixel capacitor included in the unit is output. Further, since the logic level of the pixel defect inspection circuit control signal SG is high as described above, the TFT of the inspection result display pixel formation portion GA2 connected to the output terminal of the differential voltage output buffer CMP2 is in the ON state. Thus, the pixel capacitance of the inspection test result display pixel forming portion GA2 is charged based on the difference voltage.

  As described above, corresponding to the intersections of the scanning signal line GL1 in the first row to which the scanning signal having the high logic level is supplied and the video signal lines SL1 to SLn from the first column to the n-th column. The charges accumulated in the pixel capacitors included in the provided pixel formation portion are sequentially read out. Based on the difference voltage between the detected charge voltage and the voltage of the driving video signal output from the analog buffers BF1 to BFn, the pixel capacities of the inspection result display pixel forming portions GA1 to GAn are sequentially charged. .

  FIG. 18 is a block diagram for explaining display of a pixel defect inspection result on a screen. In the present embodiment, as shown in FIG. 18A, an area (hereinafter referred to as “inspection result display unit”) 500 for displaying the result of pixel defect inspection is provided separately from the normal display unit 200. It has been. In this inspection result display section (difference display section) 500, grayscale display according to the voltage held in the pixel capacitances of the inspection result display pixel forming sections GA1 to GAn is performed. More specifically, the larger the voltage held in the pixel capacitor is, the more white it is displayed, and the smaller the voltage held in the pixel capacitor is, the more black it is displayed.

  Through the above-described operation, first, the result of the pixel defect inspection for the pixel formation portion associated with the scanning signal line in the first row is reflected on the display of the inspection result display portion 500. Further, as shown in FIG. 4, the scanning signals G1 to Gm are sequentially activated by one horizontal scanning period, so that the pixel defect inspection results for all the pixel forming portions in the display portion 200 are inspected results display portion 500. It is reflected sequentially in the display.

  FIG. 18A shows an example in which the inspection result display unit 500 is arranged on the upper portion of the display unit 200. However, the present invention is not limited to this, and for example, as shown in FIG. 18B. The inspection result display unit 500 may be disposed below the display unit 200.

<2.4 Effect>
As described above, according to the present embodiment, detection is performed by reading the voltage of the driving video signal for charging the pixel capacitor included in the pixel formation unit in the display unit 200 and the charge accumulated in the pixel capacitor. A difference voltage indicating a difference from the detected charge voltage is generated, and the pixel capacities of the inspection result display pixel forming portions GA1 to GAn are charged based on the difference voltage. In each pixel formation portion, the driving video signal used for charging the pixel capacitance and the driving video signal to be compared with the detected charge voltage are amplified by the same analog buffer. Therefore, the difference voltage between the voltage used for charging the pixel capacitance and the detected charge voltage is detected for each pixel formation unit without being affected by the variation in the characteristics of the analog buffer. Thereby, the inspection accuracy of the pixel defect inspection is increased, and the reliability with respect to the inspection result is improved. In addition, since the inspection result is reflected in the display of the inspection result display unit 500 in the liquid crystal panel, it is possible to easily confirm the result of the pixel defect inspection for each pixel forming unit performed with high accuracy.

<3. Variations>
In the first embodiment, the pixel defect determination unit 600 includes the A / D converter 61 and the digital processing device 62, but the present invention is not limited to this. For example, as illustrated in FIG. 19A, the pixel defect determination unit 600 includes a voltage measurement device 63 and a determination unit 64, and the determination unit 64 is based on the difference voltage VS measured by the voltage measurement device 63. Thus, the presence or absence of a pixel defect may be determined. Further, as shown in FIG. 19B, the pixel defect determination unit 600 includes a waveform measuring device 65 and a determination unit 64, and the determination unit 64 is based on the difference voltage VS measured by the waveform measurement device 65. Thus, the presence or absence of a pixel defect may be determined.

  In each of the above embodiments, the case where the dot sequential driving is adopted as a method for driving the video signal line has been described as an example. However, the present invention is not limited to this, and the line sequential driving is adopted. It can also be applied when When applied to line sequential driving, it is necessary to provide a differential voltage output buffer for each video signal line.

1 is a block diagram illustrating an overall configuration of a liquid crystal panel according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a detailed configuration of a pixel defect inspection circuit in the first embodiment. FIG. 4 is a circuit diagram for explaining operations of a first changeover switch and a second changeover switch in the first embodiment. It is a signal waveform diagram of a scanning signal and a pixel defect inspection circuit control signal in the first embodiment. In the said 1st Embodiment, it is a signal waveform diagram for demonstrating operation | movement of the liquid crystal panel during the period when pixel defect inspection is performed. FIG. 6 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which the video signal lines in the first column are charged in the first embodiment. FIG. 6 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which the video signal lines in the second column are charged in the first embodiment. FIG. 6 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which charges accumulated in a pixel capacitor of a pixel formation unit associated with a first column video signal line are read in the first embodiment. . FIG. 6 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which charges accumulated in a pixel capacitor of a pixel formation unit associated with the video signal line in the second column are read in the first embodiment. . It is a block diagram which shows the whole structure of the liquid crystal panel which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing a detailed configuration of a pixel defect inspection circuit in the second embodiment. FIG. 6 is a circuit diagram for explaining operations of a first changeover switch and a second changeover switch in the second embodiment. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating operation | movement of the liquid crystal panel during the period when pixel defect inspection is performed. FIG. 10 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which the video signal lines in the first column are charged in the second embodiment. FIG. 10 is a circuit diagram for explaining an operation of the liquid crystal panel during a period when the video signal lines in the second column are charged in the second embodiment. FIG. 10 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which charges accumulated in a pixel capacitor of a pixel formation unit associated with a video signal line in the first column are read in the second embodiment. . FIG. 10 is a circuit diagram for explaining an operation of the liquid crystal panel during a period in which charges accumulated in a pixel capacitor of a pixel formation unit associated with a video signal line in the second column are read in the second embodiment. . In the said 2nd Embodiment, it is a block diagram for demonstrating the display on the screen of the result of a pixel defect test | inspection. It is a block diagram which shows the structure of the pixel defect determination part which concerns on the modification of the said 1st Embodiment.

Explanation of symbols

30. Pixel defect inspection circuit (defect detection means)
DESCRIPTION OF SYMBOLS 200 ... Display part 300 ... Source driver 400 ... Gate driver AV ... Analog video signal for test BF, BF1-BFn ... Analog buffer (amplification means)
CMP, CMP1 to CMPn: differential voltage output buffer (comparator)
GL1 to GLn ... scanning signal line SG ... pixel defect inspection circuit control signal SA1 to SAn ... first changeover switch (switching means)
SB1 to SBn: second changeover switch SL1 to SLn: video signal line SW1 to SWn: driving video signal control switch

Claims (13)

A display unit including a plurality of pixel formation units each including a pixel capacitance for holding the voltage of the signal amplified by the amplification unit as a pixel value, and having a defect detection unit for detecting a pixel defect in the display unit; A display device,
The display unit
A plurality of video signal lines for transmitting signals amplified by the amplifying means to the plurality of pixel forming portions;
A plurality of scanning signal lines that intersect with the plurality of video signal lines and are selectively driven;
Including
The plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
Each pixel forming unit includes a switching element that electrically connects a video signal line passing through a corresponding intersection and a pixel capacitor in the pixel forming unit when a scanning signal line passing through the corresponding intersection is selected. Including
The defect detection means includes
A comparator having first and second input terminals for comparing a voltage applied to the first input terminal with a voltage applied to the second input terminal;
When detecting a voltage held in a pixel capacitor in each pixel formation portion, the video signal line electrically connected to the pixel capacitor in the pixel formation portion by the switching element included in the pixel formation portion is connected to the first signal line. And a connection circuit for connecting the amplifying means to the second input terminal so that the signal amplified by the amplifying means is applied to the second input terminal.
Including
The pixel defect is detected by detecting the voltage held in the pixel capacitance in each pixel forming unit and comparing the detected charge voltage, which is the detected voltage, with the voltage of the signal amplified by the amplification means. And
The connection circuit includes a plurality of switching means corresponding to the plurality of video signal lines to switch the transmission destination of the signal amplified by the amplification means,
When each switching means holds the voltage of the signal amplified by the amplifying means in the pixel capacitance in each pixel forming portion, the amplified signal is given to the corresponding video signal line, and the pixel capacitance in each pixel forming portion When detecting the voltage held at the second input terminal, the destination of the signal amplified by the amplifying means is transmitted to the corresponding video signal line and the second signal so that the amplified signal is supplied to the second input terminal. The display device is characterized in that it switches between input terminals of the display. Only one amplification means is provided,
The display device according to claim 1, wherein the defect detection unit includes only one of the comparators . Only one amplification means is provided,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the voltage held in the pixel capacitance in each pixel formation unit and the amplification Means for connecting to the second input terminal of the comparator corresponding to the video signal line;
The switching unit switches a transmission destination of the signal amplified by the amplification unit between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. The display device according to claim 1. A plurality of the amplifying means are provided so as to correspond one-to-one with the plurality of video signal lines,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the video when the voltage held in the pixel capacitance in each pixel forming unit is detected. Amplifying means corresponding to the signal line is connected to the second input terminal of the comparator corresponding to the video signal line;
The switching means determines a transmission destination of the signal amplified by the amplifying means corresponding to the video signal line between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. The display device according to claim 1, wherein the display device is switched . The defect detecting means, and outputs a difference voltage representing the difference between the voltage of the amplified signal by the detecting charge voltage and the amplifying unit, according to any one of claims 1 to 4 Display device. 6. The display device according to claim 5 , wherein the difference voltage is output to the outside so that a predetermined determination process is performed by an external defect determination unit. The display device according to claim 5 , further comprising a difference display unit that displays an image based on the difference voltage. The display device according to any one of claims 1 to 7 , wherein a driver monolithic liquid crystal panel is employed in the display unit. A display having a display unit including a plurality of pixel formation units each including a pixel capacitance for holding the voltage of the signal amplified by the amplification unit as a pixel value, and having a defect detection unit for detecting a pixel defect in the display unit An inspection system for a display device, comprising: a device; and a defect determination unit that determines the presence or absence of a pixel defect in the display unit based on an output from the defect detection unit,
The display unit
A plurality of video signal lines for transmitting signals amplified by the amplifying means to the plurality of pixel forming portions;
A plurality of scanning signal lines that intersect with the plurality of video signal lines and are selectively driven;
Including
The plurality of pixel forming portions are arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively.
Each pixel forming unit includes a switching element that electrically connects a video signal line passing through a corresponding intersection and a pixel capacitor in the pixel forming unit when a scanning signal line passing through the corresponding intersection is selected. Including
The defect detection means includes
A comparator having first and second input terminals for comparing a voltage applied to the first input terminal with a voltage applied to the second input terminal;
When detecting a voltage held in a pixel capacitor in each pixel formation portion, the video signal line electrically connected to the pixel capacitor in the pixel formation portion by the switching element included in the pixel formation portion is connected to the first signal line. And a connection circuit for connecting the amplifying means to the second input terminal so that the signal amplified by the amplifying means is applied to the second input terminal.
Including
The pixel defect is detected by detecting the voltage held in the pixel capacitance in each pixel forming unit and comparing the detected charge voltage, which is the detected voltage, with the voltage of the signal amplified by the amplification means. And
The connection circuit includes a plurality of switching means corresponding to the plurality of video signal lines to switch the transmission destination of the signal amplified by the amplification means,
When each switching means holds the voltage of the signal amplified by the amplifying means in the pixel capacitance in each pixel forming portion, the amplified signal is given to the corresponding video signal line, and the pixel capacitance in each pixel forming portion When detecting the voltage held at the second input terminal, the destination of the signal amplified by the amplifying means is transmitted to the corresponding video signal line and the second signal so that the amplified signal is supplied to the second input terminal. Inspection system characterized by switching between input terminals of Only one amplification means is provided,
The inspection system according to claim 9, wherein the defect detection unit includes only one of the comparators . Only one amplification means is provided,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the voltage held in the pixel capacitance in each pixel formation unit and the amplification Means for connecting to the second input terminal of the comparator corresponding to the video signal line;
The switching unit switches a transmission destination of the signal amplified by the amplification unit between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. The inspection system according to claim 9. A plurality of the amplifying means are provided so as to correspond one-to-one with the plurality of video signal lines,
The defect detection means includes a plurality of the comparators corresponding one-to-one with the plurality of video signal lines,
The connection circuit connects each video signal line to the first input terminal of the comparator corresponding to the video signal line and detects the video when the voltage held in the pixel capacitance in each pixel forming unit is detected. Amplifying means corresponding to the signal line is connected to the second input terminal of the comparator corresponding to the video signal line;
The switching means determines a transmission destination of the signal amplified by the amplifying means corresponding to the video signal line between the corresponding video signal line and the second input terminal of the comparator corresponding to the video signal line. The inspection system according to claim 9, wherein the inspection system is switched . The inspection system according to any one of claims 9 to 12 , wherein a driver monolithic liquid crystal panel is adopted in the display unit.

Images