JP4760819B2 - Information processing apparatus and information processing program - Google Patents

Description

  The present invention relates to an information processing apparatus and an information processing program.

  In the image processing process, a histogram is often created.

  Patent Document 1 below discloses a technique for reducing the storage area in the frequency direction by storing in a stack memory when the memory for storing the frequency of the histogram overflows.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for suppressing the memory capacity used for the histogram by thinning out image data.

  Patent Document 3 listed below discloses a technique for suppressing the memory capacity by shifting the frequency data to the right and reducing the accuracy when the histogram data overflows.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for generating a histogram from a DC component of each block unit by orthogonally transforming image data in units of blocks and compressing the image data.

  Patent Document 5 below discloses a technique for generating a histogram only for a pixel having a pixel value smaller than the first boundary value and a pixel having a pixel value larger than the second boundary value, thereby suppressing the memory capacity.

JP-A-7-182514 JP-A-8-139916 JP 2002-109535 A JP 2006-295625 A JP 11-75077 A

  An object of the present invention is to suppress the storage capacity of a work space required for image processing.

An information processing apparatus according to one embodiment of the present invention includes an acquisition unit configured to acquire coordinates in a work space based on a value of a pixel arranged in an image space, and a part forming part of the work space with respect to a storage device When setting means for setting the work space and the partial work space including the coordinates acquired by the acquisition means are not set, the acquired coordinates are included while avoiding duplication with the already set partial work space. An instruction unit that instructs the setting unit to set a partial work space; and an update unit that updates a value of the partial work space with respect to the coordinates acquired by the acquisition unit, the instruction unit including: the partial work space centered coordinates the coordinates acquired by the acquisition means, a candidate part working space to be set, if partial work space is the candidate is not a duplicate and preset portions workspace, In the candidate That the partial working space, have lines to the setting unit a command to set as a partial working space including the coordinates acquired by the acquisition means, if the partial working space which is the candidate overlaps with preset portion working space , by changing the center coordinates of the candidates part working space to identify the part working space that does not overlap the previously set partial working space, and instructs the setting to said setting means, and characterized in that To do .
An information processing program according to an aspect of the present invention includes an acquisition unit configured to acquire coordinates in a work space based on a value of a pixel arranged in the image space, and a part forming part of the work space with respect to a storage device When setting means for setting the work space and the partial work space including the coordinates acquired by the acquisition means are not set, the acquired coordinates are included while avoiding duplication with the already set partial work space. The information processing apparatus functions as an instruction unit that instructs the setting unit to set a partial work space, and an update unit that updates a value of the partial work space with respect to the coordinates acquired by the acquisition unit. The instruction means sets a partial work space having the coordinates acquired by the acquisition means as a central coordinate as a candidate of the set partial work space, and the partial work space that is the candidate overlaps with the already set partial work space. If not Sina, a partial work space is the candidate, have lines to the setting unit a command to set as a partial working space including the coordinates acquired by the acquisition means, preset partial working space which is the candidate If it overlaps with the set partial work space, the center coordinate of the candidate partial work space is changed to identify a partial work space that does not overlap with the set partial work space, and It is characterized by instructing setting .
Note that the description from the next sentence to the paragraph [0027] of this paragraph corresponds to the description of claims 1-9 described in the claims at the beginning of the application of this application.
In one aspect of the information processing apparatus of the present invention, the acquisition unit that acquires coordinates in the work space based on the values of the pixels arranged in the image space and the storage device form a part of the work space. When the setting means for setting the partial work space and the partial work space including the coordinates acquired by the acquisition means are not set, avoid the overlap with the set partial work space, and obtain the acquired coordinates. Instructing means for instructing the setting means to set a partial working space to be included, and updating means for updating the value of the partial working space with respect to the coordinates acquired by the acquiring means.

  In one aspect of the information processing apparatus of the present invention, the instruction means changes at least one of a position, a size, or a shape of a partial work space that is a candidate to be set, thereby setting the already set partial work space. A partial work space that does not overlap with is specified, and setting is instructed to the setting means.

  In one aspect of the information processing apparatus of the present invention, the instruction unit selects a space including the acquired coordinates from a space obtained by dividing the work space into a plurality of parts in advance, thereby setting the already set partial work. A partial work space that does not overlap with the space is specified, and the setting is instructed to the setting means.

  In one aspect of the information processing apparatus of the present invention, the work space is a histogram space in which a histogram is constructed, and the partial work space is a partial histogram space forming a part of the histogram space.

  In one aspect of the information processing apparatus of the present invention, the histogram space is a space having a pixel value as a coordinate axis, and the acquisition unit is configured to store the histogram space based on the pixel value arranged in the image space. Get the coordinates of.

  In one aspect of the information processing apparatus of the present invention, the image processing apparatus includes a division unit that divides the image space into a plurality of division spaces, and the acquisition unit, the setting unit, the instruction unit, and the update unit include two or more The processing for the divided space is executed separately.

  In one aspect of the information processing apparatus of the present invention, the acquisition unit, the setting unit, the instruction unit, and the update unit execute processing for two or more of the divided spaces in parallel.

  In one aspect of the information processing apparatus of the present invention, a reconfigurable circuit whose circuit specifications can be reconfigured, a plurality of the storage devices which can be inputted / outputted from the reconfigurable circuit, and a process for two or more of the divided spaces The reconfigurable circuit includes at least configuration means that configures the setting means and the updating means so that they are executed in parallel using the storage devices different from each other.

  In one aspect of the information processing apparatus of the present invention, the acquisition unit that acquires coordinates in the work space based on the values of the pixels arranged in the image space and the storage device form a part of the work space. When the setting means for setting the partial work space and the partial work space including the coordinates acquired by the acquisition means are not set, avoid the overlap with the set partial work space, and obtain the acquired coordinates. An information processing apparatus is caused to function as an instruction unit that instructs the setting unit to set a partial work space including the update unit and an update unit that updates a value of the partial work space with respect to the coordinates acquired by the acquisition unit.

  According to the first aspect of the present invention, it is possible to suppress the storage capacity of the work space used in the image processing by setting the necessary partial work space while avoiding duplication with the already set partial work space. Become.

  According to the second aspect of the present invention, since the partial work space that does not overlap with the already set partial work space is dynamically determined, it is possible to expect an effect that the partial work space can be set in the vicinity where it is actually used.

  According to the invention of claim 3, it is possible to promptly determine a partial work space that does not overlap with the already set partial work space.

  According to the invention of claim 4, it is possible to suppress the storage capacity of the histogram space used in the image processing.

  According to the invention of claim 5, it is possible to suppress the storage capacity of the histogram space having the pixel value as the coordinate axis.

  According to the sixth aspect of the present invention, it is possible to suppress the storage capacity of the histogram space by using the characteristic that neighboring pixel values tend to be similar in the image space.

  According to the invention of claim 7, it is possible to speed up the image processing for the image space.

  According to the invention of claim 8, improvement in image processing efficiency in the information processing apparatus can be expected.

  According to the ninth aspect of the present invention, it is possible to suppress the storage capacity of the work space used in the image processing by setting the necessary partial work space while avoiding duplication with the already set partial work space. A program is provided.

[Explanation of terms and concepts]
Hereinafter, terms and concepts described in the claims, the specification, or the drawings will be described.

  An information processing device may be constructed by controlling a computer (hardware) having an arithmetic processing function by controlling a program (software), or an equivalent function may be realized by hardware without using a program. Also good. The computer may be a single device or a plurality of devices that are communicably connected. The program may be installed in the computer in advance, or may be provided and installed through a recording medium or a network.

  The image space refers to a space (typically a two-dimensional space) occupied by an image (sometimes referred to as image data). Here, it is assumed that the image is expressed in a raster format including a plurality of pixels (sometimes referred to as pixel data). The acquisition means acquires one or more coordinates in the work space based on one or more pixels.

  The work space is a one-dimensional or two-dimensional space, and is a space where work related to image processing is performed. The acquisition unit acquires the coordinates of the work space, for example, according to information that the pixel has or by performing a predetermined calculation on the information that the pixel has. As the work space, a space different from the image space is typically adopted. Depending on the characteristics (for example, the size or shape) of the image space or the pixel characteristics (for example, the size or variation of the pixel value), the work space may change its size or shape. The size or shape may be determined without depending on it. Examples of the work space include a histogram space given based on pixel characteristics, various function spaces, and the like. Here, the histogram is also called a frequency distribution table or the like and represents a distribution of values (data) at each coordinate in the histogram space. The histogram is used, for example, for examining the luminance distribution (or color density distribution) of the image or examining the Hough transform result.

  The storage device is a device that can store data temporarily or permanently, and is configured using, for example, a semiconductor memory or a magnetic disk. The storage device may or may not be included in the information processing apparatus. The setting means sets the partial work space in the storage device. The setting is performed, for example, by assigning a location for storing a value at each coordinate in the partial work space to the storage area. The size and shape of the partial work space are typically determined in advance. However, the size or shape may be changed based on information related to the image (for example, the type of the image, the result of analysis performed before that). The partial work space may be a continuous partial space in the work space or a discontinuous partial space (for example, a space selected at intervals).

  The instruction means instructs the setting means to set the partial work space including the acquired coordinates when the partial work space including the acquired coordinates is not set. The instruction is performed so as to avoid a duplication with an already set partial work space (a duplication of storage locations) and set a new partial work space. The instructing means may specify a partial work space that does not overlap with the already set partial work space by changing at least one of the position, size, or shape of the partial work space that is a candidate to be set. Specifically, an example of translating a partial work space that is a candidate for setting along one or more spatial coordinate axes of the work space, or one or two or more of the partial work spaces that are candidates for setting are set Examples of reduction along the spatial coordinate axes of the above, examples of changing the shape of the partial work space that is a candidate for setting, and the like. In addition, the instruction unit specifies a partial work space that does not overlap with the previously set partial work space by selecting a space including the acquired coordinates from among a plurality of spaces obtained by dividing the work space in advance. Also good.

  The update means performs a process of updating the value for the acquired coordinates in the partial work space. Note that the data processing apparatus may further include a processing unit that performs processing relating to an image with reference to one or more (or all) updated partial work spaces.

[Embodiment]
Embodiments of the present invention are illustrated below.

  FIG. 1 is a diagram showing an outline of a hardware configuration of an image processing apparatus 10 according to the present embodiment. The image processing apparatus 10 is an example of an information processing apparatus, and includes a bus 12 as an internal communication path, a CPU (central processing unit) 14 connected to the bus 12, a memory 16, a reconfigurable device 18, a CDD (compact disk). Each component includes a drive 20, a UI (user interface) 22, a scanner 24, a printer 26, and a network interface 28.

  The CPU 14 is a device that performs arithmetic processing based on a program stored in the memory 16, and performs image processing, control of each component device, and the like. The memory 16 is a storage device made of a semiconductor element or a magnetic disk. The memory 16 stores programs, image data, and the like. The reconfigurable device 18 is a device capable of dynamically reconfiguring circuit specifications. The CDD 20 is a device that performs input / output with respect to a CD (compact disc) as a recording medium. A program for controlling the CPU 14, the reconfigurable device 18, and the like may be provided through a CD. In this case, the installation is performed via the CDD 20. The UI 22 includes a display device such as a liquid crystal display that presents image information to the user, and an input device such as a touch panel and a keyboard that receives instructions from the user. The scanner 24 is a device that reads paper and generates image data, and the printer 26 is a device that prints on paper based on the image data. The network interface 28 is a device that communicates with a network 30 such as the Internet. A program for controlling the CPU 14, the reconfigurable device 18, and the like may be provided through the network 30, and in this case, the installation is performed via the network interface 28.

  FIG. 2 is a diagram showing an outline of the hardware configuration of the reconfigurable device 18. The reconfigurable device 18 is provided with a reconfigurable area 40 as a reconfigurable circuit. The reconfigurable area 40 is provided with a plurality of ALU elements 42, 44, and 46 as PEs (processor elements) that perform arithmetic and RAM elements 50, 52, and 54 as PEs that perform storage. The configuration memory 60 is a storage device that stores data that defines the circuit specifications of the reconfigurable area 40. In accordance with the data stored in the configuration memory 60, the calculation specifications or the connection specifications in the reconfigurable area 40 are changed, and the reconfigurable area 40 can execute specific processing in hardware.

  The reconfigurable area 40 and the configuration memory 60 are connected to a bus 62 as an internal communication path. The bus 62 includes a control unit 64 that controls each component of the reconfigurable device 18, a memory 66 that stores data used in the reconfigurable area 40 and the configuration memory 60, and the bus 12 of the image processing device 10. An interface 68 for mediating the communication is provided.

  FIG. 3 shows an example in which a histogram processing function for pixel values of image data is constructed by reconfiguring the reconfigurable region 40. Here, in the reconfigurable area 40, the absolute address 70 and the “read” valid signal 72 are input and sent to the address control unit 74. The “read” valid signal 72 is a signal that defines the type of processing for the absolute address 70, and writing (generation) to the histogram is performed when Lo, and reading from the histogram is performed when Hi. As the absolute address 70, a pixel value is given when the “read” valid signal 72 is Lo, and a histogram read address is given when it is Hi.

  The address control unit 74 has an address management table 76 therein, and refers to the address management table 76 to generate a relative address 78 for writing or reading out the histogram from the absolute address 70. Further, the address control unit 74 outputs the frequency control signal 80 when the relative address 78 to be read corresponding to the absolute address 70 exists, and when it does not exist, the address control unit 74 outputs the high frequency control signal 80.

  The output relative address 78 is input to a histogram generation memory 82 constructed using RAM elements, and the histogram generation memory 82 outputs data of frequency 84 corresponding to the relative address 78. When data is written, the output frequency 84 is output to the incrementer 86, and the incrementer 86 performs one increment (that is, addition of plus 1) and re-inputs it to the histogram generation memory 82. . Further, when data is read, the output frequency 84 is output to the selection circuit SEL 88. In this SEL 88, when the frequency control signal 80 is Lo, the frequency 84 is selected, and when it is Hi, “0” is selected and output.

  FIG. 4 is a diagram illustrating an example of the address management table 76. As shown in FIG. 4, the address management table 76 includes N = 1, 2,. . . A “partial histogram” having a number is set. For each partial histogram, a memory range in the histogram generation memory 82, an offset value for conversion between an absolute address and a relative address, a central pixel value that is a pixel value arranged at the central coordinates of each partial histogram, and A range of pixel values of each partial histogram (a range of coordinate values in the partial histogram space) is registered. In the example of FIG. 4, in the partial histogram with N = 1, the memory range is (0, 0) to (X_len-1, Y_len-1), and the offset value is X_len * (N-1) * Y_len = 0 (where * Indicates multiplication). The center pixel value is (r1, g1, b1) in the RGB color system, and the pixel value range is a range from -7 to +8 (r1-7 to r1 + 8, g1-7 to g1 + 8) around the center pixel value. , B1-7 to b1 + 8). Similarly, in the partial histogram of N = 2, the memory range is (0, Y_len) to (X_len−1, 2 * Y_len−1), and the offset value is X_len * (N−1) * Y_len = X_len * Y_len, The center pixel value is set to (r2, g2, b2), and the pixel value range is set to (r2-7 to r2 + 8, g2-7 to g2 + 8, b2-7 to b2 + 8).

  FIG. 5 is a diagram schematically illustrating an example of a partial histogram secured in the histogram generation memory 82. Here, a memory range corresponding to three partial histograms given numbers N = 1, 2, 3 is secured. The size of each memory range is X_len in the horizontal direction and Y_len in the vertical direction. In each memory range, a coordinate value that fills the space of the partial histogram with the central pixel value as the center is set.

  FIG. 6 is a diagram for explaining the configuration of the address control unit 74 in detail. The address control unit 74 is provided with a range determination unit 90 and a relative address generation unit 104. The range determination unit 90 receives the absolute address 70 and the “read” valid signal 72. Then, it is determined with reference to the address management table 76 whether or not the histogram of the portion corresponding to the absolute address 70 is set in the histogram generation memory 82.

  Specifically, when writing is performed, the table read value 94 is acquired from the address management table 76, and the partial histogram in which the range corresponding to the input pixel value is set or is still set. Judge whether or not. If it is set, the center pixel value 100 and the offset value 102 of the partial histogram are transmitted to the relative address generation unit 104. On the other hand, when it has not been set yet, a new partial histogram is set so as not to overlap with the already set partial histogram. Then, the table write value 92 is transmitted to the address management table 76 for registration, and the center pixel value 100 and the offset value 102 are transmitted to the relative address generation unit 104. The relative address generation unit 104 performs address conversion based on the input absolute address 70, center pixel value 100, and offset value 102, and outputs a relative address 78.

  In addition, when performing reading, the range determination unit 90 uses the address management table 76 to determine what number of partial histograms the partial histogram corresponding to the absolute address 70 is set to. Refer to and judge. When set, the corresponding center pixel value 100 and offset value 102 are output to the relative address generation unit 104 and the Lo frequency control signal 80 is output. The mode in which the relative address generation unit 104 outputs the relative address 78 based on the input absolute address 70, the central pixel value 100, and the offset value 102 is the same as in the case of writing. On the other hand, when the partial histogram is not set, the Hi frequency control signal 80 is output to cause the SEL 88 to output “0”.

  Next, an example of processing in the image processing apparatus 10 will be described with reference to FIGS. Here, it is assumed that the image data generated by the scanner 24 is subjected to background processing using a histogram and is printed from the printer 26. Here, the background processing refers to processing for performing color density uniformity or the like on a background portion having a substantially uniform color density in image data. Removal of the show-through portion that occurs in copying is also a type of ground processing.

  FIG. 7 schematically shows an example in which a background removal block 112 as a divided space is set for the image data 110 and histogram processing is performed on the block. Here, it is assumed that each pixel of the image data 110 is expressed in a 24-bit (= 256 × 256 × 256) RGB color system having a density of 0 to 255. For this reason, in the histogram space 114, the coordinate axes of R, G, and B are set to a size of 0 to 255. For each grid, at most, the frequency of the size (number of pixels) of the image space is given.

  When a histogram is created in the histogram space 114 based on the pixel value of each pixel of the background removal block 112, a portion having a frequency other than 0 is often locally distributed like the group set 116. This is based on the characteristic that, in general image data, in an image space, the value of a pixel often changes gradually with the position (the values of neighboring pixels are similar). Therefore, the image processing apparatus 10 sets a partial histogram for a local coordinate range such as the group set 116.

  FIG. 8 is a flowchart showing the overall flow from the start to the end of the background processing. When the execution of background processing starts (S10), a background removal block is set in the image data, and the processing is sequentially performed for each block (S12). In the process, first, a histogram is generated (S14), and then the generated histogram is read (S16). Then, based on the readout result, background processing such as equalizing the color density of the portion determined to be the background is performed (S18). Subsequently, it is determined whether or not all blocks have been processed on all pages of the image data (S20). If not, the process from step S12 is repeated. If so, the process is performed. The process ends (S22).

  FIG. 9 is a flowchart for explaining the details of the histogram generation process (step S14 in FIG. 8). When the histogram generation processing for each background removal block is started, pixel values are sequentially input to the range determination unit 90 of the address control unit 74 (S30). The range determination unit 90 refers to the address management table 76 to determine whether it is “within allocated range”, that is, whether it is included in the already set partial histogram (S32).

FIG. 10 is a diagram showing an example of this determination using an abstract expression based on the C language. Here, the input 8-bit pixel values of R, G, and B are expressed as rr, gg, and bb (in this case, the absolute address based on the pixel value can be expressed in the form of 0xrrggbb. ). It is assumed that each partial histogram of the address management table 76 shown in FIG. 4 is set. In the calculation shown in FIG. 10, by calculating whether or not the pixel value (rr, gg, bb) is included in the pixel value range of the partial histogram, it is determined which partial histogram is in the allocation range. Yes.
For example, the condition “r1-7 ≦ rr ≦ r1 + 8 && g1-7 ≦ gg ≦ g1 + 8 && b1-7 ≦ bb ≦ b1 + 8” is such that rr is in the range of r1-7 to r1 + 8 and gg is g1-7. It is in the range of ˜g1 + 8 and bb is in the range of b1-7 to b1 + 8, that is, the pixel value (rr, gg, bb) is included in the partial histogram of N = 1.

  If it is determined that the pixel value is within the range of a pixel value of a partial histogram, the relative address generation unit 104 calculates a relative address based on the input pixel value, the center pixel value, and the like read from the address management table 76. (S34). For example, when it is within the range of the partial histogram of number N = 2 in the address management table 76, the input pixel value (rr, gg, bb), the center pixel value = (r2, g2, b2), and the offset value X_len * ( 2-1) Using * Y_len, the relative address is ((rr−r2) + (16 / 2-1) << 8) | ((gg−g2) + (16 / 2-1) << 4 ) | ((Bb−b2) + (16 / 2-1)) + X_len * (2-1) * Y_len. That is, the calculation of the relative address is obtained by calculating the difference between the center pixel value and the input pixel value and further adding the offset value in the histogram generation memory 82. In the histogram generation memory 82, the frequency of the relative address is increased by 1 using the incrementer 86 (S36). The processing after step S30 described above is continued until the processing for all the pixels in the block is completed (S38).

  In step S32, if it is outside the “allocated range”, the range determining unit 90 assigns a new range to the memory, that is, sets a new partial histogram (S40). In this setting, it is determined whether or not the distance between the central pixels is a predetermined value (for example, 16) or more in order to check the overlap between the partial histogram to be newly set and the already set partial histogram ( S42). If it is equal to or greater than the predetermined value, it is determined that there is no overlap, and “number”, “memory range”, “offset value”, “center pixel value”, and “pixel value range” are registered in the address management table 76 (S44). As a result, a new partial histogram area is secured in the histogram generation memory 82.

  On the other hand, when it is determined that the distance between the central pixel values is shorter than the predetermined value and there is an overlap, a partial histogram that changes the distance of the central pixel value of each partial histogram to a predetermined value or more is calculated. (S46). FIG. 11 is a diagram for explaining processing for determining the center pixel value of a new partial histogram. In the new partial histogram, first, the distance between the central coordinates (rr, gg, bb) of the partial histogram determined to be overlapped with the center coordinates of the already set partial histogram, for example, (r1, g1, b1) is evaluated. Thus, the central pixel value of the new partial histogram is determined. However, there is a possibility that the partial histogram set in this way may overlap with other partial histograms that have already been set, so it is necessary to confirm again whether or not there is overlap with other partial histograms. The new partial histogram obtained in this way is registered in the address management table 76 (S44).

  FIG. 12 is a diagram schematically showing how a new partial histogram is obtained in this way. FIG. 12A is a diagram showing the background removal block 112 of the image data 110, and the background removal block 112 shows the first three pixels 120, 122, and 124. FIGS. 12B, 12C, 12D, and 12E are diagrams showing the process of setting a partial histogram in the histogram generation memory 82 in this order.

  In the histogram generation process, first, as shown in FIG. 12B, a partial histogram 130 having a pixel value range centered on the pixel value of the first pixel 120 is stored in the memory ranges (0, 0) to (63, 63). The pixel value of the subsequent pixel 122 is not included in the partial histogram 130, and the pixel value of the pixel 122 is separated from the central pixel value (also the pixel value of the pixel 120) of the partial histogram 130 by a predetermined value or more. . In this case, as shown in FIG. 12C, a partial histogram 132 is newly set with the pixel value of the pixel 122 as the central pixel value.

  The pixel value of the next pixel 124 is not included in the range of the partial histograms 130 and 132 and is separated from the central pixel value of the partial histogram 130 by a predetermined value or more, but from the central pixel value of the partial histogram 132 from the predetermined value. Is also close. In this case, as shown in FIG. 12D, if the partial histogram 134 having the pixel value of the pixel 124 as the central pixel value is set, the partial histogram 132 overlaps. Therefore, as shown in FIG. 12E, a central pixel value 136 having a predetermined distance from the central pixel value of the partial histogram 134 is obtained, and a partial histogram 138 centering on this is set.

  FIG. 13 is a flowchart for explaining the details of the histogram reading process (step S16 in FIG. 8). In reading, a read address is input as the absolute address 70 to the address control unit 74 (S50), and Hi indicating read is input as the “read” valid signal 72. The range determination unit 90 refers to the address management table 76 to determine whether or not the range is allocated as a partial histogram (S52).

  FIG. 14 is a diagram illustrating an example of this determination using an abstract expression based on the C language. Here, from the read address 0xrrggbb, the R pixel value rr is obtained by the calculation of “rr = 0xrrggbb & 0xFF0000) >> 16, and the G pixel value gg is obtained by the calculation of“ gg = 0xrrggbb & 0xFF00) >> 8 ”. The pixel value bb is obtained by calculation of “bb = 0xrrggbb & 0xFF)”. If the obtained pixel values of (rr, gg, bb) are within the range of the partial histogram of N = 1 (r1-7 to r1 + 8, g1-7 to g1 + 8, b1-7 to b1 + 8), N Included in the partial histogram of N = 2 and within the range of the partial histogram of N = 2 (r2-7 to r2 + 8, g2-7 to g2 + 8, b2-7 to b2 + 8) To be judged.

  Thus, when it is determined that it is within the allocated range, the relative address generation unit 104 calculates the relative address (S54). For example, when it is determined that it is included in the partial histogram of N = 2, the 12-bit relative address is “((rr−r2) + (16 /) using the central pixel value (r2, g2, b2)”. 2-1) << 8) | ((gg-g2) + (16 / 2-1) << 4) | ((bb-b2) + (16 / 2-1)) + X_len * (2-1) * Y_len "is calculated. That is, the relative address is obtained by adding the offset value of the internal memory to the address obtained from the distance from the center pixel of each color component and the position of the center pixel. The relative address may be registered in the address management table 76 when the partial histogram is generated. Further, the range determination unit 90 controls the frequency control signal 80 to switch to Lo so that the SEL 88 outputs the read frequency 84 from the histogram generation memory 82 (S56).

  On the other hand, if it is determined in step S52 that it is not included in any of the partial histograms, the frequency control signal 80 is switched to Hi and controlled to output a value of “0” from the SEL 88 (S60). In subsequent step S58, it is determined whether or not all the histogram data in the range necessary for the background processing has been read (S58). If not read, the processing from step S50 is repeated, and if read, the reading processing is terminated. .

  FIG. 15 is a diagram illustrating an aspect in which such background processing is processed in parallel. Here, the image data 110 shown in FIG. 7 is converted into a plurality of strip regions 150, 152, 154,. . . , And background removal blocks 160, 162, 164,. . . Is set. The reconfigurable area 40 of the reconfigurable device 18 is reconfigured with circuit specifications for performing processing on the background removal block in each band-like area in parallel, and the histogram generation memories 170, 172, and 174 are also reconfigured. It is prepared for each band area. Generally, the background removal block requires a large memory capacity, but the memory capacity to be used is small when a partial histogram is used. Further, by setting the background removal block to be small, the maximum frequency added to the histogram is also reduced. For this reason, there is room for setting a plurality of histogram generation memories in a plurality of RAM elements in the reconfigurable area 40.

It is a figure explaining the hardware structural example of an image processing apparatus. It is a figure explaining the hardware structural example of a reconfigurable apparatus. It is a figure explaining the example of the circuit specification constructed | assembled in the reconfigurable area | region. It is a figure explaining the example of an address management table. It is a figure which shows the example of a setting of the partial histogram with respect to a histogram generation memory. It is a figure explaining the structural example of an address control part. It is a figure explaining the example of a setting of the histogram in background processing. It is a flowchart which shows the flow of ground processing. It is a flowchart which shows the production | generation process of a histogram. It is a figure which shows the example of judgment whether a pixel value is contained in a partial histogram. It is a figure which shows the example which calculates | requires the center pixel value of the partial histogram to set. It is a figure which shows the example of a change of the center pixel value of the partial histogram to set. It is a flowchart which shows the example which reads a frequency from the produced | generated histogram. It is a figure which shows the example of judgment whether a read address is contained in a partial histogram. It is a figure which shows the example which performs background processing in parallel.

Explanation of symbols

  10 image processing device, 12, 62 bus, 14 CPU, 16 memory, 18 reconfigurable device, 20 CDD, 22 UI, 24 scanner, 26 printer, 28 network interface, 30 network, 40 reconfigurable area, 42, 44 , 46 ALU element, 50, 52, 54 RAM element, 60 Config memory, 64 Control unit, 66 Memory, 68 interface, 70 Absolute address, 72 “Read” valid signal, 74 Address control unit, 76 Address management table, 78 Relative Address, 80 degrees control signal, 82, 170, 172, 174 Histogram generation memory, 84 degrees, 86 incrementer, 88 SEL, 90 range determination section, 104 relative address generation section, 110 image data, 12,160,162,164 background removal block, 114 histogram space, 116 group set, 120, 122, 124 pixels, 130,132,134,138 partial histogram, 150, 152, 154 belt-shaped region.

Claims (7)

An acquisition means for acquiring coordinates in the work space based on the values of the pixels arranged in the image space;
Setting means for setting a partial work space forming a part of the work space with respect to the storage device;
When the partial work space including the coordinates acquired by the acquisition unit is not set, the instruction to set the partial work space including the acquired coordinates is avoided while avoiding duplication with the already set partial work space. Instruction means for the setting means;
Updating means for updating the value of the partial work space with respect to the coordinates acquired by the acquiring means;
With
The instruction means includes
A partial work space having the coordinates acquired by the acquisition means as a central coordinate is set as a candidate for the partial work space to be set,
When the partial work space is the candidate is not a duplicate and preset portions workspace, a partial work space is the candidate, an instruction to set as a partial working space including the acquired coordinates by the acquisition unit There line in the setting means,
When the candidate partial work space overlaps with the preset partial work space, the partial work space that does not overlap with the preset partial work space is obtained by changing the central coordinates of the candidate partial work space. An information processing apparatus characterized by specifying the setting means and instructing the setting means for the setting . The information processing apparatus according to claim 1,
The work space is a histogram space in which a histogram is constructed,
The information processing apparatus according to claim 1, wherein the partial work space is a partial histogram space forming a part of the histogram space. The information processing apparatus according to claim 2 ,
The histogram space is a space having pixel values as coordinate axes,
The information processing apparatus according to claim 1, wherein the acquisition unit acquires coordinates in the histogram space based on values of pixels arranged in the image space. The information processing apparatus according to claim 2 ,
Dividing means for dividing the image space into a plurality of divided spaces;
The information processing apparatus, wherein the acquisition unit, the setting unit, the instruction unit, and the update unit separately execute processing for two or more of the divided spaces. The information processing apparatus according to claim 4 ,
The information processing apparatus, wherein the acquisition unit, the setting unit, the instruction unit, and the update unit execute processing on two or more of the divided spaces in parallel. The information processing apparatus according to claim 5 ,
A reconfigurable circuit with reconfigurable circuit specifications;
A plurality of the storage devices capable of inputting and outputting from the reconfigurable circuit;
The reconfigurable circuit includes at least configuration means for configuring the setting means and the updating means so that processing for two or more of the divided spaces is executed in parallel using the different storage devices. An information processing apparatus characterized by the above. An acquisition means for acquiring coordinates in the work space based on the values of the pixels arranged in the image space;
Setting means for setting a partial work space forming a part of the work space with respect to the storage device;
When the partial work space including the coordinates acquired by the acquisition unit is not set, the instruction to set the partial work space including the acquired coordinates is avoided while avoiding duplication with the already set partial work space. Instruction means for the setting means;
Updating means for updating the value of the partial work space with respect to the coordinates acquired by the acquiring means;
As an information processing device,
The instruction means includes
A partial work space having the coordinates acquired by the acquisition means as a central coordinate is set as a candidate for the partial work space to be set,
When the partial work space is the candidate is not a duplicate and preset portions workspace, a partial work space is the candidate, an instruction to set as a partial working space including the acquired coordinates by the acquisition unit There line in the setting means,
When the candidate partial work space overlaps with the preset partial work space, the partial work space that does not overlap with the preset partial work space is obtained by changing the central coordinates of the candidate partial work space. An information processing program characterized by specifying the setting means and instructing the setting means for the setting .

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