JP4759008B2 - PLL circuit using varactor for VCO - Google Patents

Description

  The present invention relates to a PLL circuit including a VCO that uses a varactor, and more particularly to a PLL circuit that can change the gain of a VCO that is a component thereof.

  Conventionally, in order to solve the conflicting demands of reducing the lockup time and phase noise in the PLL, the open loop gain (or open loop bandwidth) of the PLL is high (or wide) at the time of lockup, and after the lockup Lowering (or narrowing) has been done. As described in Non-Patent Document 1, the variable of the open loop gain of the PLL has been performed by switching the resistance of the loop filter and the sampling period of the phase comparison result. 6 is a diagram showing a block diagram of this variable method in Non-Patent Document 1, and FIG. 7 is a diagram illustrating the PLL open-loop gain-frequency characteristics and PLL open-loop phase-frequency characteristics when switched in this figure. It is a figure which shows the mode of a fluctuation | variation of both.

  In FIG. 6, when the switches 506 and 507 are closed by the control signal 510, the open loop band is narrowed. This situation is shown in a graph 601 in FIG. The phase-frequency characteristics at this time are also shown by 603 in FIG. On the other hand, when the switches 506 and 507 are opened by the control signal 510, the open loop band is widened. This situation is shown in a graph 602 in FIG. The phase-frequency characteristics at this time are also shown in the graph 604.

  The circuit of FIG. 6 also has a feature that the phase margin of the PLL does not vary because the resistance of the loop filter 503 and the sampling period of the phase comparison result of the phase comparator 501 are simultaneously switched.

Kazuo Watanabe, “Practical analog circuit design method”, General Electronic Publishing Co., pp. 193-203, Jun. 1996. Domine Leenaerts, Johan van der Tang and Cicero Vaucher, "Circuit Design for RF Transceivers" Kluwer Academic Publishers, 2001. J. Victory, Z. Yan, G. Gildenblat, C. McAndrew, and J. Zheng "A Physically Based, Scalable MOS Varactor Model and Extraction Methodology for RF Applications" IEEE ED. Vol.52 No.7, July 2005.

  However, there are some problems in controlling the loop bandwidth by this method. One of the problems is that the part of the switch 506 in FIG. 6 is a so-called analog signal line. For this reason, every time the switch is switched, there is a slight variation in the analog signal, and there is a problem that the phase must be pulled in again (lock-up operation). In mounting, the influence of jumping noise of the switching signal (switch coil current) is also assumed.

  Therefore, in view of the above points, the present invention speeds up the lock-up operation without causing the above-described problem by changing the PLL open loop gain by changing the VCO gain using the varactor in the PLL. However, an object of the present invention is to provide a PLL circuit that can reduce phase noise.

In order to solve the above problems and achieve the object of the present invention, the PLL circuit according to claim 1 of the present invention changes the Q value of the varactor in the VCO tank without changing the resonance frequency of the VCO tank. It is characterized by changing the VCO gain. That is, the invention according to claim 1 is preset with a tank circuit having two inductors (Lpv, Lnv), two pairs of reverse connection varactors (V1 to V4), and negative resistance elements (NVP, NVN). Generating at least two DC bias voltages, and applying a static DC bias voltage corresponding to one of the two DC bias voltages to each of the varactors according to an input control signal. A bias circuit (FIG. 5, R1, R2, Rb) connected to the circuit, and a resistance element (FIG. 4, Ra, R3) connected to the varactor that receives the frequency control signal and controls the oscillation frequency of the VCO . , R4 or Rb, R1, R2) and saw including a VCO having a, the bias circuit in response to said control signal, the static DC bus to be applied to the varactor By reducing the bias voltage, the Q value of the varactor is increased, the gain of the VCO is increased, and by increasing the static DC bias voltage applied to the varactor, the Q value of the varactor is decreased, Control is performed to reduce the gain of the VCO and thereby change the loop gain or the loop band of the PLL circuit including the VCO , where, according to the control signal, By changing the gain of the VCO, the loop gain or loop band of the PLL circuit including the VCO can be changed.

  The PLL circuit according to the present invention can change the PLL open loop gain in the PLL open loop band without a new PLL pull-in operation (lock-up operation) associated with the control signal. As a result, it is possible to control the PLL so as to increase the speed at the time of lockup and reduce the phase noise after the lockup.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of the first embodiment of the present invention. In FIG. 1, reference numeral 202 denotes a loop filter, reference numeral 203 denotes a charge pump, reference numeral 204 denotes a frequency phase comparator, and reference numeral 205 denotes a negative resistance generator. Reference numeral 206 denotes an LC tank, and a voltage controlled oscillator (VCO) includes a negative resistance generator 205 and an LC tank 206. Here, the LC tank 206 plays a role of determining the oscillation frequency of the VCO, and its operation is determined by the Loop Filter output signal 209 and the Q value control signal 208 for determining the frequency. The feature of the present invention resides in that the operation of the tank circuit is controlled by the Q value control signal 208. The Q value control signal 208 changes the operation state of the tank circuit including the varactor, and the VCO in the PLL circuit can be operated with desired characteristics. The phase reference signal 207 to be synchronized with the PLL is input to the frequency phase comparator 204 from the outside. A varactor is a variable capacitance element or a variable capacitance diode whose capacitance changes with voltage, and is also called a varicap (varactor diode). In this figure, a frequency dividing circuit is normally inserted between the VCO and the phase comparator, but it is not related to the present invention and is omitted for the sake of simplicity.

  First, a PLL having a tank circuit that includes a varactor will be described.

According to the non-patent document 2, the open-loop transfer function G (s) and the closed-loop transfer function H (s) of the PLL having the block configuration of FIG. 1 are expressed by the following equations. .
G (s) = Kp × Zf (s) × (2 × π × Kvr / s) (1)
H (s) = G (s) / {1 + G (s)} (2)
Here, Kp is the gain of the phase comparator (PFD), Zf (s) is the transfer function of the loop filter (LF), and Kvr is the gain of the voltage controlled oscillator (VCO). If there is a 1 / N frequency divider, 1 / N is multiplied to the right side of equation (1).

The open loop band “fc” is defined in Non-Patent Document 2 as follows.
| G (j × 2π × fc) | = 1 (3)
Here, fc is a crossover frequency of 0 db. From this, it is understood that there is a dependency relationship between the open loop band and the gain Kvr of the VCO.

Next, focusing on the VCO, the oscillation frequency is determined by the tuning frequency of the LC tank. FIG. 2 is a diagram showing an equivalent circuit of the LC tank considering loss. In FIG. 2, reference numeral 301 denotes an inductor of the LC tank, reference numeral 302 denotes a series resistance of the inductor, reference numeral 303 denotes a capacitor of the LC tank, and reference numeral 304 denotes an equivalent series resistance of the capacitor. Are connected to a control signal 305 and a common signal 306. In this case, the Q value Q (Ls) of Ls and the Q value Q (Cs) of Cs are shown as follows in Non-Patent Document 2.
Q (Ls) = ω × Ls / Rls, Q (Cs) = 1 / ω × Cs × Rls
Here, ω is an oscillation angular frequency.

The tuning angular frequency “ω _osc ” of the LC tank shown in FIG. 2 is obtained in Non-Patent Document 2 as follows.
ω _osc = Sqrt (Ls−Cs × Rls ² ) / {Sqrt (Cs × Ls) × Sq (Ls−Cs × Rcs ² )} (4)
From this equation, it can be seen that the gain Kvr of the VCO is a function of the series loss Rcs of the LC tank capacitor.

Hereinafter, using this relationship, Kvr when the capacitor Cs is Q = 10 and Kvr when Q = 40 are analytically obtained. here,
Q (cs) = 1 / (ω × Cs × Rcs),
ω = ωosc = 10 ⁹ [Hz],
Cs = 0.5E-12 [F]
Then,
When Q = 10, Rcs = 3.183 [ohm],
When Q = 40, Rcs = 0.996 [ohm]
It becomes.

For simplicity, when Rls = 0, the above-described formula (4) is
ωosc = Sqrt (Ls) / {Sqrt (Cs × Ls) × Sqrt (Ls−Cs × Rcs ² )} (5)
It is expressed.

  From this, the formula for calculating the ratio of Kvr at Q = 10 o'clock and Kvr at Q = 40 o'clock is simple, and when Rls = 0,

It can be expressed as.

Here, if fosc = 10 GHz, since Cs = 0.5E-12 [F], Ls = 5.066E-10 [H]. Substituting this into Equation 6,
2.149E-7 / 1.3376E-8 = 16.069
Is obtained. In other words, it is understood that when the Q of the varactor is increased from 10 to 40 by 4 times, Kvr changes by 16 times.

  FIG. 3a is a diagram showing a measurement result of a DC (direct current) bias vs. Q value at 500 MHz of the NMOS varactor shown in Non-Patent Document 3, and FIG. 3b is a diagram showing a DC bias vs. capacitance at 3 GHz. Similarly, FIG. 3c is a diagram showing the measurement result of the operating frequency body Q value when the DC bias is 1V. FIG. 3d shows these measurement circuits.

From these graphs, the following two physical phenomena can be read for the Q value of the varactor.
1) The Q value of the varactor is inversely proportional to the static DC bias.
2) The Q value of the varactor decreases monotonously with increasing operating frequency.

  From this, when using a normal On-Chip Inductor, the Q value is approximately 20 or less at a frequency of 1 GHz or more, but also at a frequency of 1 GHz or less, and when using an Off-Chip inductor. Then, since the Q value reaches several hundreds, it is understood that the Q value of the tank circuit can be controlled by changing the DC bias of the varactor over the entire frequency range.

  FIG. 4 is a diagram showing a circuit configuration example of a VCO suitable for implementing the present invention. In FIG. 4, V1 to V4 are varactors. Capacitors C1 to C4 and resistors R1 to R4, Ra, and Rb are added to change the operating state of the varactor having such a configuration by the Q control signal. The parts of the capacitors C1 to C4 and the resistors R1 to R4, Ra, and Rb are different from a general VCO that uses a varactor.

  The Loop Filter output signal 209 in FIG. 1, that is, the frequency control signal, is represented by Single End. However, in FIG. 4, this signal has a complementary signal configuration of CNTP and CNTN. Also, the Q control signal 208 in FIG. 1 is represented by Single End, but for the same reason, it is a complementary signal of CBIASP and CBIASN. The reason why the varactors V1 to V4 are AC-coupled to the inductors Lpv and Lnv via the capacitors C1 to C4 is to apply a static DC bias by the Q control signal 208 to each varactor. R1 to R3, Ra, and Rb only supply a static DC bias voltage, and the output impedance of the bias supply circuit (for example, the Q control circuit in FIG. 5) affects the operating state of the VCO. It is for not to be.

  In FIG. 4, the capacitor amount of the tank circuit composed of varactors V1 to V4, capacitors C1 to C4, and inductors Lpv and Lnv can be controlled by the differential voltage of VCNTP-VCNTN. The static bias voltage of the varactor can be controlled by CBIASP and CBIASN.

  FIGS. 5a and 5b are diagrams illustrating a plurality of examples of the Q control circuit connected to FIG. 4, that is, a circuit for generating CBIASP and CBIASN signals.

  First, the operation for increasing the Q value will be described with reference to FIG. 5A as an example. When the Q control circuit receives a signal to increase Q through the Q control signal 208 in FIG. 1, the Q control circuit inverts SW1 in FIG. 4 to the VL side and lowers the potentials of CBIASP and CBAISN. That is, the bias voltage is set in a more negative potential direction. As a result, the static DC operating points of the varactors V1 to V4 are lowered. Accordingly, the Q values of the varactors V1 to V4 increase. At this time, the oscillation frequency of the VCO does not change because the total capacity of the varactor is determined by the differential voltage between CNTP and CNTN. On the other hand, when an instruction to lower Q is received, SW1 is brought down to the VH side. As a result, the static DC operating points of the varactors V1 to V4 are increased, and the Q values of the varactors V1 to V4 are decreased. Here, it goes without saying that an increase in Q value results in an increase in VCO gain, and a decrease in Q value results in a decrease in VCO gain.

  Here, CBIASP and CBIASN do not have to be the same voltage. Therefore, as shown in FIG. 5b, CBIASP and CBIASN can be selected at different potentials. At this time, VL1, VL2, VH1, and VH2 are preferably selected so that the differential capacitance of the varactor has the highest linearity.

  One skilled in the art will appreciate that in FIGS. 5a and 5b, the switch portion may be an analog switch rather than a mechanical switch. Further, instead of stepwise change, it is also possible to change between two potentials linearly over time. In this case, it can be realized by making the portions shown as RP and RN in FIG. 5 a circuit having a time constant. As this circuit, a circuit having a resistor between the input and output and a capacitor between the output and the signal ground can be considered. By doing so, the influence of switching can be further reduced by appropriately selecting the time constant.

  FIG. 4 is a diagram showing an example of the present invention, and it is obvious to those skilled in the art that there are other examples that match the gist of the present invention disclosed in the above description.

It is a block diagram which shows embodiment of this invention. It is a figure which shows the equivalent circuit of a parallel LC tank. (A) is a figure which shows the DC bias-Q characteristic figure of NMOS varactor, (b) is a figure which shows the DC bias-capacitance value characteristic figure of NMOS varactor, (c) is the frequency-Q characteristic of NMOS varactor. It is a figure which shows a figure, (d) is a figure which shows the measurement circuit diagram of the NMOS varactor in (a)-(c). It is a figure which shows the VCO circuit example which concerns on embodiment of this invention. (A) is a figure which shows an example of Q control circuit, (b) is a figure which shows another example of Q control circuit. It is a figure which shows the conventional circuit system which switches the response characteristic of PLL. It is a figure which shows the open loop-gain characteristic and phase characteristic of PLL at the time of using PLL shown by FIG.

Explanation of symbols

V1 to V4 NMOS varactor Lpv LC tank configuration positive inductor Lnv LC tank configuration negative inductor VDD Positive power supply GND Reference potential CNTP Positive varactor control signal CNTN Negative varactor control signal CBIASP Positive varactor DC bias voltage CBIASN Negative varactor DC bias voltage OUTP VCO positive Output OUTN VCO negative output C1 to C4 DC blocking capacity Ls LC tank equivalent inductance Rls LC tank inductance series loss Cs LC tank equivalent capacitance Rcs LC tank capacitance series loss R1 to R4 DC coupling resistance Ra, Rb DC coupling resistance NVP Negative Positive NMOS transistor NVN for resistance generation Negative NMOS transistors PB0 and PB1 for negative resistance generation Bias current generator PMOS transistor IBIASP DC bar Iias current input terminals D1 to D3 Varactor bias generation diode VH Bias voltage VL Bias voltage RP, RN Varactor bias separation resistors R1 to R5 Varactor bias generation resistance VH1 Bias voltage VH2 Bias voltage VL1 Bias voltage VL2 Bias voltage G (s) Open circuit transfer function H (s) Closed circuit transfer function Kp Phase comparator (PFD) gain Zf (s) Loop filter (LF) transfer function Kvr Voltage controlled oscillator (VCO) gain Nfb Frequency divider frequency Fc PLL loop band ωosc tank tuning angular frequency fosc tank tuning frequency (fosc = ωosc / (2 × π))

Claims (1)

A tank circuit having two inductors, two pairs of reverse-connected varactors and a negative resistance element;
At least two DC bias voltages set in advance are generated, and a static DC bias voltage corresponding to one of the two DC bias voltages is applied to each varactor in accordance with an input control signal. A bias circuit connected to the tank circuit;
A VCO comprising: a resistance element connected to the varactor for inputting a frequency control signal to control a transmission frequency of the VCO;
The bias circuit is responsive to the control signal,
By lowering the static DC bias voltage applied to the varactor, the Q value of the varactor is increased to increase the gain of the VCO,
By increasing the static DC bias voltage applied to the varactor, the Q value of the varactor is decreased and the gain of the VCO is decreased.
Thus, the PLL circuit is controlled so as to change a loop gain or a loop band of the PLL circuit including the VCO .

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