JP4754102B2 - Negative voltage generation circuit and semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a negative voltage generation circuit, and more particularly to a technique that is particularly useful in a PLED (Phase-State Low Electron-number Drive) memory and used for a generation circuit of an off voltage supplied to a word line when a memory cell is not selected. .
[0002]
[Prior art]
In Japanese Patent Application Laid-Open No. 2000-113683, as an application technology of a PLED memory, a read MOS transistor that holds an information voltage at a gate terminal, a write transistor that applies an information voltage to the gate terminal (for example, a tunnel wall is formed in a channel portion of a MOSFET). A semiconductor memory including a memory cell including a tunnel transistor provided) and a capacitor connected to the gate terminal and controlling the voltage of the gate terminal is disclosed.
[0003]
According to such a configuration, the information voltage is held in the region surrounded by the insulating film. Therefore, by applying a negative voltage of, for example, about −3 V to the control terminal of the write transistor, the write data is very high. It can be held for a long time. That is, by applying an off voltage of about −3 V to the word line when the memory cell is not selected, data written in the memory cell can be held for a very long period when the memory cell is not selected. The interval between refresh operations performed in a DRAM (Dynamic Random Access Memory) for holding can be made very long, or refresh operations can be made unnecessary.
[0004]
Then, when the present inventors examined the negative voltage generation circuit which generate | occur | produces said off voltage, the circuit as shown, for example in FIG. 13 was considered.
In this figure, C1 is a capacitor for generating a negative voltage, M1 is a precharge MOS for charging the lower electrode of the capacitor C1 to the power supply voltage VSS on the negative side, and C2 is a reverse boost action for the voltage for driving the gate of the precharge MOS M1. Mout1 is an output transfer MOS that outputs a negative voltage generated in the capacitor C1 by reverse boosting and prevents reverse current flow during a period when no negative voltage is generated. INV1 is an upper electrode of the capacitor C1. This is an inverter that switches the voltage between positive and negative power supply voltages VCC and VSS. The inverter INV1 is configured to have a large driving force for charging the capacitor C1. The preceding inverters INV2 and INV3 are buffer inverters provided to gradually increase the signal to match the input signal to the inverter INV1.
[0005]
In FIG. 13, NOR circuits 10 and 11, AND circuit 12, and a delay circuit composed of inverter INV and capacitor C <b> 10 are used for timing signal for switching the connection of the upper electrode of capacitor C <b> 1 and for switching the connection of the lower electrode. A timing generation circuit for generating a timing signal. The MOS M21 is a voltage clamping MOS that suppresses the voltage rise at the node N2 and assists the reverse boost of the capacitor C2. The diode-connected MOSs M23 to M25 are limiter circuits that prevent the voltage at the node N2 from dropping too much. is there. The MOS M21 is a voltage clamping MOS that suppresses the voltage rise at the node N1 and assists the reverse boost of the capacitor C1, and the diode-connected MOSs M13 to M16 are limiter circuits that prevent the voltage at the node N2 from dropping too much. is there.
[0006]
[Problems to be solved by the invention]
However, since the negative voltage generating circuit as described above uses the output transfer MOS Mout1 whose gate is coupled to the drain to output the negative voltage generated in the capacitor C1, it is output from the output transfer MOS Mout1. The negative voltage becomes a difference voltage (Vg−Vth) between the gate voltage Vg and the threshold voltage Vth of the MOSFET, and becomes a voltage higher by, for example, 1 V than the negative voltage generated in the capacitor C1.
[0007]
When trying to generate an off-voltage of the PLED memory using this negative voltage generation circuit, a voltage of about 4V to 5V is required as a power supply voltage. However, in recent years, the external power supply is generally reduced to about 3V. In such a situation, there is a problem that a necessary off voltage cannot be generated.
[0008]
Further, by providing a plurality of stages of the negative voltage generation circuit as described above, the negative voltage generated in the first stage is used as the voltage on the negative side of the second stage, so that a lower voltage can be obtained from the negative voltage generation circuit in the second stage. Although it is conceivable that the charge pump circuit is stacked in a plurality of stages as described above, there is a problem that the voltage supply efficiency and the start-up characteristic are deteriorated.
[0009]
As other conventional techniques applicable as a negative voltage generating circuit, there are booster circuits disclosed in Japanese Patent Laid-Open Nos. 5-189970 and 11-328957. The configuration of such a booster circuit is used as a negative voltage generating circuit. There was no application.
[0010]
An object of the present invention is to provide a negative voltage generation circuit that is excellent in voltage supply efficiency and start-up characteristics, and that can generate a negative voltage of about -3 V using a low power supply voltage of about 3 V.
[0011]
Another object of the present invention is to provide a semiconductor memory device that uses such a negative voltage generation circuit to make the refresh interval very long and virtually eliminate the need for a refresh operation.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
[0014]
That is, it has at least a first capacitor for generating a negative voltage, and switch means for switching a connection state between the two electrodes of the first capacitor and the first power source on the positive electrode side and the second power source on the negative electrode side, The first charge pump circuit for generating a first negative voltage lower than the voltage of the second power source at one electrode of the first capacitor by switching, a plurality of capacitors, and the plurality of capacitors are connected to the positive-side first Switch means for switching between a state where one power supply and a second power supply on the negative electrode side are connected in parallel and a state where these capacitors are connected in series are connected in series by switching the switch means A second charge pump circuit for generating a second negative voltage lower than the voltage of the second power supply on one end side of the formed capacitor, wherein the second capacitor of the plurality of capacitors includes a first node and a second node. Connection with other nodes One end of the third capacitor among the plurality of capacitors is connected to the third node, the other end is connected to the first node via a delay inverter, and the first node A second charge comprising a first P-channel MOSFET connected between the first power supply and a first N-channel MOSFET connected between the first node and the third node; Backflow prevention for receiving the second negative voltage generated by the pump circuit and the second charge pump circuit at the gate and outputting the first negative voltage generated by the first charge pump circuit between the source and the drain And an output transfer MOS transistor for the negative voltage generating circuit. An output transfer MOS transistor connected between the output terminal and the fourth node and having a control terminal connected to the second node; and an input signal for receiving the input signal and setting the potential of the fourth node to a negative potential. And a second charge pump circuit that receives an input signal and sets the second node to a negative potential, 1 A first capacitor connected between the second node and the second node, one end connected to the third node, and the other end via the delay inverter. 1 A second capacitor connected to the node, and the second capacitor 1 Nodes and Positive side A first P-channel MOSFET connected between the first power source and the first power source; 1 And a second charge pump circuit including a first N-channel MOSFET connected between the second node and the third node.
[0015]
According to such means, the second charge pump circuit can generate a voltage much lower than that of the first charge pump circuit, and this voltage is used as the voltage for driving the gate of the output transfer MOS. The first negative voltage generated by the charge pump circuit can be output via the output transfer MOS without increasing the voltage. Therefore, a negative voltage of -3V can be generated using, for example, an external power supply of 3V without reducing the voltage supply efficiency and startup characteristics.
[0016]
Preferably, the switch means of the first charge pump circuit includes a second P-channel MOSFET having a common drain connected to one electrode of the first capacitor and a source connected to a first power source, and a source. A second N-channel MOSFET connected to the second power supply and a precharge MOS connected to the other electrode of the first capacitor and switching the other electrode and the second power supply to a connected or disconnected state FET It is good to be composed of
[0017]
More preferably, The other end of the third capacitor is connected to the first node via a delay inverter, Common drain of the second P-channel MOSFET and the second N-channel MOSFET Connect to It is good to be configured.
[0018]
Preferably, the control terminal is connected between the second node and the second power source, and the control terminal is the precharge MOS. FET A third P-channel MOSFET connected to the control terminal of the second power source, and the third P-channel MOSFET connected between the third node and the second power source. FET A fourth P-channel MOSFET connected to the control terminal of the precharge MOS, FET And a fifth P-channel MOSFET for clamping that lowers the potential of the control terminal to the vicinity of the voltage of the second power supply.
[0019]
Also, a read MOS transistor that holds the information voltage at the gate terminal, a write transistor that applies the information voltage to the gate terminal, and Said A capacitor having one electrode connected to the gate terminal and controlling a voltage of the gate terminal; Said Control terminal for write transistor and Said The other electrode of the capacitor is connected to the word line, Said Data input terminal of the writing transistor and the reading MOS In a semiconductor memory device including a memory cell in which a source terminal or a drain terminal of a transistor is connected to a data line, when the memory cell is not selected Said The above-described negative voltage generation circuit may be applied as a circuit for generating a voltage supplied to the word line.
[0020]
By supplying a negative voltage when not selected in this way, the information voltage held at the gate terminal of the read MOS transistor can be held for a very long time.
[0021]
Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a preferred negative voltage generating circuit to which the present invention is applied. The negative voltage generation circuit of this embodiment includes a capacitor C1, a first charge pump circuit including a precharge MOS M1 corresponding to the capacitor C1 and inverters INV1 to INV3, a plurality of capacitors C3 and C4, and corresponding precharge transistors. A second charge pump circuit comprising charge MOSs M3 and M4, connection switching P-channel MOS MP1 and N-channel MOSMN1, delay inverter INV4, and the like, and gate driving of the precharge MOSs M1, M3 and M4 A capacitor C2 for generating a reverse voltage, an output transfer MOSMout1 for outputting a negative voltage generated by the first charge pump circuit and preventing a reverse current flow, NOR circuits 10 and 11, a NAND circuit 12, Inverter INV for delay And a and a timing generation circuit consisting of the capacitor C10. The capacitor C4 is connected between the node N5 that is the first node and the node N3 that is the second node. The capacitor C3 has one end connected to the node N4, which is the third node, and the other end connected to the node N5 via the delay inverter INV4.
[0022]
In addition, the negative voltage generation circuit assists the reverse boost action of the first charge pump circuit, 4 A clamp MOS M11 that pulls down the voltage of the node N1 to near the negative power supply voltage VSS (for example, ground potential). 4 A limiter circuit composed of diode-connected MOSs M13 to M16 for limiting a voltage drop when an excessive negative voltage is generated at the node N1 for some reason, and a second node N2 for assisting the reverse boosting action of the capacitor C2. Clamp MOS M21 that lowers the voltage near the negative power supply voltage VSS, and diode-connected MOSs M23 to M25 that limit the voltage drop below that when the voltage at the second node N2 is excessively negative for some reason A limiter circuit or the like is provided.
[0023]
The inverter INV1 that charges and discharges the capacitor C1 in the first charge pump circuit is designed to have a large driving force in accordance with the capacitor C1. The preceding inverters INV2 and INV3 are designed so that the driving force gradually increases in order to drive the inverter INV1 having a large driving force. When the precharge MOS M1 is in the on state, the upper electrode of the capacitor C1 is charged to the power supply voltage VCC by the inverter INV1, and then the precharge MOS M2 is turned off to connect the upper electrode of the capacitor C1 to the negative voltage by the inverter INV1. By knocking down to the power supply voltage VSS, a reverse voltage is boosted to the lower electrode of the capacitor C1 to a negative voltage (−2 × (VCC−VSS)) that is twice the power supply voltage.
[0024]
The second charge pump circuit generates a plurality of capacitors C3 and C4 in individual capacitors by reverse boosting action by switching from a state in which the capacitors C3 and C4 are connected in parallel between the power supply voltages VCC and VSS to a state in which they are connected in series. The voltage obtained by adding the negative voltage 2 It is generated at the node N3.
[0025]
That is, when the precharge MOSs M3 and M4 are in the on state, the inverter INV4 for one capacitor C3 and the P-channel MOS MP1 for the other capacitor C4 are turned on, so that the upper portions of the capacitors C3 and C4 The electrode is charged to the power supply voltage VCC. Next, the precharge MOSs M3 and M4 are turned off, and the P channel MOS MP1 is turned off and the N channel MOS MN1 is turned on, so that the lower electrode of the capacitor C3 and the upper electrode of the capacitor C4 are connected. . Further, the inverter INV4 knocks down the upper electrode of the capacitor C3 to the negative power supply voltage VSS, so that the two capacitors C3 and C4 are connected in series and are subjected to a reverse boost action, and the power supply voltage is applied to the lower electrode of the capacitor C4. Negative voltage (−2 × (VCC−VSS)) is generated.
[0026]
The delay inverter INV4 adjusts the timing so that the reverse boost operation of the cascaded capacitors C3 and C4 is performed at the timing when the precharge MOS M3 is completely turned off.
[0027]
The negative voltage generated by the first charge pump circuit is supplied to the drain terminal of the output transfer MOS Mout1, and the negative voltage generated by the second charge pump circuit is applied to the gate terminal of the output transfer MOS Mout1. Since the negative voltage applied to the gate terminal is much lower than the negative voltage output to the drain terminal, the negative voltage of the first charge pump circuit is output from the source terminal of the output transfer MOS Mout1 with almost no voltage increase.
[0028]
FIG. 2 is a circuit diagram showing a second embodiment of a preferred negative voltage generating circuit to which the present invention is applied.
The negative voltage generating circuit of the second embodiment is an example in which a countermeasure against the withstand voltage of the gate of the N-channel MOS MN2 that connects the two capacitors C3 and C4 of the second charge pump circuit in series is taken. Since the source terminal of the N-channel MOS MN2 is connected to the lower electrode of the capacitor C3, a negative power supply voltage VSS or a negative voltage (VSS-VCC) at the time of reverse boost is applied thereto. Therefore, when the output voltage of the NOR circuit 11 is applied to the gate terminal, the gate-source voltage becomes very large during reverse boost. Therefore, in this embodiment, the gate of the N-channel MOS MN2 is connected to the negative power supply voltage VSS so that an excessive voltage is not applied between the gate and the source.
[0029]
According to such a configuration, at the time of reverse boost, the potential of the lower electrode of the capacitor C3 becomes lower than the power supply voltage VSS, so that the N-channel MOS MN2 is automatically turned on, and the first embodiment of FIG. The substantially same operation as that of the circuit is performed.
[0030]
However, since the timing at which the N-channel MOS MN2 is turned on is delayed by that amount, the signal at the common drain of the N-channel MOS MN2 and the P-channel MOS MP1 cannot be used as a signal for reverse boosting the capacitor C2 at the subsequent stage. . Therefore, in this embodiment, the charging and discharging of the upper electrode of the capacitor C3 is performed by the inverter IN1 that charges and discharges the capacitor C4 of the first charge pump circuit. In this configuration, since the delay action is exerted by the inverters IN1 to INV3, the charge / discharge timing of the capacitor C3 is substantially the same as that of the circuit of the first embodiment of FIG.
[0031]
FIG. 3 is a circuit diagram showing an example of a transmission circuit for supplying a clock signal to the negative voltage generation circuit.
The circuit of FIG. 3 is an example of an oscillation circuit that supplies the clock signal OSC to the NOR circuit 10 of the timing generation circuit in the negative voltage generation circuit of FIGS. 1 and 2, and is an inverter ring type oscillator. When the active signal ACTB is low level and the low level, the NMOS of the first stage inverter INV10
MN10 is turned on, and the inverter ring performs a transmission operation.
[0032]
In this transmission circuit, MOS MT1 to MT4 formed in the second to fifth stage inverters INV12 to INV15 are formed with different element sizes between P channel types or N channel types, By selecting the MOSFET to be turned on and the MOSFET to be turned off among the MOSs MT1 to MT4 by the signal MODE2, the delays of the inverters INV12 to INV15 are changed so that the oscillation frequency can be switched between two ways. It has become.
[0033]
Next, the operation principle of the second charge pump that generates the gate drive voltage of the output transfer MOS Mout1 in the negative voltage generation circuit shown in FIGS. 1 and 2 will be described in a simplified manner.
[0034]
FIG. 4 is a diagram schematically showing a multiple boost type charge pump circuit in order to explain the negative voltage generation principle of the second charge pump circuit described above.
As shown in FIG. 4A, this charge pump circuit is shown in FIG. 4B from the state where four capacitors C21 to C24 are connected in parallel between the positive and negative power supply voltages VCC and VSS. Thus, the four capacitors C21 to C24 are converted into a state of being connected in series, and the negative power supply voltage VSS is connected to the high potential side electrodes of the four capacitors C21 to C24 connected in series. This is a circuit for generating a negative voltage with a low potential at the electrode on the low potential side.
[0035]
In FIG. 4, S1 to S4 and S31 to S34 are switches for switching the connection states of the capacitors C21 to C24 as described above, and Co is a load capacitance at the output node Nout.
[0036]
FIG. 5 is a diagram showing signal waveforms at each node in the charge pump circuit of FIG. In FIG. 5, an initial state (1) in which the switches S1 to S4 are on and the switches S31 to S34 are connected to the left terminal TL, and the switches S1 to S4 are on and the switches S31 to S34 are connected to the upper terminal TU. The operation waveforms are divided into a connected charging period {circle around (2)} and a discharging period {circle around (3)} in which the switches S1 to S4 are off and the switches S31 to S34 are connected to the left terminal TL.
[0037]
First, in the initial state (1), the potentials of the nodes N21 to N24 and the output node Nout of the upper electrodes of the capacitors C21 to C24 are the negative power supply voltage VSS (0 V).
[0038]
Next, when the charging period {circle over (2)}, the four capacitors C21 to C24 are charged, and the potentials of the nodes N21 to N24 of the upper electrodes are raised from 0V to the positive power supply voltage VCC.
[0039]
Next, in the discharge period (3), the upper electrode of the first capacitor C21 is connected to the power supply voltage VSS, so that the potential of the node N21 drops to the voltage VSS (0 V). In addition, the potential of the node N22 of the upper electrode of the second capacitor C22 connected to the lower electrode of the first capacitor C21 is such that the charge charged in the capacitor C21 slightly moves toward the load capacitor Co. The voltage between both poles of the capacitor C21 is somewhat reduced to −η × VCC. Here, Cη = 4C / (4Co + C) and C = C21 + C22 + C23 + C24. C21 to C24 and Co indicate capacitance values of the capacitors C21 to C24 and Co, respectively.
[0040]
Similarly, the potential of the node N23 connected to the lower electrode of the second capacitor C22 is −η × 2VCC, the potential of the node N24 connected to the lower electrode of the third capacitor C23 is −η × 3VCC, and the fourth The potential of the output node Nout connected to the lower electrode of the capacitor C24 is −η × 4VCC, and a very low negative voltage can be obtained with high efficiency and high speed. Furthermore, it is possible to generate a lower negative voltage by increasing the number of stages of the plurality of capacitors.
[0041]
FIG. 6 shows a MOS configuration diagram of a charge pump circuit in which the number of capacitor stages in the circuit of FIG.
6, CA1 to CAn are n-stage capacitors, MS1 to MSn are precharge MOSs corresponding to the switches S1 to S4 in FIG. 4, and INVS31 to INVS3n are CMOS inverter switches corresponding to the switches S31 to S34 in FIG. It is.
[0042]
The limiter circuit including the NOR circuits 10 and 11, the NAND circuit 12, the capacitor C2, the clamp MOS M21, and the MOSs M23 to M25 is the same as that shown in FIG. The delay circuit 13 provided in front of the NOR circuit 11 and the NAND circuit 12 corresponds to the delay circuit including the inverter INV and the capacitor C10 in FIG. 1, and is provided in front of the first-stage inverter switch INVS31. The delay circuit 14 corresponds to the delay action of the inverter INV4 and the MOS MP1 and MN1 in FIG.
[0043]
FIG. 7 shows a signal waveform diagram of each node in the charge pump circuit.
According to such a charge pump circuit, the output NS1 of the NAND circuit 12 becomes a low level after the delay of the delay circuit 13 has elapsed from the fall of the externally input clock signal OSC, and then the rise of the clock signal OSC. Immediately goes high. On the other hand, the output NS3 of the NOR circuit 11 becomes low level immediately after the fall of the clock signal OSC inputted externally, and becomes high level after the delay of the delay circuit 13 has elapsed from the rise of the clock signal OSC. In this way, a narrow timing pulse for operating the precharge MOSs MS1 to MSn connected to the lower electrode side of each of the capacitors CA1 to CAn and a width for operating the inverter switches INVS31 to INVS3n connected to the upper electrode side. Wide timing pulses are generated.
[0044]
Thus, similarly to the reverse boost operation shown in FIG. 5, the reverse boost operation by the n-stage capacitors CA1 to CAn occurs, and a negative voltage of −η × n × VCC is generated at the output node Nout.
[0045]
The delay circuit 14 provided on the front stage side of the first stage capacitor CA1 performs the reverse boost operation of the cascaded capacitors CA1 to CAn at the timing when the precharge MOSs MS1 to MSn are completely turned off. To match the timing.
[0046]
FIG. 8 is a circuit diagram of an example in which an output transfer MOS Mout2 is added to the charge pump circuit of FIG. 6, and FIG. 9 is a diagram showing signal waveforms at each node in the charge pump circuit.
[0047]
As shown in FIG. 8, when the output transfer MOS Mout2 is added before the output node Nout, the negative voltage generated by the reverse boosting action of the n-stage capacitors CA1 to CAn charges the load capacitance Co. Since the load capacitance Co is maintained without reverse flow, the negative boost voltage is lowered until the charge voltage of the load capacitance Co is finally saturated by repeating the reverse boost operation of the n-stage capacitors CA1 to CAn. I will do it. In the saturated state, the potential of the node NGn of the lower electrode of the n-th capacitor CAn is −n × VCC because there is no charge transfer to the load capacitance Co, and the potential of the output node Nout is the output transfer MOS Mout2. The potential is higher by the threshold voltage Vth of −n × VCC + Vth.
[0048]
FIG. 10 is a circuit diagram showing an example in which the N-channel MOSFET and the precharge MOS are withstand voltage countermeasures in the charge pump circuit of FIG. 6, and FIG. 11 is a diagram showing signal waveforms at each node in this circuit.
[0049]
In the charge pump circuit of FIG. 6, negative voltages (−η × VCC) to (−η × n × VCC) are applied to the source terminals of the NMOS MN32 to MN3n of the second to n-th stage inverter switches INVS32 to INVS3n. Since the voltage is applied, a large voltage is applied between the gate and source of the NMOS MN32 to MN3n. Similarly, since negative voltages (−η × VCC) to (−η × n × VCC) are applied to the drain terminals of the precharge MOSs MS1 to MSn, between the gates and drains of the precharge MOSs MS1 to MSn. A large voltage is applied.
[0050]
In the charge pump circuit of FIG. 10, in order to increase the gate-source breakdown voltage of the NMOS MN32 to MN3n, the gate terminals of the NMOS MN32 to MN3n are connected to inverter switches INVS31, INVS32. Are connected to the source terminals of NMOS MN31, MN32. With this connection, the gate-source voltages of the NMOSs MN32 to MN3n are approximately within the power supply voltage VCC, and gate breakdown can be prevented. Also, the capacitors CA1, CA2,. .
[0051]
In addition, in order to increase the gate-drain breakdown voltage of the precharge MOSs MS1 to MSn, capacitors CC1 to CCn are provided between the gates and drains of the precharge MOSs MS1 to MSn, and clamp MOSs M21 and Limiter circuits L1 to Ln are provided. The limiter circuits L1 to Ln are set to a limiting voltage corresponding to the magnitude of the negative voltage generated at the drain terminals of the precharge MOSs MS1 to MSn.
[0052]
According to such a configuration, as shown in the signal waveform of the node NS2n in FIG. 11, at the timing when the negative voltage is generated in the lower electrodes of the capacitors CA1 to CAn in a plurality of stages due to the reverse boost action, the negative voltage is It is transmitted to the gate terminal side of the precharge MOSs MS1 to MSn via the capacitors CC1 to CCn. Therefore, the gate-drain voltage does not exceed a predetermined value, and gate breakdown can be prevented. In addition, since the gate voltage does not become lower than the set value by the limiter circuits L1 to Ln, the precharge MOSs MS1 to MSn are controlled to be off during this period, and normal operation as the precharge MOS is obtained.
[0053]
As described above, the circuit for generating a negative voltage by switching a plurality of capacitors from a parallel connection to a series connection has been described with some variations. Such a circuit is illustrated in the second precharge of FIGS. It can be applied as a circuit. Further, the present invention may be applied to the first precharge circuit that generates an output negative voltage.
[0054]
FIG. 12 is a circuit block diagram showing a PLED memory useful by applying the above-described negative voltage generation circuit.
[0055]
This PLED memory is described in detail in Japanese Patent Application Laid-Open No. 2000-113683. Although details are omitted, a read transistor QR composed of an N-channel MOSFET, a write transistor QW composed of a tunnel transistor, and A plurality of memory cells MC having a coupling capacitor C for controlling the gate voltage of the read transistor QR, and a source voltage control circuit SVC for controlling the source voltage supplied to each memory cell MC via the source line SL; A data control register DCR that supplies three levels of voltages at the time of writing, reading and non-selection to a plurality of word lines WL to which each memory cell MC is coupled for each row, and each data line before the read operation Precharge MOS Qp for precharging to a predetermined voltage VDD, complementary before read operation A pair of data input / output lines I / O and I / OB are precharge MOS Qp2 for precharging to a predetermined voltage VDD / 2, and a data line DL of a selected column is connected to the data input / output lines I / O and I / OB. Column switch Qy, a sense amplifier SA that amplifies a data signal read to a pair of data input / output lines I / O and I / OB, an input / output data buffer DB that inputs / outputs data to / from the outside, etc. It has.
[0056]
In the memory cell MC, one electrode of the coupling capacitor C and the gate of the writing transistor QW are connected to the word line WL, and one data terminal (for example, source or drain) of the reading transistor QR and the writing transistor QW One data terminal (for example, source or drain) is connected to the data line DL.
[0057]
The tunnel transistor used for the write transistor QW is a vertical transistor in which gate electrodes are arranged on both sides of a plurality of stacked layers (for example, four layers) of polysilicon via a gate oxide film. A tunnel film made of, for example, a thin silicon nitride film is formed between the polysilicon layers.
[0058]
In such a memory cell MC, the stored data is held at the connection node NM to which the gate electrode of the read transistor QR is connected. Since the connection node NM has a structure surrounded by an insulating film, there is no problem that a leakage current is generated from the pn junction or the stored data is inverted due to a soft error unlike a DRAM cell. When the memory cell MC is not selected, a constant off voltage is applied to the gate of the write transistor QW to sufficiently turn off the write transistor QW, so that the stored data signal flows to the data line DL. Can be kept low enough. Therefore, the data retention time of the memory cell MC becomes long, so that the necessary refresh time can be made extremely long, or the refresh operation is not necessary and can be made virtually non-volatile.
[0059]
In this semiconductor memory, it is the data control register DCR that applies the above-mentioned off-voltage to the word line WL when the memory cell MC is in a non-selected state. A circuit NVG is used.
[0060]
As described above, according to the negative voltage generation circuit of FIGS. 1 and 2, the first charge pump circuit that performs the two-stage reverse boost using the capacitors C3 and C4 causes the capacitor C1 to generate the reverse boost voltage. Since a voltage much lower than that of the charge pump circuit is generated and this voltage is used as a voltage for driving the gate of the output transfer MOS Mout1, the first negative voltage generated by the first charge pump circuit is increased in voltage. Can be output via the output transfer MOS Mout1. Therefore, a negative voltage of -3V can be generated using, for example, an external power supply of 3V without reducing the voltage supply efficiency and startup characteristics.
[0061]
Further, according to the negative voltage generating circuit of FIG. 2, the gate terminal of the NMOS MN2 corresponding to the second capacitor C4 of the second charge pump circuit that performs the two-stage boost is connected to the power supply voltage VSS. Compared to the case of FIG. 1 coupled to the gate terminal of MP1, the voltage applied between the gate and source of the NMOS MN2 or between the gate and drain can be reduced, and the breakdown voltage of the circuit can be increased.
[0062]
Further, according to the negative voltage generation circuit of FIG. 1 or FIG. 2, the timing of charging / discharging the first capacitor C3 of the second charge pump circuit that performs the two-stage boost is set to the timing of the second capacitor C4 by the inverters INV4 and INV4. Since the delay is further delayed, the negative voltage can be generated stably and efficiently.
[0063]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
[0064]
For example, in the embodiment shown in FIGS. 1 and 2, the first charge pump circuit for generating the output voltage using the capacitor C1 has a single capacitor C1. A charge pump circuit that switches a plurality of capacitors from parallel to serial can also be applied.
[0065]
In the above description, the off-voltage generation circuit of the PLED memory, which is a field of use that is based on the invention made by the present inventor, has been described. However, the present invention is not limited to this and requires a negative voltage. It can be widely used for semiconductor integrated circuits.
[0066]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0067]
That is, according to the present invention, a voltage much lower than that of the first charge pump circuit is generated by the second charge pump circuit, and this voltage is used as a voltage for driving the gate of the output transfer MOS. The first negative voltage generated in the pump circuit can be output via the output transfer MOS without increasing the voltage. Therefore, there is an effect that a negative voltage of −3 V can be generated using, for example, an external power supply of 3 V without reducing the voltage supply efficiency and the start-up characteristics.
[0068]
Furthermore, in the second charge pump circuit that generates a negative voltage using a plurality of capacitors, the gate terminal of the N-channel MOSFET that connects one electrode of the capacitor in the former stage to the other electrode of the capacitor in the latter stage is connected to the first electrode on the negative electrode side. By being configured to be connected to the two power supplies or the source terminal of the N-channel MOSFET corresponding to the capacitor in the previous stage, there is an effect that the breakdown voltage of the N-channel MOSFET can be improved.
[0069]
In addition, according to the semiconductor memory device of the present invention, a low-voltage power supply of about 3 V is used by applying the negative voltage generation circuit as described above as an off-voltage generation circuit that is applied to unselected word lines. Even in such a case, there is an effect that an appropriate off voltage can be generated to make the refresh interval very long, or the refresh operation can be made unnecessary.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a preferred negative voltage generating circuit to which the present invention is applied.
FIG. 2 is a circuit diagram showing a second embodiment of a preferred negative voltage generating circuit to which the present invention is applied.
FIG. 3 is a circuit diagram illustrating an example of a transmission circuit that supplies a clock signal to a negative voltage generation circuit.
FIG. 4 is a simplified diagram of a charge pump circuit illustrating a negative voltage generation principle of a second charge pump circuit.
FIG. 5 is a diagram showing signal waveforms at each node in the circuit of FIG. 4;
6 is a MOS configuration diagram of a charge pump circuit in which the number of capacitor stages is configured to be n in accordance with the operation principle of FIG. 4;
7 is a diagram showing signal waveforms at each node in the charge pump circuit of FIG. 6;
8 is a circuit diagram showing an example in which an output transfer MOS is added to the charge pump circuit of FIG. 6;
9 is a diagram showing signal waveforms at each node in the charge pump circuit of FIG. 8;
10 is a circuit diagram showing an example in which a countermeasure against withstand voltage is taken for the N-channel MOSFET and the precharge MOS in the circuit of FIG. 6;
11 is a diagram showing signal waveforms at each node in the charge pump circuit of FIG. 10;
FIG. 12 is a circuit block diagram showing a PLED memory to which the negative voltage generation circuit of the embodiment is applied.
FIG. 13 is a circuit diagram showing an example of a negative voltage generation circuit previously examined by the inventors as a circuit for generating an off voltage of a PLED memory.
[Explanation of symbols]
C1 Capacitor of the first charge pump circuit
C3, C4 Capacitor of second charge pump circuit
INV1-INV3 CMOS inverter
INV4 delay inverter
M1, M3, M4 Precharge MOS
MP1 P-channel MOSFET
MN1, MN2 N-channel MOSFET
Mout1 output transfer MOS

Claims (6)

A first capacitor for generating a negative voltage; and at least switch means for switching a connection state between the two electrodes of the first capacitor and the first power source on the positive electrode side and the second power source on the negative electrode side. A first charge pump circuit for generating a first negative voltage lower than the voltage of the second power source at one electrode of the first capacitor by:
Switch means for switching between a plurality of capacitors and a state in which the plurality of capacitors are connected in parallel between a first power source on the positive electrode side and a second power source on the negative electrode side and a state in which the plurality of capacitors are connected in series And a second charge pump circuit for generating a second negative voltage lower than the voltage of the second power source on one end side of the capacitors connected in series by switching of the switch means, the second volume of the capacity is connected between the first node and the second node, one end of the third capacitor of the plurality of capacitance is connected to the third node, the other end delay And a first P-channel MOSFET connected to the first node via an inverter, and connected between the first node and the first power source, and the first node and the first node. First N-channel connected between the three nodes A second charge pump circuit comprising a channel MOSFET,
An output transfer for backflow prevention that receives the second negative voltage generated by the second charge pump circuit at the gate and outputs the first negative voltage generated by the first charge pump circuit through between the source and the drain. A MOS transistor;
A negative voltage generating circuit comprising: The switch means of the first charge pump circuit includes a second P-channel MOSFET having a common drain connected to one electrode of the first capacitor and a source connected to the first power source, and a source connected to the first power source. A second N-channel MOSFET connected to two power sources, and a precharge MOS FET connected to the other electrode of the first capacitor and switching the other electrode and the second power source to a connected or disconnected state. The negative voltage generation circuit according to claim 1, wherein the negative voltage generation circuit is configured. The other end of the third capacitor is connected to the common drain of the second P-channel MOSFET and the second N-channel MOSFET instead of being connected to the first node via a delay inverter. The negative voltage generation circuit according to claim 2. A third P-channel MOSFET connected between the second node and the second power supply and having a control terminal connected to a control terminal of the precharge MOS FET ;
A fourth P-channel MOSFET connected between the third node and the second power supply and having a control terminal connected to the control terminal of the precharge MOS FET ;
4. The negative voltage according to claim 2, further comprising: a fifth P-channel MOSFET for clamping that lowers the potential of the control terminal of the precharge MOS FET to the vicinity of the voltage of the second power supply. Generation circuit. An output transfer MOS transistor connected between the output terminal and the fourth node and having a control terminal connected to the second node;
A first charge pump circuit that receives an input signal and sets the potential of the fourth node to a negative potential;
A second charge pump circuit for receiving an input signal and setting the second node to a negative potential; a first capacitor connected between the first node and the second node; It is connected to the third node, connected between the second capacitor and the other end is connected to said first node through a delay inverter, a first power source of the first node and the positive side And a second charge pump circuit including a first P-channel MOSFET and a first N-channel MOSFET connected between the first node and the third node. Negative voltage generator. A read MOS transistor for holding the information voltage at the gate terminal, a write transistor for applying the information voltage to the gate terminal, and a capacitor for controlling one of the electrodes connected to the gate terminal and controlling the voltage of the gate terminal; The control terminal of the write transistor and the other electrode of the capacitor are connected to a word line, and the data input terminal of the write transistor and the source terminal or drain terminal of the read MOS transistor are connected to a data line. In a semiconductor memory device having a memory cell formed,
6. A semiconductor memory device comprising the negative voltage generation circuit according to claim 1 as a circuit for generating a voltage supplied to the word line when a memory cell is not selected.

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